Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
4eb3c30b JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
7e044e05 | 15 | #include <linux/types.h> |
1da177e4 LT |
16 | #include <linux/delay.h> |
17 | #include <linux/module.h> | |
1da177e4 LT |
18 | #include <linux/interrupt.h> |
19 | #include <linux/ioport.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/serio.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/rcupdate.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
553a05b8 | 25 | #include <linux/i8042.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1c5dd134 | 27 | #include <linux/suspend.h> |
1da177e4 LT |
28 | |
29 | #include <asm/io.h> | |
30 | ||
31 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
32 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
33 | MODULE_LICENSE("GPL"); | |
34 | ||
386b3849 | 35 | static bool i8042_nokbd; |
945ef0d4 DT |
36 | module_param_named(nokbd, i8042_nokbd, bool, 0); |
37 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
38 | ||
386b3849 | 39 | static bool i8042_noaux; |
1da177e4 LT |
40 | module_param_named(noaux, i8042_noaux, bool, 0); |
41 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
42 | ||
e55a3366 | 43 | static bool i8042_nomux; |
1da177e4 | 44 | module_param_named(nomux, i8042_nomux, bool, 0); |
2c860a11 | 45 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); |
1da177e4 | 46 | |
386b3849 | 47 | static bool i8042_unlock; |
1da177e4 LT |
48 | module_param_named(unlock, i8042_unlock, bool, 0); |
49 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
50 | ||
386b3849 | 51 | static bool i8042_reset; |
1da177e4 LT |
52 | module_param_named(reset, i8042_reset, bool, 0); |
53 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
54 | ||
386b3849 | 55 | static bool i8042_direct; |
1da177e4 LT |
56 | module_param_named(direct, i8042_direct, bool, 0); |
57 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
58 | ||
386b3849 | 59 | static bool i8042_dumbkbd; |
1da177e4 LT |
60 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); |
61 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
62 | ||
386b3849 | 63 | static bool i8042_noloop; |
1da177e4 LT |
64 | module_param_named(noloop, i8042_noloop, bool, 0); |
65 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
66 | ||
f8313ef1 JK |
67 | static bool i8042_notimeout; |
68 | module_param_named(notimeout, i8042_notimeout, bool, 0); | |
69 | MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); | |
70 | ||
148e9a71 SV |
71 | static bool i8042_kbdreset; |
72 | module_param_named(kbdreset, i8042_kbdreset, bool, 0); | |
73 | MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); | |
74 | ||
8987fec0 | 75 | #ifdef CONFIG_X86 |
386b3849 | 76 | static bool i8042_dritek; |
8987fec0 CC |
77 | module_param_named(dritek, i8042_dritek, bool, 0); |
78 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
79 | #endif | |
80 | ||
1da177e4 | 81 | #ifdef CONFIG_PNP |
386b3849 | 82 | static bool i8042_nopnp; |
1da177e4 LT |
83 | module_param_named(nopnp, i8042_nopnp, bool, 0); |
84 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
85 | #endif | |
86 | ||
87 | #define DEBUG | |
88 | #ifdef DEBUG | |
386b3849 | 89 | static bool i8042_debug; |
1da177e4 LT |
90 | module_param_named(debug, i8042_debug, bool, 0600); |
91 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
e1443d28 SCP |
92 | |
93 | static bool i8042_unmask_kbd_data; | |
94 | module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); | |
95 | MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); | |
1da177e4 LT |
96 | #endif |
97 | ||
1c7827ae | 98 | static bool i8042_bypass_aux_irq_test; |
a7c5868c HG |
99 | static char i8042_kbd_firmware_id[128]; |
100 | static char i8042_aux_firmware_id[128]; | |
1c7827ae | 101 | |
1da177e4 LT |
102 | #include "i8042.h" |
103 | ||
181d683d DT |
104 | /* |
105 | * i8042_lock protects serialization between i8042_command and | |
106 | * the interrupt handler. | |
107 | */ | |
1da177e4 LT |
108 | static DEFINE_SPINLOCK(i8042_lock); |
109 | ||
181d683d DT |
110 | /* |
111 | * Writers to AUX and KBD ports as well as users issuing i8042_command | |
112 | * directly should acquire i8042_mutex (by means of calling | |
113 | * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that | |
114 | * they do not disturb each other (unfortunately in many i8042 | |
115 | * implementations write to one of the ports will immediately abort | |
116 | * command that is being processed by another port). | |
117 | */ | |
118 | static DEFINE_MUTEX(i8042_mutex); | |
119 | ||
1da177e4 LT |
120 | struct i8042_port { |
121 | struct serio *serio; | |
122 | int irq; | |
386b3849 | 123 | bool exists; |
e1443d28 | 124 | bool driver_bound; |
1da177e4 | 125 | signed char mux; |
1da177e4 LT |
126 | }; |
127 | ||
128 | #define I8042_KBD_PORT_NO 0 | |
129 | #define I8042_AUX_PORT_NO 1 | |
130 | #define I8042_MUX_PORT_NO 2 | |
131 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
132 | |
133 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
134 | |
135 | static unsigned char i8042_initial_ctr; | |
136 | static unsigned char i8042_ctr; | |
386b3849 DT |
137 | static bool i8042_mux_present; |
138 | static bool i8042_kbd_irq_registered; | |
139 | static bool i8042_aux_irq_registered; | |
817e6ba3 | 140 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 | 141 | static struct platform_device *i8042_platform_device; |
e1443d28 | 142 | static struct notifier_block i8042_kbd_bind_notifier_block; |
1da177e4 | 143 | |
7d12e780 | 144 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
967c9ef9 MG |
145 | static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, |
146 | struct serio *serio); | |
1da177e4 | 147 | |
181d683d DT |
148 | void i8042_lock_chip(void) |
149 | { | |
150 | mutex_lock(&i8042_mutex); | |
151 | } | |
152 | EXPORT_SYMBOL(i8042_lock_chip); | |
153 | ||
154 | void i8042_unlock_chip(void) | |
155 | { | |
156 | mutex_unlock(&i8042_mutex); | |
157 | } | |
158 | EXPORT_SYMBOL(i8042_unlock_chip); | |
159 | ||
967c9ef9 MG |
160 | int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, |
161 | struct serio *serio)) | |
162 | { | |
163 | unsigned long flags; | |
164 | int ret = 0; | |
165 | ||
166 | spin_lock_irqsave(&i8042_lock, flags); | |
167 | ||
168 | if (i8042_platform_filter) { | |
169 | ret = -EBUSY; | |
170 | goto out; | |
171 | } | |
172 | ||
173 | i8042_platform_filter = filter; | |
174 | ||
175 | out: | |
176 | spin_unlock_irqrestore(&i8042_lock, flags); | |
177 | return ret; | |
178 | } | |
179 | EXPORT_SYMBOL(i8042_install_filter); | |
180 | ||
181 | int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, | |
182 | struct serio *port)) | |
183 | { | |
184 | unsigned long flags; | |
185 | int ret = 0; | |
186 | ||
187 | spin_lock_irqsave(&i8042_lock, flags); | |
188 | ||
189 | if (i8042_platform_filter != filter) { | |
190 | ret = -EINVAL; | |
191 | goto out; | |
192 | } | |
193 | ||
194 | i8042_platform_filter = NULL; | |
195 | ||
196 | out: | |
197 | spin_unlock_irqrestore(&i8042_lock, flags); | |
198 | return ret; | |
199 | } | |
200 | EXPORT_SYMBOL(i8042_remove_filter); | |
201 | ||
1da177e4 LT |
202 | /* |
203 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
204 | * be ready for reading values from it / writing values to it. | |
205 | * Called always with i8042_lock held. | |
206 | */ | |
207 | ||
208 | static int i8042_wait_read(void) | |
209 | { | |
210 | int i = 0; | |
de9ce703 | 211 | |
1da177e4 LT |
212 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
213 | udelay(50); | |
214 | i++; | |
215 | } | |
216 | return -(i == I8042_CTL_TIMEOUT); | |
217 | } | |
218 | ||
219 | static int i8042_wait_write(void) | |
220 | { | |
221 | int i = 0; | |
de9ce703 | 222 | |
1da177e4 LT |
223 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
224 | udelay(50); | |
225 | i++; | |
226 | } | |
227 | return -(i == I8042_CTL_TIMEOUT); | |
228 | } | |
229 | ||
230 | /* | |
231 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
232 | * of the i8042 down the toilet. | |
233 | */ | |
234 | ||
235 | static int i8042_flush(void) | |
236 | { | |
237 | unsigned long flags; | |
238 | unsigned char data, str; | |
2f0d2604 AM |
239 | int count = 0; |
240 | int retval = 0; | |
1da177e4 LT |
241 | |
242 | spin_lock_irqsave(&i8042_lock, flags); | |
243 | ||
2f0d2604 AM |
244 | while ((str = i8042_read_status()) & I8042_STR_OBF) { |
245 | if (count++ < I8042_BUFFER_SIZE) { | |
246 | udelay(50); | |
247 | data = i8042_read_data(); | |
248 | dbg("%02x <- i8042 (flush, %s)\n", | |
249 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
250 | } else { | |
251 | retval = -EIO; | |
252 | break; | |
253 | } | |
1da177e4 LT |
254 | } |
255 | ||
256 | spin_unlock_irqrestore(&i8042_lock, flags); | |
257 | ||
2f0d2604 | 258 | return retval; |
1da177e4 LT |
259 | } |
260 | ||
261 | /* | |
262 | * i8042_command() executes a command on the i8042. It also sends the input | |
263 | * parameter(s) of the commands to it, and receives the output value(s). The | |
264 | * parameters are to be stored in the param array, and the output is placed | |
265 | * into the same array. The number of the parameters and output values is | |
266 | * encoded in bits 8-11 of the command number. | |
267 | */ | |
268 | ||
de9ce703 | 269 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 270 | { |
de9ce703 | 271 | int i, error; |
1da177e4 LT |
272 | |
273 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
274 | return -1; | |
275 | ||
de9ce703 DT |
276 | error = i8042_wait_write(); |
277 | if (error) | |
278 | return error; | |
463a4f76 | 279 | |
4eb3c30b | 280 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
463a4f76 DT |
281 | i8042_write_command(command & 0xff); |
282 | ||
283 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 DT |
284 | error = i8042_wait_write(); |
285 | if (error) | |
286 | return error; | |
4eb3c30b | 287 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
463a4f76 | 288 | i8042_write_data(param[i]); |
1da177e4 LT |
289 | } |
290 | ||
463a4f76 | 291 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
292 | error = i8042_wait_read(); |
293 | if (error) { | |
4eb3c30b | 294 | dbg(" -- i8042 (timeout)\n"); |
de9ce703 DT |
295 | return error; |
296 | } | |
1da177e4 | 297 | |
463a4f76 DT |
298 | if (command == I8042_CMD_AUX_LOOP && |
299 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
4eb3c30b | 300 | dbg(" -- i8042 (auxerr)\n"); |
de9ce703 | 301 | return -1; |
1da177e4 LT |
302 | } |
303 | ||
463a4f76 | 304 | param[i] = i8042_read_data(); |
4eb3c30b | 305 | dbg("%02x <- i8042 (return)\n", param[i]); |
463a4f76 | 306 | } |
1da177e4 | 307 | |
de9ce703 DT |
308 | return 0; |
309 | } | |
1da177e4 | 310 | |
553a05b8 | 311 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
312 | { |
313 | unsigned long flags; | |
314 | int retval; | |
315 | ||
316 | spin_lock_irqsave(&i8042_lock, flags); | |
317 | retval = __i8042_command(param, command); | |
463a4f76 | 318 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 319 | |
1da177e4 LT |
320 | return retval; |
321 | } | |
553a05b8 | 322 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
323 | |
324 | /* | |
325 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
326 | */ | |
327 | ||
328 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
329 | { | |
330 | unsigned long flags; | |
331 | int retval = 0; | |
332 | ||
333 | spin_lock_irqsave(&i8042_lock, flags); | |
334 | ||
de9ce703 | 335 | if (!(retval = i8042_wait_write())) { |
4eb3c30b | 336 | dbg("%02x -> i8042 (kbd-data)\n", c); |
1da177e4 LT |
337 | i8042_write_data(c); |
338 | } | |
339 | ||
340 | spin_unlock_irqrestore(&i8042_lock, flags); | |
341 | ||
342 | return retval; | |
343 | } | |
344 | ||
345 | /* | |
346 | * i8042_aux_write() sends a byte out through the aux interface. | |
347 | */ | |
348 | ||
349 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
350 | { | |
351 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 352 | |
f4e3c711 DT |
353 | return i8042_command(&c, port->mux == -1 ? |
354 | I8042_CMD_AUX_SEND : | |
355 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
356 | } |
357 | ||
5ddbc77c DT |
358 | |
359 | /* | |
360 | * i8042_aux_close attempts to clear AUX or KBD port state by disabling | |
361 | * and then re-enabling it. | |
362 | */ | |
363 | ||
364 | static void i8042_port_close(struct serio *serio) | |
365 | { | |
366 | int irq_bit; | |
367 | int disable_bit; | |
368 | const char *port_name; | |
369 | ||
370 | if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { | |
371 | irq_bit = I8042_CTR_AUXINT; | |
372 | disable_bit = I8042_CTR_AUXDIS; | |
373 | port_name = "AUX"; | |
374 | } else { | |
375 | irq_bit = I8042_CTR_KBDINT; | |
376 | disable_bit = I8042_CTR_KBDDIS; | |
377 | port_name = "KBD"; | |
378 | } | |
379 | ||
380 | i8042_ctr &= ~irq_bit; | |
381 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 382 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
5ddbc77c DT |
383 | |
384 | udelay(50); | |
385 | ||
386 | i8042_ctr &= ~disable_bit; | |
387 | i8042_ctr |= irq_bit; | |
388 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 389 | pr_err("Can't reactivate %s port\n", port_name); |
5ddbc77c DT |
390 | |
391 | /* | |
392 | * See if there is any data appeared while we were messing with | |
393 | * port state. | |
394 | */ | |
395 | i8042_interrupt(0, NULL); | |
396 | } | |
397 | ||
1da177e4 LT |
398 | /* |
399 | * i8042_start() is called by serio core when port is about to finish | |
400 | * registering. It will mark port as existing so i8042_interrupt can | |
401 | * start sending data through it. | |
402 | */ | |
403 | static int i8042_start(struct serio *serio) | |
404 | { | |
405 | struct i8042_port *port = serio->port_data; | |
406 | ||
386b3849 | 407 | port->exists = true; |
1da177e4 LT |
408 | mb(); |
409 | return 0; | |
410 | } | |
411 | ||
412 | /* | |
413 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
414 | * will not try to send data to the port that is about to go away. | |
415 | * The function is called by serio core as part of unregister procedure. | |
416 | */ | |
417 | static void i8042_stop(struct serio *serio) | |
418 | { | |
419 | struct i8042_port *port = serio->port_data; | |
420 | ||
386b3849 | 421 | port->exists = false; |
a8399c51 DT |
422 | |
423 | /* | |
424 | * We synchronize with both AUX and KBD IRQs because there is | |
425 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
426 | * and vice versa. | |
427 | */ | |
428 | synchronize_irq(I8042_AUX_IRQ); | |
429 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
430 | port->serio = NULL; |
431 | } | |
432 | ||
4e8d340d DT |
433 | /* |
434 | * i8042_filter() filters out unwanted bytes from the input data stream. | |
435 | * It is called from i8042_interrupt and thus is running with interrupts | |
436 | * off and i8042_lock held. | |
437 | */ | |
967c9ef9 MG |
438 | static bool i8042_filter(unsigned char data, unsigned char str, |
439 | struct serio *serio) | |
4e8d340d DT |
440 | { |
441 | if (unlikely(i8042_suppress_kbd_ack)) { | |
442 | if ((~str & I8042_STR_AUXDATA) && | |
443 | (data == 0xfa || data == 0xfe)) { | |
444 | i8042_suppress_kbd_ack--; | |
445 | dbg("Extra keyboard ACK - filtered out\n"); | |
446 | return true; | |
447 | } | |
448 | } | |
449 | ||
967c9ef9 | 450 | if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { |
0747e3bc | 451 | dbg("Filtered out by platform filter\n"); |
967c9ef9 MG |
452 | return true; |
453 | } | |
454 | ||
4e8d340d DT |
455 | return false; |
456 | } | |
457 | ||
1da177e4 LT |
458 | /* |
459 | * i8042_interrupt() is the most important function in this driver - | |
460 | * it handles the interrupts from the i8042, and sends incoming bytes | |
461 | * to the upper layers. | |
462 | */ | |
463 | ||
7d12e780 | 464 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
465 | { |
466 | struct i8042_port *port; | |
967c9ef9 | 467 | struct serio *serio; |
1da177e4 LT |
468 | unsigned long flags; |
469 | unsigned char str, data; | |
470 | unsigned int dfl; | |
471 | unsigned int port_no; | |
4e8d340d | 472 | bool filtered; |
817e6ba3 | 473 | int ret = 1; |
1da177e4 | 474 | |
1da177e4 | 475 | spin_lock_irqsave(&i8042_lock, flags); |
4e8d340d | 476 | |
1da177e4 LT |
477 | str = i8042_read_status(); |
478 | if (unlikely(~str & I8042_STR_OBF)) { | |
479 | spin_unlock_irqrestore(&i8042_lock, flags); | |
4eb3c30b JP |
480 | if (irq) |
481 | dbg("Interrupt %d, without any data\n", irq); | |
1da177e4 LT |
482 | ret = 0; |
483 | goto out; | |
484 | } | |
4e8d340d | 485 | |
1da177e4 | 486 | data = i8042_read_data(); |
1da177e4 LT |
487 | |
488 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
489 | static unsigned long last_transmit; | |
490 | static unsigned char last_str; | |
491 | ||
492 | dfl = 0; | |
493 | if (str & I8042_STR_MUXERR) { | |
4eb3c30b JP |
494 | dbg("MUX error, status is %02x, data is %02x\n", |
495 | str, data); | |
1da177e4 LT |
496 | /* |
497 | * When MUXERR condition is signalled the data register can only contain | |
498 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
499 | * it is not always the case. Some KBCs also report 0xfc when there is |
500 | * nothing connected to the port while others sometimes get confused which | |
501 | * port the data came from and signal error leaving the data intact. They | |
502 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
503 | * to legacy mode yet, when we see one we'll add proper handling). | |
504 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
505 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
506 | * was transmitted (if transmission happened not too long ago). |
507 | */ | |
a216a4b6 DT |
508 | |
509 | switch (data) { | |
510 | default: | |
1da177e4 LT |
511 | if (time_before(jiffies, last_transmit + HZ/10)) { |
512 | str = last_str; | |
513 | break; | |
514 | } | |
515 | /* fall through - report timeout */ | |
a216a4b6 | 516 | case 0xfc: |
1da177e4 LT |
517 | case 0xfd: |
518 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
519 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
520 | } | |
521 | } | |
522 | ||
523 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
524 | last_str = str; | |
525 | last_transmit = jiffies; | |
526 | } else { | |
527 | ||
528 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
f8313ef1 | 529 | ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); |
1da177e4 LT |
530 | |
531 | port_no = (str & I8042_STR_AUXDATA) ? | |
532 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
533 | } | |
534 | ||
535 | port = &i8042_ports[port_no]; | |
967c9ef9 | 536 | serio = port->exists ? port->serio : NULL; |
1da177e4 | 537 | |
e1443d28 SCP |
538 | filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", |
539 | port_no, irq, | |
540 | dfl & SERIO_PARITY ? ", bad parity" : "", | |
541 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
1da177e4 | 542 | |
967c9ef9 | 543 | filtered = i8042_filter(data, str, serio); |
4e8d340d DT |
544 | |
545 | spin_unlock_irqrestore(&i8042_lock, flags); | |
817e6ba3 | 546 | |
4e8d340d | 547 | if (likely(port->exists && !filtered)) |
967c9ef9 | 548 | serio_interrupt(serio, data, dfl); |
1da177e4 | 549 | |
0854e52d | 550 | out: |
1da177e4 LT |
551 | return IRQ_RETVAL(ret); |
552 | } | |
553 | ||
de9ce703 | 554 | /* |
5ddbc77c | 555 | * i8042_enable_kbd_port enables keyboard port on chip |
de9ce703 DT |
556 | */ |
557 | ||
558 | static int i8042_enable_kbd_port(void) | |
559 | { | |
560 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
561 | i8042_ctr |= I8042_CTR_KBDINT; | |
562 | ||
563 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
564 | i8042_ctr &= ~I8042_CTR_KBDINT; |
565 | i8042_ctr |= I8042_CTR_KBDDIS; | |
4eb3c30b | 566 | pr_err("Failed to enable KBD port\n"); |
de9ce703 DT |
567 | return -EIO; |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | /* | |
574 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
575 | */ | |
576 | ||
577 | static int i8042_enable_aux_port(void) | |
578 | { | |
579 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
580 | i8042_ctr |= I8042_CTR_AUXINT; | |
581 | ||
582 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
583 | i8042_ctr &= ~I8042_CTR_AUXINT; |
584 | i8042_ctr |= I8042_CTR_AUXDIS; | |
4eb3c30b | 585 | pr_err("Failed to enable AUX port\n"); |
de9ce703 DT |
586 | return -EIO; |
587 | } | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | /* | |
593 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
594 | * the controller has been switched into Multiplexed mode | |
595 | */ | |
596 | ||
597 | static int i8042_enable_mux_ports(void) | |
598 | { | |
599 | unsigned char param; | |
600 | int i; | |
601 | ||
602 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
603 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
604 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
605 | } | |
606 | ||
607 | return i8042_enable_aux_port(); | |
608 | } | |
609 | ||
1da177e4 | 610 | /* |
386b3849 DT |
611 | * i8042_set_mux_mode checks whether the controller has an |
612 | * active multiplexor and puts the chip into Multiplexed (true) | |
613 | * or Legacy (false) mode. | |
1da177e4 LT |
614 | */ |
615 | ||
386b3849 | 616 | static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) |
1da177e4 LT |
617 | { |
618 | ||
386b3849 | 619 | unsigned char param, val; |
1da177e4 LT |
620 | /* |
621 | * Get rid of bytes in the queue. | |
622 | */ | |
623 | ||
624 | i8042_flush(); | |
625 | ||
626 | /* | |
627 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 628 | * mouse interface, the last should be version. |
1da177e4 LT |
629 | */ |
630 | ||
386b3849 DT |
631 | param = val = 0xf0; |
632 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
633 | return -1; | |
634 | param = val = multiplex ? 0x56 : 0xf6; | |
635 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
1da177e4 | 636 | return -1; |
386b3849 DT |
637 | param = val = multiplex ? 0xa4 : 0xa5; |
638 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) | |
1da177e4 | 639 | return -1; |
386b3849 DT |
640 | |
641 | /* | |
642 | * Workaround for interference with USB Legacy emulation | |
643 | * that causes a v10.12 MUX to be found. | |
644 | */ | |
645 | if (param == 0xac) | |
1da177e4 LT |
646 | return -1; |
647 | ||
648 | if (mux_version) | |
463a4f76 | 649 | *mux_version = param; |
1da177e4 LT |
650 | |
651 | return 0; | |
652 | } | |
653 | ||
1da177e4 | 654 | /* |
de9ce703 DT |
655 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
656 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
657 | * LCS/Telegraphics. | |
1da177e4 LT |
658 | */ |
659 | ||
f8113416 | 660 | static int __init i8042_check_mux(void) |
1da177e4 | 661 | { |
de9ce703 DT |
662 | unsigned char mux_version; |
663 | ||
386b3849 | 664 | if (i8042_set_mux_mode(true, &mux_version)) |
de9ce703 DT |
665 | return -1; |
666 | ||
4eb3c30b | 667 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
de9ce703 | 668 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
1da177e4 | 669 | |
de9ce703 DT |
670 | /* |
671 | * Disable all muxed ports by disabling AUX. | |
672 | */ | |
1da177e4 LT |
673 | i8042_ctr |= I8042_CTR_AUXDIS; |
674 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
675 | ||
676 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 677 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
de9ce703 | 678 | return -EIO; |
1da177e4 LT |
679 | } |
680 | ||
386b3849 | 681 | i8042_mux_present = true; |
1da177e4 LT |
682 | |
683 | return 0; | |
684 | } | |
685 | ||
1da177e4 | 686 | /* |
de9ce703 | 687 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 688 | */ |
f8113416 DT |
689 | static struct completion i8042_aux_irq_delivered __initdata; |
690 | static bool i8042_irq_being_tested __initdata; | |
1da177e4 | 691 | |
f8113416 | 692 | static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 693 | { |
de9ce703 DT |
694 | unsigned long flags; |
695 | unsigned char str, data; | |
e3758b2a | 696 | int ret = 0; |
1da177e4 | 697 | |
de9ce703 DT |
698 | spin_lock_irqsave(&i8042_lock, flags); |
699 | str = i8042_read_status(); | |
700 | if (str & I8042_STR_OBF) { | |
701 | data = i8042_read_data(); | |
4eb3c30b JP |
702 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
703 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
de9ce703 DT |
704 | if (i8042_irq_being_tested && |
705 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
706 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 707 | ret = 1; |
de9ce703 DT |
708 | } |
709 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 710 | |
e3758b2a | 711 | return IRQ_RETVAL(ret); |
1da177e4 LT |
712 | } |
713 | ||
d2ada559 RS |
714 | /* |
715 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
716 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
717 | * port. | |
718 | */ | |
f8113416 | 719 | static int __init i8042_toggle_aux(bool on) |
d2ada559 RS |
720 | { |
721 | unsigned char param; | |
722 | int i; | |
723 | ||
724 | if (i8042_command(¶m, | |
725 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
726 | return -1; | |
727 | ||
728 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
729 | for (i = 0; i < 100; i++) { | |
730 | udelay(50); | |
731 | ||
732 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
733 | return -1; | |
734 | ||
735 | if (!(param & I8042_CTR_AUXDIS) == on) | |
736 | return 0; | |
737 | } | |
738 | ||
739 | return -1; | |
740 | } | |
1da177e4 LT |
741 | |
742 | /* | |
743 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
744 | * the presence of an AUX interface. | |
745 | */ | |
746 | ||
f8113416 | 747 | static int __init i8042_check_aux(void) |
1da177e4 | 748 | { |
de9ce703 | 749 | int retval = -1; |
386b3849 DT |
750 | bool irq_registered = false; |
751 | bool aux_loop_broken = false; | |
de9ce703 | 752 | unsigned long flags; |
1da177e4 | 753 | unsigned char param; |
1da177e4 LT |
754 | |
755 | /* | |
756 | * Get rid of bytes in the queue. | |
757 | */ | |
758 | ||
759 | i8042_flush(); | |
760 | ||
761 | /* | |
762 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
763 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
764 | * though it has an AUX port. | |
765 | */ | |
766 | ||
767 | param = 0x5a; | |
3ca5de6d DT |
768 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
769 | if (retval || param != 0x5a) { | |
1da177e4 LT |
770 | |
771 | /* | |
772 | * External connection test - filters out AT-soldered PS/2 i8042's | |
773 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
774 | * 0xfa - no error on some notebooks which ignore the spec | |
775 | * Because it's common for chipsets to return error on perfectly functioning | |
776 | * AUX ports, we test for this only when the LOOP command failed. | |
777 | */ | |
778 | ||
de9ce703 DT |
779 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
780 | (param && param != 0xfa && param != 0xff)) | |
781 | return -1; | |
1e4865f8 | 782 | |
3ca5de6d DT |
783 | /* |
784 | * If AUX_LOOP completed without error but returned unexpected data | |
785 | * mark it as broken | |
786 | */ | |
787 | if (!retval) | |
386b3849 | 788 | aux_loop_broken = true; |
1da177e4 LT |
789 | } |
790 | ||
791 | /* | |
792 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
793 | */ | |
794 | ||
386b3849 | 795 | if (i8042_toggle_aux(false)) { |
4eb3c30b JP |
796 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
797 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); | |
1da177e4 LT |
798 | } |
799 | ||
386b3849 | 800 | if (i8042_toggle_aux(true)) |
1da177e4 LT |
801 | return -1; |
802 | ||
148e9a71 SV |
803 | /* |
804 | * Reset keyboard (needed on some laptops to successfully detect | |
805 | * touchpad, e.g., some Gigabyte laptop models with Elantech | |
806 | * touchpads). | |
807 | */ | |
808 | if (i8042_kbdreset) { | |
809 | pr_warn("Attempting to reset device connected to KBD port\n"); | |
810 | i8042_kbd_write(NULL, (unsigned char) 0xff); | |
811 | } | |
812 | ||
1da177e4 | 813 | /* |
de9ce703 DT |
814 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
815 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
816 | */ |
817 | ||
1c7827ae | 818 | if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { |
de9ce703 DT |
819 | /* |
820 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
821 | * is working and hope we are right. | |
822 | */ | |
823 | retval = 0; | |
824 | goto out; | |
825 | } | |
1da177e4 | 826 | |
de9ce703 DT |
827 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
828 | "i8042", i8042_platform_device)) | |
829 | goto out; | |
1da177e4 | 830 | |
386b3849 | 831 | irq_registered = true; |
de9ce703 DT |
832 | |
833 | if (i8042_enable_aux_port()) | |
834 | goto out; | |
835 | ||
836 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 837 | |
de9ce703 | 838 | init_completion(&i8042_aux_irq_delivered); |
386b3849 | 839 | i8042_irq_being_tested = true; |
de9ce703 DT |
840 | |
841 | param = 0xa5; | |
842 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
843 | ||
844 | spin_unlock_irqrestore(&i8042_lock, flags); | |
845 | ||
846 | if (retval) | |
847 | goto out; | |
1da177e4 | 848 | |
de9ce703 DT |
849 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
850 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 851 | /* |
de9ce703 DT |
852 | * AUX IRQ was never delivered so we need to flush the controller to |
853 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 854 | */ |
4eb3c30b | 855 | dbg(" -- i8042 (aux irq test timeout)\n"); |
de9ce703 DT |
856 | i8042_flush(); |
857 | retval = -1; | |
858 | } | |
1da177e4 | 859 | |
de9ce703 | 860 | out: |
1da177e4 | 861 | |
de9ce703 DT |
862 | /* |
863 | * Disable the interface. | |
864 | */ | |
1da177e4 | 865 | |
de9ce703 DT |
866 | i8042_ctr |= I8042_CTR_AUXDIS; |
867 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 868 | |
de9ce703 DT |
869 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
870 | retval = -1; | |
1da177e4 | 871 | |
de9ce703 DT |
872 | if (irq_registered) |
873 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 874 | |
de9ce703 DT |
875 | return retval; |
876 | } | |
1da177e4 | 877 | |
de9ce703 | 878 | static int i8042_controller_check(void) |
1da177e4 | 879 | { |
2f0d2604 | 880 | if (i8042_flush()) { |
f5d75341 | 881 | pr_info("No controller found\n"); |
de9ce703 DT |
882 | return -ENODEV; |
883 | } | |
884 | ||
885 | return 0; | |
1da177e4 LT |
886 | } |
887 | ||
de9ce703 | 888 | static int i8042_controller_selftest(void) |
2673c836 VP |
889 | { |
890 | unsigned char param; | |
5ea2fc64 | 891 | int i = 0; |
2673c836 | 892 | |
5ea2fc64 AV |
893 | /* |
894 | * We try this 5 times; on some really fragile systems this does not | |
895 | * take the first time... | |
896 | */ | |
897 | do { | |
898 | ||
899 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
a2a94e73 | 900 | pr_err("i8042 controller selftest timeout\n"); |
5ea2fc64 AV |
901 | return -ENODEV; |
902 | } | |
903 | ||
904 | if (param == I8042_RET_CTL_TEST) | |
905 | return 0; | |
2673c836 | 906 | |
a2a94e73 PB |
907 | dbg("i8042 controller selftest: %#x != %#x\n", |
908 | param, I8042_RET_CTL_TEST); | |
5ea2fc64 AV |
909 | msleep(50); |
910 | } while (i++ < 5); | |
2673c836 | 911 | |
5ea2fc64 AV |
912 | #ifdef CONFIG_X86 |
913 | /* | |
914 | * On x86, we don't fail entire i8042 initialization if controller | |
915 | * reset fails in hopes that keyboard port will still be functional | |
916 | * and user will still get a working keyboard. This is especially | |
917 | * important on netbooks. On other arches we trust hardware more. | |
918 | */ | |
4eb3c30b | 919 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
2673c836 | 920 | return 0; |
5ea2fc64 | 921 | #else |
a2a94e73 | 922 | pr_err("i8042 controller selftest failed\n"); |
5ea2fc64 AV |
923 | return -EIO; |
924 | #endif | |
2673c836 | 925 | } |
1da177e4 LT |
926 | |
927 | /* | |
928 | * i8042_controller init initializes the i8042 controller, and, | |
929 | * most importantly, sets it into non-xlated mode if that's | |
930 | * desired. | |
931 | */ | |
932 | ||
933 | static int i8042_controller_init(void) | |
934 | { | |
935 | unsigned long flags; | |
ee1e82ce DT |
936 | int n = 0; |
937 | unsigned char ctr[2]; | |
1da177e4 | 938 | |
1da177e4 | 939 | /* |
ee1e82ce | 940 | * Save the CTR for restore on unload / reboot. |
1da177e4 LT |
941 | */ |
942 | ||
ee1e82ce DT |
943 | do { |
944 | if (n >= 10) { | |
4eb3c30b | 945 | pr_err("Unable to get stable CTR read\n"); |
ee1e82ce DT |
946 | return -EIO; |
947 | } | |
948 | ||
949 | if (n != 0) | |
950 | udelay(50); | |
951 | ||
952 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | |
4eb3c30b | 953 | pr_err("Can't read CTR while initializing i8042\n"); |
ee1e82ce DT |
954 | return -EIO; |
955 | } | |
956 | ||
957 | } while (n < 2 || ctr[0] != ctr[1]); | |
1da177e4 | 958 | |
ee1e82ce | 959 | i8042_initial_ctr = i8042_ctr = ctr[0]; |
1da177e4 LT |
960 | |
961 | /* | |
962 | * Disable the keyboard interface and interrupt. | |
963 | */ | |
964 | ||
965 | i8042_ctr |= I8042_CTR_KBDDIS; | |
966 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
967 | ||
968 | /* | |
969 | * Handle keylock. | |
970 | */ | |
971 | ||
972 | spin_lock_irqsave(&i8042_lock, flags); | |
973 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
974 | if (i8042_unlock) | |
975 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 976 | else |
4eb3c30b | 977 | pr_warn("Warning: Keylock active\n"); |
1da177e4 LT |
978 | } |
979 | spin_unlock_irqrestore(&i8042_lock, flags); | |
980 | ||
981 | /* | |
982 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
983 | * bother enabling translating and be happy. | |
984 | */ | |
985 | ||
986 | if (~i8042_ctr & I8042_CTR_XLATE) | |
386b3849 | 987 | i8042_direct = true; |
1da177e4 LT |
988 | |
989 | /* | |
990 | * Set nontranslated mode for the kbd interface if requested by an option. | |
991 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
992 | * interface is. We don't do this by default, since it can confuse notebook | |
993 | * BIOSes. | |
994 | */ | |
995 | ||
996 | if (i8042_direct) | |
997 | i8042_ctr &= ~I8042_CTR_XLATE; | |
998 | ||
999 | /* | |
1000 | * Write CTR back. | |
1001 | */ | |
1002 | ||
1003 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1004 | pr_err("Can't write CTR while initializing i8042\n"); |
de9ce703 | 1005 | return -EIO; |
1da177e4 LT |
1006 | } |
1007 | ||
ee1e82ce DT |
1008 | /* |
1009 | * Flush whatever accumulated while we were disabling keyboard port. | |
1010 | */ | |
1011 | ||
1012 | i8042_flush(); | |
1013 | ||
1da177e4 LT |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | ||
1018 | /* | |
de9ce703 | 1019 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 1020 | */ |
de9ce703 | 1021 | |
1729ad1f | 1022 | static void i8042_controller_reset(bool force_reset) |
1da177e4 | 1023 | { |
de9ce703 | 1024 | i8042_flush(); |
1da177e4 | 1025 | |
8d04ddb6 DT |
1026 | /* |
1027 | * Disable both KBD and AUX interfaces so they don't get in the way | |
1028 | */ | |
1029 | ||
1030 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
1031 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
1032 | ||
ee1e82ce | 1033 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
4eb3c30b | 1034 | pr_warn("Can't write CTR while resetting\n"); |
5ddbc77c | 1035 | |
1da177e4 LT |
1036 | /* |
1037 | * Disable MUX mode if present. | |
1038 | */ | |
1039 | ||
1040 | if (i8042_mux_present) | |
386b3849 | 1041 | i8042_set_mux_mode(false, NULL); |
1da177e4 LT |
1042 | |
1043 | /* | |
de9ce703 | 1044 | * Reset the controller if requested. |
1da177e4 LT |
1045 | */ |
1046 | ||
1729ad1f | 1047 | if (i8042_reset || force_reset) |
1ca56e51 | 1048 | i8042_controller_selftest(); |
1da177e4 | 1049 | |
de9ce703 DT |
1050 | /* |
1051 | * Restore the original control register setting. | |
1052 | */ | |
1053 | ||
1054 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 1055 | pr_warn("Can't restore CTR\n"); |
1da177e4 LT |
1056 | } |
1057 | ||
1058 | ||
1da177e4 | 1059 | /* |
c7ff0d9c TS |
1060 | * i8042_panic_blink() will turn the keyboard LEDs on or off and is called |
1061 | * when kernel panics. Flashing LEDs is useful for users running X who may | |
aa5e5dc2 | 1062 | * not see the console and will help distinguishing panics from "real" |
1da177e4 LT |
1063 | * lockups. |
1064 | * | |
1065 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
1066 | * waiting for KBC to free up even if KBD interrupt is off | |
1067 | */ | |
1068 | ||
1069 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
1070 | ||
c7ff0d9c | 1071 | static long i8042_panic_blink(int state) |
1da177e4 LT |
1072 | { |
1073 | long delay = 0; | |
c7ff0d9c | 1074 | char led; |
1da177e4 | 1075 | |
c7ff0d9c | 1076 | led = (state) ? 0x01 | 0x04 : 0; |
1da177e4 LT |
1077 | while (i8042_read_status() & I8042_STR_IBF) |
1078 | DELAY; | |
4eb3c30b | 1079 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
19f3c3e3 | 1080 | i8042_suppress_kbd_ack = 2; |
1da177e4 LT |
1081 | i8042_write_data(0xed); /* set leds */ |
1082 | DELAY; | |
1083 | while (i8042_read_status() & I8042_STR_IBF) | |
1084 | DELAY; | |
1085 | DELAY; | |
4eb3c30b | 1086 | dbg("%02x -> i8042 (panic blink)\n", led); |
1da177e4 LT |
1087 | i8042_write_data(led); |
1088 | DELAY; | |
1da177e4 LT |
1089 | return delay; |
1090 | } | |
1091 | ||
1092 | #undef DELAY | |
1093 | ||
d35895db BP |
1094 | #ifdef CONFIG_X86 |
1095 | static void i8042_dritek_enable(void) | |
1096 | { | |
594d6363 | 1097 | unsigned char param = 0x90; |
d35895db BP |
1098 | int error; |
1099 | ||
1100 | error = i8042_command(¶m, 0x1059); | |
1101 | if (error) | |
4eb3c30b | 1102 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
d35895db BP |
1103 | } |
1104 | #endif | |
1105 | ||
82dd9eff | 1106 | #ifdef CONFIG_PM |
7e044e05 | 1107 | |
1da177e4 | 1108 | /* |
ebd7768d DT |
1109 | * Here we try to reset everything back to a state we had |
1110 | * before suspending. | |
1da177e4 LT |
1111 | */ |
1112 | ||
1ca56e51 | 1113 | static int i8042_controller_resume(bool force_reset) |
1da177e4 | 1114 | { |
de9ce703 | 1115 | int error; |
1da177e4 | 1116 | |
de9ce703 DT |
1117 | error = i8042_controller_check(); |
1118 | if (error) | |
1119 | return error; | |
2673c836 | 1120 | |
1ca56e51 DT |
1121 | if (i8042_reset || force_reset) { |
1122 | error = i8042_controller_selftest(); | |
1123 | if (error) | |
1124 | return error; | |
1125 | } | |
1da177e4 LT |
1126 | |
1127 | /* | |
82dd9eff | 1128 | * Restore original CTR value and disable all ports |
1da177e4 LT |
1129 | */ |
1130 | ||
82dd9eff DT |
1131 | i8042_ctr = i8042_initial_ctr; |
1132 | if (i8042_direct) | |
1133 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
1134 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1135 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
1136 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1137 | pr_warn("Can't write CTR to resume, retrying...\n"); |
2f6a77d5 JK |
1138 | msleep(50); |
1139 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1140 | pr_err("CTR write retry failed\n"); |
2f6a77d5 JK |
1141 | return -EIO; |
1142 | } | |
de9ce703 | 1143 | } |
1da177e4 | 1144 | |
d35895db BP |
1145 | |
1146 | #ifdef CONFIG_X86 | |
1147 | if (i8042_dritek) | |
1148 | i8042_dritek_enable(); | |
1149 | #endif | |
1150 | ||
de9ce703 | 1151 | if (i8042_mux_present) { |
386b3849 | 1152 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
4eb3c30b | 1153 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
de9ce703 DT |
1154 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
1155 | i8042_enable_aux_port(); | |
1da177e4 | 1156 | |
de9ce703 DT |
1157 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
1158 | i8042_enable_kbd_port(); | |
1159 | ||
7d12e780 | 1160 | i8042_interrupt(0, NULL); |
1da177e4 LT |
1161 | |
1162 | return 0; | |
1da177e4 | 1163 | } |
ebd7768d | 1164 | |
1ca56e51 DT |
1165 | /* |
1166 | * Here we try to restore the original BIOS settings to avoid | |
1167 | * upsetting it. | |
1168 | */ | |
1169 | ||
1729ad1f | 1170 | static int i8042_pm_suspend(struct device *dev) |
1ca56e51 | 1171 | { |
f13b2065 RW |
1172 | int i; |
1173 | ||
1c5dd134 RW |
1174 | if (pm_suspend_via_firmware()) |
1175 | i8042_controller_reset(true); | |
1ca56e51 | 1176 | |
f13b2065 RW |
1177 | /* Set up serio interrupts for system wakeup. */ |
1178 | for (i = 0; i < I8042_NUM_PORTS; i++) { | |
1179 | struct serio *serio = i8042_ports[i].serio; | |
1180 | ||
1181 | if (serio && device_may_wakeup(&serio->dev)) | |
1182 | enable_irq_wake(i8042_ports[i].irq); | |
1183 | } | |
1184 | ||
1ca56e51 DT |
1185 | return 0; |
1186 | } | |
1187 | ||
1c5dd134 RW |
1188 | static int i8042_pm_resume_noirq(struct device *dev) |
1189 | { | |
1190 | if (!pm_resume_via_firmware()) | |
1191 | i8042_interrupt(0, NULL); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
1ca56e51 DT |
1196 | static int i8042_pm_resume(struct device *dev) |
1197 | { | |
1c5dd134 | 1198 | bool force_reset; |
f13b2065 RW |
1199 | int i; |
1200 | ||
1201 | for (i = 0; i < I8042_NUM_PORTS; i++) { | |
1202 | struct serio *serio = i8042_ports[i].serio; | |
1203 | ||
1204 | if (serio && device_may_wakeup(&serio->dev)) | |
1205 | disable_irq_wake(i8042_ports[i].irq); | |
1206 | } | |
1207 | ||
1ca56e51 | 1208 | /* |
1c5dd134 RW |
1209 | * If platform firmware was not going to be involved in suspend, we did |
1210 | * not restore the controller state to whatever it had been at boot | |
1211 | * time, so we do not need to do anything. | |
1ca56e51 | 1212 | */ |
1c5dd134 RW |
1213 | if (!pm_suspend_via_firmware()) |
1214 | return 0; | |
1215 | ||
1216 | /* | |
1217 | * We only need to reset the controller if we are resuming after handing | |
1218 | * off control to the platform firmware, otherwise we can simply restore | |
1219 | * the mode. | |
1220 | */ | |
1221 | force_reset = pm_resume_via_firmware(); | |
1222 | ||
1223 | return i8042_controller_resume(force_reset); | |
1ca56e51 DT |
1224 | } |
1225 | ||
c2d1a2a1 AJ |
1226 | static int i8042_pm_thaw(struct device *dev) |
1227 | { | |
1228 | i8042_interrupt(0, NULL); | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1729ad1f DT |
1233 | static int i8042_pm_reset(struct device *dev) |
1234 | { | |
1235 | i8042_controller_reset(false); | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1ca56e51 DT |
1240 | static int i8042_pm_restore(struct device *dev) |
1241 | { | |
1242 | return i8042_controller_resume(false); | |
1243 | } | |
1244 | ||
ebd7768d | 1245 | static const struct dev_pm_ops i8042_pm_ops = { |
1729ad1f | 1246 | .suspend = i8042_pm_suspend, |
1c5dd134 | 1247 | .resume_noirq = i8042_pm_resume_noirq, |
1ca56e51 | 1248 | .resume = i8042_pm_resume, |
c2d1a2a1 | 1249 | .thaw = i8042_pm_thaw, |
ebd7768d DT |
1250 | .poweroff = i8042_pm_reset, |
1251 | .restore = i8042_pm_restore, | |
1252 | }; | |
1253 | ||
82dd9eff | 1254 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1255 | |
1256 | /* | |
1257 | * We need to reset the 8042 back to original mode on system shutdown, | |
1258 | * because otherwise BIOSes will be confused. | |
1259 | */ | |
1260 | ||
3ae5eaec | 1261 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 1262 | { |
1729ad1f | 1263 | i8042_controller_reset(false); |
1da177e4 LT |
1264 | } |
1265 | ||
f8113416 | 1266 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
1267 | { |
1268 | struct serio *serio; | |
1269 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1270 | ||
d39969de | 1271 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1272 | if (!serio) |
1273 | return -ENOMEM; | |
1274 | ||
1275 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1276 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1277 | serio->start = i8042_start; |
1278 | serio->stop = i8042_stop; | |
5ddbc77c | 1279 | serio->close = i8042_port_close; |
0854e52d DT |
1280 | serio->port_data = port; |
1281 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1282 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d | 1283 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
a7c5868c HG |
1284 | strlcpy(serio->firmware_id, i8042_kbd_firmware_id, |
1285 | sizeof(serio->firmware_id)); | |
0854e52d DT |
1286 | |
1287 | port->serio = serio; | |
de9ce703 | 1288 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1289 | |
de9ce703 | 1290 | return 0; |
1da177e4 LT |
1291 | } |
1292 | ||
f8113416 | 1293 | static int __init i8042_create_aux_port(int idx) |
1da177e4 LT |
1294 | { |
1295 | struct serio *serio; | |
de9ce703 DT |
1296 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1297 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1298 | |
d39969de | 1299 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1300 | if (!serio) |
1301 | return -ENOMEM; | |
1302 | ||
1303 | serio->id.type = SERIO_8042; | |
1304 | serio->write = i8042_aux_write; | |
0854e52d DT |
1305 | serio->start = i8042_start; |
1306 | serio->stop = i8042_stop; | |
1307 | serio->port_data = port; | |
1308 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1309 | if (idx < 0) { |
1310 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1311 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
a7c5868c HG |
1312 | strlcpy(serio->firmware_id, i8042_aux_firmware_id, |
1313 | sizeof(serio->firmware_id)); | |
5ddbc77c | 1314 | serio->close = i8042_port_close; |
de9ce703 DT |
1315 | } else { |
1316 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1317 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
266e43c4 HG |
1318 | strlcpy(serio->firmware_id, i8042_aux_firmware_id, |
1319 | sizeof(serio->firmware_id)); | |
de9ce703 | 1320 | } |
0854e52d DT |
1321 | |
1322 | port->serio = serio; | |
de9ce703 DT |
1323 | port->mux = idx; |
1324 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1325 | |
de9ce703 | 1326 | return 0; |
1da177e4 LT |
1327 | } |
1328 | ||
f8113416 | 1329 | static void __init i8042_free_kbd_port(void) |
1da177e4 | 1330 | { |
de9ce703 DT |
1331 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1332 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1333 | } | |
1da177e4 | 1334 | |
f8113416 | 1335 | static void __init i8042_free_aux_ports(void) |
de9ce703 DT |
1336 | { |
1337 | int i; | |
0854e52d | 1338 | |
de9ce703 DT |
1339 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1340 | kfree(i8042_ports[i].serio); | |
1341 | i8042_ports[i].serio = NULL; | |
1342 | } | |
1343 | } | |
0854e52d | 1344 | |
f8113416 | 1345 | static void __init i8042_register_ports(void) |
de9ce703 DT |
1346 | { |
1347 | int i; | |
0854e52d | 1348 | |
de9ce703 | 1349 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
f13b2065 RW |
1350 | struct serio *serio = i8042_ports[i].serio; |
1351 | ||
1352 | if (serio) { | |
de9ce703 | 1353 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", |
f13b2065 | 1354 | serio->name, |
de9ce703 DT |
1355 | (unsigned long) I8042_DATA_REG, |
1356 | (unsigned long) I8042_COMMAND_REG, | |
1357 | i8042_ports[i].irq); | |
f13b2065 RW |
1358 | serio_register_port(serio); |
1359 | device_set_wakeup_capable(&serio->dev, true); | |
de9ce703 DT |
1360 | } |
1361 | } | |
1da177e4 LT |
1362 | } |
1363 | ||
e2619cf7 | 1364 | static void i8042_unregister_ports(void) |
1da177e4 | 1365 | { |
de9ce703 | 1366 | int i; |
1da177e4 | 1367 | |
de9ce703 DT |
1368 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1369 | if (i8042_ports[i].serio) { | |
1370 | serio_unregister_port(i8042_ports[i].serio); | |
1371 | i8042_ports[i].serio = NULL; | |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | ||
181d683d DT |
1376 | /* |
1377 | * Checks whether port belongs to i8042 controller. | |
1378 | */ | |
1379 | bool i8042_check_port_owner(const struct serio *port) | |
1380 | { | |
1381 | int i; | |
1382 | ||
1383 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1384 | if (i8042_ports[i].serio == port) | |
1385 | return true; | |
1386 | ||
1387 | return false; | |
1388 | } | |
1389 | EXPORT_SYMBOL(i8042_check_port_owner); | |
1390 | ||
de9ce703 DT |
1391 | static void i8042_free_irqs(void) |
1392 | { | |
1393 | if (i8042_aux_irq_registered) | |
1394 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1395 | if (i8042_kbd_irq_registered) | |
1396 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1397 | ||
386b3849 | 1398 | i8042_aux_irq_registered = i8042_kbd_irq_registered = false; |
de9ce703 DT |
1399 | } |
1400 | ||
f8113416 | 1401 | static int __init i8042_setup_aux(void) |
de9ce703 DT |
1402 | { |
1403 | int (*aux_enable)(void); | |
1404 | int error; | |
1405 | int i; | |
1da177e4 | 1406 | |
de9ce703 | 1407 | if (i8042_check_aux()) |
87fd6318 | 1408 | return -ENODEV; |
1da177e4 | 1409 | |
de9ce703 DT |
1410 | if (i8042_nomux || i8042_check_mux()) { |
1411 | error = i8042_create_aux_port(-1); | |
1412 | if (error) | |
1413 | goto err_free_ports; | |
1414 | aux_enable = i8042_enable_aux_port; | |
1415 | } else { | |
1416 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1417 | error = i8042_create_aux_port(i); | |
1418 | if (error) | |
1419 | goto err_free_ports; | |
0854e52d | 1420 | } |
de9ce703 | 1421 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1422 | } |
1423 | ||
de9ce703 DT |
1424 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1425 | "i8042", i8042_platform_device); | |
1426 | if (error) | |
1427 | goto err_free_ports; | |
945ef0d4 | 1428 | |
de9ce703 DT |
1429 | if (aux_enable()) |
1430 | goto err_free_irq; | |
1da177e4 | 1431 | |
386b3849 | 1432 | i8042_aux_irq_registered = true; |
1da177e4 | 1433 | return 0; |
0854e52d | 1434 | |
de9ce703 DT |
1435 | err_free_irq: |
1436 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1437 | err_free_ports: | |
1438 | i8042_free_aux_ports(); | |
1439 | return error; | |
1440 | } | |
0854e52d | 1441 | |
f8113416 | 1442 | static int __init i8042_setup_kbd(void) |
de9ce703 DT |
1443 | { |
1444 | int error; | |
1445 | ||
1446 | error = i8042_create_kbd_port(); | |
1447 | if (error) | |
1448 | return error; | |
1449 | ||
1450 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1451 | "i8042", i8042_platform_device); | |
1452 | if (error) | |
1453 | goto err_free_port; | |
1454 | ||
1455 | error = i8042_enable_kbd_port(); | |
1456 | if (error) | |
1457 | goto err_free_irq; | |
1458 | ||
386b3849 | 1459 | i8042_kbd_irq_registered = true; |
de9ce703 DT |
1460 | return 0; |
1461 | ||
1462 | err_free_irq: | |
1463 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1464 | err_free_port: | |
1465 | i8042_free_kbd_port(); | |
1466 | return error; | |
1da177e4 LT |
1467 | } |
1468 | ||
e1443d28 SCP |
1469 | static int i8042_kbd_bind_notifier(struct notifier_block *nb, |
1470 | unsigned long action, void *data) | |
1471 | { | |
1472 | struct device *dev = data; | |
1473 | struct serio *serio = to_serio_port(dev); | |
1474 | struct i8042_port *port = serio->port_data; | |
1475 | ||
1476 | if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) | |
1477 | return 0; | |
1478 | ||
1479 | switch (action) { | |
1480 | case BUS_NOTIFY_BOUND_DRIVER: | |
1481 | port->driver_bound = true; | |
1482 | break; | |
1483 | ||
1484 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1485 | port->driver_bound = false; | |
1486 | break; | |
1487 | } | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
f8113416 | 1492 | static int __init i8042_probe(struct platform_device *dev) |
1da177e4 | 1493 | { |
de9ce703 | 1494 | int error; |
1da177e4 | 1495 | |
ec62e1c8 DT |
1496 | i8042_platform_device = dev; |
1497 | ||
1ca56e51 DT |
1498 | if (i8042_reset) { |
1499 | error = i8042_controller_selftest(); | |
1500 | if (error) | |
1501 | return error; | |
1502 | } | |
1da177e4 | 1503 | |
de9ce703 DT |
1504 | error = i8042_controller_init(); |
1505 | if (error) | |
1506 | return error; | |
1507 | ||
d35895db BP |
1508 | #ifdef CONFIG_X86 |
1509 | if (i8042_dritek) | |
1510 | i8042_dritek_enable(); | |
1511 | #endif | |
1512 | ||
de9ce703 DT |
1513 | if (!i8042_noaux) { |
1514 | error = i8042_setup_aux(); | |
1515 | if (error && error != -ENODEV && error != -EBUSY) | |
1516 | goto out_fail; | |
1517 | } | |
1518 | ||
1519 | if (!i8042_nokbd) { | |
1520 | error = i8042_setup_kbd(); | |
1521 | if (error) | |
1522 | goto out_fail; | |
1523 | } | |
de9ce703 DT |
1524 | /* |
1525 | * Ok, everything is ready, let's register all serio ports | |
1526 | */ | |
1527 | i8042_register_ports(); | |
1528 | ||
1529 | return 0; | |
1530 | ||
1531 | out_fail: | |
1532 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1533 | i8042_free_irqs(); | |
1729ad1f | 1534 | i8042_controller_reset(false); |
ec62e1c8 | 1535 | i8042_platform_device = NULL; |
de9ce703 DT |
1536 | |
1537 | return error; | |
1538 | } | |
1539 | ||
e2619cf7 | 1540 | static int i8042_remove(struct platform_device *dev) |
de9ce703 DT |
1541 | { |
1542 | i8042_unregister_ports(); | |
1543 | i8042_free_irqs(); | |
1729ad1f | 1544 | i8042_controller_reset(false); |
ec62e1c8 | 1545 | i8042_platform_device = NULL; |
1da177e4 | 1546 | |
87fd6318 DT |
1547 | return 0; |
1548 | } | |
1549 | ||
1550 | static struct platform_driver i8042_driver = { | |
1551 | .driver = { | |
1552 | .name = "i8042", | |
ebd7768d DT |
1553 | #ifdef CONFIG_PM |
1554 | .pm = &i8042_pm_ops, | |
1555 | #endif | |
87fd6318 | 1556 | }, |
1cb0aa88 | 1557 | .remove = i8042_remove, |
82dd9eff | 1558 | .shutdown = i8042_shutdown, |
87fd6318 DT |
1559 | }; |
1560 | ||
e1443d28 SCP |
1561 | static struct notifier_block i8042_kbd_bind_notifier_block = { |
1562 | .notifier_call = i8042_kbd_bind_notifier, | |
1563 | }; | |
1564 | ||
87fd6318 DT |
1565 | static int __init i8042_init(void) |
1566 | { | |
ec62e1c8 | 1567 | struct platform_device *pdev; |
87fd6318 DT |
1568 | int err; |
1569 | ||
1570 | dbg_init(); | |
1571 | ||
1572 | err = i8042_platform_init(); | |
1573 | if (err) | |
1574 | return err; | |
1575 | ||
de9ce703 DT |
1576 | err = i8042_controller_check(); |
1577 | if (err) | |
1578 | goto err_platform_exit; | |
87fd6318 | 1579 | |
ec62e1c8 DT |
1580 | pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); |
1581 | if (IS_ERR(pdev)) { | |
1582 | err = PTR_ERR(pdev); | |
f8113416 | 1583 | goto err_platform_exit; |
87fd6318 DT |
1584 | } |
1585 | ||
e1443d28 | 1586 | bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); |
de9ce703 DT |
1587 | panic_blink = i8042_panic_blink; |
1588 | ||
87fd6318 DT |
1589 | return 0; |
1590 | ||
87fd6318 DT |
1591 | err_platform_exit: |
1592 | i8042_platform_exit(); | |
87fd6318 DT |
1593 | return err; |
1594 | } | |
1595 | ||
1596 | static void __exit i8042_exit(void) | |
1597 | { | |
f8113416 | 1598 | platform_device_unregister(i8042_platform_device); |
af045b86 | 1599 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1600 | i8042_platform_exit(); |
1601 | ||
e1443d28 | 1602 | bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); |
1da177e4 LT |
1603 | panic_blink = NULL; |
1604 | } | |
1605 | ||
1606 | module_init(i8042_init); | |
1607 | module_exit(i8042_exit); |