Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
403f81d8 | 30 | #include <linux/amd-iommu.h> |
17f5b569 | 31 | #include <asm/msidef.h> |
b6c02715 | 32 | #include <asm/proto.h> |
46a7fa27 | 33 | #include <asm/iommu.h> |
1d9b16d1 | 34 | #include <asm/gart.h> |
27c2127a | 35 | #include <asm/dma.h> |
403f81d8 JR |
36 | |
37 | #include "amd_iommu_proto.h" | |
38 | #include "amd_iommu_types.h" | |
b6c02715 JR |
39 | |
40 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
41 | ||
815b33fd | 42 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 43 | |
b6c02715 JR |
44 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
45 | ||
bd60b735 JR |
46 | /* A list of preallocated protection domains */ |
47 | static LIST_HEAD(iommu_pd_list); | |
48 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
49 | ||
8fa5f802 JR |
50 | /* List of all available dev_data structures */ |
51 | static LIST_HEAD(dev_data_list); | |
52 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
53 | ||
0feae533 JR |
54 | /* |
55 | * Domain for untranslated devices - only allocated | |
56 | * if iommu=pt passed on kernel cmd line. | |
57 | */ | |
58 | static struct protection_domain *pt_domain; | |
59 | ||
26961efe | 60 | static struct iommu_ops amd_iommu_ops; |
26961efe | 61 | |
431b2a20 JR |
62 | /* |
63 | * general struct to manage commands send to an IOMMU | |
64 | */ | |
d6449536 | 65 | struct iommu_cmd { |
b6c02715 JR |
66 | u32 data[4]; |
67 | }; | |
68 | ||
04bfdd84 | 69 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 70 | |
15898bbc JR |
71 | /**************************************************************************** |
72 | * | |
73 | * Helper functions | |
74 | * | |
75 | ****************************************************************************/ | |
76 | ||
f62dda66 | 77 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
78 | { |
79 | struct iommu_dev_data *dev_data; | |
80 | unsigned long flags; | |
81 | ||
82 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
83 | if (!dev_data) | |
84 | return NULL; | |
85 | ||
f62dda66 | 86 | dev_data->devid = devid; |
8fa5f802 JR |
87 | atomic_set(&dev_data->bind, 0); |
88 | ||
89 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
90 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
91 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
92 | ||
93 | return dev_data; | |
94 | } | |
95 | ||
96 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
97 | { | |
98 | unsigned long flags; | |
99 | ||
100 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
101 | list_del(&dev_data->dev_data_list); | |
102 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
103 | ||
104 | kfree(dev_data); | |
105 | } | |
106 | ||
3b03bb74 JR |
107 | static struct iommu_dev_data *search_dev_data(u16 devid) |
108 | { | |
109 | struct iommu_dev_data *dev_data; | |
110 | unsigned long flags; | |
111 | ||
112 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
113 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
114 | if (dev_data->devid == devid) | |
115 | goto out_unlock; | |
116 | } | |
117 | ||
118 | dev_data = NULL; | |
119 | ||
120 | out_unlock: | |
121 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
122 | ||
123 | return dev_data; | |
124 | } | |
125 | ||
126 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
127 | { | |
128 | struct iommu_dev_data *dev_data; | |
129 | ||
130 | dev_data = search_dev_data(devid); | |
131 | ||
132 | if (dev_data == NULL) | |
133 | dev_data = alloc_dev_data(devid); | |
134 | ||
135 | return dev_data; | |
136 | } | |
137 | ||
15898bbc JR |
138 | static inline u16 get_device_id(struct device *dev) |
139 | { | |
140 | struct pci_dev *pdev = to_pci_dev(dev); | |
141 | ||
142 | return calc_devid(pdev->bus->number, pdev->devfn); | |
143 | } | |
144 | ||
657cbb6b JR |
145 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
146 | { | |
147 | return dev->archdata.iommu; | |
148 | } | |
149 | ||
71c70984 JR |
150 | /* |
151 | * In this function the list of preallocated protection domains is traversed to | |
152 | * find the domain for a specific device | |
153 | */ | |
154 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
155 | { | |
156 | struct dma_ops_domain *entry, *ret = NULL; | |
157 | unsigned long flags; | |
158 | u16 alias = amd_iommu_alias_table[devid]; | |
159 | ||
160 | if (list_empty(&iommu_pd_list)) | |
161 | return NULL; | |
162 | ||
163 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
164 | ||
165 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
166 | if (entry->target_dev == devid || | |
167 | entry->target_dev == alias) { | |
168 | ret = entry; | |
169 | break; | |
170 | } | |
171 | } | |
172 | ||
173 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
98fc5a69 JR |
178 | /* |
179 | * This function checks if the driver got a valid device from the caller to | |
180 | * avoid dereferencing invalid pointers. | |
181 | */ | |
182 | static bool check_device(struct device *dev) | |
183 | { | |
184 | u16 devid; | |
185 | ||
186 | if (!dev || !dev->dma_mask) | |
187 | return false; | |
188 | ||
189 | /* No device or no PCI device */ | |
339d3261 | 190 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
191 | return false; |
192 | ||
193 | devid = get_device_id(dev); | |
194 | ||
195 | /* Out of our scope? */ | |
196 | if (devid > amd_iommu_last_bdf) | |
197 | return false; | |
198 | ||
199 | if (amd_iommu_rlookup_table[devid] == NULL) | |
200 | return false; | |
201 | ||
202 | return true; | |
203 | } | |
204 | ||
657cbb6b JR |
205 | static int iommu_init_device(struct device *dev) |
206 | { | |
207 | struct iommu_dev_data *dev_data; | |
8fa5f802 | 208 | u16 alias; |
657cbb6b JR |
209 | |
210 | if (dev->archdata.iommu) | |
211 | return 0; | |
212 | ||
3b03bb74 | 213 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
214 | if (!dev_data) |
215 | return -ENOMEM; | |
216 | ||
f62dda66 | 217 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 218 | if (alias != dev_data->devid) { |
71f77580 | 219 | struct iommu_dev_data *alias_data; |
b00d3bcf | 220 | |
71f77580 JR |
221 | alias_data = find_dev_data(alias); |
222 | if (alias_data == NULL) { | |
223 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
224 | dev_name(dev)); | |
2b02b091 JR |
225 | free_dev_data(dev_data); |
226 | return -ENOTSUPP; | |
227 | } | |
71f77580 | 228 | dev_data->alias_data = alias_data; |
26018874 | 229 | } |
657cbb6b JR |
230 | |
231 | dev->archdata.iommu = dev_data; | |
232 | ||
657cbb6b JR |
233 | return 0; |
234 | } | |
235 | ||
26018874 JR |
236 | static void iommu_ignore_device(struct device *dev) |
237 | { | |
238 | u16 devid, alias; | |
239 | ||
240 | devid = get_device_id(dev); | |
241 | alias = amd_iommu_alias_table[devid]; | |
242 | ||
243 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
244 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
245 | ||
246 | amd_iommu_rlookup_table[devid] = NULL; | |
247 | amd_iommu_rlookup_table[alias] = NULL; | |
248 | } | |
249 | ||
657cbb6b JR |
250 | static void iommu_uninit_device(struct device *dev) |
251 | { | |
8fa5f802 JR |
252 | /* |
253 | * Nothing to do here - we keep dev_data around for unplugged devices | |
254 | * and reuse it when the device is re-plugged - not doing so would | |
255 | * introduce a ton of races. | |
256 | */ | |
657cbb6b | 257 | } |
b7cc9554 JR |
258 | |
259 | void __init amd_iommu_uninit_devices(void) | |
260 | { | |
8fa5f802 | 261 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
262 | struct pci_dev *pdev = NULL; |
263 | ||
264 | for_each_pci_dev(pdev) { | |
265 | ||
266 | if (!check_device(&pdev->dev)) | |
267 | continue; | |
268 | ||
269 | iommu_uninit_device(&pdev->dev); | |
270 | } | |
8fa5f802 JR |
271 | |
272 | /* Free all of our dev_data structures */ | |
273 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
274 | free_dev_data(dev_data); | |
b7cc9554 JR |
275 | } |
276 | ||
277 | int __init amd_iommu_init_devices(void) | |
278 | { | |
279 | struct pci_dev *pdev = NULL; | |
280 | int ret = 0; | |
281 | ||
282 | for_each_pci_dev(pdev) { | |
283 | ||
284 | if (!check_device(&pdev->dev)) | |
285 | continue; | |
286 | ||
287 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
288 | if (ret == -ENOTSUPP) |
289 | iommu_ignore_device(&pdev->dev); | |
290 | else if (ret) | |
b7cc9554 JR |
291 | goto out_free; |
292 | } | |
293 | ||
294 | return 0; | |
295 | ||
296 | out_free: | |
297 | ||
298 | amd_iommu_uninit_devices(); | |
299 | ||
300 | return ret; | |
301 | } | |
7f26508b JR |
302 | #ifdef CONFIG_AMD_IOMMU_STATS |
303 | ||
304 | /* | |
305 | * Initialization code for statistics collection | |
306 | */ | |
307 | ||
da49f6df | 308 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 309 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 310 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 311 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 312 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 313 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 314 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 315 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 316 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 317 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 318 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 319 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 320 | |
7f26508b | 321 | static struct dentry *stats_dir; |
7f26508b JR |
322 | static struct dentry *de_fflush; |
323 | ||
324 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
325 | { | |
326 | if (stats_dir == NULL) | |
327 | return; | |
328 | ||
329 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
330 | &cnt->value); | |
331 | } | |
332 | ||
333 | static void amd_iommu_stats_init(void) | |
334 | { | |
335 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
336 | if (stats_dir == NULL) | |
337 | return; | |
338 | ||
7f26508b JR |
339 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
340 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
341 | |
342 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 343 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 344 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 345 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 346 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 347 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 348 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 349 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 350 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 351 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 352 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 353 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
354 | } |
355 | ||
356 | #endif | |
357 | ||
a80dc3e0 JR |
358 | /**************************************************************************** |
359 | * | |
360 | * Interrupt handling functions | |
361 | * | |
362 | ****************************************************************************/ | |
363 | ||
e3e59876 JR |
364 | static void dump_dte_entry(u16 devid) |
365 | { | |
366 | int i; | |
367 | ||
368 | for (i = 0; i < 8; ++i) | |
369 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
370 | amd_iommu_dev_table[devid].data[i]); | |
371 | } | |
372 | ||
945b4ac4 JR |
373 | static void dump_command(unsigned long phys_addr) |
374 | { | |
375 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
376 | int i; | |
377 | ||
378 | for (i = 0; i < 4; ++i) | |
379 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
380 | } | |
381 | ||
a345b23b | 382 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
383 | { |
384 | u32 *event = __evt; | |
385 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
386 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
387 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
388 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
389 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
390 | ||
4c6f40d4 | 391 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
392 | |
393 | switch (type) { | |
394 | case EVENT_TYPE_ILL_DEV: | |
395 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
396 | "address=0x%016llx flags=0x%04x]\n", | |
397 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
398 | address, flags); | |
e3e59876 | 399 | dump_dte_entry(devid); |
90008ee4 JR |
400 | break; |
401 | case EVENT_TYPE_IO_FAULT: | |
402 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
403 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
404 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
405 | domid, address, flags); | |
406 | break; | |
407 | case EVENT_TYPE_DEV_TAB_ERR: | |
408 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
409 | "address=0x%016llx flags=0x%04x]\n", | |
410 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
411 | address, flags); | |
412 | break; | |
413 | case EVENT_TYPE_PAGE_TAB_ERR: | |
414 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
415 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
416 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
417 | domid, address, flags); | |
418 | break; | |
419 | case EVENT_TYPE_ILL_CMD: | |
420 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 421 | dump_command(address); |
90008ee4 JR |
422 | break; |
423 | case EVENT_TYPE_CMD_HARD_ERR: | |
424 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
425 | "flags=0x%04x]\n", address, flags); | |
426 | break; | |
427 | case EVENT_TYPE_IOTLB_INV_TO: | |
428 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
429 | "address=0x%016llx]\n", | |
430 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
431 | address); | |
432 | break; | |
433 | case EVENT_TYPE_INV_DEV_REQ: | |
434 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
435 | "address=0x%016llx flags=0x%04x]\n", | |
436 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
437 | address, flags); | |
438 | break; | |
439 | default: | |
440 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
441 | } | |
442 | } | |
443 | ||
444 | static void iommu_poll_events(struct amd_iommu *iommu) | |
445 | { | |
446 | u32 head, tail; | |
447 | unsigned long flags; | |
448 | ||
449 | spin_lock_irqsave(&iommu->lock, flags); | |
450 | ||
451 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
452 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
453 | ||
454 | while (head != tail) { | |
a345b23b | 455 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
456 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
457 | } | |
458 | ||
459 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
460 | ||
461 | spin_unlock_irqrestore(&iommu->lock, flags); | |
462 | } | |
463 | ||
72fe00f0 | 464 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 465 | { |
90008ee4 JR |
466 | struct amd_iommu *iommu; |
467 | ||
3bd22172 | 468 | for_each_iommu(iommu) |
90008ee4 JR |
469 | iommu_poll_events(iommu); |
470 | ||
471 | return IRQ_HANDLED; | |
a80dc3e0 JR |
472 | } |
473 | ||
72fe00f0 JR |
474 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
475 | { | |
476 | return IRQ_WAKE_THREAD; | |
477 | } | |
478 | ||
431b2a20 JR |
479 | /**************************************************************************** |
480 | * | |
481 | * IOMMU command queuing functions | |
482 | * | |
483 | ****************************************************************************/ | |
484 | ||
ac0ea6e9 JR |
485 | static int wait_on_sem(volatile u64 *sem) |
486 | { | |
487 | int i = 0; | |
488 | ||
489 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
490 | udelay(1); | |
491 | i += 1; | |
492 | } | |
493 | ||
494 | if (i == LOOP_TIMEOUT) { | |
495 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
496 | return -EIO; | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
503 | struct iommu_cmd *cmd, | |
504 | u32 tail) | |
a19ae1ec | 505 | { |
a19ae1ec JR |
506 | u8 *target; |
507 | ||
8a7c5ef3 | 508 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
509 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
510 | ||
511 | /* Copy command to buffer */ | |
512 | memcpy(target, cmd, sizeof(*cmd)); | |
513 | ||
514 | /* Tell the IOMMU about it */ | |
a19ae1ec | 515 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 516 | } |
a19ae1ec | 517 | |
815b33fd | 518 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 519 | { |
815b33fd JR |
520 | WARN_ON(address & 0x7ULL); |
521 | ||
ded46737 | 522 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
523 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
524 | cmd->data[1] = upper_32_bits(__pa(address)); | |
525 | cmd->data[2] = 1; | |
ded46737 JR |
526 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
527 | } | |
528 | ||
94fe79e2 JR |
529 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
530 | { | |
531 | memset(cmd, 0, sizeof(*cmd)); | |
532 | cmd->data[0] = devid; | |
533 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
534 | } | |
535 | ||
11b6402c JR |
536 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
537 | size_t size, u16 domid, int pde) | |
538 | { | |
539 | u64 pages; | |
540 | int s; | |
541 | ||
542 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
543 | s = 0; | |
544 | ||
545 | if (pages > 1) { | |
546 | /* | |
547 | * If we have to flush more than one page, flush all | |
548 | * TLB entries for this domain | |
549 | */ | |
550 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
551 | s = 1; | |
552 | } | |
553 | ||
554 | address &= PAGE_MASK; | |
555 | ||
556 | memset(cmd, 0, sizeof(*cmd)); | |
557 | cmd->data[1] |= domid; | |
558 | cmd->data[2] = lower_32_bits(address); | |
559 | cmd->data[3] = upper_32_bits(address); | |
560 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
561 | if (s) /* size bit - we flush more than one 4kb page */ | |
562 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
563 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
564 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
565 | } | |
566 | ||
cb41ed85 JR |
567 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
568 | u64 address, size_t size) | |
569 | { | |
570 | u64 pages; | |
571 | int s; | |
572 | ||
573 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
574 | s = 0; | |
575 | ||
576 | if (pages > 1) { | |
577 | /* | |
578 | * If we have to flush more than one page, flush all | |
579 | * TLB entries for this domain | |
580 | */ | |
581 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
582 | s = 1; | |
583 | } | |
584 | ||
585 | address &= PAGE_MASK; | |
586 | ||
587 | memset(cmd, 0, sizeof(*cmd)); | |
588 | cmd->data[0] = devid; | |
589 | cmd->data[0] |= (qdep & 0xff) << 24; | |
590 | cmd->data[1] = devid; | |
591 | cmd->data[2] = lower_32_bits(address); | |
592 | cmd->data[3] = upper_32_bits(address); | |
593 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
594 | if (s) | |
595 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
596 | } | |
597 | ||
58fc7f14 JR |
598 | static void build_inv_all(struct iommu_cmd *cmd) |
599 | { | |
600 | memset(cmd, 0, sizeof(*cmd)); | |
601 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
602 | } |
603 | ||
431b2a20 | 604 | /* |
431b2a20 | 605 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 606 | * hardware about the new command. |
431b2a20 | 607 | */ |
f1ca1512 JR |
608 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
609 | struct iommu_cmd *cmd, | |
610 | bool sync) | |
a19ae1ec | 611 | { |
ac0ea6e9 | 612 | u32 left, tail, head, next_tail; |
a19ae1ec | 613 | unsigned long flags; |
a19ae1ec | 614 | |
549c90dc | 615 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
616 | |
617 | again: | |
a19ae1ec | 618 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 619 | |
ac0ea6e9 JR |
620 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
621 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
622 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
623 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 624 | |
ac0ea6e9 JR |
625 | if (left <= 2) { |
626 | struct iommu_cmd sync_cmd; | |
627 | volatile u64 sem = 0; | |
628 | int ret; | |
8d201968 | 629 | |
ac0ea6e9 JR |
630 | build_completion_wait(&sync_cmd, (u64)&sem); |
631 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 632 | |
ac0ea6e9 JR |
633 | spin_unlock_irqrestore(&iommu->lock, flags); |
634 | ||
635 | if ((ret = wait_on_sem(&sem)) != 0) | |
636 | return ret; | |
637 | ||
638 | goto again; | |
8d201968 JR |
639 | } |
640 | ||
ac0ea6e9 JR |
641 | copy_cmd_to_buffer(iommu, cmd, tail); |
642 | ||
643 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 644 | iommu->need_sync = sync; |
ac0ea6e9 | 645 | |
a19ae1ec | 646 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 647 | |
815b33fd | 648 | return 0; |
8d201968 JR |
649 | } |
650 | ||
f1ca1512 JR |
651 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
652 | { | |
653 | return iommu_queue_command_sync(iommu, cmd, true); | |
654 | } | |
655 | ||
8d201968 JR |
656 | /* |
657 | * This function queues a completion wait command into the command | |
658 | * buffer of an IOMMU | |
659 | */ | |
a19ae1ec | 660 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
661 | { |
662 | struct iommu_cmd cmd; | |
815b33fd | 663 | volatile u64 sem = 0; |
ac0ea6e9 | 664 | int ret; |
8d201968 | 665 | |
09ee17eb | 666 | if (!iommu->need_sync) |
815b33fd | 667 | return 0; |
09ee17eb | 668 | |
815b33fd | 669 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 670 | |
f1ca1512 | 671 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 672 | if (ret) |
815b33fd | 673 | return ret; |
8d201968 | 674 | |
ac0ea6e9 | 675 | return wait_on_sem(&sem); |
8d201968 JR |
676 | } |
677 | ||
d8c13085 | 678 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 679 | { |
d8c13085 | 680 | struct iommu_cmd cmd; |
a19ae1ec | 681 | |
d8c13085 | 682 | build_inv_dte(&cmd, devid); |
7e4f88da | 683 | |
d8c13085 JR |
684 | return iommu_queue_command(iommu, &cmd); |
685 | } | |
09ee17eb | 686 | |
7d0c5cc5 JR |
687 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
688 | { | |
689 | u32 devid; | |
09ee17eb | 690 | |
7d0c5cc5 JR |
691 | for (devid = 0; devid <= 0xffff; ++devid) |
692 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 693 | |
7d0c5cc5 JR |
694 | iommu_completion_wait(iommu); |
695 | } | |
84df8175 | 696 | |
7d0c5cc5 JR |
697 | /* |
698 | * This function uses heavy locking and may disable irqs for some time. But | |
699 | * this is no issue because it is only called during resume. | |
700 | */ | |
701 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
702 | { | |
703 | u32 dom_id; | |
a19ae1ec | 704 | |
7d0c5cc5 JR |
705 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
706 | struct iommu_cmd cmd; | |
707 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
708 | dom_id, 1); | |
709 | iommu_queue_command(iommu, &cmd); | |
710 | } | |
8eed9833 | 711 | |
7d0c5cc5 | 712 | iommu_completion_wait(iommu); |
a19ae1ec JR |
713 | } |
714 | ||
58fc7f14 | 715 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 716 | { |
58fc7f14 | 717 | struct iommu_cmd cmd; |
0518a3a4 | 718 | |
58fc7f14 | 719 | build_inv_all(&cmd); |
0518a3a4 | 720 | |
58fc7f14 JR |
721 | iommu_queue_command(iommu, &cmd); |
722 | iommu_completion_wait(iommu); | |
723 | } | |
724 | ||
7d0c5cc5 JR |
725 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
726 | { | |
58fc7f14 JR |
727 | if (iommu_feature(iommu, FEATURE_IA)) { |
728 | iommu_flush_all(iommu); | |
729 | } else { | |
730 | iommu_flush_dte_all(iommu); | |
731 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
732 | } |
733 | } | |
734 | ||
431b2a20 | 735 | /* |
cb41ed85 | 736 | * Command send function for flushing on-device TLB |
431b2a20 | 737 | */ |
6c542047 JR |
738 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
739 | u64 address, size_t size) | |
3fa43655 JR |
740 | { |
741 | struct amd_iommu *iommu; | |
b00d3bcf | 742 | struct iommu_cmd cmd; |
cb41ed85 | 743 | int qdep; |
3fa43655 | 744 | |
ea61cddb JR |
745 | qdep = dev_data->ats.qdep; |
746 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 747 | |
ea61cddb | 748 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
749 | |
750 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
751 | } |
752 | ||
431b2a20 | 753 | /* |
431b2a20 | 754 | * Command send function for invalidating a device table entry |
431b2a20 | 755 | */ |
6c542047 | 756 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 757 | { |
3fa43655 | 758 | struct amd_iommu *iommu; |
ee2fa743 | 759 | int ret; |
a19ae1ec | 760 | |
6c542047 | 761 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 762 | |
f62dda66 | 763 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
764 | if (ret) |
765 | return ret; | |
766 | ||
ea61cddb | 767 | if (dev_data->ats.enabled) |
6c542047 | 768 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 769 | |
ee2fa743 | 770 | return ret; |
a19ae1ec JR |
771 | } |
772 | ||
431b2a20 JR |
773 | /* |
774 | * TLB invalidation function which is called from the mapping functions. | |
775 | * It invalidates a single PTE if the range to flush is within a single | |
776 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
777 | */ | |
17b124bf JR |
778 | static void __domain_flush_pages(struct protection_domain *domain, |
779 | u64 address, size_t size, int pde) | |
a19ae1ec | 780 | { |
cb41ed85 | 781 | struct iommu_dev_data *dev_data; |
11b6402c JR |
782 | struct iommu_cmd cmd; |
783 | int ret = 0, i; | |
a19ae1ec | 784 | |
11b6402c | 785 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 786 | |
6de8ad9b JR |
787 | for (i = 0; i < amd_iommus_present; ++i) { |
788 | if (!domain->dev_iommu[i]) | |
789 | continue; | |
790 | ||
791 | /* | |
792 | * Devices of this domain are behind this IOMMU | |
793 | * We need a TLB flush | |
794 | */ | |
11b6402c | 795 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
796 | } |
797 | ||
cb41ed85 | 798 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 799 | |
ea61cddb | 800 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
801 | continue; |
802 | ||
6c542047 | 803 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
804 | } |
805 | ||
11b6402c | 806 | WARN_ON(ret); |
6de8ad9b JR |
807 | } |
808 | ||
17b124bf JR |
809 | static void domain_flush_pages(struct protection_domain *domain, |
810 | u64 address, size_t size) | |
6de8ad9b | 811 | { |
17b124bf | 812 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 813 | } |
b6c02715 | 814 | |
1c655773 | 815 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 816 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 817 | { |
17b124bf | 818 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
819 | } |
820 | ||
42a49f96 | 821 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 822 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 823 | { |
17b124bf | 824 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
825 | } |
826 | ||
17b124bf | 827 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 828 | { |
17b124bf | 829 | int i; |
18811f55 | 830 | |
17b124bf JR |
831 | for (i = 0; i < amd_iommus_present; ++i) { |
832 | if (!domain->dev_iommu[i]) | |
833 | continue; | |
bfd1be18 | 834 | |
17b124bf JR |
835 | /* |
836 | * Devices of this domain are behind this IOMMU | |
837 | * We need to wait for completion of all commands. | |
838 | */ | |
839 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 840 | } |
e394d72a JR |
841 | } |
842 | ||
b00d3bcf | 843 | |
09b42804 | 844 | /* |
b00d3bcf | 845 | * This function flushes the DTEs for all devices in domain |
09b42804 | 846 | */ |
17b124bf | 847 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 848 | { |
b00d3bcf | 849 | struct iommu_dev_data *dev_data; |
b26e81b8 | 850 | |
b00d3bcf | 851 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 852 | device_flush_dte(dev_data); |
a345b23b JR |
853 | } |
854 | ||
431b2a20 JR |
855 | /**************************************************************************** |
856 | * | |
857 | * The functions below are used the create the page table mappings for | |
858 | * unity mapped regions. | |
859 | * | |
860 | ****************************************************************************/ | |
861 | ||
308973d3 JR |
862 | /* |
863 | * This function is used to add another level to an IO page table. Adding | |
864 | * another level increases the size of the address space by 9 bits to a size up | |
865 | * to 64 bits. | |
866 | */ | |
867 | static bool increase_address_space(struct protection_domain *domain, | |
868 | gfp_t gfp) | |
869 | { | |
870 | u64 *pte; | |
871 | ||
872 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
873 | /* address space already 64 bit large */ | |
874 | return false; | |
875 | ||
876 | pte = (void *)get_zeroed_page(gfp); | |
877 | if (!pte) | |
878 | return false; | |
879 | ||
880 | *pte = PM_LEVEL_PDE(domain->mode, | |
881 | virt_to_phys(domain->pt_root)); | |
882 | domain->pt_root = pte; | |
883 | domain->mode += 1; | |
884 | domain->updated = true; | |
885 | ||
886 | return true; | |
887 | } | |
888 | ||
889 | static u64 *alloc_pte(struct protection_domain *domain, | |
890 | unsigned long address, | |
cbb9d729 | 891 | unsigned long page_size, |
308973d3 JR |
892 | u64 **pte_page, |
893 | gfp_t gfp) | |
894 | { | |
cbb9d729 | 895 | int level, end_lvl; |
308973d3 | 896 | u64 *pte, *page; |
cbb9d729 JR |
897 | |
898 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
899 | |
900 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
901 | increase_address_space(domain, gfp); | |
902 | ||
cbb9d729 JR |
903 | level = domain->mode - 1; |
904 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
905 | address = PAGE_SIZE_ALIGN(address, page_size); | |
906 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
907 | |
908 | while (level > end_lvl) { | |
909 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
910 | page = (u64 *)get_zeroed_page(gfp); | |
911 | if (!page) | |
912 | return NULL; | |
913 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
914 | } | |
915 | ||
cbb9d729 JR |
916 | /* No level skipping support yet */ |
917 | if (PM_PTE_LEVEL(*pte) != level) | |
918 | return NULL; | |
919 | ||
308973d3 JR |
920 | level -= 1; |
921 | ||
922 | pte = IOMMU_PTE_PAGE(*pte); | |
923 | ||
924 | if (pte_page && level == end_lvl) | |
925 | *pte_page = pte; | |
926 | ||
927 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
928 | } | |
929 | ||
930 | return pte; | |
931 | } | |
932 | ||
933 | /* | |
934 | * This function checks if there is a PTE for a given dma address. If | |
935 | * there is one, it returns the pointer to it. | |
936 | */ | |
24cd7723 | 937 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
938 | { |
939 | int level; | |
940 | u64 *pte; | |
941 | ||
24cd7723 JR |
942 | if (address > PM_LEVEL_SIZE(domain->mode)) |
943 | return NULL; | |
944 | ||
945 | level = domain->mode - 1; | |
946 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 947 | |
24cd7723 JR |
948 | while (level > 0) { |
949 | ||
950 | /* Not Present */ | |
308973d3 JR |
951 | if (!IOMMU_PTE_PRESENT(*pte)) |
952 | return NULL; | |
953 | ||
24cd7723 JR |
954 | /* Large PTE */ |
955 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
956 | unsigned long pte_mask, __pte; | |
957 | ||
958 | /* | |
959 | * If we have a series of large PTEs, make | |
960 | * sure to return a pointer to the first one. | |
961 | */ | |
962 | pte_mask = PTE_PAGE_SIZE(*pte); | |
963 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
964 | __pte = ((unsigned long)pte) & pte_mask; | |
965 | ||
966 | return (u64 *)__pte; | |
967 | } | |
968 | ||
969 | /* No level skipping support yet */ | |
970 | if (PM_PTE_LEVEL(*pte) != level) | |
971 | return NULL; | |
972 | ||
308973d3 JR |
973 | level -= 1; |
974 | ||
24cd7723 | 975 | /* Walk to the next level */ |
308973d3 JR |
976 | pte = IOMMU_PTE_PAGE(*pte); |
977 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
978 | } |
979 | ||
980 | return pte; | |
981 | } | |
982 | ||
431b2a20 JR |
983 | /* |
984 | * Generic mapping functions. It maps a physical address into a DMA | |
985 | * address space. It allocates the page table pages if necessary. | |
986 | * In the future it can be extended to a generic mapping function | |
987 | * supporting all features of AMD IOMMU page tables like level skipping | |
988 | * and full 64 bit address spaces. | |
989 | */ | |
38e817fe JR |
990 | static int iommu_map_page(struct protection_domain *dom, |
991 | unsigned long bus_addr, | |
992 | unsigned long phys_addr, | |
abdc5eb3 | 993 | int prot, |
cbb9d729 | 994 | unsigned long page_size) |
bd0e5211 | 995 | { |
8bda3092 | 996 | u64 __pte, *pte; |
cbb9d729 | 997 | int i, count; |
abdc5eb3 | 998 | |
bad1cac2 | 999 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1000 | return -EINVAL; |
1001 | ||
cbb9d729 JR |
1002 | bus_addr = PAGE_ALIGN(bus_addr); |
1003 | phys_addr = PAGE_ALIGN(phys_addr); | |
1004 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1005 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1006 | ||
1007 | for (i = 0; i < count; ++i) | |
1008 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1009 | return -EBUSY; | |
bd0e5211 | 1010 | |
cbb9d729 JR |
1011 | if (page_size > PAGE_SIZE) { |
1012 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1013 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1014 | } else | |
1015 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1016 | |
bd0e5211 JR |
1017 | if (prot & IOMMU_PROT_IR) |
1018 | __pte |= IOMMU_PTE_IR; | |
1019 | if (prot & IOMMU_PROT_IW) | |
1020 | __pte |= IOMMU_PTE_IW; | |
1021 | ||
cbb9d729 JR |
1022 | for (i = 0; i < count; ++i) |
1023 | pte[i] = __pte; | |
bd0e5211 | 1024 | |
04bfdd84 JR |
1025 | update_domain(dom); |
1026 | ||
bd0e5211 JR |
1027 | return 0; |
1028 | } | |
1029 | ||
24cd7723 JR |
1030 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1031 | unsigned long bus_addr, | |
1032 | unsigned long page_size) | |
eb74ff6c | 1033 | { |
24cd7723 JR |
1034 | unsigned long long unmap_size, unmapped; |
1035 | u64 *pte; | |
1036 | ||
1037 | BUG_ON(!is_power_of_2(page_size)); | |
1038 | ||
1039 | unmapped = 0; | |
eb74ff6c | 1040 | |
24cd7723 JR |
1041 | while (unmapped < page_size) { |
1042 | ||
1043 | pte = fetch_pte(dom, bus_addr); | |
1044 | ||
1045 | if (!pte) { | |
1046 | /* | |
1047 | * No PTE for this address | |
1048 | * move forward in 4kb steps | |
1049 | */ | |
1050 | unmap_size = PAGE_SIZE; | |
1051 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1052 | /* 4kb PTE found for this address */ | |
1053 | unmap_size = PAGE_SIZE; | |
1054 | *pte = 0ULL; | |
1055 | } else { | |
1056 | int count, i; | |
1057 | ||
1058 | /* Large PTE found which maps this address */ | |
1059 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1060 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1061 | for (i = 0; i < count; i++) | |
1062 | pte[i] = 0ULL; | |
1063 | } | |
1064 | ||
1065 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1066 | unmapped += unmap_size; | |
1067 | } | |
1068 | ||
1069 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1070 | |
24cd7723 | 1071 | return unmapped; |
eb74ff6c | 1072 | } |
eb74ff6c | 1073 | |
431b2a20 JR |
1074 | /* |
1075 | * This function checks if a specific unity mapping entry is needed for | |
1076 | * this specific IOMMU. | |
1077 | */ | |
bd0e5211 JR |
1078 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1079 | struct unity_map_entry *entry) | |
1080 | { | |
1081 | u16 bdf, i; | |
1082 | ||
1083 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1084 | bdf = amd_iommu_alias_table[i]; | |
1085 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1086 | return 1; | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
431b2a20 JR |
1092 | /* |
1093 | * This function actually applies the mapping to the page table of the | |
1094 | * dma_ops domain. | |
1095 | */ | |
bd0e5211 JR |
1096 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1097 | struct unity_map_entry *e) | |
1098 | { | |
1099 | u64 addr; | |
1100 | int ret; | |
1101 | ||
1102 | for (addr = e->address_start; addr < e->address_end; | |
1103 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1104 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1105 | PAGE_SIZE); |
bd0e5211 JR |
1106 | if (ret) |
1107 | return ret; | |
1108 | /* | |
1109 | * if unity mapping is in aperture range mark the page | |
1110 | * as allocated in the aperture | |
1111 | */ | |
1112 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1113 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1114 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1115 | } |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
171e7b37 JR |
1120 | /* |
1121 | * Init the unity mappings for a specific IOMMU in the system | |
1122 | * | |
1123 | * Basically iterates over all unity mapping entries and applies them to | |
1124 | * the default domain DMA of that IOMMU if necessary. | |
1125 | */ | |
1126 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1127 | { | |
1128 | struct unity_map_entry *entry; | |
1129 | int ret; | |
1130 | ||
1131 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1132 | if (!iommu_for_unity_map(iommu, entry)) | |
1133 | continue; | |
1134 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1135 | if (ret) | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
431b2a20 JR |
1142 | /* |
1143 | * Inits the unity mappings required for a specific device | |
1144 | */ | |
bd0e5211 JR |
1145 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1146 | u16 devid) | |
1147 | { | |
1148 | struct unity_map_entry *e; | |
1149 | int ret; | |
1150 | ||
1151 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1152 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1153 | continue; | |
1154 | ret = dma_ops_unity_map(dma_dom, e); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
431b2a20 JR |
1162 | /**************************************************************************** |
1163 | * | |
1164 | * The next functions belong to the address allocator for the dma_ops | |
1165 | * interface functions. They work like the allocators in the other IOMMU | |
1166 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1167 | * the aperture. Maybe it could be enhanced in the future to a more | |
1168 | * efficient allocator. | |
1169 | * | |
1170 | ****************************************************************************/ | |
d3086444 | 1171 | |
431b2a20 | 1172 | /* |
384de729 | 1173 | * The address allocator core functions. |
431b2a20 JR |
1174 | * |
1175 | * called with domain->lock held | |
1176 | */ | |
384de729 | 1177 | |
171e7b37 JR |
1178 | /* |
1179 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1180 | * ranges. | |
1181 | */ | |
1182 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1183 | unsigned long start_page, | |
1184 | unsigned int pages) | |
1185 | { | |
1186 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1187 | ||
1188 | if (start_page + pages > last_page) | |
1189 | pages = last_page - start_page; | |
1190 | ||
1191 | for (i = start_page; i < start_page + pages; ++i) { | |
1192 | int index = i / APERTURE_RANGE_PAGES; | |
1193 | int page = i % APERTURE_RANGE_PAGES; | |
1194 | __set_bit(page, dom->aperture[index]->bitmap); | |
1195 | } | |
1196 | } | |
1197 | ||
9cabe89b JR |
1198 | /* |
1199 | * This function is used to add a new aperture range to an existing | |
1200 | * aperture in case of dma_ops domain allocation or address allocation | |
1201 | * failure. | |
1202 | */ | |
576175c2 | 1203 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1204 | bool populate, gfp_t gfp) |
1205 | { | |
1206 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1207 | struct amd_iommu *iommu; |
17f5b569 | 1208 | unsigned long i, old_size; |
9cabe89b | 1209 | |
f5e9705c JR |
1210 | #ifdef CONFIG_IOMMU_STRESS |
1211 | populate = false; | |
1212 | #endif | |
1213 | ||
9cabe89b JR |
1214 | if (index >= APERTURE_MAX_RANGES) |
1215 | return -ENOMEM; | |
1216 | ||
1217 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1218 | if (!dma_dom->aperture[index]) | |
1219 | return -ENOMEM; | |
1220 | ||
1221 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1222 | if (!dma_dom->aperture[index]->bitmap) | |
1223 | goto out_free; | |
1224 | ||
1225 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1226 | ||
1227 | if (populate) { | |
1228 | unsigned long address = dma_dom->aperture_size; | |
1229 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1230 | u64 *pte, *pte_page; | |
1231 | ||
1232 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1233 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1234 | &pte_page, gfp); |
1235 | if (!pte) | |
1236 | goto out_free; | |
1237 | ||
1238 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1239 | ||
1240 | address += APERTURE_RANGE_SIZE / 64; | |
1241 | } | |
1242 | } | |
1243 | ||
17f5b569 | 1244 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1245 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1246 | ||
17f5b569 JR |
1247 | /* Reserve address range used for MSI messages */ |
1248 | if (old_size < MSI_ADDR_BASE_LO && | |
1249 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1250 | unsigned long spage; | |
1251 | int pages; | |
1252 | ||
1253 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1254 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1255 | ||
1256 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1257 | } | |
1258 | ||
b595076a | 1259 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1260 | for_each_iommu(iommu) { |
1261 | if (iommu->exclusion_start && | |
1262 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1263 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1264 | unsigned long startpage; | |
1265 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1266 | iommu->exclusion_length, | |
1267 | PAGE_SIZE); | |
1268 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1269 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1270 | } | |
00cd122a JR |
1271 | } |
1272 | ||
1273 | /* | |
1274 | * Check for areas already mapped as present in the new aperture | |
1275 | * range and mark those pages as reserved in the allocator. Such | |
1276 | * mappings may already exist as a result of requested unity | |
1277 | * mappings for devices. | |
1278 | */ | |
1279 | for (i = dma_dom->aperture[index]->offset; | |
1280 | i < dma_dom->aperture_size; | |
1281 | i += PAGE_SIZE) { | |
24cd7723 | 1282 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1283 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1284 | continue; | |
1285 | ||
fcd0861d | 1286 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1287 | } |
1288 | ||
04bfdd84 JR |
1289 | update_domain(&dma_dom->domain); |
1290 | ||
9cabe89b JR |
1291 | return 0; |
1292 | ||
1293 | out_free: | |
04bfdd84 JR |
1294 | update_domain(&dma_dom->domain); |
1295 | ||
9cabe89b JR |
1296 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1297 | ||
1298 | kfree(dma_dom->aperture[index]); | |
1299 | dma_dom->aperture[index] = NULL; | |
1300 | ||
1301 | return -ENOMEM; | |
1302 | } | |
1303 | ||
384de729 JR |
1304 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1305 | struct dma_ops_domain *dom, | |
1306 | unsigned int pages, | |
1307 | unsigned long align_mask, | |
1308 | u64 dma_mask, | |
1309 | unsigned long start) | |
1310 | { | |
803b8cb4 | 1311 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1312 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1313 | int i = start >> APERTURE_RANGE_SHIFT; | |
1314 | unsigned long boundary_size; | |
1315 | unsigned long address = -1; | |
1316 | unsigned long limit; | |
1317 | ||
803b8cb4 JR |
1318 | next_bit >>= PAGE_SHIFT; |
1319 | ||
384de729 JR |
1320 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1321 | PAGE_SIZE) >> PAGE_SHIFT; | |
1322 | ||
1323 | for (;i < max_index; ++i) { | |
1324 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1325 | ||
1326 | if (dom->aperture[i]->offset >= dma_mask) | |
1327 | break; | |
1328 | ||
1329 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1330 | dma_mask >> PAGE_SHIFT); | |
1331 | ||
1332 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1333 | limit, next_bit, pages, 0, | |
1334 | boundary_size, align_mask); | |
1335 | if (address != -1) { | |
1336 | address = dom->aperture[i]->offset + | |
1337 | (address << PAGE_SHIFT); | |
803b8cb4 | 1338 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1339 | break; |
1340 | } | |
1341 | ||
1342 | next_bit = 0; | |
1343 | } | |
1344 | ||
1345 | return address; | |
1346 | } | |
1347 | ||
d3086444 JR |
1348 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1349 | struct dma_ops_domain *dom, | |
6d4f343f | 1350 | unsigned int pages, |
832a90c3 JR |
1351 | unsigned long align_mask, |
1352 | u64 dma_mask) | |
d3086444 | 1353 | { |
d3086444 | 1354 | unsigned long address; |
d3086444 | 1355 | |
fe16f088 JR |
1356 | #ifdef CONFIG_IOMMU_STRESS |
1357 | dom->next_address = 0; | |
1358 | dom->need_flush = true; | |
1359 | #endif | |
d3086444 | 1360 | |
384de729 | 1361 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1362 | dma_mask, dom->next_address); |
d3086444 | 1363 | |
1c655773 | 1364 | if (address == -1) { |
803b8cb4 | 1365 | dom->next_address = 0; |
384de729 JR |
1366 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1367 | dma_mask, 0); | |
1c655773 JR |
1368 | dom->need_flush = true; |
1369 | } | |
d3086444 | 1370 | |
384de729 | 1371 | if (unlikely(address == -1)) |
8fd524b3 | 1372 | address = DMA_ERROR_CODE; |
d3086444 JR |
1373 | |
1374 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1375 | ||
1376 | return address; | |
1377 | } | |
1378 | ||
431b2a20 JR |
1379 | /* |
1380 | * The address free function. | |
1381 | * | |
1382 | * called with domain->lock held | |
1383 | */ | |
d3086444 JR |
1384 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1385 | unsigned long address, | |
1386 | unsigned int pages) | |
1387 | { | |
384de729 JR |
1388 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1389 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1390 | |
384de729 JR |
1391 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1392 | ||
47bccd6b JR |
1393 | #ifdef CONFIG_IOMMU_STRESS |
1394 | if (i < 4) | |
1395 | return; | |
1396 | #endif | |
80be308d | 1397 | |
803b8cb4 | 1398 | if (address >= dom->next_address) |
80be308d | 1399 | dom->need_flush = true; |
384de729 JR |
1400 | |
1401 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1402 | |
a66022c4 | 1403 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1404 | |
d3086444 JR |
1405 | } |
1406 | ||
431b2a20 JR |
1407 | /**************************************************************************** |
1408 | * | |
1409 | * The next functions belong to the domain allocation. A domain is | |
1410 | * allocated for every IOMMU as the default domain. If device isolation | |
1411 | * is enabled, every device get its own domain. The most important thing | |
1412 | * about domains is the page table mapping the DMA address space they | |
1413 | * contain. | |
1414 | * | |
1415 | ****************************************************************************/ | |
1416 | ||
aeb26f55 JR |
1417 | /* |
1418 | * This function adds a protection domain to the global protection domain list | |
1419 | */ | |
1420 | static void add_domain_to_list(struct protection_domain *domain) | |
1421 | { | |
1422 | unsigned long flags; | |
1423 | ||
1424 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1425 | list_add(&domain->list, &amd_iommu_pd_list); | |
1426 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1427 | } | |
1428 | ||
1429 | /* | |
1430 | * This function removes a protection domain to the global | |
1431 | * protection domain list | |
1432 | */ | |
1433 | static void del_domain_from_list(struct protection_domain *domain) | |
1434 | { | |
1435 | unsigned long flags; | |
1436 | ||
1437 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1438 | list_del(&domain->list); | |
1439 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1440 | } | |
1441 | ||
ec487d1a JR |
1442 | static u16 domain_id_alloc(void) |
1443 | { | |
1444 | unsigned long flags; | |
1445 | int id; | |
1446 | ||
1447 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1448 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1449 | BUG_ON(id == 0); | |
1450 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1451 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1452 | else | |
1453 | id = 0; | |
1454 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1455 | ||
1456 | return id; | |
1457 | } | |
1458 | ||
a2acfb75 JR |
1459 | static void domain_id_free(int id) |
1460 | { | |
1461 | unsigned long flags; | |
1462 | ||
1463 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1464 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1465 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1466 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1467 | } | |
a2acfb75 | 1468 | |
86db2e5d | 1469 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1470 | { |
1471 | int i, j; | |
1472 | u64 *p1, *p2, *p3; | |
1473 | ||
86db2e5d | 1474 | p1 = domain->pt_root; |
ec487d1a JR |
1475 | |
1476 | if (!p1) | |
1477 | return; | |
1478 | ||
1479 | for (i = 0; i < 512; ++i) { | |
1480 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1481 | continue; | |
1482 | ||
1483 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1484 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1485 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1486 | continue; | |
1487 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1488 | free_page((unsigned long)p3); | |
1489 | } | |
1490 | ||
1491 | free_page((unsigned long)p2); | |
1492 | } | |
1493 | ||
1494 | free_page((unsigned long)p1); | |
86db2e5d JR |
1495 | |
1496 | domain->pt_root = NULL; | |
ec487d1a JR |
1497 | } |
1498 | ||
431b2a20 JR |
1499 | /* |
1500 | * Free a domain, only used if something went wrong in the | |
1501 | * allocation path and we need to free an already allocated page table | |
1502 | */ | |
ec487d1a JR |
1503 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1504 | { | |
384de729 JR |
1505 | int i; |
1506 | ||
ec487d1a JR |
1507 | if (!dom) |
1508 | return; | |
1509 | ||
aeb26f55 JR |
1510 | del_domain_from_list(&dom->domain); |
1511 | ||
86db2e5d | 1512 | free_pagetable(&dom->domain); |
ec487d1a | 1513 | |
384de729 JR |
1514 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1515 | if (!dom->aperture[i]) | |
1516 | continue; | |
1517 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1518 | kfree(dom->aperture[i]); | |
1519 | } | |
ec487d1a JR |
1520 | |
1521 | kfree(dom); | |
1522 | } | |
1523 | ||
431b2a20 JR |
1524 | /* |
1525 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1526 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1527 | * structures required for the dma_ops interface |
1528 | */ | |
87a64d52 | 1529 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1530 | { |
1531 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1532 | |
1533 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1534 | if (!dma_dom) | |
1535 | return NULL; | |
1536 | ||
1537 | spin_lock_init(&dma_dom->domain.lock); | |
1538 | ||
1539 | dma_dom->domain.id = domain_id_alloc(); | |
1540 | if (dma_dom->domain.id == 0) | |
1541 | goto free_dma_dom; | |
7c392cbe | 1542 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1543 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1544 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1545 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1546 | dma_dom->domain.priv = dma_dom; |
1547 | if (!dma_dom->domain.pt_root) | |
1548 | goto free_dma_dom; | |
ec487d1a | 1549 | |
1c655773 | 1550 | dma_dom->need_flush = false; |
bd60b735 | 1551 | dma_dom->target_dev = 0xffff; |
1c655773 | 1552 | |
aeb26f55 JR |
1553 | add_domain_to_list(&dma_dom->domain); |
1554 | ||
576175c2 | 1555 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1556 | goto free_dma_dom; |
ec487d1a | 1557 | |
431b2a20 | 1558 | /* |
ec487d1a JR |
1559 | * mark the first page as allocated so we never return 0 as |
1560 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1561 | */ |
384de729 | 1562 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1563 | dma_dom->next_address = 0; |
ec487d1a | 1564 | |
ec487d1a JR |
1565 | |
1566 | return dma_dom; | |
1567 | ||
1568 | free_dma_dom: | |
1569 | dma_ops_domain_free(dma_dom); | |
1570 | ||
1571 | return NULL; | |
1572 | } | |
1573 | ||
5b28df6f JR |
1574 | /* |
1575 | * little helper function to check whether a given protection domain is a | |
1576 | * dma_ops domain | |
1577 | */ | |
1578 | static bool dma_ops_domain(struct protection_domain *domain) | |
1579 | { | |
1580 | return domain->flags & PD_DMA_OPS_MASK; | |
1581 | } | |
1582 | ||
fd7b5535 | 1583 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1584 | { |
b20ac0d4 | 1585 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1586 | u32 flags = 0; |
863c74eb | 1587 | |
38ddf41b JR |
1588 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1589 | << DEV_ENTRY_MODE_SHIFT; | |
1590 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1591 | |
fd7b5535 JR |
1592 | if (ats) |
1593 | flags |= DTE_FLAG_IOTLB; | |
1594 | ||
1595 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1596 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1597 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1598 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1599 | } |
1600 | ||
1601 | static void clear_dte_entry(u16 devid) | |
1602 | { | |
15898bbc JR |
1603 | /* remove entry from the device table seen by the hardware */ |
1604 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1605 | amd_iommu_dev_table[devid].data[1] = 0; | |
1606 | amd_iommu_dev_table[devid].data[2] = 0; | |
1607 | ||
1608 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1609 | } |
1610 | ||
ec9e79ef JR |
1611 | static void do_attach(struct iommu_dev_data *dev_data, |
1612 | struct protection_domain *domain) | |
7f760ddd | 1613 | { |
7f760ddd | 1614 | struct amd_iommu *iommu; |
ec9e79ef | 1615 | bool ats; |
fd7b5535 | 1616 | |
ec9e79ef JR |
1617 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1618 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1619 | |
1620 | /* Update data structures */ | |
1621 | dev_data->domain = domain; | |
1622 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1623 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1624 | |
1625 | /* Do reference counting */ | |
1626 | domain->dev_iommu[iommu->index] += 1; | |
1627 | domain->dev_cnt += 1; | |
1628 | ||
1629 | /* Flush the DTE entry */ | |
6c542047 | 1630 | device_flush_dte(dev_data); |
7f760ddd JR |
1631 | } |
1632 | ||
ec9e79ef | 1633 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1634 | { |
7f760ddd | 1635 | struct amd_iommu *iommu; |
7f760ddd | 1636 | |
ec9e79ef | 1637 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1638 | |
1639 | /* decrease reference counters */ | |
7f760ddd JR |
1640 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1641 | dev_data->domain->dev_cnt -= 1; | |
1642 | ||
1643 | /* Update data structures */ | |
1644 | dev_data->domain = NULL; | |
1645 | list_del(&dev_data->list); | |
f62dda66 | 1646 | clear_dte_entry(dev_data->devid); |
15898bbc | 1647 | |
7f760ddd | 1648 | /* Flush the DTE entry */ |
6c542047 | 1649 | device_flush_dte(dev_data); |
2b681faf JR |
1650 | } |
1651 | ||
1652 | /* | |
1653 | * If a device is not yet associated with a domain, this function does | |
1654 | * assigns it visible for the hardware | |
1655 | */ | |
ec9e79ef | 1656 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1657 | struct protection_domain *domain) |
2b681faf | 1658 | { |
84fe6c19 | 1659 | int ret; |
657cbb6b | 1660 | |
2b681faf JR |
1661 | /* lock domain */ |
1662 | spin_lock(&domain->lock); | |
1663 | ||
71f77580 JR |
1664 | if (dev_data->alias_data != NULL) { |
1665 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1666 | |
2b02b091 JR |
1667 | /* Some sanity checks */ |
1668 | ret = -EBUSY; | |
1669 | if (alias_data->domain != NULL && | |
1670 | alias_data->domain != domain) | |
1671 | goto out_unlock; | |
eba6ac60 | 1672 | |
2b02b091 JR |
1673 | if (dev_data->domain != NULL && |
1674 | dev_data->domain != domain) | |
1675 | goto out_unlock; | |
15898bbc | 1676 | |
2b02b091 | 1677 | /* Do real assignment */ |
7f760ddd | 1678 | if (alias_data->domain == NULL) |
ec9e79ef | 1679 | do_attach(alias_data, domain); |
24100055 JR |
1680 | |
1681 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1682 | } |
15898bbc | 1683 | |
7f760ddd | 1684 | if (dev_data->domain == NULL) |
ec9e79ef | 1685 | do_attach(dev_data, domain); |
eba6ac60 | 1686 | |
24100055 JR |
1687 | atomic_inc(&dev_data->bind); |
1688 | ||
84fe6c19 JL |
1689 | ret = 0; |
1690 | ||
1691 | out_unlock: | |
1692 | ||
eba6ac60 JR |
1693 | /* ready */ |
1694 | spin_unlock(&domain->lock); | |
15898bbc | 1695 | |
84fe6c19 | 1696 | return ret; |
0feae533 | 1697 | } |
b20ac0d4 | 1698 | |
407d733e JR |
1699 | /* |
1700 | * If a device is not yet associated with a domain, this function does | |
1701 | * assigns it visible for the hardware | |
1702 | */ | |
15898bbc JR |
1703 | static int attach_device(struct device *dev, |
1704 | struct protection_domain *domain) | |
0feae533 | 1705 | { |
fd7b5535 | 1706 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 1707 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1708 | unsigned long flags; |
15898bbc | 1709 | int ret; |
eba6ac60 | 1710 | |
ea61cddb JR |
1711 | dev_data = get_dev_data(dev); |
1712 | ||
1713 | if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
1714 | dev_data->ats.enabled = true; | |
1715 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1716 | } | |
fd7b5535 | 1717 | |
eba6ac60 | 1718 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1719 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1720 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1721 | ||
0feae533 JR |
1722 | /* |
1723 | * We might boot into a crash-kernel here. The crashed kernel | |
1724 | * left the caches in the IOMMU dirty. So we have to flush | |
1725 | * here to evict all dirty stuff. | |
1726 | */ | |
17b124bf | 1727 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1728 | |
1729 | return ret; | |
b20ac0d4 JR |
1730 | } |
1731 | ||
355bf553 JR |
1732 | /* |
1733 | * Removes a device from a protection domain (unlocked) | |
1734 | */ | |
ec9e79ef | 1735 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 1736 | { |
2ca76279 | 1737 | struct protection_domain *domain; |
7c392cbe | 1738 | unsigned long flags; |
c4596114 | 1739 | |
7f760ddd | 1740 | BUG_ON(!dev_data->domain); |
355bf553 | 1741 | |
2ca76279 JR |
1742 | domain = dev_data->domain; |
1743 | ||
1744 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1745 | |
71f77580 JR |
1746 | if (dev_data->alias_data != NULL) { |
1747 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
1748 | ||
7f760ddd | 1749 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 1750 | do_detach(alias_data); |
24100055 JR |
1751 | } |
1752 | ||
7f760ddd | 1753 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 1754 | do_detach(dev_data); |
7f760ddd | 1755 | |
2ca76279 | 1756 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1757 | |
1758 | /* | |
1759 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1760 | * passthrough domain if it is detached from any other domain. |
1761 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1762 | */ |
d3ad9373 JR |
1763 | if (iommu_pass_through && |
1764 | (dev_data->domain == NULL && domain != pt_domain)) | |
ec9e79ef | 1765 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
1766 | } |
1767 | ||
1768 | /* | |
1769 | * Removes a device from a protection domain (with devtable_lock held) | |
1770 | */ | |
15898bbc | 1771 | static void detach_device(struct device *dev) |
355bf553 | 1772 | { |
ea61cddb | 1773 | struct iommu_dev_data *dev_data; |
355bf553 JR |
1774 | unsigned long flags; |
1775 | ||
ec9e79ef JR |
1776 | dev_data = get_dev_data(dev); |
1777 | ||
355bf553 JR |
1778 | /* lock device table */ |
1779 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 1780 | __detach_device(dev_data); |
355bf553 | 1781 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 1782 | |
ea61cddb JR |
1783 | if (dev_data->ats.enabled) { |
1784 | pci_disable_ats(to_pci_dev(dev)); | |
1785 | dev_data->ats.enabled = false; | |
1786 | } | |
355bf553 | 1787 | } |
e275a2a0 | 1788 | |
15898bbc JR |
1789 | /* |
1790 | * Find out the protection domain structure for a given PCI device. This | |
1791 | * will give us the pointer to the page table root for example. | |
1792 | */ | |
1793 | static struct protection_domain *domain_for_device(struct device *dev) | |
1794 | { | |
71f77580 | 1795 | struct iommu_dev_data *dev_data; |
2b02b091 | 1796 | struct protection_domain *dom = NULL; |
15898bbc | 1797 | unsigned long flags; |
15898bbc | 1798 | |
657cbb6b | 1799 | dev_data = get_dev_data(dev); |
15898bbc | 1800 | |
2b02b091 JR |
1801 | if (dev_data->domain) |
1802 | return dev_data->domain; | |
15898bbc | 1803 | |
71f77580 JR |
1804 | if (dev_data->alias_data != NULL) { |
1805 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
1806 | |
1807 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1808 | if (alias_data->domain != NULL) { | |
1809 | __attach_device(dev_data, alias_data->domain); | |
1810 | dom = alias_data->domain; | |
1811 | } | |
1812 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1813 | } | |
15898bbc JR |
1814 | |
1815 | return dom; | |
1816 | } | |
1817 | ||
e275a2a0 JR |
1818 | static int device_change_notifier(struct notifier_block *nb, |
1819 | unsigned long action, void *data) | |
1820 | { | |
1821 | struct device *dev = data; | |
98fc5a69 | 1822 | u16 devid; |
e275a2a0 JR |
1823 | struct protection_domain *domain; |
1824 | struct dma_ops_domain *dma_domain; | |
1825 | struct amd_iommu *iommu; | |
1ac4cbbc | 1826 | unsigned long flags; |
e275a2a0 | 1827 | |
98fc5a69 JR |
1828 | if (!check_device(dev)) |
1829 | return 0; | |
e275a2a0 | 1830 | |
98fc5a69 JR |
1831 | devid = get_device_id(dev); |
1832 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1833 | |
1834 | switch (action) { | |
c1eee67b | 1835 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1836 | |
1837 | domain = domain_for_device(dev); | |
1838 | ||
e275a2a0 JR |
1839 | if (!domain) |
1840 | goto out; | |
a1ca331c JR |
1841 | if (iommu_pass_through) |
1842 | break; | |
15898bbc | 1843 | detach_device(dev); |
1ac4cbbc JR |
1844 | break; |
1845 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1846 | |
1847 | iommu_init_device(dev); | |
1848 | ||
1849 | domain = domain_for_device(dev); | |
1850 | ||
1ac4cbbc JR |
1851 | /* allocate a protection domain if a device is added */ |
1852 | dma_domain = find_protection_domain(devid); | |
1853 | if (dma_domain) | |
1854 | goto out; | |
87a64d52 | 1855 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1856 | if (!dma_domain) |
1857 | goto out; | |
1858 | dma_domain->target_dev = devid; | |
1859 | ||
1860 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1861 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1862 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1863 | ||
e275a2a0 | 1864 | break; |
657cbb6b JR |
1865 | case BUS_NOTIFY_DEL_DEVICE: |
1866 | ||
1867 | iommu_uninit_device(dev); | |
1868 | ||
e275a2a0 JR |
1869 | default: |
1870 | goto out; | |
1871 | } | |
1872 | ||
e275a2a0 JR |
1873 | iommu_completion_wait(iommu); |
1874 | ||
1875 | out: | |
1876 | return 0; | |
1877 | } | |
1878 | ||
b25ae679 | 1879 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1880 | .notifier_call = device_change_notifier, |
1881 | }; | |
355bf553 | 1882 | |
8638c491 JR |
1883 | void amd_iommu_init_notifier(void) |
1884 | { | |
1885 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1886 | } | |
1887 | ||
431b2a20 JR |
1888 | /***************************************************************************** |
1889 | * | |
1890 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1891 | * | |
1892 | *****************************************************************************/ | |
1893 | ||
1894 | /* | |
1895 | * In the dma_ops path we only have the struct device. This function | |
1896 | * finds the corresponding IOMMU, the protection domain and the | |
1897 | * requestor id for a given device. | |
1898 | * If the device is not yet associated with a domain this is also done | |
1899 | * in this function. | |
1900 | */ | |
94f6d190 | 1901 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1902 | { |
94f6d190 | 1903 | struct protection_domain *domain; |
b20ac0d4 | 1904 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1905 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1906 | |
f99c0f1c | 1907 | if (!check_device(dev)) |
94f6d190 | 1908 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1909 | |
94f6d190 JR |
1910 | domain = domain_for_device(dev); |
1911 | if (domain != NULL && !dma_ops_domain(domain)) | |
1912 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1913 | |
94f6d190 JR |
1914 | if (domain != NULL) |
1915 | return domain; | |
b20ac0d4 | 1916 | |
15898bbc | 1917 | /* Device not bount yet - bind it */ |
94f6d190 | 1918 | dma_dom = find_protection_domain(devid); |
15898bbc | 1919 | if (!dma_dom) |
94f6d190 JR |
1920 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1921 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1922 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1923 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1924 | |
94f6d190 | 1925 | return &dma_dom->domain; |
b20ac0d4 JR |
1926 | } |
1927 | ||
04bfdd84 JR |
1928 | static void update_device_table(struct protection_domain *domain) |
1929 | { | |
492667da | 1930 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1931 | |
ea61cddb JR |
1932 | list_for_each_entry(dev_data, &domain->dev_list, list) |
1933 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
1934 | } |
1935 | ||
1936 | static void update_domain(struct protection_domain *domain) | |
1937 | { | |
1938 | if (!domain->updated) | |
1939 | return; | |
1940 | ||
1941 | update_device_table(domain); | |
17b124bf JR |
1942 | |
1943 | domain_flush_devices(domain); | |
1944 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1945 | |
1946 | domain->updated = false; | |
1947 | } | |
1948 | ||
8bda3092 JR |
1949 | /* |
1950 | * This function fetches the PTE for a given address in the aperture | |
1951 | */ | |
1952 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1953 | unsigned long address) | |
1954 | { | |
384de729 | 1955 | struct aperture_range *aperture; |
8bda3092 JR |
1956 | u64 *pte, *pte_page; |
1957 | ||
384de729 JR |
1958 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1959 | if (!aperture) | |
1960 | return NULL; | |
1961 | ||
1962 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1963 | if (!pte) { |
cbb9d729 | 1964 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1965 | GFP_ATOMIC); |
384de729 JR |
1966 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1967 | } else | |
8c8c143c | 1968 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1969 | |
04bfdd84 | 1970 | update_domain(&dom->domain); |
8bda3092 JR |
1971 | |
1972 | return pte; | |
1973 | } | |
1974 | ||
431b2a20 JR |
1975 | /* |
1976 | * This is the generic map function. It maps one 4kb page at paddr to | |
1977 | * the given address in the DMA address space for the domain. | |
1978 | */ | |
680525e0 | 1979 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1980 | unsigned long address, |
1981 | phys_addr_t paddr, | |
1982 | int direction) | |
1983 | { | |
1984 | u64 *pte, __pte; | |
1985 | ||
1986 | WARN_ON(address > dom->aperture_size); | |
1987 | ||
1988 | paddr &= PAGE_MASK; | |
1989 | ||
8bda3092 | 1990 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1991 | if (!pte) |
8fd524b3 | 1992 | return DMA_ERROR_CODE; |
cb76c322 JR |
1993 | |
1994 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1995 | ||
1996 | if (direction == DMA_TO_DEVICE) | |
1997 | __pte |= IOMMU_PTE_IR; | |
1998 | else if (direction == DMA_FROM_DEVICE) | |
1999 | __pte |= IOMMU_PTE_IW; | |
2000 | else if (direction == DMA_BIDIRECTIONAL) | |
2001 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2002 | ||
2003 | WARN_ON(*pte); | |
2004 | ||
2005 | *pte = __pte; | |
2006 | ||
2007 | return (dma_addr_t)address; | |
2008 | } | |
2009 | ||
431b2a20 JR |
2010 | /* |
2011 | * The generic unmapping function for on page in the DMA address space. | |
2012 | */ | |
680525e0 | 2013 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2014 | unsigned long address) |
2015 | { | |
384de729 | 2016 | struct aperture_range *aperture; |
cb76c322 JR |
2017 | u64 *pte; |
2018 | ||
2019 | if (address >= dom->aperture_size) | |
2020 | return; | |
2021 | ||
384de729 JR |
2022 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2023 | if (!aperture) | |
2024 | return; | |
2025 | ||
2026 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2027 | if (!pte) | |
2028 | return; | |
cb76c322 | 2029 | |
8c8c143c | 2030 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2031 | |
2032 | WARN_ON(!*pte); | |
2033 | ||
2034 | *pte = 0ULL; | |
2035 | } | |
2036 | ||
431b2a20 JR |
2037 | /* |
2038 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2039 | * contiguous memory region into DMA address space. It is used by all |
2040 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2041 | * Must be called with the domain lock held. |
2042 | */ | |
cb76c322 | 2043 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2044 | struct dma_ops_domain *dma_dom, |
2045 | phys_addr_t paddr, | |
2046 | size_t size, | |
6d4f343f | 2047 | int dir, |
832a90c3 JR |
2048 | bool align, |
2049 | u64 dma_mask) | |
cb76c322 JR |
2050 | { |
2051 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2052 | dma_addr_t address, start, ret; |
cb76c322 | 2053 | unsigned int pages; |
6d4f343f | 2054 | unsigned long align_mask = 0; |
cb76c322 JR |
2055 | int i; |
2056 | ||
e3c449f5 | 2057 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2058 | paddr &= PAGE_MASK; |
2059 | ||
8ecaf8f1 JR |
2060 | INC_STATS_COUNTER(total_map_requests); |
2061 | ||
c1858976 JR |
2062 | if (pages > 1) |
2063 | INC_STATS_COUNTER(cross_page); | |
2064 | ||
6d4f343f JR |
2065 | if (align) |
2066 | align_mask = (1UL << get_order(size)) - 1; | |
2067 | ||
11b83888 | 2068 | retry: |
832a90c3 JR |
2069 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2070 | dma_mask); | |
8fd524b3 | 2071 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2072 | /* |
2073 | * setting next_address here will let the address | |
2074 | * allocator only scan the new allocated range in the | |
2075 | * first run. This is a small optimization. | |
2076 | */ | |
2077 | dma_dom->next_address = dma_dom->aperture_size; | |
2078 | ||
576175c2 | 2079 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2080 | goto out; |
2081 | ||
2082 | /* | |
af901ca1 | 2083 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2084 | * allocation again |
2085 | */ | |
2086 | goto retry; | |
2087 | } | |
cb76c322 JR |
2088 | |
2089 | start = address; | |
2090 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2091 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2092 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2093 | goto out_unmap; |
2094 | ||
cb76c322 JR |
2095 | paddr += PAGE_SIZE; |
2096 | start += PAGE_SIZE; | |
2097 | } | |
2098 | address += offset; | |
2099 | ||
5774f7c5 JR |
2100 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2101 | ||
afa9fdc2 | 2102 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2103 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2104 | dma_dom->need_flush = false; |
318afd41 | 2105 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2106 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2107 | |
cb76c322 JR |
2108 | out: |
2109 | return address; | |
53812c11 JR |
2110 | |
2111 | out_unmap: | |
2112 | ||
2113 | for (--i; i >= 0; --i) { | |
2114 | start -= PAGE_SIZE; | |
680525e0 | 2115 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2116 | } |
2117 | ||
2118 | dma_ops_free_addresses(dma_dom, address, pages); | |
2119 | ||
8fd524b3 | 2120 | return DMA_ERROR_CODE; |
cb76c322 JR |
2121 | } |
2122 | ||
431b2a20 JR |
2123 | /* |
2124 | * Does the reverse of the __map_single function. Must be called with | |
2125 | * the domain lock held too | |
2126 | */ | |
cd8c82e8 | 2127 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2128 | dma_addr_t dma_addr, |
2129 | size_t size, | |
2130 | int dir) | |
2131 | { | |
04e0463e | 2132 | dma_addr_t flush_addr; |
cb76c322 JR |
2133 | dma_addr_t i, start; |
2134 | unsigned int pages; | |
2135 | ||
8fd524b3 | 2136 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2137 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2138 | return; |
2139 | ||
04e0463e | 2140 | flush_addr = dma_addr; |
e3c449f5 | 2141 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2142 | dma_addr &= PAGE_MASK; |
2143 | start = dma_addr; | |
2144 | ||
2145 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2146 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2147 | start += PAGE_SIZE; |
2148 | } | |
2149 | ||
5774f7c5 JR |
2150 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2151 | ||
cb76c322 | 2152 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2153 | |
80be308d | 2154 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2155 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2156 | dma_dom->need_flush = false; |
2157 | } | |
cb76c322 JR |
2158 | } |
2159 | ||
431b2a20 JR |
2160 | /* |
2161 | * The exported map_single function for dma_ops. | |
2162 | */ | |
51491367 FT |
2163 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2164 | unsigned long offset, size_t size, | |
2165 | enum dma_data_direction dir, | |
2166 | struct dma_attrs *attrs) | |
4da70b9e JR |
2167 | { |
2168 | unsigned long flags; | |
4da70b9e | 2169 | struct protection_domain *domain; |
4da70b9e | 2170 | dma_addr_t addr; |
832a90c3 | 2171 | u64 dma_mask; |
51491367 | 2172 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2173 | |
0f2a86f2 JR |
2174 | INC_STATS_COUNTER(cnt_map_single); |
2175 | ||
94f6d190 JR |
2176 | domain = get_domain(dev); |
2177 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2178 | return (dma_addr_t)paddr; |
94f6d190 JR |
2179 | else if (IS_ERR(domain)) |
2180 | return DMA_ERROR_CODE; | |
4da70b9e | 2181 | |
f99c0f1c JR |
2182 | dma_mask = *dev->dma_mask; |
2183 | ||
4da70b9e | 2184 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2185 | |
cd8c82e8 | 2186 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2187 | dma_mask); |
8fd524b3 | 2188 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2189 | goto out; |
2190 | ||
17b124bf | 2191 | domain_flush_complete(domain); |
4da70b9e JR |
2192 | |
2193 | out: | |
2194 | spin_unlock_irqrestore(&domain->lock, flags); | |
2195 | ||
2196 | return addr; | |
2197 | } | |
2198 | ||
431b2a20 JR |
2199 | /* |
2200 | * The exported unmap_single function for dma_ops. | |
2201 | */ | |
51491367 FT |
2202 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2203 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2204 | { |
2205 | unsigned long flags; | |
4da70b9e | 2206 | struct protection_domain *domain; |
4da70b9e | 2207 | |
146a6917 JR |
2208 | INC_STATS_COUNTER(cnt_unmap_single); |
2209 | ||
94f6d190 JR |
2210 | domain = get_domain(dev); |
2211 | if (IS_ERR(domain)) | |
5b28df6f JR |
2212 | return; |
2213 | ||
4da70b9e JR |
2214 | spin_lock_irqsave(&domain->lock, flags); |
2215 | ||
cd8c82e8 | 2216 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2217 | |
17b124bf | 2218 | domain_flush_complete(domain); |
4da70b9e JR |
2219 | |
2220 | spin_unlock_irqrestore(&domain->lock, flags); | |
2221 | } | |
2222 | ||
431b2a20 JR |
2223 | /* |
2224 | * This is a special map_sg function which is used if we should map a | |
2225 | * device which is not handled by an AMD IOMMU in the system. | |
2226 | */ | |
65b050ad JR |
2227 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2228 | int nelems, int dir) | |
2229 | { | |
2230 | struct scatterlist *s; | |
2231 | int i; | |
2232 | ||
2233 | for_each_sg(sglist, s, nelems, i) { | |
2234 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2235 | s->dma_length = s->length; | |
2236 | } | |
2237 | ||
2238 | return nelems; | |
2239 | } | |
2240 | ||
431b2a20 JR |
2241 | /* |
2242 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2243 | * lists). | |
2244 | */ | |
65b050ad | 2245 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2246 | int nelems, enum dma_data_direction dir, |
2247 | struct dma_attrs *attrs) | |
65b050ad JR |
2248 | { |
2249 | unsigned long flags; | |
65b050ad | 2250 | struct protection_domain *domain; |
65b050ad JR |
2251 | int i; |
2252 | struct scatterlist *s; | |
2253 | phys_addr_t paddr; | |
2254 | int mapped_elems = 0; | |
832a90c3 | 2255 | u64 dma_mask; |
65b050ad | 2256 | |
d03f067a JR |
2257 | INC_STATS_COUNTER(cnt_map_sg); |
2258 | ||
94f6d190 JR |
2259 | domain = get_domain(dev); |
2260 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2261 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2262 | else if (IS_ERR(domain)) |
2263 | return 0; | |
dbcc112e | 2264 | |
832a90c3 | 2265 | dma_mask = *dev->dma_mask; |
65b050ad | 2266 | |
65b050ad JR |
2267 | spin_lock_irqsave(&domain->lock, flags); |
2268 | ||
2269 | for_each_sg(sglist, s, nelems, i) { | |
2270 | paddr = sg_phys(s); | |
2271 | ||
cd8c82e8 | 2272 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2273 | paddr, s->length, dir, false, |
2274 | dma_mask); | |
65b050ad JR |
2275 | |
2276 | if (s->dma_address) { | |
2277 | s->dma_length = s->length; | |
2278 | mapped_elems++; | |
2279 | } else | |
2280 | goto unmap; | |
65b050ad JR |
2281 | } |
2282 | ||
17b124bf | 2283 | domain_flush_complete(domain); |
65b050ad JR |
2284 | |
2285 | out: | |
2286 | spin_unlock_irqrestore(&domain->lock, flags); | |
2287 | ||
2288 | return mapped_elems; | |
2289 | unmap: | |
2290 | for_each_sg(sglist, s, mapped_elems, i) { | |
2291 | if (s->dma_address) | |
cd8c82e8 | 2292 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2293 | s->dma_length, dir); |
2294 | s->dma_address = s->dma_length = 0; | |
2295 | } | |
2296 | ||
2297 | mapped_elems = 0; | |
2298 | ||
2299 | goto out; | |
2300 | } | |
2301 | ||
431b2a20 JR |
2302 | /* |
2303 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2304 | * lists). | |
2305 | */ | |
65b050ad | 2306 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2307 | int nelems, enum dma_data_direction dir, |
2308 | struct dma_attrs *attrs) | |
65b050ad JR |
2309 | { |
2310 | unsigned long flags; | |
65b050ad JR |
2311 | struct protection_domain *domain; |
2312 | struct scatterlist *s; | |
65b050ad JR |
2313 | int i; |
2314 | ||
55877a6b JR |
2315 | INC_STATS_COUNTER(cnt_unmap_sg); |
2316 | ||
94f6d190 JR |
2317 | domain = get_domain(dev); |
2318 | if (IS_ERR(domain)) | |
5b28df6f JR |
2319 | return; |
2320 | ||
65b050ad JR |
2321 | spin_lock_irqsave(&domain->lock, flags); |
2322 | ||
2323 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2324 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2325 | s->dma_length, dir); |
65b050ad JR |
2326 | s->dma_address = s->dma_length = 0; |
2327 | } | |
2328 | ||
17b124bf | 2329 | domain_flush_complete(domain); |
65b050ad JR |
2330 | |
2331 | spin_unlock_irqrestore(&domain->lock, flags); | |
2332 | } | |
2333 | ||
431b2a20 JR |
2334 | /* |
2335 | * The exported alloc_coherent function for dma_ops. | |
2336 | */ | |
5d8b53cf JR |
2337 | static void *alloc_coherent(struct device *dev, size_t size, |
2338 | dma_addr_t *dma_addr, gfp_t flag) | |
2339 | { | |
2340 | unsigned long flags; | |
2341 | void *virt_addr; | |
5d8b53cf | 2342 | struct protection_domain *domain; |
5d8b53cf | 2343 | phys_addr_t paddr; |
832a90c3 | 2344 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2345 | |
c8f0fb36 JR |
2346 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2347 | ||
94f6d190 JR |
2348 | domain = get_domain(dev); |
2349 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2350 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2351 | *dma_addr = __pa(virt_addr); | |
2352 | return virt_addr; | |
94f6d190 JR |
2353 | } else if (IS_ERR(domain)) |
2354 | return NULL; | |
5d8b53cf | 2355 | |
f99c0f1c JR |
2356 | dma_mask = dev->coherent_dma_mask; |
2357 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2358 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2359 | |
2360 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2361 | if (!virt_addr) | |
b25ae679 | 2362 | return NULL; |
5d8b53cf | 2363 | |
5d8b53cf JR |
2364 | paddr = virt_to_phys(virt_addr); |
2365 | ||
832a90c3 JR |
2366 | if (!dma_mask) |
2367 | dma_mask = *dev->dma_mask; | |
2368 | ||
5d8b53cf JR |
2369 | spin_lock_irqsave(&domain->lock, flags); |
2370 | ||
cd8c82e8 | 2371 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2372 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2373 | |
8fd524b3 | 2374 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2375 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2376 | goto out_free; |
367d04c4 | 2377 | } |
5d8b53cf | 2378 | |
17b124bf | 2379 | domain_flush_complete(domain); |
5d8b53cf | 2380 | |
5d8b53cf JR |
2381 | spin_unlock_irqrestore(&domain->lock, flags); |
2382 | ||
2383 | return virt_addr; | |
5b28df6f JR |
2384 | |
2385 | out_free: | |
2386 | ||
2387 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2388 | ||
2389 | return NULL; | |
5d8b53cf JR |
2390 | } |
2391 | ||
431b2a20 JR |
2392 | /* |
2393 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2394 | */ |
5d8b53cf JR |
2395 | static void free_coherent(struct device *dev, size_t size, |
2396 | void *virt_addr, dma_addr_t dma_addr) | |
2397 | { | |
2398 | unsigned long flags; | |
5d8b53cf | 2399 | struct protection_domain *domain; |
5d8b53cf | 2400 | |
5d31ee7e JR |
2401 | INC_STATS_COUNTER(cnt_free_coherent); |
2402 | ||
94f6d190 JR |
2403 | domain = get_domain(dev); |
2404 | if (IS_ERR(domain)) | |
5b28df6f JR |
2405 | goto free_mem; |
2406 | ||
5d8b53cf JR |
2407 | spin_lock_irqsave(&domain->lock, flags); |
2408 | ||
cd8c82e8 | 2409 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2410 | |
17b124bf | 2411 | domain_flush_complete(domain); |
5d8b53cf JR |
2412 | |
2413 | spin_unlock_irqrestore(&domain->lock, flags); | |
2414 | ||
2415 | free_mem: | |
2416 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2417 | } | |
2418 | ||
b39ba6ad JR |
2419 | /* |
2420 | * This function is called by the DMA layer to find out if we can handle a | |
2421 | * particular device. It is part of the dma_ops. | |
2422 | */ | |
2423 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2424 | { | |
420aef8a | 2425 | return check_device(dev); |
b39ba6ad JR |
2426 | } |
2427 | ||
c432f3df | 2428 | /* |
431b2a20 JR |
2429 | * The function for pre-allocating protection domains. |
2430 | * | |
c432f3df JR |
2431 | * If the driver core informs the DMA layer if a driver grabs a device |
2432 | * we don't need to preallocate the protection domains anymore. | |
2433 | * For now we have to. | |
2434 | */ | |
0e93dd88 | 2435 | static void prealloc_protection_domains(void) |
c432f3df JR |
2436 | { |
2437 | struct pci_dev *dev = NULL; | |
2438 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2439 | u16 devid; |
c432f3df | 2440 | |
d18c69d3 | 2441 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2442 | |
2443 | /* Do we handle this device? */ | |
2444 | if (!check_device(&dev->dev)) | |
c432f3df | 2445 | continue; |
98fc5a69 JR |
2446 | |
2447 | /* Is there already any domain for it? */ | |
15898bbc | 2448 | if (domain_for_device(&dev->dev)) |
c432f3df | 2449 | continue; |
98fc5a69 JR |
2450 | |
2451 | devid = get_device_id(&dev->dev); | |
2452 | ||
87a64d52 | 2453 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2454 | if (!dma_dom) |
2455 | continue; | |
2456 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2457 | dma_dom->target_dev = devid; |
2458 | ||
15898bbc | 2459 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2460 | |
bd60b735 | 2461 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2462 | } |
2463 | } | |
2464 | ||
160c1d8e | 2465 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2466 | .alloc_coherent = alloc_coherent, |
2467 | .free_coherent = free_coherent, | |
51491367 FT |
2468 | .map_page = map_page, |
2469 | .unmap_page = unmap_page, | |
6631ee9d JR |
2470 | .map_sg = map_sg, |
2471 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2472 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2473 | }; |
2474 | ||
27c2127a JR |
2475 | static unsigned device_dma_ops_init(void) |
2476 | { | |
2477 | struct pci_dev *pdev = NULL; | |
2478 | unsigned unhandled = 0; | |
2479 | ||
2480 | for_each_pci_dev(pdev) { | |
2481 | if (!check_device(&pdev->dev)) { | |
2482 | unhandled += 1; | |
2483 | continue; | |
2484 | } | |
2485 | ||
2486 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2487 | } | |
2488 | ||
2489 | return unhandled; | |
2490 | } | |
2491 | ||
431b2a20 JR |
2492 | /* |
2493 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2494 | */ | |
f5325094 JR |
2495 | |
2496 | void __init amd_iommu_init_api(void) | |
2497 | { | |
2cc21c42 | 2498 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2499 | } |
2500 | ||
6631ee9d JR |
2501 | int __init amd_iommu_init_dma_ops(void) |
2502 | { | |
2503 | struct amd_iommu *iommu; | |
27c2127a | 2504 | int ret, unhandled; |
6631ee9d | 2505 | |
431b2a20 JR |
2506 | /* |
2507 | * first allocate a default protection domain for every IOMMU we | |
2508 | * found in the system. Devices not assigned to any other | |
2509 | * protection domain will be assigned to the default one. | |
2510 | */ | |
3bd22172 | 2511 | for_each_iommu(iommu) { |
87a64d52 | 2512 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2513 | if (iommu->default_dom == NULL) |
2514 | return -ENOMEM; | |
e2dc14a2 | 2515 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2516 | ret = iommu_init_unity_mappings(iommu); |
2517 | if (ret) | |
2518 | goto free_domains; | |
2519 | } | |
2520 | ||
431b2a20 | 2521 | /* |
8793abeb | 2522 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2523 | */ |
8793abeb | 2524 | prealloc_protection_domains(); |
6631ee9d JR |
2525 | |
2526 | iommu_detected = 1; | |
75f1cdf1 | 2527 | swiotlb = 0; |
6631ee9d | 2528 | |
431b2a20 | 2529 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2530 | unhandled = device_dma_ops_init(); |
2531 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2532 | /* There are unhandled devices - initialize swiotlb for them */ | |
2533 | swiotlb = 1; | |
2534 | } | |
6631ee9d | 2535 | |
7f26508b JR |
2536 | amd_iommu_stats_init(); |
2537 | ||
6631ee9d JR |
2538 | return 0; |
2539 | ||
2540 | free_domains: | |
2541 | ||
3bd22172 | 2542 | for_each_iommu(iommu) { |
6631ee9d JR |
2543 | if (iommu->default_dom) |
2544 | dma_ops_domain_free(iommu->default_dom); | |
2545 | } | |
2546 | ||
2547 | return ret; | |
2548 | } | |
6d98cd80 JR |
2549 | |
2550 | /***************************************************************************** | |
2551 | * | |
2552 | * The following functions belong to the exported interface of AMD IOMMU | |
2553 | * | |
2554 | * This interface allows access to lower level functions of the IOMMU | |
2555 | * like protection domain handling and assignement of devices to domains | |
2556 | * which is not possible with the dma_ops interface. | |
2557 | * | |
2558 | *****************************************************************************/ | |
2559 | ||
6d98cd80 JR |
2560 | static void cleanup_domain(struct protection_domain *domain) |
2561 | { | |
492667da | 2562 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2563 | unsigned long flags; |
6d98cd80 JR |
2564 | |
2565 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2566 | ||
492667da | 2567 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2568 | __detach_device(dev_data); |
492667da JR |
2569 | atomic_set(&dev_data->bind, 0); |
2570 | } | |
6d98cd80 JR |
2571 | |
2572 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2573 | } | |
2574 | ||
2650815f JR |
2575 | static void protection_domain_free(struct protection_domain *domain) |
2576 | { | |
2577 | if (!domain) | |
2578 | return; | |
2579 | ||
aeb26f55 JR |
2580 | del_domain_from_list(domain); |
2581 | ||
2650815f JR |
2582 | if (domain->id) |
2583 | domain_id_free(domain->id); | |
2584 | ||
2585 | kfree(domain); | |
2586 | } | |
2587 | ||
2588 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2589 | { |
2590 | struct protection_domain *domain; | |
2591 | ||
2592 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2593 | if (!domain) | |
2650815f | 2594 | return NULL; |
c156e347 JR |
2595 | |
2596 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2597 | mutex_init(&domain->api_lock); |
c156e347 JR |
2598 | domain->id = domain_id_alloc(); |
2599 | if (!domain->id) | |
2650815f | 2600 | goto out_err; |
7c392cbe | 2601 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2602 | |
aeb26f55 JR |
2603 | add_domain_to_list(domain); |
2604 | ||
2650815f JR |
2605 | return domain; |
2606 | ||
2607 | out_err: | |
2608 | kfree(domain); | |
2609 | ||
2610 | return NULL; | |
2611 | } | |
2612 | ||
2613 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2614 | { | |
2615 | struct protection_domain *domain; | |
2616 | ||
2617 | domain = protection_domain_alloc(); | |
2618 | if (!domain) | |
c156e347 | 2619 | goto out_free; |
2650815f JR |
2620 | |
2621 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2622 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2623 | if (!domain->pt_root) | |
2624 | goto out_free; | |
2625 | ||
2626 | dom->priv = domain; | |
2627 | ||
2628 | return 0; | |
2629 | ||
2630 | out_free: | |
2650815f | 2631 | protection_domain_free(domain); |
c156e347 JR |
2632 | |
2633 | return -ENOMEM; | |
2634 | } | |
2635 | ||
98383fc3 JR |
2636 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2637 | { | |
2638 | struct protection_domain *domain = dom->priv; | |
2639 | ||
2640 | if (!domain) | |
2641 | return; | |
2642 | ||
2643 | if (domain->dev_cnt > 0) | |
2644 | cleanup_domain(domain); | |
2645 | ||
2646 | BUG_ON(domain->dev_cnt != 0); | |
2647 | ||
2648 | free_pagetable(domain); | |
2649 | ||
8b408fe4 | 2650 | protection_domain_free(domain); |
98383fc3 JR |
2651 | |
2652 | dom->priv = NULL; | |
2653 | } | |
2654 | ||
684f2888 JR |
2655 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2656 | struct device *dev) | |
2657 | { | |
657cbb6b | 2658 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2659 | struct amd_iommu *iommu; |
684f2888 JR |
2660 | u16 devid; |
2661 | ||
98fc5a69 | 2662 | if (!check_device(dev)) |
684f2888 JR |
2663 | return; |
2664 | ||
98fc5a69 | 2665 | devid = get_device_id(dev); |
684f2888 | 2666 | |
657cbb6b | 2667 | if (dev_data->domain != NULL) |
15898bbc | 2668 | detach_device(dev); |
684f2888 JR |
2669 | |
2670 | iommu = amd_iommu_rlookup_table[devid]; | |
2671 | if (!iommu) | |
2672 | return; | |
2673 | ||
684f2888 JR |
2674 | iommu_completion_wait(iommu); |
2675 | } | |
2676 | ||
01106066 JR |
2677 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2678 | struct device *dev) | |
2679 | { | |
2680 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2681 | struct iommu_dev_data *dev_data; |
01106066 | 2682 | struct amd_iommu *iommu; |
15898bbc | 2683 | int ret; |
01106066 | 2684 | |
98fc5a69 | 2685 | if (!check_device(dev)) |
01106066 JR |
2686 | return -EINVAL; |
2687 | ||
657cbb6b JR |
2688 | dev_data = dev->archdata.iommu; |
2689 | ||
f62dda66 | 2690 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2691 | if (!iommu) |
2692 | return -EINVAL; | |
2693 | ||
657cbb6b | 2694 | if (dev_data->domain) |
15898bbc | 2695 | detach_device(dev); |
01106066 | 2696 | |
15898bbc | 2697 | ret = attach_device(dev, domain); |
01106066 JR |
2698 | |
2699 | iommu_completion_wait(iommu); | |
2700 | ||
15898bbc | 2701 | return ret; |
01106066 JR |
2702 | } |
2703 | ||
468e2366 JR |
2704 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2705 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2706 | { |
468e2366 | 2707 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2708 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2709 | int prot = 0; |
2710 | int ret; | |
2711 | ||
2712 | if (iommu_prot & IOMMU_READ) | |
2713 | prot |= IOMMU_PROT_IR; | |
2714 | if (iommu_prot & IOMMU_WRITE) | |
2715 | prot |= IOMMU_PROT_IW; | |
2716 | ||
5d214fe6 | 2717 | mutex_lock(&domain->api_lock); |
795e74f7 | 2718 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2719 | mutex_unlock(&domain->api_lock); |
2720 | ||
795e74f7 | 2721 | return ret; |
c6229ca6 JR |
2722 | } |
2723 | ||
468e2366 JR |
2724 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2725 | int gfp_order) | |
eb74ff6c | 2726 | { |
eb74ff6c | 2727 | struct protection_domain *domain = dom->priv; |
468e2366 | 2728 | unsigned long page_size, unmap_size; |
eb74ff6c | 2729 | |
468e2366 | 2730 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2731 | |
5d214fe6 | 2732 | mutex_lock(&domain->api_lock); |
468e2366 | 2733 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2734 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2735 | |
17b124bf | 2736 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2737 | |
468e2366 | 2738 | return get_order(unmap_size); |
eb74ff6c JR |
2739 | } |
2740 | ||
645c4c8d JR |
2741 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2742 | unsigned long iova) | |
2743 | { | |
2744 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2745 | unsigned long offset_mask; |
645c4c8d | 2746 | phys_addr_t paddr; |
f03152bb | 2747 | u64 *pte, __pte; |
645c4c8d | 2748 | |
24cd7723 | 2749 | pte = fetch_pte(domain, iova); |
645c4c8d | 2750 | |
a6d41a40 | 2751 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2752 | return 0; |
2753 | ||
f03152bb JR |
2754 | if (PM_PTE_LEVEL(*pte) == 0) |
2755 | offset_mask = PAGE_SIZE - 1; | |
2756 | else | |
2757 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2758 | ||
2759 | __pte = *pte & PM_ADDR_MASK; | |
2760 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2761 | |
2762 | return paddr; | |
2763 | } | |
2764 | ||
dbb9fd86 SY |
2765 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2766 | unsigned long cap) | |
2767 | { | |
80a506b8 JR |
2768 | switch (cap) { |
2769 | case IOMMU_CAP_CACHE_COHERENCY: | |
2770 | return 1; | |
2771 | } | |
2772 | ||
dbb9fd86 SY |
2773 | return 0; |
2774 | } | |
2775 | ||
26961efe JR |
2776 | static struct iommu_ops amd_iommu_ops = { |
2777 | .domain_init = amd_iommu_domain_init, | |
2778 | .domain_destroy = amd_iommu_domain_destroy, | |
2779 | .attach_dev = amd_iommu_attach_device, | |
2780 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2781 | .map = amd_iommu_map, |
2782 | .unmap = amd_iommu_unmap, | |
26961efe | 2783 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2784 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2785 | }; |
2786 | ||
0feae533 JR |
2787 | /***************************************************************************** |
2788 | * | |
2789 | * The next functions do a basic initialization of IOMMU for pass through | |
2790 | * mode | |
2791 | * | |
2792 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2793 | * DMA-API translation. | |
2794 | * | |
2795 | *****************************************************************************/ | |
2796 | ||
2797 | int __init amd_iommu_init_passthrough(void) | |
2798 | { | |
15898bbc | 2799 | struct amd_iommu *iommu; |
0feae533 | 2800 | struct pci_dev *dev = NULL; |
15898bbc | 2801 | u16 devid; |
0feae533 | 2802 | |
af901ca1 | 2803 | /* allocate passthrough domain */ |
0feae533 JR |
2804 | pt_domain = protection_domain_alloc(); |
2805 | if (!pt_domain) | |
2806 | return -ENOMEM; | |
2807 | ||
2808 | pt_domain->mode |= PAGE_MODE_NONE; | |
2809 | ||
6c54aabd | 2810 | for_each_pci_dev(dev) { |
98fc5a69 | 2811 | if (!check_device(&dev->dev)) |
0feae533 JR |
2812 | continue; |
2813 | ||
98fc5a69 JR |
2814 | devid = get_device_id(&dev->dev); |
2815 | ||
15898bbc | 2816 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2817 | if (!iommu) |
2818 | continue; | |
2819 | ||
15898bbc | 2820 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2821 | } |
2822 | ||
2823 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2824 | ||
2825 | return 0; | |
2826 | } |