Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
7c71d306 | 37 | #include <linux/irqdomain.h> |
5f6bed50 | 38 | #include <linux/percpu.h> |
2b324506 JR |
39 | #include <asm/irq_remapping.h> |
40 | #include <asm/io_apic.h> | |
41 | #include <asm/apic.h> | |
42 | #include <asm/hw_irq.h> | |
17f5b569 | 43 | #include <asm/msidef.h> |
b6c02715 | 44 | #include <asm/proto.h> |
46a7fa27 | 45 | #include <asm/iommu.h> |
1d9b16d1 | 46 | #include <asm/gart.h> |
27c2127a | 47 | #include <asm/dma.h> |
403f81d8 JR |
48 | |
49 | #include "amd_iommu_proto.h" | |
50 | #include "amd_iommu_types.h" | |
6b474b82 | 51 | #include "irq_remapping.h" |
b6c02715 JR |
52 | |
53 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
54 | ||
815b33fd | 55 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 56 | |
aa3de9c0 OBC |
57 | /* |
58 | * This bitmap is used to advertise the page sizes our hardware support | |
59 | * to the IOMMU core, which will then use this information to split | |
60 | * physically contiguous memory regions it is mapping into page sizes | |
61 | * that we support. | |
62 | * | |
954e3dd8 | 63 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 64 | */ |
954e3dd8 | 65 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 66 | |
b6c02715 JR |
67 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
68 | ||
8fa5f802 JR |
69 | /* List of all available dev_data structures */ |
70 | static LIST_HEAD(dev_data_list); | |
71 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
72 | ||
6efed63b JR |
73 | LIST_HEAD(ioapic_map); |
74 | LIST_HEAD(hpet_map); | |
75 | ||
0feae533 JR |
76 | /* |
77 | * Domain for untranslated devices - only allocated | |
78 | * if iommu=pt passed on kernel cmd line. | |
79 | */ | |
b22f6434 | 80 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 81 | |
72e1dcc4 | 82 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 83 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 84 | |
ac1534a5 JR |
85 | static struct dma_map_ops amd_iommu_dma_ops; |
86 | ||
50917e26 JR |
87 | /* |
88 | * This struct contains device specific data for the IOMMU | |
89 | */ | |
90 | struct iommu_dev_data { | |
91 | struct list_head list; /* For domain->dev_list */ | |
92 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 93 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 JR |
94 | u16 devid; /* PCI Device ID */ |
95 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
1e6a7b04 | 96 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
97 | struct { |
98 | bool enabled; | |
99 | int qdep; | |
100 | } ats; /* ATS state */ | |
101 | bool pri_tlp; /* PASID TLB required for | |
102 | PPR completions */ | |
103 | u32 errata; /* Bitmap for errata to apply */ | |
104 | }; | |
105 | ||
431b2a20 JR |
106 | /* |
107 | * general struct to manage commands send to an IOMMU | |
108 | */ | |
d6449536 | 109 | struct iommu_cmd { |
b6c02715 JR |
110 | u32 data[4]; |
111 | }; | |
112 | ||
05152a04 JR |
113 | struct kmem_cache *amd_iommu_irq_cache; |
114 | ||
04bfdd84 | 115 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 116 | static int protection_domain_init(struct protection_domain *domain); |
c1eee67b | 117 | |
007b74ba JR |
118 | /* |
119 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
120 | * DMA address space each. This struct represents one such range. | |
121 | */ | |
122 | struct aperture_range { | |
123 | ||
08c5fb93 JR |
124 | spinlock_t bitmap_lock; |
125 | ||
007b74ba JR |
126 | /* address allocation bitmap */ |
127 | unsigned long *bitmap; | |
ae62d49c | 128 | unsigned long offset; |
60e6a7cb | 129 | unsigned long next_bit; |
007b74ba JR |
130 | |
131 | /* | |
132 | * Array of PTE pages for the aperture. In this array we save all the | |
133 | * leaf pages of the domain page table used for the aperture. This way | |
134 | * we don't need to walk the page table to find a specific PTE. We can | |
135 | * just calculate its address in constant time. | |
136 | */ | |
137 | u64 *pte_pages[64]; | |
007b74ba JR |
138 | }; |
139 | ||
140 | /* | |
141 | * Data container for a dma_ops specific protection domain | |
142 | */ | |
143 | struct dma_ops_domain { | |
144 | /* generic protection domain information */ | |
145 | struct protection_domain domain; | |
146 | ||
147 | /* size of the aperture for the mappings */ | |
148 | unsigned long aperture_size; | |
149 | ||
ebaecb42 | 150 | /* aperture index we start searching for free addresses */ |
5f6bed50 | 151 | u32 __percpu *next_index; |
007b74ba JR |
152 | |
153 | /* address space relevant data */ | |
154 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; | |
007b74ba JR |
155 | }; |
156 | ||
15898bbc JR |
157 | /**************************************************************************** |
158 | * | |
159 | * Helper functions | |
160 | * | |
161 | ****************************************************************************/ | |
162 | ||
3f4b87b9 JR |
163 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
164 | { | |
165 | return container_of(dom, struct protection_domain, domain); | |
166 | } | |
167 | ||
f62dda66 | 168 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
169 | { |
170 | struct iommu_dev_data *dev_data; | |
171 | unsigned long flags; | |
172 | ||
173 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
174 | if (!dev_data) | |
175 | return NULL; | |
176 | ||
f62dda66 | 177 | dev_data->devid = devid; |
8fa5f802 JR |
178 | |
179 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
180 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
181 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
182 | ||
183 | return dev_data; | |
184 | } | |
185 | ||
3b03bb74 JR |
186 | static struct iommu_dev_data *search_dev_data(u16 devid) |
187 | { | |
188 | struct iommu_dev_data *dev_data; | |
189 | unsigned long flags; | |
190 | ||
191 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
192 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
193 | if (dev_data->devid == devid) | |
194 | goto out_unlock; | |
195 | } | |
196 | ||
197 | dev_data = NULL; | |
198 | ||
199 | out_unlock: | |
200 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
201 | ||
202 | return dev_data; | |
203 | } | |
204 | ||
205 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
206 | { | |
207 | struct iommu_dev_data *dev_data; | |
208 | ||
209 | dev_data = search_dev_data(devid); | |
210 | ||
211 | if (dev_data == NULL) | |
212 | dev_data = alloc_dev_data(devid); | |
213 | ||
214 | return dev_data; | |
215 | } | |
216 | ||
15898bbc JR |
217 | static inline u16 get_device_id(struct device *dev) |
218 | { | |
219 | struct pci_dev *pdev = to_pci_dev(dev); | |
220 | ||
6f2729ba | 221 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
222 | } |
223 | ||
657cbb6b JR |
224 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
225 | { | |
226 | return dev->archdata.iommu; | |
227 | } | |
228 | ||
5abcdba4 JR |
229 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
230 | { | |
231 | static const int caps[] = { | |
232 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
233 | PCI_EXT_CAP_ID_PRI, |
234 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
235 | }; |
236 | int i, pos; | |
237 | ||
238 | for (i = 0; i < 3; ++i) { | |
239 | pos = pci_find_ext_capability(pdev, caps[i]); | |
240 | if (pos == 0) | |
241 | return false; | |
242 | } | |
243 | ||
244 | return true; | |
245 | } | |
246 | ||
6a113ddc JR |
247 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
248 | { | |
249 | struct iommu_dev_data *dev_data; | |
250 | ||
251 | dev_data = get_dev_data(&pdev->dev); | |
252 | ||
253 | return dev_data->errata & (1 << erratum) ? true : false; | |
254 | } | |
255 | ||
71c70984 | 256 | /* |
0bb6e243 JR |
257 | * This function actually applies the mapping to the page table of the |
258 | * dma_ops domain. | |
71c70984 | 259 | */ |
0bb6e243 JR |
260 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
261 | struct unity_map_entry *e) | |
71c70984 | 262 | { |
0bb6e243 | 263 | u64 addr; |
71c70984 | 264 | |
0bb6e243 JR |
265 | for (addr = e->address_start; addr < e->address_end; |
266 | addr += PAGE_SIZE) { | |
267 | if (addr < dma_dom->aperture_size) | |
268 | __set_bit(addr >> PAGE_SHIFT, | |
269 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 270 | } |
0bb6e243 | 271 | } |
71c70984 | 272 | |
0bb6e243 JR |
273 | /* |
274 | * Inits the unity mappings required for a specific device | |
275 | */ | |
276 | static void init_unity_mappings_for_device(struct device *dev, | |
277 | struct dma_ops_domain *dma_dom) | |
278 | { | |
279 | struct unity_map_entry *e; | |
280 | u16 devid; | |
71c70984 | 281 | |
0bb6e243 | 282 | devid = get_device_id(dev); |
71c70984 | 283 | |
0bb6e243 JR |
284 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
285 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
286 | continue; | |
287 | alloc_unity_mapping(dma_dom, e); | |
288 | } | |
71c70984 JR |
289 | } |
290 | ||
98fc5a69 JR |
291 | /* |
292 | * This function checks if the driver got a valid device from the caller to | |
293 | * avoid dereferencing invalid pointers. | |
294 | */ | |
295 | static bool check_device(struct device *dev) | |
296 | { | |
297 | u16 devid; | |
298 | ||
299 | if (!dev || !dev->dma_mask) | |
300 | return false; | |
301 | ||
b82a2272 YW |
302 | /* No PCI device */ |
303 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
304 | return false; |
305 | ||
306 | devid = get_device_id(dev); | |
307 | ||
308 | /* Out of our scope? */ | |
309 | if (devid > amd_iommu_last_bdf) | |
310 | return false; | |
311 | ||
312 | if (amd_iommu_rlookup_table[devid] == NULL) | |
313 | return false; | |
314 | ||
315 | return true; | |
316 | } | |
317 | ||
25b11ce2 | 318 | static void init_iommu_group(struct device *dev) |
2851db21 | 319 | { |
0bb6e243 JR |
320 | struct dma_ops_domain *dma_domain; |
321 | struct iommu_domain *domain; | |
2851db21 | 322 | struct iommu_group *group; |
2851db21 | 323 | |
65d5352f | 324 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
325 | if (IS_ERR(group)) |
326 | return; | |
327 | ||
328 | domain = iommu_group_default_domain(group); | |
329 | if (!domain) | |
330 | goto out; | |
331 | ||
332 | dma_domain = to_pdomain(domain)->priv; | |
333 | ||
334 | init_unity_mappings_for_device(dev, dma_domain); | |
335 | out: | |
336 | iommu_group_put(group); | |
eb9c9527 AW |
337 | } |
338 | ||
339 | static int iommu_init_device(struct device *dev) | |
340 | { | |
341 | struct pci_dev *pdev = to_pci_dev(dev); | |
342 | struct iommu_dev_data *dev_data; | |
eb9c9527 AW |
343 | |
344 | if (dev->archdata.iommu) | |
345 | return 0; | |
346 | ||
347 | dev_data = find_dev_data(get_device_id(dev)); | |
348 | if (!dev_data) | |
349 | return -ENOMEM; | |
350 | ||
5abcdba4 JR |
351 | if (pci_iommuv2_capable(pdev)) { |
352 | struct amd_iommu *iommu; | |
353 | ||
354 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
355 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
356 | } | |
357 | ||
657cbb6b JR |
358 | dev->archdata.iommu = dev_data; |
359 | ||
066f2e98 AW |
360 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
361 | dev); | |
362 | ||
657cbb6b JR |
363 | return 0; |
364 | } | |
365 | ||
26018874 JR |
366 | static void iommu_ignore_device(struct device *dev) |
367 | { | |
368 | u16 devid, alias; | |
369 | ||
370 | devid = get_device_id(dev); | |
371 | alias = amd_iommu_alias_table[devid]; | |
372 | ||
373 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
374 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
375 | ||
376 | amd_iommu_rlookup_table[devid] = NULL; | |
377 | amd_iommu_rlookup_table[alias] = NULL; | |
378 | } | |
379 | ||
657cbb6b JR |
380 | static void iommu_uninit_device(struct device *dev) |
381 | { | |
c1931090 AW |
382 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
383 | ||
384 | if (!dev_data) | |
385 | return; | |
386 | ||
066f2e98 AW |
387 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
388 | dev); | |
389 | ||
9dcd6130 AW |
390 | iommu_group_remove_device(dev); |
391 | ||
aafd8ba0 JR |
392 | /* Remove dma-ops */ |
393 | dev->archdata.dma_ops = NULL; | |
394 | ||
8fa5f802 | 395 | /* |
c1931090 AW |
396 | * We keep dev_data around for unplugged devices and reuse it when the |
397 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 398 | */ |
657cbb6b | 399 | } |
b7cc9554 | 400 | |
7f26508b JR |
401 | #ifdef CONFIG_AMD_IOMMU_STATS |
402 | ||
403 | /* | |
404 | * Initialization code for statistics collection | |
405 | */ | |
406 | ||
da49f6df | 407 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 408 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 409 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 410 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 411 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 412 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 413 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 414 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 415 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 416 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 417 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 418 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
419 | DECLARE_STATS_COUNTER(complete_ppr); |
420 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
421 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
422 | DECLARE_STATS_COUNTER(pri_requests); | |
423 | ||
7f26508b | 424 | static struct dentry *stats_dir; |
7f26508b JR |
425 | static struct dentry *de_fflush; |
426 | ||
427 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
428 | { | |
429 | if (stats_dir == NULL) | |
430 | return; | |
431 | ||
432 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
433 | &cnt->value); | |
434 | } | |
435 | ||
436 | static void amd_iommu_stats_init(void) | |
437 | { | |
438 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
439 | if (stats_dir == NULL) | |
440 | return; | |
441 | ||
7f26508b | 442 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 443 | &amd_iommu_unmap_flush); |
da49f6df JR |
444 | |
445 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 446 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 447 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 448 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 449 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 450 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 451 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 452 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 453 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 454 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 455 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 456 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
457 | amd_iommu_stats_add(&complete_ppr); |
458 | amd_iommu_stats_add(&invalidate_iotlb); | |
459 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
460 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
461 | } |
462 | ||
463 | #endif | |
464 | ||
a80dc3e0 JR |
465 | /**************************************************************************** |
466 | * | |
467 | * Interrupt handling functions | |
468 | * | |
469 | ****************************************************************************/ | |
470 | ||
e3e59876 JR |
471 | static void dump_dte_entry(u16 devid) |
472 | { | |
473 | int i; | |
474 | ||
ee6c2868 JR |
475 | for (i = 0; i < 4; ++i) |
476 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
477 | amd_iommu_dev_table[devid].data[i]); |
478 | } | |
479 | ||
945b4ac4 JR |
480 | static void dump_command(unsigned long phys_addr) |
481 | { | |
482 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
483 | int i; | |
484 | ||
485 | for (i = 0; i < 4; ++i) | |
486 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
487 | } | |
488 | ||
a345b23b | 489 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 490 | { |
3d06fca8 JR |
491 | int type, devid, domid, flags; |
492 | volatile u32 *event = __evt; | |
493 | int count = 0; | |
494 | u64 address; | |
495 | ||
496 | retry: | |
497 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
498 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
499 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
500 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
501 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
502 | ||
503 | if (type == 0) { | |
504 | /* Did we hit the erratum? */ | |
505 | if (++count == LOOP_TIMEOUT) { | |
506 | pr_err("AMD-Vi: No event written to event log\n"); | |
507 | return; | |
508 | } | |
509 | udelay(1); | |
510 | goto retry; | |
511 | } | |
90008ee4 | 512 | |
4c6f40d4 | 513 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
514 | |
515 | switch (type) { | |
516 | case EVENT_TYPE_ILL_DEV: | |
517 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
518 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 519 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 520 | address, flags); |
e3e59876 | 521 | dump_dte_entry(devid); |
90008ee4 JR |
522 | break; |
523 | case EVENT_TYPE_IO_FAULT: | |
524 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
525 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 526 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
527 | domid, address, flags); |
528 | break; | |
529 | case EVENT_TYPE_DEV_TAB_ERR: | |
530 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
531 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 532 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
533 | address, flags); |
534 | break; | |
535 | case EVENT_TYPE_PAGE_TAB_ERR: | |
536 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
537 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 538 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
539 | domid, address, flags); |
540 | break; | |
541 | case EVENT_TYPE_ILL_CMD: | |
542 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 543 | dump_command(address); |
90008ee4 JR |
544 | break; |
545 | case EVENT_TYPE_CMD_HARD_ERR: | |
546 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
547 | "flags=0x%04x]\n", address, flags); | |
548 | break; | |
549 | case EVENT_TYPE_IOTLB_INV_TO: | |
550 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
551 | "address=0x%016llx]\n", | |
c5081cd7 | 552 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
553 | address); |
554 | break; | |
555 | case EVENT_TYPE_INV_DEV_REQ: | |
556 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
557 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 558 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
559 | address, flags); |
560 | break; | |
561 | default: | |
562 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
563 | } | |
3d06fca8 JR |
564 | |
565 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
566 | } |
567 | ||
568 | static void iommu_poll_events(struct amd_iommu *iommu) | |
569 | { | |
570 | u32 head, tail; | |
90008ee4 JR |
571 | |
572 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
573 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
574 | ||
575 | while (head != tail) { | |
a345b23b | 576 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 577 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
578 | } |
579 | ||
580 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
581 | } |
582 | ||
eee53537 | 583 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
584 | { |
585 | struct amd_iommu_fault fault; | |
72e1dcc4 | 586 | |
399be2f5 JR |
587 | INC_STATS_COUNTER(pri_requests); |
588 | ||
72e1dcc4 JR |
589 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
590 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
591 | return; | |
592 | } | |
593 | ||
594 | fault.address = raw[1]; | |
595 | fault.pasid = PPR_PASID(raw[0]); | |
596 | fault.device_id = PPR_DEVID(raw[0]); | |
597 | fault.tag = PPR_TAG(raw[0]); | |
598 | fault.flags = PPR_FLAGS(raw[0]); | |
599 | ||
72e1dcc4 JR |
600 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
601 | } | |
602 | ||
603 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
604 | { | |
72e1dcc4 JR |
605 | u32 head, tail; |
606 | ||
607 | if (iommu->ppr_log == NULL) | |
608 | return; | |
609 | ||
72e1dcc4 JR |
610 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
611 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
612 | ||
613 | while (head != tail) { | |
eee53537 JR |
614 | volatile u64 *raw; |
615 | u64 entry[2]; | |
616 | int i; | |
617 | ||
618 | raw = (u64 *)(iommu->ppr_log + head); | |
619 | ||
620 | /* | |
621 | * Hardware bug: Interrupt may arrive before the entry is | |
622 | * written to memory. If this happens we need to wait for the | |
623 | * entry to arrive. | |
624 | */ | |
625 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
626 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
627 | break; | |
628 | udelay(1); | |
629 | } | |
72e1dcc4 | 630 | |
eee53537 JR |
631 | /* Avoid memcpy function-call overhead */ |
632 | entry[0] = raw[0]; | |
633 | entry[1] = raw[1]; | |
72e1dcc4 | 634 | |
eee53537 JR |
635 | /* |
636 | * To detect the hardware bug we need to clear the entry | |
637 | * back to zero. | |
638 | */ | |
639 | raw[0] = raw[1] = 0UL; | |
640 | ||
641 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
642 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
643 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 644 | |
eee53537 JR |
645 | /* Handle PPR entry */ |
646 | iommu_handle_ppr_entry(iommu, entry); | |
647 | ||
eee53537 JR |
648 | /* Refresh ring-buffer information */ |
649 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
650 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
651 | } | |
72e1dcc4 JR |
652 | } |
653 | ||
72fe00f0 | 654 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 655 | { |
3f398bc7 SS |
656 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
657 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 658 | |
3f398bc7 SS |
659 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
660 | /* Enable EVT and PPR interrupts again */ | |
661 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
662 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 663 | |
3f398bc7 SS |
664 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
665 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
666 | iommu_poll_events(iommu); | |
667 | } | |
90008ee4 | 668 | |
3f398bc7 SS |
669 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
670 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
671 | iommu_poll_ppr_log(iommu); | |
672 | } | |
90008ee4 | 673 | |
3f398bc7 SS |
674 | /* |
675 | * Hardware bug: ERBT1312 | |
676 | * When re-enabling interrupt (by writing 1 | |
677 | * to clear the bit), the hardware might also try to set | |
678 | * the interrupt bit in the event status register. | |
679 | * In this scenario, the bit will be set, and disable | |
680 | * subsequent interrupts. | |
681 | * | |
682 | * Workaround: The IOMMU driver should read back the | |
683 | * status register and check if the interrupt bits are cleared. | |
684 | * If not, driver will need to go through the interrupt handler | |
685 | * again and re-clear the bits | |
686 | */ | |
687 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
688 | } | |
90008ee4 | 689 | return IRQ_HANDLED; |
a80dc3e0 JR |
690 | } |
691 | ||
72fe00f0 JR |
692 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
693 | { | |
694 | return IRQ_WAKE_THREAD; | |
695 | } | |
696 | ||
431b2a20 JR |
697 | /**************************************************************************** |
698 | * | |
699 | * IOMMU command queuing functions | |
700 | * | |
701 | ****************************************************************************/ | |
702 | ||
ac0ea6e9 JR |
703 | static int wait_on_sem(volatile u64 *sem) |
704 | { | |
705 | int i = 0; | |
706 | ||
707 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
708 | udelay(1); | |
709 | i += 1; | |
710 | } | |
711 | ||
712 | if (i == LOOP_TIMEOUT) { | |
713 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
714 | return -EIO; | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
721 | struct iommu_cmd *cmd, | |
722 | u32 tail) | |
a19ae1ec | 723 | { |
a19ae1ec JR |
724 | u8 *target; |
725 | ||
8a7c5ef3 | 726 | target = iommu->cmd_buf + tail; |
deba4bce | 727 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
728 | |
729 | /* Copy command to buffer */ | |
730 | memcpy(target, cmd, sizeof(*cmd)); | |
731 | ||
732 | /* Tell the IOMMU about it */ | |
a19ae1ec | 733 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 734 | } |
a19ae1ec | 735 | |
815b33fd | 736 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 737 | { |
815b33fd JR |
738 | WARN_ON(address & 0x7ULL); |
739 | ||
ded46737 | 740 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
741 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
742 | cmd->data[1] = upper_32_bits(__pa(address)); | |
743 | cmd->data[2] = 1; | |
ded46737 JR |
744 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
745 | } | |
746 | ||
94fe79e2 JR |
747 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
748 | { | |
749 | memset(cmd, 0, sizeof(*cmd)); | |
750 | cmd->data[0] = devid; | |
751 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
752 | } | |
753 | ||
11b6402c JR |
754 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
755 | size_t size, u16 domid, int pde) | |
756 | { | |
757 | u64 pages; | |
ae0cbbb1 | 758 | bool s; |
11b6402c JR |
759 | |
760 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 761 | s = false; |
11b6402c JR |
762 | |
763 | if (pages > 1) { | |
764 | /* | |
765 | * If we have to flush more than one page, flush all | |
766 | * TLB entries for this domain | |
767 | */ | |
768 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 769 | s = true; |
11b6402c JR |
770 | } |
771 | ||
772 | address &= PAGE_MASK; | |
773 | ||
774 | memset(cmd, 0, sizeof(*cmd)); | |
775 | cmd->data[1] |= domid; | |
776 | cmd->data[2] = lower_32_bits(address); | |
777 | cmd->data[3] = upper_32_bits(address); | |
778 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
779 | if (s) /* size bit - we flush more than one 4kb page */ | |
780 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 781 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
782 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
783 | } | |
784 | ||
cb41ed85 JR |
785 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
786 | u64 address, size_t size) | |
787 | { | |
788 | u64 pages; | |
ae0cbbb1 | 789 | bool s; |
cb41ed85 JR |
790 | |
791 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 792 | s = false; |
cb41ed85 JR |
793 | |
794 | if (pages > 1) { | |
795 | /* | |
796 | * If we have to flush more than one page, flush all | |
797 | * TLB entries for this domain | |
798 | */ | |
799 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 800 | s = true; |
cb41ed85 JR |
801 | } |
802 | ||
803 | address &= PAGE_MASK; | |
804 | ||
805 | memset(cmd, 0, sizeof(*cmd)); | |
806 | cmd->data[0] = devid; | |
807 | cmd->data[0] |= (qdep & 0xff) << 24; | |
808 | cmd->data[1] = devid; | |
809 | cmd->data[2] = lower_32_bits(address); | |
810 | cmd->data[3] = upper_32_bits(address); | |
811 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
812 | if (s) | |
813 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
814 | } | |
815 | ||
22e266c7 JR |
816 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
817 | u64 address, bool size) | |
818 | { | |
819 | memset(cmd, 0, sizeof(*cmd)); | |
820 | ||
821 | address &= ~(0xfffULL); | |
822 | ||
a919a018 | 823 | cmd->data[0] = pasid; |
22e266c7 JR |
824 | cmd->data[1] = domid; |
825 | cmd->data[2] = lower_32_bits(address); | |
826 | cmd->data[3] = upper_32_bits(address); | |
827 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
828 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
829 | if (size) | |
830 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
831 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
832 | } | |
833 | ||
834 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
835 | int qdep, u64 address, bool size) | |
836 | { | |
837 | memset(cmd, 0, sizeof(*cmd)); | |
838 | ||
839 | address &= ~(0xfffULL); | |
840 | ||
841 | cmd->data[0] = devid; | |
e8d2d82d | 842 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
843 | cmd->data[0] |= (qdep & 0xff) << 24; |
844 | cmd->data[1] = devid; | |
e8d2d82d | 845 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
846 | cmd->data[2] = lower_32_bits(address); |
847 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
848 | cmd->data[3] = upper_32_bits(address); | |
849 | if (size) | |
850 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
851 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
852 | } | |
853 | ||
c99afa25 JR |
854 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
855 | int status, int tag, bool gn) | |
856 | { | |
857 | memset(cmd, 0, sizeof(*cmd)); | |
858 | ||
859 | cmd->data[0] = devid; | |
860 | if (gn) { | |
a919a018 | 861 | cmd->data[1] = pasid; |
c99afa25 JR |
862 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
863 | } | |
864 | cmd->data[3] = tag & 0x1ff; | |
865 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
866 | ||
867 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
868 | } | |
869 | ||
58fc7f14 JR |
870 | static void build_inv_all(struct iommu_cmd *cmd) |
871 | { | |
872 | memset(cmd, 0, sizeof(*cmd)); | |
873 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
874 | } |
875 | ||
7ef2798d JR |
876 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
877 | { | |
878 | memset(cmd, 0, sizeof(*cmd)); | |
879 | cmd->data[0] = devid; | |
880 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
881 | } | |
882 | ||
431b2a20 | 883 | /* |
431b2a20 | 884 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 885 | * hardware about the new command. |
431b2a20 | 886 | */ |
f1ca1512 JR |
887 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
888 | struct iommu_cmd *cmd, | |
889 | bool sync) | |
a19ae1ec | 890 | { |
ac0ea6e9 | 891 | u32 left, tail, head, next_tail; |
a19ae1ec | 892 | unsigned long flags; |
a19ae1ec | 893 | |
ac0ea6e9 | 894 | again: |
a19ae1ec | 895 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 896 | |
ac0ea6e9 JR |
897 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
898 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
899 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
900 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 901 | |
ac0ea6e9 JR |
902 | if (left <= 2) { |
903 | struct iommu_cmd sync_cmd; | |
904 | volatile u64 sem = 0; | |
905 | int ret; | |
8d201968 | 906 | |
ac0ea6e9 JR |
907 | build_completion_wait(&sync_cmd, (u64)&sem); |
908 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 909 | |
ac0ea6e9 JR |
910 | spin_unlock_irqrestore(&iommu->lock, flags); |
911 | ||
912 | if ((ret = wait_on_sem(&sem)) != 0) | |
913 | return ret; | |
914 | ||
915 | goto again; | |
8d201968 JR |
916 | } |
917 | ||
ac0ea6e9 JR |
918 | copy_cmd_to_buffer(iommu, cmd, tail); |
919 | ||
920 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 921 | iommu->need_sync = sync; |
ac0ea6e9 | 922 | |
a19ae1ec | 923 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 924 | |
815b33fd | 925 | return 0; |
8d201968 JR |
926 | } |
927 | ||
f1ca1512 JR |
928 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
929 | { | |
930 | return iommu_queue_command_sync(iommu, cmd, true); | |
931 | } | |
932 | ||
8d201968 JR |
933 | /* |
934 | * This function queues a completion wait command into the command | |
935 | * buffer of an IOMMU | |
936 | */ | |
a19ae1ec | 937 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
938 | { |
939 | struct iommu_cmd cmd; | |
815b33fd | 940 | volatile u64 sem = 0; |
ac0ea6e9 | 941 | int ret; |
8d201968 | 942 | |
09ee17eb | 943 | if (!iommu->need_sync) |
815b33fd | 944 | return 0; |
09ee17eb | 945 | |
815b33fd | 946 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 947 | |
f1ca1512 | 948 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 949 | if (ret) |
815b33fd | 950 | return ret; |
8d201968 | 951 | |
ac0ea6e9 | 952 | return wait_on_sem(&sem); |
8d201968 JR |
953 | } |
954 | ||
d8c13085 | 955 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 956 | { |
d8c13085 | 957 | struct iommu_cmd cmd; |
a19ae1ec | 958 | |
d8c13085 | 959 | build_inv_dte(&cmd, devid); |
7e4f88da | 960 | |
d8c13085 JR |
961 | return iommu_queue_command(iommu, &cmd); |
962 | } | |
09ee17eb | 963 | |
7d0c5cc5 JR |
964 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
965 | { | |
966 | u32 devid; | |
09ee17eb | 967 | |
7d0c5cc5 JR |
968 | for (devid = 0; devid <= 0xffff; ++devid) |
969 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 970 | |
7d0c5cc5 JR |
971 | iommu_completion_wait(iommu); |
972 | } | |
84df8175 | 973 | |
7d0c5cc5 JR |
974 | /* |
975 | * This function uses heavy locking and may disable irqs for some time. But | |
976 | * this is no issue because it is only called during resume. | |
977 | */ | |
978 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
979 | { | |
980 | u32 dom_id; | |
a19ae1ec | 981 | |
7d0c5cc5 JR |
982 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
983 | struct iommu_cmd cmd; | |
984 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
985 | dom_id, 1); | |
986 | iommu_queue_command(iommu, &cmd); | |
987 | } | |
8eed9833 | 988 | |
7d0c5cc5 | 989 | iommu_completion_wait(iommu); |
a19ae1ec JR |
990 | } |
991 | ||
58fc7f14 | 992 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 993 | { |
58fc7f14 | 994 | struct iommu_cmd cmd; |
0518a3a4 | 995 | |
58fc7f14 | 996 | build_inv_all(&cmd); |
0518a3a4 | 997 | |
58fc7f14 JR |
998 | iommu_queue_command(iommu, &cmd); |
999 | iommu_completion_wait(iommu); | |
1000 | } | |
1001 | ||
7ef2798d JR |
1002 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1003 | { | |
1004 | struct iommu_cmd cmd; | |
1005 | ||
1006 | build_inv_irt(&cmd, devid); | |
1007 | ||
1008 | iommu_queue_command(iommu, &cmd); | |
1009 | } | |
1010 | ||
1011 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1012 | { | |
1013 | u32 devid; | |
1014 | ||
1015 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1016 | iommu_flush_irt(iommu, devid); | |
1017 | ||
1018 | iommu_completion_wait(iommu); | |
1019 | } | |
1020 | ||
7d0c5cc5 JR |
1021 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1022 | { | |
58fc7f14 JR |
1023 | if (iommu_feature(iommu, FEATURE_IA)) { |
1024 | iommu_flush_all(iommu); | |
1025 | } else { | |
1026 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1027 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1028 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1029 | } |
1030 | } | |
1031 | ||
431b2a20 | 1032 | /* |
cb41ed85 | 1033 | * Command send function for flushing on-device TLB |
431b2a20 | 1034 | */ |
6c542047 JR |
1035 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1036 | u64 address, size_t size) | |
3fa43655 JR |
1037 | { |
1038 | struct amd_iommu *iommu; | |
b00d3bcf | 1039 | struct iommu_cmd cmd; |
cb41ed85 | 1040 | int qdep; |
3fa43655 | 1041 | |
ea61cddb JR |
1042 | qdep = dev_data->ats.qdep; |
1043 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1044 | |
ea61cddb | 1045 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1046 | |
1047 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1048 | } |
1049 | ||
431b2a20 | 1050 | /* |
431b2a20 | 1051 | * Command send function for invalidating a device table entry |
431b2a20 | 1052 | */ |
6c542047 | 1053 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1054 | { |
3fa43655 | 1055 | struct amd_iommu *iommu; |
e25bfb56 | 1056 | u16 alias; |
ee2fa743 | 1057 | int ret; |
a19ae1ec | 1058 | |
6c542047 | 1059 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 1060 | alias = amd_iommu_alias_table[dev_data->devid]; |
a19ae1ec | 1061 | |
f62dda66 | 1062 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1063 | if (!ret && alias != dev_data->devid) |
1064 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1065 | if (ret) |
1066 | return ret; | |
1067 | ||
ea61cddb | 1068 | if (dev_data->ats.enabled) |
6c542047 | 1069 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1070 | |
ee2fa743 | 1071 | return ret; |
a19ae1ec JR |
1072 | } |
1073 | ||
431b2a20 JR |
1074 | /* |
1075 | * TLB invalidation function which is called from the mapping functions. | |
1076 | * It invalidates a single PTE if the range to flush is within a single | |
1077 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1078 | */ | |
17b124bf JR |
1079 | static void __domain_flush_pages(struct protection_domain *domain, |
1080 | u64 address, size_t size, int pde) | |
a19ae1ec | 1081 | { |
cb41ed85 | 1082 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1083 | struct iommu_cmd cmd; |
1084 | int ret = 0, i; | |
a19ae1ec | 1085 | |
11b6402c | 1086 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1087 | |
6de8ad9b JR |
1088 | for (i = 0; i < amd_iommus_present; ++i) { |
1089 | if (!domain->dev_iommu[i]) | |
1090 | continue; | |
1091 | ||
1092 | /* | |
1093 | * Devices of this domain are behind this IOMMU | |
1094 | * We need a TLB flush | |
1095 | */ | |
11b6402c | 1096 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1097 | } |
1098 | ||
cb41ed85 | 1099 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1100 | |
ea61cddb | 1101 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1102 | continue; |
1103 | ||
6c542047 | 1104 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1105 | } |
1106 | ||
11b6402c | 1107 | WARN_ON(ret); |
6de8ad9b JR |
1108 | } |
1109 | ||
17b124bf JR |
1110 | static void domain_flush_pages(struct protection_domain *domain, |
1111 | u64 address, size_t size) | |
6de8ad9b | 1112 | { |
17b124bf | 1113 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1114 | } |
b6c02715 | 1115 | |
1c655773 | 1116 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1117 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1118 | { |
17b124bf | 1119 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1120 | } |
1121 | ||
42a49f96 | 1122 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1123 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1124 | { |
17b124bf | 1125 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1126 | } |
1127 | ||
17b124bf | 1128 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1129 | { |
17b124bf | 1130 | int i; |
18811f55 | 1131 | |
17b124bf JR |
1132 | for (i = 0; i < amd_iommus_present; ++i) { |
1133 | if (!domain->dev_iommu[i]) | |
1134 | continue; | |
bfd1be18 | 1135 | |
17b124bf JR |
1136 | /* |
1137 | * Devices of this domain are behind this IOMMU | |
1138 | * We need to wait for completion of all commands. | |
1139 | */ | |
1140 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1141 | } |
e394d72a JR |
1142 | } |
1143 | ||
b00d3bcf | 1144 | |
09b42804 | 1145 | /* |
b00d3bcf | 1146 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1147 | */ |
17b124bf | 1148 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1149 | { |
b00d3bcf | 1150 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1151 | |
b00d3bcf | 1152 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1153 | device_flush_dte(dev_data); |
a345b23b JR |
1154 | } |
1155 | ||
431b2a20 JR |
1156 | /**************************************************************************** |
1157 | * | |
1158 | * The functions below are used the create the page table mappings for | |
1159 | * unity mapped regions. | |
1160 | * | |
1161 | ****************************************************************************/ | |
1162 | ||
308973d3 JR |
1163 | /* |
1164 | * This function is used to add another level to an IO page table. Adding | |
1165 | * another level increases the size of the address space by 9 bits to a size up | |
1166 | * to 64 bits. | |
1167 | */ | |
1168 | static bool increase_address_space(struct protection_domain *domain, | |
1169 | gfp_t gfp) | |
1170 | { | |
1171 | u64 *pte; | |
1172 | ||
1173 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1174 | /* address space already 64 bit large */ | |
1175 | return false; | |
1176 | ||
1177 | pte = (void *)get_zeroed_page(gfp); | |
1178 | if (!pte) | |
1179 | return false; | |
1180 | ||
1181 | *pte = PM_LEVEL_PDE(domain->mode, | |
1182 | virt_to_phys(domain->pt_root)); | |
1183 | domain->pt_root = pte; | |
1184 | domain->mode += 1; | |
1185 | domain->updated = true; | |
1186 | ||
1187 | return true; | |
1188 | } | |
1189 | ||
1190 | static u64 *alloc_pte(struct protection_domain *domain, | |
1191 | unsigned long address, | |
cbb9d729 | 1192 | unsigned long page_size, |
308973d3 JR |
1193 | u64 **pte_page, |
1194 | gfp_t gfp) | |
1195 | { | |
cbb9d729 | 1196 | int level, end_lvl; |
308973d3 | 1197 | u64 *pte, *page; |
cbb9d729 JR |
1198 | |
1199 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1200 | |
1201 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1202 | increase_address_space(domain, gfp); | |
1203 | ||
cbb9d729 JR |
1204 | level = domain->mode - 1; |
1205 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1206 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1207 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1208 | |
1209 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1210 | u64 __pte, __npte; |
1211 | ||
1212 | __pte = *pte; | |
1213 | ||
1214 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1215 | page = (u64 *)get_zeroed_page(gfp); |
1216 | if (!page) | |
1217 | return NULL; | |
7bfa5bd2 JR |
1218 | |
1219 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1220 | ||
1221 | if (cmpxchg64(pte, __pte, __npte)) { | |
1222 | free_page((unsigned long)page); | |
1223 | continue; | |
1224 | } | |
308973d3 JR |
1225 | } |
1226 | ||
cbb9d729 JR |
1227 | /* No level skipping support yet */ |
1228 | if (PM_PTE_LEVEL(*pte) != level) | |
1229 | return NULL; | |
1230 | ||
308973d3 JR |
1231 | level -= 1; |
1232 | ||
1233 | pte = IOMMU_PTE_PAGE(*pte); | |
1234 | ||
1235 | if (pte_page && level == end_lvl) | |
1236 | *pte_page = pte; | |
1237 | ||
1238 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1239 | } | |
1240 | ||
1241 | return pte; | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * This function checks if there is a PTE for a given dma address. If | |
1246 | * there is one, it returns the pointer to it. | |
1247 | */ | |
3039ca1b JR |
1248 | static u64 *fetch_pte(struct protection_domain *domain, |
1249 | unsigned long address, | |
1250 | unsigned long *page_size) | |
308973d3 JR |
1251 | { |
1252 | int level; | |
1253 | u64 *pte; | |
1254 | ||
24cd7723 JR |
1255 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1256 | return NULL; | |
1257 | ||
3039ca1b JR |
1258 | level = domain->mode - 1; |
1259 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1260 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1261 | |
24cd7723 JR |
1262 | while (level > 0) { |
1263 | ||
1264 | /* Not Present */ | |
308973d3 JR |
1265 | if (!IOMMU_PTE_PRESENT(*pte)) |
1266 | return NULL; | |
1267 | ||
24cd7723 | 1268 | /* Large PTE */ |
3039ca1b JR |
1269 | if (PM_PTE_LEVEL(*pte) == 7 || |
1270 | PM_PTE_LEVEL(*pte) == 0) | |
1271 | break; | |
24cd7723 JR |
1272 | |
1273 | /* No level skipping support yet */ | |
1274 | if (PM_PTE_LEVEL(*pte) != level) | |
1275 | return NULL; | |
1276 | ||
308973d3 JR |
1277 | level -= 1; |
1278 | ||
24cd7723 | 1279 | /* Walk to the next level */ |
3039ca1b JR |
1280 | pte = IOMMU_PTE_PAGE(*pte); |
1281 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1282 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1283 | } | |
1284 | ||
1285 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1286 | unsigned long pte_mask; | |
1287 | ||
1288 | /* | |
1289 | * If we have a series of large PTEs, make | |
1290 | * sure to return a pointer to the first one. | |
1291 | */ | |
1292 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1293 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1294 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1295 | } |
1296 | ||
1297 | return pte; | |
1298 | } | |
1299 | ||
431b2a20 JR |
1300 | /* |
1301 | * Generic mapping functions. It maps a physical address into a DMA | |
1302 | * address space. It allocates the page table pages if necessary. | |
1303 | * In the future it can be extended to a generic mapping function | |
1304 | * supporting all features of AMD IOMMU page tables like level skipping | |
1305 | * and full 64 bit address spaces. | |
1306 | */ | |
38e817fe JR |
1307 | static int iommu_map_page(struct protection_domain *dom, |
1308 | unsigned long bus_addr, | |
1309 | unsigned long phys_addr, | |
abdc5eb3 | 1310 | int prot, |
cbb9d729 | 1311 | unsigned long page_size) |
bd0e5211 | 1312 | { |
8bda3092 | 1313 | u64 __pte, *pte; |
cbb9d729 | 1314 | int i, count; |
abdc5eb3 | 1315 | |
d4b03664 JR |
1316 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1317 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1318 | ||
bad1cac2 | 1319 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1320 | return -EINVAL; |
1321 | ||
d4b03664 JR |
1322 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1323 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1324 | |
63eaa75e ML |
1325 | if (!pte) |
1326 | return -ENOMEM; | |
1327 | ||
cbb9d729 JR |
1328 | for (i = 0; i < count; ++i) |
1329 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1330 | return -EBUSY; | |
bd0e5211 | 1331 | |
d4b03664 | 1332 | if (count > 1) { |
cbb9d729 JR |
1333 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1334 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1335 | } else | |
1336 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1337 | |
bd0e5211 JR |
1338 | if (prot & IOMMU_PROT_IR) |
1339 | __pte |= IOMMU_PTE_IR; | |
1340 | if (prot & IOMMU_PROT_IW) | |
1341 | __pte |= IOMMU_PTE_IW; | |
1342 | ||
cbb9d729 JR |
1343 | for (i = 0; i < count; ++i) |
1344 | pte[i] = __pte; | |
bd0e5211 | 1345 | |
04bfdd84 JR |
1346 | update_domain(dom); |
1347 | ||
bd0e5211 JR |
1348 | return 0; |
1349 | } | |
1350 | ||
24cd7723 JR |
1351 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1352 | unsigned long bus_addr, | |
1353 | unsigned long page_size) | |
eb74ff6c | 1354 | { |
71b390e9 JR |
1355 | unsigned long long unmapped; |
1356 | unsigned long unmap_size; | |
24cd7723 JR |
1357 | u64 *pte; |
1358 | ||
1359 | BUG_ON(!is_power_of_2(page_size)); | |
1360 | ||
1361 | unmapped = 0; | |
eb74ff6c | 1362 | |
24cd7723 JR |
1363 | while (unmapped < page_size) { |
1364 | ||
71b390e9 JR |
1365 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1366 | ||
1367 | if (pte) { | |
1368 | int i, count; | |
1369 | ||
1370 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1371 | for (i = 0; i < count; i++) |
1372 | pte[i] = 0ULL; | |
1373 | } | |
1374 | ||
1375 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1376 | unmapped += unmap_size; | |
1377 | } | |
1378 | ||
60d0ca3c | 1379 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1380 | |
24cd7723 | 1381 | return unmapped; |
eb74ff6c | 1382 | } |
eb74ff6c | 1383 | |
431b2a20 JR |
1384 | /**************************************************************************** |
1385 | * | |
1386 | * The next functions belong to the address allocator for the dma_ops | |
1387 | * interface functions. They work like the allocators in the other IOMMU | |
1388 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1389 | * the aperture. Maybe it could be enhanced in the future to a more | |
1390 | * efficient allocator. | |
1391 | * | |
1392 | ****************************************************************************/ | |
d3086444 | 1393 | |
431b2a20 | 1394 | /* |
384de729 | 1395 | * The address allocator core functions. |
431b2a20 JR |
1396 | * |
1397 | * called with domain->lock held | |
1398 | */ | |
384de729 | 1399 | |
171e7b37 JR |
1400 | /* |
1401 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1402 | * ranges. | |
1403 | */ | |
1404 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1405 | unsigned long start_page, | |
1406 | unsigned int pages) | |
1407 | { | |
1408 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1409 | ||
1410 | if (start_page + pages > last_page) | |
1411 | pages = last_page - start_page; | |
1412 | ||
1413 | for (i = start_page; i < start_page + pages; ++i) { | |
1414 | int index = i / APERTURE_RANGE_PAGES; | |
1415 | int page = i % APERTURE_RANGE_PAGES; | |
1416 | __set_bit(page, dom->aperture[index]->bitmap); | |
1417 | } | |
1418 | } | |
1419 | ||
9cabe89b JR |
1420 | /* |
1421 | * This function is used to add a new aperture range to an existing | |
1422 | * aperture in case of dma_ops domain allocation or address allocation | |
1423 | * failure. | |
1424 | */ | |
576175c2 | 1425 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1426 | bool populate, gfp_t gfp) |
1427 | { | |
1428 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
5d7c94c3 | 1429 | unsigned long i, old_size, pte_pgsize; |
a73c1566 JR |
1430 | struct aperture_range *range; |
1431 | struct amd_iommu *iommu; | |
1432 | unsigned long flags; | |
9cabe89b | 1433 | |
f5e9705c JR |
1434 | #ifdef CONFIG_IOMMU_STRESS |
1435 | populate = false; | |
1436 | #endif | |
1437 | ||
9cabe89b JR |
1438 | if (index >= APERTURE_MAX_RANGES) |
1439 | return -ENOMEM; | |
1440 | ||
a73c1566 JR |
1441 | range = kzalloc(sizeof(struct aperture_range), gfp); |
1442 | if (!range) | |
9cabe89b JR |
1443 | return -ENOMEM; |
1444 | ||
a73c1566 JR |
1445 | range->bitmap = (void *)get_zeroed_page(gfp); |
1446 | if (!range->bitmap) | |
9cabe89b JR |
1447 | goto out_free; |
1448 | ||
a73c1566 | 1449 | range->offset = dma_dom->aperture_size; |
9cabe89b | 1450 | |
a73c1566 | 1451 | spin_lock_init(&range->bitmap_lock); |
08c5fb93 | 1452 | |
9cabe89b JR |
1453 | if (populate) { |
1454 | unsigned long address = dma_dom->aperture_size; | |
1455 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1456 | u64 *pte, *pte_page; | |
1457 | ||
1458 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1459 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1460 | &pte_page, gfp); |
1461 | if (!pte) | |
1462 | goto out_free; | |
1463 | ||
a73c1566 | 1464 | range->pte_pages[i] = pte_page; |
9cabe89b JR |
1465 | |
1466 | address += APERTURE_RANGE_SIZE / 64; | |
1467 | } | |
1468 | } | |
1469 | ||
92d420ec JR |
1470 | spin_lock_irqsave(&dma_dom->domain.lock, flags); |
1471 | ||
a73c1566 | 1472 | /* First take the bitmap_lock and then publish the range */ |
92d420ec | 1473 | spin_lock(&range->bitmap_lock); |
a73c1566 JR |
1474 | |
1475 | old_size = dma_dom->aperture_size; | |
1476 | dma_dom->aperture[index] = range; | |
1477 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
9cabe89b | 1478 | |
17f5b569 JR |
1479 | /* Reserve address range used for MSI messages */ |
1480 | if (old_size < MSI_ADDR_BASE_LO && | |
1481 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1482 | unsigned long spage; | |
1483 | int pages; | |
1484 | ||
1485 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1486 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1487 | ||
1488 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1489 | } | |
1490 | ||
b595076a | 1491 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1492 | for_each_iommu(iommu) { |
1493 | if (iommu->exclusion_start && | |
1494 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1495 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1496 | unsigned long startpage; | |
1497 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1498 | iommu->exclusion_length, | |
1499 | PAGE_SIZE); | |
1500 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1501 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1502 | } | |
00cd122a JR |
1503 | } |
1504 | ||
1505 | /* | |
1506 | * Check for areas already mapped as present in the new aperture | |
1507 | * range and mark those pages as reserved in the allocator. Such | |
1508 | * mappings may already exist as a result of requested unity | |
1509 | * mappings for devices. | |
1510 | */ | |
1511 | for (i = dma_dom->aperture[index]->offset; | |
1512 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1513 | i += pte_pgsize) { |
3039ca1b | 1514 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1515 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1516 | continue; | |
1517 | ||
5d7c94c3 JR |
1518 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1519 | pte_pgsize >> 12); | |
00cd122a JR |
1520 | } |
1521 | ||
04bfdd84 JR |
1522 | update_domain(&dma_dom->domain); |
1523 | ||
92d420ec JR |
1524 | spin_unlock(&range->bitmap_lock); |
1525 | ||
1526 | spin_unlock_irqrestore(&dma_dom->domain.lock, flags); | |
a73c1566 | 1527 | |
9cabe89b JR |
1528 | return 0; |
1529 | ||
1530 | out_free: | |
04bfdd84 JR |
1531 | update_domain(&dma_dom->domain); |
1532 | ||
a73c1566 | 1533 | free_page((unsigned long)range->bitmap); |
9cabe89b | 1534 | |
a73c1566 | 1535 | kfree(range); |
9cabe89b JR |
1536 | |
1537 | return -ENOMEM; | |
1538 | } | |
1539 | ||
ccb50e03 JR |
1540 | static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom, |
1541 | struct aperture_range *range, | |
a0f51447 | 1542 | unsigned long pages, |
a0f51447 JR |
1543 | unsigned long dma_mask, |
1544 | unsigned long boundary_size, | |
7b5e25b8 JR |
1545 | unsigned long align_mask, |
1546 | bool trylock) | |
a0f51447 JR |
1547 | { |
1548 | unsigned long offset, limit, flags; | |
1549 | dma_addr_t address; | |
ccb50e03 | 1550 | bool flush = false; |
a0f51447 JR |
1551 | |
1552 | offset = range->offset >> PAGE_SHIFT; | |
1553 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1554 | dma_mask >> PAGE_SHIFT); | |
1555 | ||
7b5e25b8 JR |
1556 | if (trylock) { |
1557 | if (!spin_trylock_irqsave(&range->bitmap_lock, flags)) | |
1558 | return -1; | |
1559 | } else { | |
1560 | spin_lock_irqsave(&range->bitmap_lock, flags); | |
1561 | } | |
1562 | ||
60e6a7cb JR |
1563 | address = iommu_area_alloc(range->bitmap, limit, range->next_bit, |
1564 | pages, offset, boundary_size, align_mask); | |
ccb50e03 | 1565 | if (address == -1) { |
60e6a7cb JR |
1566 | /* Nothing found, retry one time */ |
1567 | address = iommu_area_alloc(range->bitmap, limit, | |
1568 | 0, pages, offset, boundary_size, | |
1569 | align_mask); | |
ccb50e03 JR |
1570 | flush = true; |
1571 | } | |
60e6a7cb JR |
1572 | |
1573 | if (address != -1) | |
1574 | range->next_bit = address + pages; | |
1575 | ||
a0f51447 JR |
1576 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
1577 | ||
ccb50e03 JR |
1578 | if (flush) { |
1579 | domain_flush_tlb(&dom->domain); | |
1580 | domain_flush_complete(&dom->domain); | |
1581 | } | |
1582 | ||
a0f51447 JR |
1583 | return address; |
1584 | } | |
1585 | ||
384de729 JR |
1586 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1587 | struct dma_ops_domain *dom, | |
1588 | unsigned int pages, | |
1589 | unsigned long align_mask, | |
05ab49e0 | 1590 | u64 dma_mask) |
384de729 | 1591 | { |
ab7032bb | 1592 | unsigned long boundary_size, mask; |
384de729 | 1593 | unsigned long address = -1; |
7b5e25b8 | 1594 | bool first = true; |
5f6bed50 JR |
1595 | u32 start, i; |
1596 | ||
1597 | preempt_disable(); | |
384de729 | 1598 | |
e6aabee0 JR |
1599 | mask = dma_get_seg_boundary(dev); |
1600 | ||
7b5e25b8 | 1601 | again: |
5f6bed50 JR |
1602 | start = this_cpu_read(*dom->next_index); |
1603 | ||
1604 | /* Sanity check - is it really necessary? */ | |
1605 | if (unlikely(start > APERTURE_MAX_RANGES)) { | |
1606 | start = 0; | |
1607 | this_cpu_write(*dom->next_index, 0); | |
1608 | } | |
1609 | ||
e6aabee0 JR |
1610 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : |
1611 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 | 1612 | |
2a87442c JR |
1613 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1614 | struct aperture_range *range; | |
5f6bed50 JR |
1615 | int index; |
1616 | ||
1617 | index = (start + i) % APERTURE_MAX_RANGES; | |
ccb50e03 | 1618 | |
5f6bed50 | 1619 | range = dom->aperture[index]; |
2a87442c JR |
1620 | |
1621 | if (!range || range->offset >= dma_mask) | |
1622 | continue; | |
384de729 | 1623 | |
2a87442c | 1624 | address = dma_ops_aperture_alloc(dom, range, pages, |
60e6a7cb | 1625 | dma_mask, boundary_size, |
7b5e25b8 | 1626 | align_mask, first); |
384de729 | 1627 | if (address != -1) { |
2a87442c | 1628 | address = range->offset + (address << PAGE_SHIFT); |
5f6bed50 | 1629 | this_cpu_write(*dom->next_index, index); |
384de729 JR |
1630 | break; |
1631 | } | |
384de729 JR |
1632 | } |
1633 | ||
7b5e25b8 JR |
1634 | if (address == -1 && first) { |
1635 | first = false; | |
1636 | goto again; | |
1637 | } | |
1638 | ||
5f6bed50 JR |
1639 | preempt_enable(); |
1640 | ||
384de729 JR |
1641 | return address; |
1642 | } | |
1643 | ||
d3086444 JR |
1644 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1645 | struct dma_ops_domain *dom, | |
6d4f343f | 1646 | unsigned int pages, |
832a90c3 JR |
1647 | unsigned long align_mask, |
1648 | u64 dma_mask) | |
d3086444 | 1649 | { |
266a3bd2 | 1650 | unsigned long address = -1; |
d3086444 | 1651 | |
266a3bd2 JR |
1652 | while (address == -1) { |
1653 | address = dma_ops_area_alloc(dev, dom, pages, | |
1654 | align_mask, dma_mask); | |
1655 | ||
7bfa5bd2 | 1656 | if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC)) |
266a3bd2 JR |
1657 | break; |
1658 | } | |
d3086444 | 1659 | |
384de729 | 1660 | if (unlikely(address == -1)) |
8fd524b3 | 1661 | address = DMA_ERROR_CODE; |
d3086444 JR |
1662 | |
1663 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1664 | ||
1665 | return address; | |
1666 | } | |
1667 | ||
431b2a20 JR |
1668 | /* |
1669 | * The address free function. | |
1670 | * | |
1671 | * called with domain->lock held | |
1672 | */ | |
d3086444 JR |
1673 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1674 | unsigned long address, | |
1675 | unsigned int pages) | |
1676 | { | |
384de729 JR |
1677 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1678 | struct aperture_range *range = dom->aperture[i]; | |
08c5fb93 | 1679 | unsigned long flags; |
80be308d | 1680 | |
384de729 JR |
1681 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1682 | ||
47bccd6b JR |
1683 | #ifdef CONFIG_IOMMU_STRESS |
1684 | if (i < 4) | |
1685 | return; | |
1686 | #endif | |
80be308d | 1687 | |
4eeca8c5 | 1688 | if (amd_iommu_unmap_flush) { |
d41ab098 JR |
1689 | domain_flush_tlb(&dom->domain); |
1690 | domain_flush_complete(&dom->domain); | |
1691 | } | |
384de729 JR |
1692 | |
1693 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1694 | |
08c5fb93 | 1695 | spin_lock_irqsave(&range->bitmap_lock, flags); |
4eeca8c5 JR |
1696 | if (address + pages > range->next_bit) |
1697 | range->next_bit = address + pages; | |
a66022c4 | 1698 | bitmap_clear(range->bitmap, address, pages); |
08c5fb93 | 1699 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
384de729 | 1700 | |
d3086444 JR |
1701 | } |
1702 | ||
431b2a20 JR |
1703 | /**************************************************************************** |
1704 | * | |
1705 | * The next functions belong to the domain allocation. A domain is | |
1706 | * allocated for every IOMMU as the default domain. If device isolation | |
1707 | * is enabled, every device get its own domain. The most important thing | |
1708 | * about domains is the page table mapping the DMA address space they | |
1709 | * contain. | |
1710 | * | |
1711 | ****************************************************************************/ | |
1712 | ||
aeb26f55 JR |
1713 | /* |
1714 | * This function adds a protection domain to the global protection domain list | |
1715 | */ | |
1716 | static void add_domain_to_list(struct protection_domain *domain) | |
1717 | { | |
1718 | unsigned long flags; | |
1719 | ||
1720 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1721 | list_add(&domain->list, &amd_iommu_pd_list); | |
1722 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1723 | } | |
1724 | ||
1725 | /* | |
1726 | * This function removes a protection domain to the global | |
1727 | * protection domain list | |
1728 | */ | |
1729 | static void del_domain_from_list(struct protection_domain *domain) | |
1730 | { | |
1731 | unsigned long flags; | |
1732 | ||
1733 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1734 | list_del(&domain->list); | |
1735 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1736 | } | |
1737 | ||
ec487d1a JR |
1738 | static u16 domain_id_alloc(void) |
1739 | { | |
1740 | unsigned long flags; | |
1741 | int id; | |
1742 | ||
1743 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1744 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1745 | BUG_ON(id == 0); | |
1746 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1747 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1748 | else | |
1749 | id = 0; | |
1750 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1751 | ||
1752 | return id; | |
1753 | } | |
1754 | ||
a2acfb75 JR |
1755 | static void domain_id_free(int id) |
1756 | { | |
1757 | unsigned long flags; | |
1758 | ||
1759 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1760 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1761 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1762 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1763 | } | |
a2acfb75 | 1764 | |
5c34c403 JR |
1765 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1766 | static void free_pt_##LVL (unsigned long __pt) \ | |
1767 | { \ | |
1768 | unsigned long p; \ | |
1769 | u64 *pt; \ | |
1770 | int i; \ | |
1771 | \ | |
1772 | pt = (u64 *)__pt; \ | |
1773 | \ | |
1774 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1775 | /* PTE present? */ \ |
5c34c403 JR |
1776 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1777 | continue; \ | |
1778 | \ | |
0b3fff54 JR |
1779 | /* Large PTE? */ \ |
1780 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1781 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1782 | continue; \ | |
1783 | \ | |
5c34c403 JR |
1784 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1785 | FN(p); \ | |
1786 | } \ | |
1787 | free_page((unsigned long)pt); \ | |
1788 | } | |
1789 | ||
1790 | DEFINE_FREE_PT_FN(l2, free_page) | |
1791 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1792 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1793 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1794 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1795 | ||
86db2e5d | 1796 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1797 | { |
5c34c403 | 1798 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1799 | |
5c34c403 JR |
1800 | switch (domain->mode) { |
1801 | case PAGE_MODE_NONE: | |
1802 | break; | |
1803 | case PAGE_MODE_1_LEVEL: | |
1804 | free_page(root); | |
1805 | break; | |
1806 | case PAGE_MODE_2_LEVEL: | |
1807 | free_pt_l2(root); | |
1808 | break; | |
1809 | case PAGE_MODE_3_LEVEL: | |
1810 | free_pt_l3(root); | |
1811 | break; | |
1812 | case PAGE_MODE_4_LEVEL: | |
1813 | free_pt_l4(root); | |
1814 | break; | |
1815 | case PAGE_MODE_5_LEVEL: | |
1816 | free_pt_l5(root); | |
1817 | break; | |
1818 | case PAGE_MODE_6_LEVEL: | |
1819 | free_pt_l6(root); | |
1820 | break; | |
1821 | default: | |
1822 | BUG(); | |
ec487d1a | 1823 | } |
ec487d1a JR |
1824 | } |
1825 | ||
b16137b1 JR |
1826 | static void free_gcr3_tbl_level1(u64 *tbl) |
1827 | { | |
1828 | u64 *ptr; | |
1829 | int i; | |
1830 | ||
1831 | for (i = 0; i < 512; ++i) { | |
1832 | if (!(tbl[i] & GCR3_VALID)) | |
1833 | continue; | |
1834 | ||
1835 | ptr = __va(tbl[i] & PAGE_MASK); | |
1836 | ||
1837 | free_page((unsigned long)ptr); | |
1838 | } | |
1839 | } | |
1840 | ||
1841 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1842 | { | |
1843 | u64 *ptr; | |
1844 | int i; | |
1845 | ||
1846 | for (i = 0; i < 512; ++i) { | |
1847 | if (!(tbl[i] & GCR3_VALID)) | |
1848 | continue; | |
1849 | ||
1850 | ptr = __va(tbl[i] & PAGE_MASK); | |
1851 | ||
1852 | free_gcr3_tbl_level1(ptr); | |
1853 | } | |
1854 | } | |
1855 | ||
52815b75 JR |
1856 | static void free_gcr3_table(struct protection_domain *domain) |
1857 | { | |
b16137b1 JR |
1858 | if (domain->glx == 2) |
1859 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1860 | else if (domain->glx == 1) | |
1861 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1862 | else |
1863 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1864 | |
52815b75 JR |
1865 | free_page((unsigned long)domain->gcr3_tbl); |
1866 | } | |
1867 | ||
431b2a20 JR |
1868 | /* |
1869 | * Free a domain, only used if something went wrong in the | |
1870 | * allocation path and we need to free an already allocated page table | |
1871 | */ | |
ec487d1a JR |
1872 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1873 | { | |
384de729 JR |
1874 | int i; |
1875 | ||
ec487d1a JR |
1876 | if (!dom) |
1877 | return; | |
1878 | ||
5f6bed50 JR |
1879 | free_percpu(dom->next_index); |
1880 | ||
aeb26f55 JR |
1881 | del_domain_from_list(&dom->domain); |
1882 | ||
86db2e5d | 1883 | free_pagetable(&dom->domain); |
ec487d1a | 1884 | |
384de729 JR |
1885 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1886 | if (!dom->aperture[i]) | |
1887 | continue; | |
1888 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1889 | kfree(dom->aperture[i]); | |
1890 | } | |
ec487d1a JR |
1891 | |
1892 | kfree(dom); | |
1893 | } | |
1894 | ||
a639a8ee JR |
1895 | static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom, |
1896 | int max_apertures) | |
1897 | { | |
1898 | int ret, i, apertures; | |
1899 | ||
1900 | apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
1901 | ret = 0; | |
1902 | ||
1903 | for (i = apertures; i < max_apertures; ++i) { | |
1904 | ret = alloc_new_range(dma_dom, false, GFP_KERNEL); | |
1905 | if (ret) | |
1906 | break; | |
1907 | } | |
1908 | ||
1909 | return ret; | |
1910 | } | |
1911 | ||
431b2a20 JR |
1912 | /* |
1913 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1914 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1915 | * structures required for the dma_ops interface |
1916 | */ | |
87a64d52 | 1917 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1918 | { |
1919 | struct dma_ops_domain *dma_dom; | |
5f6bed50 | 1920 | int cpu; |
ec487d1a JR |
1921 | |
1922 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1923 | if (!dma_dom) | |
1924 | return NULL; | |
1925 | ||
7a5a566e | 1926 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1927 | goto free_dma_dom; |
7a5a566e | 1928 | |
5f6bed50 JR |
1929 | dma_dom->next_index = alloc_percpu(u32); |
1930 | if (!dma_dom->next_index) | |
1931 | goto free_dma_dom; | |
1932 | ||
8f7a017c | 1933 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1934 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1935 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1936 | dma_dom->domain.priv = dma_dom; |
1937 | if (!dma_dom->domain.pt_root) | |
1938 | goto free_dma_dom; | |
ec487d1a | 1939 | |
aeb26f55 JR |
1940 | add_domain_to_list(&dma_dom->domain); |
1941 | ||
576175c2 | 1942 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1943 | goto free_dma_dom; |
ec487d1a | 1944 | |
431b2a20 | 1945 | /* |
ec487d1a JR |
1946 | * mark the first page as allocated so we never return 0 as |
1947 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1948 | */ |
384de729 | 1949 | dma_dom->aperture[0]->bitmap[0] = 1; |
ec487d1a | 1950 | |
5f6bed50 JR |
1951 | for_each_possible_cpu(cpu) |
1952 | *per_cpu_ptr(dma_dom->next_index, cpu) = 0; | |
ec487d1a JR |
1953 | |
1954 | return dma_dom; | |
1955 | ||
1956 | free_dma_dom: | |
1957 | dma_ops_domain_free(dma_dom); | |
1958 | ||
1959 | return NULL; | |
1960 | } | |
1961 | ||
5b28df6f JR |
1962 | /* |
1963 | * little helper function to check whether a given protection domain is a | |
1964 | * dma_ops domain | |
1965 | */ | |
1966 | static bool dma_ops_domain(struct protection_domain *domain) | |
1967 | { | |
1968 | return domain->flags & PD_DMA_OPS_MASK; | |
1969 | } | |
1970 | ||
fd7b5535 | 1971 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1972 | { |
132bd68f | 1973 | u64 pte_root = 0; |
ee6c2868 | 1974 | u64 flags = 0; |
863c74eb | 1975 | |
132bd68f JR |
1976 | if (domain->mode != PAGE_MODE_NONE) |
1977 | pte_root = virt_to_phys(domain->pt_root); | |
1978 | ||
38ddf41b JR |
1979 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1980 | << DEV_ENTRY_MODE_SHIFT; | |
1981 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1982 | |
ee6c2868 JR |
1983 | flags = amd_iommu_dev_table[devid].data[1]; |
1984 | ||
fd7b5535 JR |
1985 | if (ats) |
1986 | flags |= DTE_FLAG_IOTLB; | |
1987 | ||
52815b75 JR |
1988 | if (domain->flags & PD_IOMMUV2_MASK) { |
1989 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1990 | u64 glx = domain->glx; | |
1991 | u64 tmp; | |
1992 | ||
1993 | pte_root |= DTE_FLAG_GV; | |
1994 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1995 | ||
1996 | /* First mask out possible old values for GCR3 table */ | |
1997 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1998 | flags &= ~tmp; | |
1999 | ||
2000 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2001 | flags &= ~tmp; | |
2002 | ||
2003 | /* Encode GCR3 table into DTE */ | |
2004 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2005 | pte_root |= tmp; | |
2006 | ||
2007 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2008 | flags |= tmp; | |
2009 | ||
2010 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2011 | flags |= tmp; | |
2012 | } | |
2013 | ||
ee6c2868 JR |
2014 | flags &= ~(0xffffUL); |
2015 | flags |= domain->id; | |
2016 | ||
2017 | amd_iommu_dev_table[devid].data[1] = flags; | |
2018 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2019 | } |
2020 | ||
2021 | static void clear_dte_entry(u16 devid) | |
2022 | { | |
15898bbc | 2023 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
2024 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
2025 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
2026 | |
2027 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2028 | } |
2029 | ||
ec9e79ef JR |
2030 | static void do_attach(struct iommu_dev_data *dev_data, |
2031 | struct protection_domain *domain) | |
7f760ddd | 2032 | { |
7f760ddd | 2033 | struct amd_iommu *iommu; |
e25bfb56 | 2034 | u16 alias; |
ec9e79ef | 2035 | bool ats; |
fd7b5535 | 2036 | |
ec9e79ef | 2037 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 2038 | alias = amd_iommu_alias_table[dev_data->devid]; |
ec9e79ef | 2039 | ats = dev_data->ats.enabled; |
7f760ddd JR |
2040 | |
2041 | /* Update data structures */ | |
2042 | dev_data->domain = domain; | |
2043 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
2044 | |
2045 | /* Do reference counting */ | |
2046 | domain->dev_iommu[iommu->index] += 1; | |
2047 | domain->dev_cnt += 1; | |
2048 | ||
e25bfb56 JR |
2049 | /* Update device table */ |
2050 | set_dte_entry(dev_data->devid, domain, ats); | |
2051 | if (alias != dev_data->devid) | |
2052 | set_dte_entry(dev_data->devid, domain, ats); | |
2053 | ||
6c542047 | 2054 | device_flush_dte(dev_data); |
7f760ddd JR |
2055 | } |
2056 | ||
ec9e79ef | 2057 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2058 | { |
7f760ddd | 2059 | struct amd_iommu *iommu; |
e25bfb56 | 2060 | u16 alias; |
7f760ddd | 2061 | |
5adad991 JR |
2062 | /* |
2063 | * First check if the device is still attached. It might already | |
2064 | * be detached from its domain because the generic | |
2065 | * iommu_detach_group code detached it and we try again here in | |
2066 | * our alias handling. | |
2067 | */ | |
2068 | if (!dev_data->domain) | |
2069 | return; | |
2070 | ||
ec9e79ef | 2071 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 2072 | alias = amd_iommu_alias_table[dev_data->devid]; |
15898bbc JR |
2073 | |
2074 | /* decrease reference counters */ | |
7f760ddd JR |
2075 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2076 | dev_data->domain->dev_cnt -= 1; | |
2077 | ||
2078 | /* Update data structures */ | |
2079 | dev_data->domain = NULL; | |
2080 | list_del(&dev_data->list); | |
f62dda66 | 2081 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
2082 | if (alias != dev_data->devid) |
2083 | clear_dte_entry(alias); | |
15898bbc | 2084 | |
7f760ddd | 2085 | /* Flush the DTE entry */ |
6c542047 | 2086 | device_flush_dte(dev_data); |
2b681faf JR |
2087 | } |
2088 | ||
2089 | /* | |
2090 | * If a device is not yet associated with a domain, this function does | |
2091 | * assigns it visible for the hardware | |
2092 | */ | |
ec9e79ef | 2093 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2094 | struct protection_domain *domain) |
2b681faf | 2095 | { |
84fe6c19 | 2096 | int ret; |
657cbb6b | 2097 | |
272e4f99 JR |
2098 | /* |
2099 | * Must be called with IRQs disabled. Warn here to detect early | |
2100 | * when its not. | |
2101 | */ | |
2102 | WARN_ON(!irqs_disabled()); | |
2103 | ||
2b681faf JR |
2104 | /* lock domain */ |
2105 | spin_lock(&domain->lock); | |
2106 | ||
397111ab | 2107 | ret = -EBUSY; |
150952f9 | 2108 | if (dev_data->domain != NULL) |
397111ab | 2109 | goto out_unlock; |
15898bbc | 2110 | |
397111ab | 2111 | /* Attach alias group root */ |
150952f9 | 2112 | do_attach(dev_data, domain); |
24100055 | 2113 | |
84fe6c19 JL |
2114 | ret = 0; |
2115 | ||
2116 | out_unlock: | |
2117 | ||
eba6ac60 JR |
2118 | /* ready */ |
2119 | spin_unlock(&domain->lock); | |
15898bbc | 2120 | |
84fe6c19 | 2121 | return ret; |
0feae533 | 2122 | } |
b20ac0d4 | 2123 | |
52815b75 JR |
2124 | |
2125 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2126 | { | |
2127 | pci_disable_ats(pdev); | |
2128 | pci_disable_pri(pdev); | |
2129 | pci_disable_pasid(pdev); | |
2130 | } | |
2131 | ||
6a113ddc JR |
2132 | /* FIXME: Change generic reset-function to do the same */ |
2133 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2134 | { | |
2135 | u16 control; | |
2136 | int pos; | |
2137 | ||
46277b75 | 2138 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2139 | if (!pos) |
2140 | return -EINVAL; | |
2141 | ||
46277b75 JR |
2142 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2143 | control |= PCI_PRI_CTRL_RESET; | |
2144 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2145 | |
2146 | return 0; | |
2147 | } | |
2148 | ||
52815b75 JR |
2149 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2150 | { | |
6a113ddc JR |
2151 | bool reset_enable; |
2152 | int reqs, ret; | |
2153 | ||
2154 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2155 | reqs = 32; | |
2156 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2157 | reqs = 1; | |
2158 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2159 | |
2160 | /* Only allow access to user-accessible pages */ | |
2161 | ret = pci_enable_pasid(pdev, 0); | |
2162 | if (ret) | |
2163 | goto out_err; | |
2164 | ||
2165 | /* First reset the PRI state of the device */ | |
2166 | ret = pci_reset_pri(pdev); | |
2167 | if (ret) | |
2168 | goto out_err; | |
2169 | ||
6a113ddc JR |
2170 | /* Enable PRI */ |
2171 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2172 | if (ret) |
2173 | goto out_err; | |
2174 | ||
6a113ddc JR |
2175 | if (reset_enable) { |
2176 | ret = pri_reset_while_enabled(pdev); | |
2177 | if (ret) | |
2178 | goto out_err; | |
2179 | } | |
2180 | ||
52815b75 JR |
2181 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2182 | if (ret) | |
2183 | goto out_err; | |
2184 | ||
2185 | return 0; | |
2186 | ||
2187 | out_err: | |
2188 | pci_disable_pri(pdev); | |
2189 | pci_disable_pasid(pdev); | |
2190 | ||
2191 | return ret; | |
2192 | } | |
2193 | ||
c99afa25 | 2194 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2195 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2196 | |
98f1ad25 | 2197 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2198 | { |
a3b93121 | 2199 | u16 status; |
c99afa25 JR |
2200 | int pos; |
2201 | ||
46277b75 | 2202 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2203 | if (!pos) |
2204 | return false; | |
2205 | ||
a3b93121 | 2206 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2207 | |
a3b93121 | 2208 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2209 | } |
2210 | ||
407d733e | 2211 | /* |
df805abb | 2212 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2213 | * assigns it visible for the hardware |
2214 | */ | |
15898bbc JR |
2215 | static int attach_device(struct device *dev, |
2216 | struct protection_domain *domain) | |
0feae533 | 2217 | { |
fd7b5535 | 2218 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2219 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2220 | unsigned long flags; |
15898bbc | 2221 | int ret; |
eba6ac60 | 2222 | |
ea61cddb JR |
2223 | dev_data = get_dev_data(dev); |
2224 | ||
52815b75 | 2225 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2226 | if (!dev_data->passthrough) |
52815b75 JR |
2227 | return -EINVAL; |
2228 | ||
02ca2021 JR |
2229 | if (dev_data->iommu_v2) { |
2230 | if (pdev_iommuv2_enable(pdev) != 0) | |
2231 | return -EINVAL; | |
52815b75 | 2232 | |
02ca2021 JR |
2233 | dev_data->ats.enabled = true; |
2234 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2235 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2236 | } | |
52815b75 JR |
2237 | } else if (amd_iommu_iotlb_sup && |
2238 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2239 | dev_data->ats.enabled = true; |
2240 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2241 | } | |
fd7b5535 | 2242 | |
eba6ac60 | 2243 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2244 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2245 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2246 | ||
0feae533 JR |
2247 | /* |
2248 | * We might boot into a crash-kernel here. The crashed kernel | |
2249 | * left the caches in the IOMMU dirty. So we have to flush | |
2250 | * here to evict all dirty stuff. | |
2251 | */ | |
17b124bf | 2252 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2253 | |
2254 | return ret; | |
b20ac0d4 JR |
2255 | } |
2256 | ||
355bf553 JR |
2257 | /* |
2258 | * Removes a device from a protection domain (unlocked) | |
2259 | */ | |
ec9e79ef | 2260 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2261 | { |
2ca76279 | 2262 | struct protection_domain *domain; |
c4596114 | 2263 | |
272e4f99 JR |
2264 | /* |
2265 | * Must be called with IRQs disabled. Warn here to detect early | |
2266 | * when its not. | |
2267 | */ | |
2268 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2269 | |
f34c73f5 JR |
2270 | if (WARN_ON(!dev_data->domain)) |
2271 | return; | |
24100055 | 2272 | |
2ca76279 | 2273 | domain = dev_data->domain; |
71f77580 | 2274 | |
f1dd0a8b | 2275 | spin_lock(&domain->lock); |
24100055 | 2276 | |
150952f9 | 2277 | do_detach(dev_data); |
7f760ddd | 2278 | |
f1dd0a8b | 2279 | spin_unlock(&domain->lock); |
355bf553 JR |
2280 | } |
2281 | ||
2282 | /* | |
2283 | * Removes a device from a protection domain (with devtable_lock held) | |
2284 | */ | |
15898bbc | 2285 | static void detach_device(struct device *dev) |
355bf553 | 2286 | { |
52815b75 | 2287 | struct protection_domain *domain; |
ea61cddb | 2288 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2289 | unsigned long flags; |
2290 | ||
ec9e79ef | 2291 | dev_data = get_dev_data(dev); |
52815b75 | 2292 | domain = dev_data->domain; |
ec9e79ef | 2293 | |
355bf553 JR |
2294 | /* lock device table */ |
2295 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2296 | __detach_device(dev_data); |
355bf553 | 2297 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2298 | |
02ca2021 | 2299 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2300 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2301 | else if (dev_data->ats.enabled) | |
ea61cddb | 2302 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2303 | |
2304 | dev_data->ats.enabled = false; | |
355bf553 | 2305 | } |
e275a2a0 | 2306 | |
aafd8ba0 | 2307 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2308 | { |
5abcdba4 | 2309 | struct iommu_dev_data *dev_data; |
07ee8694 | 2310 | struct iommu_domain *domain; |
e275a2a0 | 2311 | struct amd_iommu *iommu; |
5abcdba4 | 2312 | u16 devid; |
aafd8ba0 | 2313 | int ret; |
e275a2a0 | 2314 | |
aafd8ba0 | 2315 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2316 | return 0; |
e275a2a0 | 2317 | |
aafd8ba0 JR |
2318 | devid = get_device_id(dev); |
2319 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2320 | |
aafd8ba0 | 2321 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2322 | if (ret) { |
2323 | if (ret != -ENOTSUPP) | |
2324 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2325 | dev_name(dev)); | |
657cbb6b | 2326 | |
aafd8ba0 | 2327 | iommu_ignore_device(dev); |
343e9cac | 2328 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2329 | goto out; |
2330 | } | |
2331 | init_iommu_group(dev); | |
2c9195e9 | 2332 | |
07ee8694 | 2333 | dev_data = get_dev_data(dev); |
2c9195e9 | 2334 | |
4d58b8a6 | 2335 | BUG_ON(!dev_data); |
657cbb6b | 2336 | |
1e6a7b04 | 2337 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2338 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2339 | |
07ee8694 JR |
2340 | /* Domains are initialized for this device - have a look what we ended up with */ |
2341 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2342 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2343 | dev_data->passthrough = true; |
32302324 | 2344 | else |
2c9195e9 | 2345 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2346 | |
aafd8ba0 | 2347 | out: |
e275a2a0 JR |
2348 | iommu_completion_wait(iommu); |
2349 | ||
e275a2a0 JR |
2350 | return 0; |
2351 | } | |
2352 | ||
aafd8ba0 | 2353 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2354 | { |
aafd8ba0 JR |
2355 | struct amd_iommu *iommu; |
2356 | u16 devid; | |
2357 | ||
2358 | if (!check_device(dev)) | |
2359 | return; | |
2360 | ||
2361 | devid = get_device_id(dev); | |
2362 | iommu = amd_iommu_rlookup_table[devid]; | |
2363 | ||
2364 | iommu_uninit_device(dev); | |
2365 | iommu_completion_wait(iommu); | |
8638c491 JR |
2366 | } |
2367 | ||
431b2a20 JR |
2368 | /***************************************************************************** |
2369 | * | |
2370 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2371 | * | |
2372 | *****************************************************************************/ | |
2373 | ||
2374 | /* | |
2375 | * In the dma_ops path we only have the struct device. This function | |
2376 | * finds the corresponding IOMMU, the protection domain and the | |
2377 | * requestor id for a given device. | |
2378 | * If the device is not yet associated with a domain this is also done | |
2379 | * in this function. | |
2380 | */ | |
94f6d190 | 2381 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2382 | { |
94f6d190 | 2383 | struct protection_domain *domain; |
063071df | 2384 | struct iommu_domain *io_domain; |
b20ac0d4 | 2385 | |
f99c0f1c | 2386 | if (!check_device(dev)) |
94f6d190 | 2387 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2388 | |
063071df | 2389 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2390 | if (!io_domain) |
2391 | return NULL; | |
b20ac0d4 | 2392 | |
0bb6e243 JR |
2393 | domain = to_pdomain(io_domain); |
2394 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2395 | return ERR_PTR(-EBUSY); |
f91ba190 | 2396 | |
0bb6e243 | 2397 | return domain; |
b20ac0d4 JR |
2398 | } |
2399 | ||
04bfdd84 JR |
2400 | static void update_device_table(struct protection_domain *domain) |
2401 | { | |
492667da | 2402 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2403 | |
ea61cddb JR |
2404 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2405 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2406 | } |
2407 | ||
2408 | static void update_domain(struct protection_domain *domain) | |
2409 | { | |
2410 | if (!domain->updated) | |
2411 | return; | |
2412 | ||
2413 | update_device_table(domain); | |
17b124bf JR |
2414 | |
2415 | domain_flush_devices(domain); | |
2416 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2417 | |
2418 | domain->updated = false; | |
2419 | } | |
2420 | ||
8bda3092 JR |
2421 | /* |
2422 | * This function fetches the PTE for a given address in the aperture | |
2423 | */ | |
2424 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2425 | unsigned long address) | |
2426 | { | |
384de729 | 2427 | struct aperture_range *aperture; |
8bda3092 JR |
2428 | u64 *pte, *pte_page; |
2429 | ||
384de729 JR |
2430 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2431 | if (!aperture) | |
2432 | return NULL; | |
2433 | ||
2434 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2435 | if (!pte) { |
cbb9d729 | 2436 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2437 | GFP_ATOMIC); |
384de729 JR |
2438 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2439 | } else | |
8c8c143c | 2440 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2441 | |
04bfdd84 | 2442 | update_domain(&dom->domain); |
8bda3092 JR |
2443 | |
2444 | return pte; | |
2445 | } | |
2446 | ||
431b2a20 JR |
2447 | /* |
2448 | * This is the generic map function. It maps one 4kb page at paddr to | |
2449 | * the given address in the DMA address space for the domain. | |
2450 | */ | |
680525e0 | 2451 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2452 | unsigned long address, |
2453 | phys_addr_t paddr, | |
2454 | int direction) | |
2455 | { | |
2456 | u64 *pte, __pte; | |
2457 | ||
2458 | WARN_ON(address > dom->aperture_size); | |
2459 | ||
2460 | paddr &= PAGE_MASK; | |
2461 | ||
8bda3092 | 2462 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2463 | if (!pte) |
8fd524b3 | 2464 | return DMA_ERROR_CODE; |
cb76c322 JR |
2465 | |
2466 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2467 | ||
2468 | if (direction == DMA_TO_DEVICE) | |
2469 | __pte |= IOMMU_PTE_IR; | |
2470 | else if (direction == DMA_FROM_DEVICE) | |
2471 | __pte |= IOMMU_PTE_IW; | |
2472 | else if (direction == DMA_BIDIRECTIONAL) | |
2473 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2474 | ||
a7fb668f | 2475 | WARN_ON_ONCE(*pte); |
cb76c322 JR |
2476 | |
2477 | *pte = __pte; | |
2478 | ||
2479 | return (dma_addr_t)address; | |
2480 | } | |
2481 | ||
431b2a20 JR |
2482 | /* |
2483 | * The generic unmapping function for on page in the DMA address space. | |
2484 | */ | |
680525e0 | 2485 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2486 | unsigned long address) |
2487 | { | |
384de729 | 2488 | struct aperture_range *aperture; |
cb76c322 JR |
2489 | u64 *pte; |
2490 | ||
2491 | if (address >= dom->aperture_size) | |
2492 | return; | |
2493 | ||
384de729 JR |
2494 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2495 | if (!aperture) | |
2496 | return; | |
2497 | ||
2498 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2499 | if (!pte) | |
2500 | return; | |
cb76c322 | 2501 | |
8c8c143c | 2502 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 | 2503 | |
a7fb668f | 2504 | WARN_ON_ONCE(!*pte); |
cb76c322 JR |
2505 | |
2506 | *pte = 0ULL; | |
2507 | } | |
2508 | ||
431b2a20 JR |
2509 | /* |
2510 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2511 | * contiguous memory region into DMA address space. It is used by all |
2512 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2513 | * Must be called with the domain lock held. |
2514 | */ | |
cb76c322 | 2515 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2516 | struct dma_ops_domain *dma_dom, |
2517 | phys_addr_t paddr, | |
2518 | size_t size, | |
6d4f343f | 2519 | int dir, |
832a90c3 JR |
2520 | bool align, |
2521 | u64 dma_mask) | |
cb76c322 JR |
2522 | { |
2523 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2524 | dma_addr_t address, start, ret; |
cb76c322 | 2525 | unsigned int pages; |
6d4f343f | 2526 | unsigned long align_mask = 0; |
cb76c322 JR |
2527 | int i; |
2528 | ||
e3c449f5 | 2529 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2530 | paddr &= PAGE_MASK; |
2531 | ||
8ecaf8f1 JR |
2532 | INC_STATS_COUNTER(total_map_requests); |
2533 | ||
c1858976 JR |
2534 | if (pages > 1) |
2535 | INC_STATS_COUNTER(cross_page); | |
2536 | ||
6d4f343f JR |
2537 | if (align) |
2538 | align_mask = (1UL << get_order(size)) - 1; | |
2539 | ||
832a90c3 JR |
2540 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2541 | dma_mask); | |
ebaecb42 | 2542 | |
266a3bd2 JR |
2543 | if (address == DMA_ERROR_CODE) |
2544 | goto out; | |
cb76c322 JR |
2545 | |
2546 | start = address; | |
2547 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2548 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2549 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2550 | goto out_unmap; |
2551 | ||
cb76c322 JR |
2552 | paddr += PAGE_SIZE; |
2553 | start += PAGE_SIZE; | |
2554 | } | |
2555 | address += offset; | |
2556 | ||
5774f7c5 JR |
2557 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2558 | ||
ab7032bb | 2559 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2560 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2561 | domain_flush_complete(&dma_dom->domain); |
2562 | } | |
270cab24 | 2563 | |
cb76c322 JR |
2564 | out: |
2565 | return address; | |
53812c11 JR |
2566 | |
2567 | out_unmap: | |
2568 | ||
2569 | for (--i; i >= 0; --i) { | |
2570 | start -= PAGE_SIZE; | |
680525e0 | 2571 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2572 | } |
2573 | ||
2574 | dma_ops_free_addresses(dma_dom, address, pages); | |
2575 | ||
8fd524b3 | 2576 | return DMA_ERROR_CODE; |
cb76c322 JR |
2577 | } |
2578 | ||
431b2a20 JR |
2579 | /* |
2580 | * Does the reverse of the __map_single function. Must be called with | |
2581 | * the domain lock held too | |
2582 | */ | |
cd8c82e8 | 2583 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2584 | dma_addr_t dma_addr, |
2585 | size_t size, | |
2586 | int dir) | |
2587 | { | |
04e0463e | 2588 | dma_addr_t flush_addr; |
cb76c322 JR |
2589 | dma_addr_t i, start; |
2590 | unsigned int pages; | |
2591 | ||
8fd524b3 | 2592 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2593 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2594 | return; |
2595 | ||
04e0463e | 2596 | flush_addr = dma_addr; |
e3c449f5 | 2597 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2598 | dma_addr &= PAGE_MASK; |
2599 | start = dma_addr; | |
2600 | ||
2601 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2602 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2603 | start += PAGE_SIZE; |
2604 | } | |
2605 | ||
84b3a0bc JR |
2606 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2607 | ||
2608 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
cb76c322 JR |
2609 | } |
2610 | ||
431b2a20 JR |
2611 | /* |
2612 | * The exported map_single function for dma_ops. | |
2613 | */ | |
51491367 FT |
2614 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2615 | unsigned long offset, size_t size, | |
2616 | enum dma_data_direction dir, | |
2617 | struct dma_attrs *attrs) | |
4da70b9e | 2618 | { |
92d420ec | 2619 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2620 | struct protection_domain *domain; |
832a90c3 | 2621 | u64 dma_mask; |
4da70b9e | 2622 | |
0f2a86f2 JR |
2623 | INC_STATS_COUNTER(cnt_map_single); |
2624 | ||
94f6d190 JR |
2625 | domain = get_domain(dev); |
2626 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2627 | return (dma_addr_t)paddr; |
94f6d190 JR |
2628 | else if (IS_ERR(domain)) |
2629 | return DMA_ERROR_CODE; | |
4da70b9e | 2630 | |
f99c0f1c JR |
2631 | dma_mask = *dev->dma_mask; |
2632 | ||
92d420ec | 2633 | return __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2634 | dma_mask); |
4da70b9e JR |
2635 | } |
2636 | ||
431b2a20 JR |
2637 | /* |
2638 | * The exported unmap_single function for dma_ops. | |
2639 | */ | |
51491367 FT |
2640 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2641 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e | 2642 | { |
4da70b9e | 2643 | struct protection_domain *domain; |
4da70b9e | 2644 | |
146a6917 JR |
2645 | INC_STATS_COUNTER(cnt_unmap_single); |
2646 | ||
94f6d190 JR |
2647 | domain = get_domain(dev); |
2648 | if (IS_ERR(domain)) | |
5b28df6f JR |
2649 | return; |
2650 | ||
cd8c82e8 | 2651 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e JR |
2652 | } |
2653 | ||
431b2a20 JR |
2654 | /* |
2655 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2656 | * lists). | |
2657 | */ | |
65b050ad | 2658 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2659 | int nelems, enum dma_data_direction dir, |
2660 | struct dma_attrs *attrs) | |
65b050ad | 2661 | { |
65b050ad | 2662 | struct protection_domain *domain; |
65b050ad JR |
2663 | int i; |
2664 | struct scatterlist *s; | |
2665 | phys_addr_t paddr; | |
2666 | int mapped_elems = 0; | |
832a90c3 | 2667 | u64 dma_mask; |
65b050ad | 2668 | |
d03f067a JR |
2669 | INC_STATS_COUNTER(cnt_map_sg); |
2670 | ||
94f6d190 | 2671 | domain = get_domain(dev); |
a0e191b2 | 2672 | if (IS_ERR(domain)) |
94f6d190 | 2673 | return 0; |
dbcc112e | 2674 | |
832a90c3 | 2675 | dma_mask = *dev->dma_mask; |
65b050ad | 2676 | |
65b050ad JR |
2677 | for_each_sg(sglist, s, nelems, i) { |
2678 | paddr = sg_phys(s); | |
2679 | ||
cd8c82e8 | 2680 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2681 | paddr, s->length, dir, false, |
2682 | dma_mask); | |
65b050ad JR |
2683 | |
2684 | if (s->dma_address) { | |
2685 | s->dma_length = s->length; | |
2686 | mapped_elems++; | |
2687 | } else | |
2688 | goto unmap; | |
65b050ad JR |
2689 | } |
2690 | ||
65b050ad | 2691 | return mapped_elems; |
92d420ec | 2692 | |
65b050ad JR |
2693 | unmap: |
2694 | for_each_sg(sglist, s, mapped_elems, i) { | |
2695 | if (s->dma_address) | |
cd8c82e8 | 2696 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2697 | s->dma_length, dir); |
2698 | s->dma_address = s->dma_length = 0; | |
2699 | } | |
2700 | ||
92d420ec | 2701 | return 0; |
65b050ad JR |
2702 | } |
2703 | ||
431b2a20 JR |
2704 | /* |
2705 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2706 | * lists). | |
2707 | */ | |
65b050ad | 2708 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2709 | int nelems, enum dma_data_direction dir, |
2710 | struct dma_attrs *attrs) | |
65b050ad | 2711 | { |
65b050ad JR |
2712 | struct protection_domain *domain; |
2713 | struct scatterlist *s; | |
65b050ad JR |
2714 | int i; |
2715 | ||
55877a6b JR |
2716 | INC_STATS_COUNTER(cnt_unmap_sg); |
2717 | ||
94f6d190 JR |
2718 | domain = get_domain(dev); |
2719 | if (IS_ERR(domain)) | |
5b28df6f JR |
2720 | return; |
2721 | ||
65b050ad | 2722 | for_each_sg(sglist, s, nelems, i) { |
cd8c82e8 | 2723 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2724 | s->dma_length, dir); |
65b050ad JR |
2725 | s->dma_address = s->dma_length = 0; |
2726 | } | |
65b050ad JR |
2727 | } |
2728 | ||
431b2a20 JR |
2729 | /* |
2730 | * The exported alloc_coherent function for dma_ops. | |
2731 | */ | |
5d8b53cf | 2732 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2733 | dma_addr_t *dma_addr, gfp_t flag, |
2734 | struct dma_attrs *attrs) | |
5d8b53cf | 2735 | { |
832a90c3 | 2736 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2737 | struct protection_domain *domain; |
3b839a57 | 2738 | struct page *page; |
5d8b53cf | 2739 | |
c8f0fb36 JR |
2740 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2741 | ||
94f6d190 JR |
2742 | domain = get_domain(dev); |
2743 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2744 | page = alloc_pages(flag, get_order(size)); |
2745 | *dma_addr = page_to_phys(page); | |
2746 | return page_address(page); | |
94f6d190 JR |
2747 | } else if (IS_ERR(domain)) |
2748 | return NULL; | |
5d8b53cf | 2749 | |
3b839a57 | 2750 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2751 | dma_mask = dev->coherent_dma_mask; |
2752 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2753 | flag |= __GFP_ZERO; |
5d8b53cf | 2754 | |
3b839a57 JR |
2755 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2756 | if (!page) { | |
d0164adc | 2757 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2758 | return NULL; |
5d8b53cf | 2759 | |
3b839a57 JR |
2760 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2761 | get_order(size)); | |
2762 | if (!page) | |
2763 | return NULL; | |
2764 | } | |
5d8b53cf | 2765 | |
832a90c3 JR |
2766 | if (!dma_mask) |
2767 | dma_mask = *dev->dma_mask; | |
2768 | ||
3b839a57 | 2769 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2770 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2771 | |
92d420ec | 2772 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2773 | goto out_free; |
5d8b53cf | 2774 | |
3b839a57 | 2775 | return page_address(page); |
5b28df6f JR |
2776 | |
2777 | out_free: | |
2778 | ||
3b839a57 JR |
2779 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2780 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2781 | |
2782 | return NULL; | |
5d8b53cf JR |
2783 | } |
2784 | ||
431b2a20 JR |
2785 | /* |
2786 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2787 | */ |
5d8b53cf | 2788 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2789 | void *virt_addr, dma_addr_t dma_addr, |
2790 | struct dma_attrs *attrs) | |
5d8b53cf | 2791 | { |
5d8b53cf | 2792 | struct protection_domain *domain; |
3b839a57 | 2793 | struct page *page; |
5d8b53cf | 2794 | |
5d31ee7e JR |
2795 | INC_STATS_COUNTER(cnt_free_coherent); |
2796 | ||
3b839a57 JR |
2797 | page = virt_to_page(virt_addr); |
2798 | size = PAGE_ALIGN(size); | |
2799 | ||
94f6d190 JR |
2800 | domain = get_domain(dev); |
2801 | if (IS_ERR(domain)) | |
5b28df6f JR |
2802 | goto free_mem; |
2803 | ||
cd8c82e8 | 2804 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2805 | |
5d8b53cf | 2806 | free_mem: |
3b839a57 JR |
2807 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2808 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2809 | } |
2810 | ||
b39ba6ad JR |
2811 | /* |
2812 | * This function is called by the DMA layer to find out if we can handle a | |
2813 | * particular device. It is part of the dma_ops. | |
2814 | */ | |
2815 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2816 | { | |
420aef8a | 2817 | return check_device(dev); |
b39ba6ad JR |
2818 | } |
2819 | ||
a639a8ee JR |
2820 | static int set_dma_mask(struct device *dev, u64 mask) |
2821 | { | |
2822 | struct protection_domain *domain; | |
2823 | int max_apertures = 1; | |
2824 | ||
2825 | domain = get_domain(dev); | |
2826 | if (IS_ERR(domain)) | |
2827 | return PTR_ERR(domain); | |
2828 | ||
2829 | if (mask == DMA_BIT_MASK(64)) | |
2830 | max_apertures = 8; | |
2831 | else if (mask > DMA_BIT_MASK(32)) | |
2832 | max_apertures = 4; | |
2833 | ||
2834 | /* | |
2835 | * To prevent lock contention it doesn't make sense to allocate more | |
2836 | * apertures than online cpus | |
2837 | */ | |
2838 | if (max_apertures > num_online_cpus()) | |
2839 | max_apertures = num_online_cpus(); | |
2840 | ||
2841 | if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures)) | |
2842 | dev_err(dev, "Can't allocate %d iommu apertures\n", | |
2843 | max_apertures); | |
2844 | ||
2845 | return 0; | |
2846 | } | |
2847 | ||
160c1d8e | 2848 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2849 | .alloc = alloc_coherent, |
2850 | .free = free_coherent, | |
2851 | .map_page = map_page, | |
2852 | .unmap_page = unmap_page, | |
2853 | .map_sg = map_sg, | |
2854 | .unmap_sg = unmap_sg, | |
2855 | .dma_supported = amd_iommu_dma_supported, | |
2856 | .set_dma_mask = set_dma_mask, | |
6631ee9d JR |
2857 | }; |
2858 | ||
3a18404c | 2859 | int __init amd_iommu_init_api(void) |
27c2127a | 2860 | { |
3a18404c | 2861 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2862 | } |
2863 | ||
6631ee9d JR |
2864 | int __init amd_iommu_init_dma_ops(void) |
2865 | { | |
32302324 | 2866 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2867 | iommu_detected = 1; |
6631ee9d | 2868 | |
52717828 JR |
2869 | /* |
2870 | * In case we don't initialize SWIOTLB (actually the common case | |
2871 | * when AMD IOMMU is enabled), make sure there are global | |
2872 | * dma_ops set as a fall-back for devices not handled by this | |
2873 | * driver (for example non-PCI devices). | |
2874 | */ | |
2875 | if (!swiotlb) | |
2876 | dma_ops = &nommu_dma_ops; | |
2877 | ||
7f26508b JR |
2878 | amd_iommu_stats_init(); |
2879 | ||
62410eeb JR |
2880 | if (amd_iommu_unmap_flush) |
2881 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2882 | else | |
2883 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2884 | ||
6631ee9d | 2885 | return 0; |
6631ee9d | 2886 | } |
6d98cd80 JR |
2887 | |
2888 | /***************************************************************************** | |
2889 | * | |
2890 | * The following functions belong to the exported interface of AMD IOMMU | |
2891 | * | |
2892 | * This interface allows access to lower level functions of the IOMMU | |
2893 | * like protection domain handling and assignement of devices to domains | |
2894 | * which is not possible with the dma_ops interface. | |
2895 | * | |
2896 | *****************************************************************************/ | |
2897 | ||
6d98cd80 JR |
2898 | static void cleanup_domain(struct protection_domain *domain) |
2899 | { | |
9b29d3c6 | 2900 | struct iommu_dev_data *entry; |
6d98cd80 | 2901 | unsigned long flags; |
6d98cd80 JR |
2902 | |
2903 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2904 | ||
9b29d3c6 JR |
2905 | while (!list_empty(&domain->dev_list)) { |
2906 | entry = list_first_entry(&domain->dev_list, | |
2907 | struct iommu_dev_data, list); | |
2908 | __detach_device(entry); | |
492667da | 2909 | } |
6d98cd80 JR |
2910 | |
2911 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2912 | } | |
2913 | ||
2650815f JR |
2914 | static void protection_domain_free(struct protection_domain *domain) |
2915 | { | |
2916 | if (!domain) | |
2917 | return; | |
2918 | ||
aeb26f55 JR |
2919 | del_domain_from_list(domain); |
2920 | ||
2650815f JR |
2921 | if (domain->id) |
2922 | domain_id_free(domain->id); | |
2923 | ||
2924 | kfree(domain); | |
2925 | } | |
2926 | ||
7a5a566e JR |
2927 | static int protection_domain_init(struct protection_domain *domain) |
2928 | { | |
2929 | spin_lock_init(&domain->lock); | |
2930 | mutex_init(&domain->api_lock); | |
2931 | domain->id = domain_id_alloc(); | |
2932 | if (!domain->id) | |
2933 | return -ENOMEM; | |
2934 | INIT_LIST_HEAD(&domain->dev_list); | |
2935 | ||
2936 | return 0; | |
2937 | } | |
2938 | ||
2650815f | 2939 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2940 | { |
2941 | struct protection_domain *domain; | |
2942 | ||
2943 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2944 | if (!domain) | |
2650815f | 2945 | return NULL; |
c156e347 | 2946 | |
7a5a566e | 2947 | if (protection_domain_init(domain)) |
2650815f JR |
2948 | goto out_err; |
2949 | ||
aeb26f55 JR |
2950 | add_domain_to_list(domain); |
2951 | ||
2650815f JR |
2952 | return domain; |
2953 | ||
2954 | out_err: | |
2955 | kfree(domain); | |
2956 | ||
2957 | return NULL; | |
2958 | } | |
2959 | ||
3f4b87b9 | 2960 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2961 | { |
3f4b87b9 | 2962 | struct protection_domain *pdomain; |
0bb6e243 | 2963 | struct dma_ops_domain *dma_domain; |
2650815f | 2964 | |
0bb6e243 JR |
2965 | switch (type) { |
2966 | case IOMMU_DOMAIN_UNMANAGED: | |
2967 | pdomain = protection_domain_alloc(); | |
2968 | if (!pdomain) | |
2969 | return NULL; | |
c156e347 | 2970 | |
0bb6e243 JR |
2971 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2972 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2973 | if (!pdomain->pt_root) { | |
2974 | protection_domain_free(pdomain); | |
2975 | return NULL; | |
2976 | } | |
c156e347 | 2977 | |
0bb6e243 JR |
2978 | pdomain->domain.geometry.aperture_start = 0; |
2979 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2980 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2981 | |
0bb6e243 JR |
2982 | break; |
2983 | case IOMMU_DOMAIN_DMA: | |
2984 | dma_domain = dma_ops_domain_alloc(); | |
2985 | if (!dma_domain) { | |
2986 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2987 | return NULL; | |
2988 | } | |
2989 | pdomain = &dma_domain->domain; | |
2990 | break; | |
07f643a3 JR |
2991 | case IOMMU_DOMAIN_IDENTITY: |
2992 | pdomain = protection_domain_alloc(); | |
2993 | if (!pdomain) | |
2994 | return NULL; | |
c156e347 | 2995 | |
07f643a3 JR |
2996 | pdomain->mode = PAGE_MODE_NONE; |
2997 | break; | |
0bb6e243 JR |
2998 | default: |
2999 | return NULL; | |
3000 | } | |
c156e347 | 3001 | |
3f4b87b9 | 3002 | return &pdomain->domain; |
c156e347 JR |
3003 | } |
3004 | ||
3f4b87b9 | 3005 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3006 | { |
3f4b87b9 | 3007 | struct protection_domain *domain; |
98383fc3 | 3008 | |
3f4b87b9 | 3009 | if (!dom) |
98383fc3 JR |
3010 | return; |
3011 | ||
3f4b87b9 JR |
3012 | domain = to_pdomain(dom); |
3013 | ||
98383fc3 JR |
3014 | if (domain->dev_cnt > 0) |
3015 | cleanup_domain(domain); | |
3016 | ||
3017 | BUG_ON(domain->dev_cnt != 0); | |
3018 | ||
132bd68f JR |
3019 | if (domain->mode != PAGE_MODE_NONE) |
3020 | free_pagetable(domain); | |
98383fc3 | 3021 | |
52815b75 JR |
3022 | if (domain->flags & PD_IOMMUV2_MASK) |
3023 | free_gcr3_table(domain); | |
3024 | ||
8b408fe4 | 3025 | protection_domain_free(domain); |
98383fc3 JR |
3026 | } |
3027 | ||
684f2888 JR |
3028 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3029 | struct device *dev) | |
3030 | { | |
657cbb6b | 3031 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3032 | struct amd_iommu *iommu; |
684f2888 JR |
3033 | u16 devid; |
3034 | ||
98fc5a69 | 3035 | if (!check_device(dev)) |
684f2888 JR |
3036 | return; |
3037 | ||
98fc5a69 | 3038 | devid = get_device_id(dev); |
684f2888 | 3039 | |
657cbb6b | 3040 | if (dev_data->domain != NULL) |
15898bbc | 3041 | detach_device(dev); |
684f2888 JR |
3042 | |
3043 | iommu = amd_iommu_rlookup_table[devid]; | |
3044 | if (!iommu) | |
3045 | return; | |
3046 | ||
684f2888 JR |
3047 | iommu_completion_wait(iommu); |
3048 | } | |
3049 | ||
01106066 JR |
3050 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3051 | struct device *dev) | |
3052 | { | |
3f4b87b9 | 3053 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3054 | struct iommu_dev_data *dev_data; |
01106066 | 3055 | struct amd_iommu *iommu; |
15898bbc | 3056 | int ret; |
01106066 | 3057 | |
98fc5a69 | 3058 | if (!check_device(dev)) |
01106066 JR |
3059 | return -EINVAL; |
3060 | ||
657cbb6b JR |
3061 | dev_data = dev->archdata.iommu; |
3062 | ||
f62dda66 | 3063 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3064 | if (!iommu) |
3065 | return -EINVAL; | |
3066 | ||
657cbb6b | 3067 | if (dev_data->domain) |
15898bbc | 3068 | detach_device(dev); |
01106066 | 3069 | |
15898bbc | 3070 | ret = attach_device(dev, domain); |
01106066 JR |
3071 | |
3072 | iommu_completion_wait(iommu); | |
3073 | ||
15898bbc | 3074 | return ret; |
01106066 JR |
3075 | } |
3076 | ||
468e2366 | 3077 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3078 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3079 | { |
3f4b87b9 | 3080 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3081 | int prot = 0; |
3082 | int ret; | |
3083 | ||
132bd68f JR |
3084 | if (domain->mode == PAGE_MODE_NONE) |
3085 | return -EINVAL; | |
3086 | ||
c6229ca6 JR |
3087 | if (iommu_prot & IOMMU_READ) |
3088 | prot |= IOMMU_PROT_IR; | |
3089 | if (iommu_prot & IOMMU_WRITE) | |
3090 | prot |= IOMMU_PROT_IW; | |
3091 | ||
5d214fe6 | 3092 | mutex_lock(&domain->api_lock); |
795e74f7 | 3093 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3094 | mutex_unlock(&domain->api_lock); |
3095 | ||
795e74f7 | 3096 | return ret; |
c6229ca6 JR |
3097 | } |
3098 | ||
5009065d OBC |
3099 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3100 | size_t page_size) | |
eb74ff6c | 3101 | { |
3f4b87b9 | 3102 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3103 | size_t unmap_size; |
eb74ff6c | 3104 | |
132bd68f JR |
3105 | if (domain->mode == PAGE_MODE_NONE) |
3106 | return -EINVAL; | |
3107 | ||
5d214fe6 | 3108 | mutex_lock(&domain->api_lock); |
468e2366 | 3109 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3110 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3111 | |
17b124bf | 3112 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3113 | |
5009065d | 3114 | return unmap_size; |
eb74ff6c JR |
3115 | } |
3116 | ||
645c4c8d | 3117 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3118 | dma_addr_t iova) |
645c4c8d | 3119 | { |
3f4b87b9 | 3120 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3121 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3122 | u64 *pte, __pte; |
645c4c8d | 3123 | |
132bd68f JR |
3124 | if (domain->mode == PAGE_MODE_NONE) |
3125 | return iova; | |
3126 | ||
3039ca1b | 3127 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3128 | |
a6d41a40 | 3129 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3130 | return 0; |
3131 | ||
b24b1b63 JR |
3132 | offset_mask = pte_pgsize - 1; |
3133 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3134 | |
b24b1b63 | 3135 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3136 | } |
3137 | ||
ab636481 | 3138 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3139 | { |
80a506b8 JR |
3140 | switch (cap) { |
3141 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3142 | return true; |
bdddadcb | 3143 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3144 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3145 | case IOMMU_CAP_NOEXEC: |
3146 | return false; | |
80a506b8 JR |
3147 | } |
3148 | ||
ab636481 | 3149 | return false; |
dbb9fd86 SY |
3150 | } |
3151 | ||
35cf248f JR |
3152 | static void amd_iommu_get_dm_regions(struct device *dev, |
3153 | struct list_head *head) | |
3154 | { | |
3155 | struct unity_map_entry *entry; | |
3156 | u16 devid; | |
3157 | ||
3158 | devid = get_device_id(dev); | |
3159 | ||
3160 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3161 | struct iommu_dm_region *region; | |
3162 | ||
3163 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3164 | continue; | |
3165 | ||
3166 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3167 | if (!region) { | |
3168 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3169 | dev_name(dev)); | |
3170 | return; | |
3171 | } | |
3172 | ||
3173 | region->start = entry->address_start; | |
3174 | region->length = entry->address_end - entry->address_start; | |
3175 | if (entry->prot & IOMMU_PROT_IR) | |
3176 | region->prot |= IOMMU_READ; | |
3177 | if (entry->prot & IOMMU_PROT_IW) | |
3178 | region->prot |= IOMMU_WRITE; | |
3179 | ||
3180 | list_add_tail(®ion->list, head); | |
3181 | } | |
3182 | } | |
3183 | ||
3184 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3185 | struct list_head *head) | |
3186 | { | |
3187 | struct iommu_dm_region *entry, *next; | |
3188 | ||
3189 | list_for_each_entry_safe(entry, next, head, list) | |
3190 | kfree(entry); | |
3191 | } | |
3192 | ||
b22f6434 | 3193 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3194 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3195 | .domain_alloc = amd_iommu_domain_alloc, |
3196 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3197 | .attach_dev = amd_iommu_attach_device, |
3198 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3199 | .map = amd_iommu_map, |
3200 | .unmap = amd_iommu_unmap, | |
315786eb | 3201 | .map_sg = default_iommu_map_sg, |
26961efe | 3202 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3203 | .add_device = amd_iommu_add_device, |
3204 | .remove_device = amd_iommu_remove_device, | |
a960fadb | 3205 | .device_group = pci_device_group, |
35cf248f JR |
3206 | .get_dm_regions = amd_iommu_get_dm_regions, |
3207 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3208 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3209 | }; |
3210 | ||
0feae533 JR |
3211 | /***************************************************************************** |
3212 | * | |
3213 | * The next functions do a basic initialization of IOMMU for pass through | |
3214 | * mode | |
3215 | * | |
3216 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3217 | * DMA-API translation. | |
3218 | * | |
3219 | *****************************************************************************/ | |
3220 | ||
72e1dcc4 JR |
3221 | /* IOMMUv2 specific functions */ |
3222 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3223 | { | |
3224 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3225 | } | |
3226 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3227 | ||
3228 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3229 | { | |
3230 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3231 | } | |
3232 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3233 | |
3234 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3235 | { | |
3f4b87b9 | 3236 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3237 | unsigned long flags; |
3238 | ||
3239 | spin_lock_irqsave(&domain->lock, flags); | |
3240 | ||
3241 | /* Update data structure */ | |
3242 | domain->mode = PAGE_MODE_NONE; | |
3243 | domain->updated = true; | |
3244 | ||
3245 | /* Make changes visible to IOMMUs */ | |
3246 | update_domain(domain); | |
3247 | ||
3248 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3249 | free_pagetable(domain); | |
3250 | ||
3251 | spin_unlock_irqrestore(&domain->lock, flags); | |
3252 | } | |
3253 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3254 | |
3255 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3256 | { | |
3f4b87b9 | 3257 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3258 | unsigned long flags; |
3259 | int levels, ret; | |
3260 | ||
3261 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3262 | return -EINVAL; | |
3263 | ||
3264 | /* Number of GCR3 table levels required */ | |
3265 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3266 | levels += 1; | |
3267 | ||
3268 | if (levels > amd_iommu_max_glx_val) | |
3269 | return -EINVAL; | |
3270 | ||
3271 | spin_lock_irqsave(&domain->lock, flags); | |
3272 | ||
3273 | /* | |
3274 | * Save us all sanity checks whether devices already in the | |
3275 | * domain support IOMMUv2. Just force that the domain has no | |
3276 | * devices attached when it is switched into IOMMUv2 mode. | |
3277 | */ | |
3278 | ret = -EBUSY; | |
3279 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3280 | goto out; | |
3281 | ||
3282 | ret = -ENOMEM; | |
3283 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3284 | if (domain->gcr3_tbl == NULL) | |
3285 | goto out; | |
3286 | ||
3287 | domain->glx = levels; | |
3288 | domain->flags |= PD_IOMMUV2_MASK; | |
3289 | domain->updated = true; | |
3290 | ||
3291 | update_domain(domain); | |
3292 | ||
3293 | ret = 0; | |
3294 | ||
3295 | out: | |
3296 | spin_unlock_irqrestore(&domain->lock, flags); | |
3297 | ||
3298 | return ret; | |
3299 | } | |
3300 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3301 | |
3302 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3303 | u64 address, bool size) | |
3304 | { | |
3305 | struct iommu_dev_data *dev_data; | |
3306 | struct iommu_cmd cmd; | |
3307 | int i, ret; | |
3308 | ||
3309 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3310 | return -EINVAL; | |
3311 | ||
3312 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3313 | ||
3314 | /* | |
3315 | * IOMMU TLB needs to be flushed before Device TLB to | |
3316 | * prevent device TLB refill from IOMMU TLB | |
3317 | */ | |
3318 | for (i = 0; i < amd_iommus_present; ++i) { | |
3319 | if (domain->dev_iommu[i] == 0) | |
3320 | continue; | |
3321 | ||
3322 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3323 | if (ret != 0) | |
3324 | goto out; | |
3325 | } | |
3326 | ||
3327 | /* Wait until IOMMU TLB flushes are complete */ | |
3328 | domain_flush_complete(domain); | |
3329 | ||
3330 | /* Now flush device TLBs */ | |
3331 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3332 | struct amd_iommu *iommu; | |
3333 | int qdep; | |
3334 | ||
1c1cc454 JR |
3335 | /* |
3336 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3337 | * domain. | |
3338 | */ | |
3339 | if (!dev_data->ats.enabled) | |
3340 | continue; | |
22e266c7 JR |
3341 | |
3342 | qdep = dev_data->ats.qdep; | |
3343 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3344 | ||
3345 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3346 | qdep, address, size); | |
3347 | ||
3348 | ret = iommu_queue_command(iommu, &cmd); | |
3349 | if (ret != 0) | |
3350 | goto out; | |
3351 | } | |
3352 | ||
3353 | /* Wait until all device TLBs are flushed */ | |
3354 | domain_flush_complete(domain); | |
3355 | ||
3356 | ret = 0; | |
3357 | ||
3358 | out: | |
3359 | ||
3360 | return ret; | |
3361 | } | |
3362 | ||
3363 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3364 | u64 address) | |
3365 | { | |
399be2f5 JR |
3366 | INC_STATS_COUNTER(invalidate_iotlb); |
3367 | ||
22e266c7 JR |
3368 | return __flush_pasid(domain, pasid, address, false); |
3369 | } | |
3370 | ||
3371 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3372 | u64 address) | |
3373 | { | |
3f4b87b9 | 3374 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3375 | unsigned long flags; |
3376 | int ret; | |
3377 | ||
3378 | spin_lock_irqsave(&domain->lock, flags); | |
3379 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3380 | spin_unlock_irqrestore(&domain->lock, flags); | |
3381 | ||
3382 | return ret; | |
3383 | } | |
3384 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3385 | ||
3386 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3387 | { | |
399be2f5 JR |
3388 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3389 | ||
22e266c7 JR |
3390 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3391 | true); | |
3392 | } | |
3393 | ||
3394 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3395 | { | |
3f4b87b9 | 3396 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3397 | unsigned long flags; |
3398 | int ret; | |
3399 | ||
3400 | spin_lock_irqsave(&domain->lock, flags); | |
3401 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3402 | spin_unlock_irqrestore(&domain->lock, flags); | |
3403 | ||
3404 | return ret; | |
3405 | } | |
3406 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3407 | ||
b16137b1 JR |
3408 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3409 | { | |
3410 | int index; | |
3411 | u64 *pte; | |
3412 | ||
3413 | while (true) { | |
3414 | ||
3415 | index = (pasid >> (9 * level)) & 0x1ff; | |
3416 | pte = &root[index]; | |
3417 | ||
3418 | if (level == 0) | |
3419 | break; | |
3420 | ||
3421 | if (!(*pte & GCR3_VALID)) { | |
3422 | if (!alloc) | |
3423 | return NULL; | |
3424 | ||
3425 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3426 | if (root == NULL) | |
3427 | return NULL; | |
3428 | ||
3429 | *pte = __pa(root) | GCR3_VALID; | |
3430 | } | |
3431 | ||
3432 | root = __va(*pte & PAGE_MASK); | |
3433 | ||
3434 | level -= 1; | |
3435 | } | |
3436 | ||
3437 | return pte; | |
3438 | } | |
3439 | ||
3440 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3441 | unsigned long cr3) | |
3442 | { | |
3443 | u64 *pte; | |
3444 | ||
3445 | if (domain->mode != PAGE_MODE_NONE) | |
3446 | return -EINVAL; | |
3447 | ||
3448 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3449 | if (pte == NULL) | |
3450 | return -ENOMEM; | |
3451 | ||
3452 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3453 | ||
3454 | return __amd_iommu_flush_tlb(domain, pasid); | |
3455 | } | |
3456 | ||
3457 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3458 | { | |
3459 | u64 *pte; | |
3460 | ||
3461 | if (domain->mode != PAGE_MODE_NONE) | |
3462 | return -EINVAL; | |
3463 | ||
3464 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3465 | if (pte == NULL) | |
3466 | return 0; | |
3467 | ||
3468 | *pte = 0; | |
3469 | ||
3470 | return __amd_iommu_flush_tlb(domain, pasid); | |
3471 | } | |
3472 | ||
3473 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3474 | unsigned long cr3) | |
3475 | { | |
3f4b87b9 | 3476 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3477 | unsigned long flags; |
3478 | int ret; | |
3479 | ||
3480 | spin_lock_irqsave(&domain->lock, flags); | |
3481 | ret = __set_gcr3(domain, pasid, cr3); | |
3482 | spin_unlock_irqrestore(&domain->lock, flags); | |
3483 | ||
3484 | return ret; | |
3485 | } | |
3486 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3487 | ||
3488 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3489 | { | |
3f4b87b9 | 3490 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3491 | unsigned long flags; |
3492 | int ret; | |
3493 | ||
3494 | spin_lock_irqsave(&domain->lock, flags); | |
3495 | ret = __clear_gcr3(domain, pasid); | |
3496 | spin_unlock_irqrestore(&domain->lock, flags); | |
3497 | ||
3498 | return ret; | |
3499 | } | |
3500 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3501 | |
3502 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3503 | int status, int tag) | |
3504 | { | |
3505 | struct iommu_dev_data *dev_data; | |
3506 | struct amd_iommu *iommu; | |
3507 | struct iommu_cmd cmd; | |
3508 | ||
399be2f5 JR |
3509 | INC_STATS_COUNTER(complete_ppr); |
3510 | ||
c99afa25 JR |
3511 | dev_data = get_dev_data(&pdev->dev); |
3512 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3513 | ||
3514 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3515 | tag, dev_data->pri_tlp); | |
3516 | ||
3517 | return iommu_queue_command(iommu, &cmd); | |
3518 | } | |
3519 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3520 | |
3521 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3522 | { | |
3f4b87b9 | 3523 | struct protection_domain *pdomain; |
f3572db8 | 3524 | |
3f4b87b9 JR |
3525 | pdomain = get_domain(&pdev->dev); |
3526 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3527 | return NULL; |
3528 | ||
3529 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3530 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3531 | return NULL; |
3532 | ||
3f4b87b9 | 3533 | return &pdomain->domain; |
f3572db8 JR |
3534 | } |
3535 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3536 | |
3537 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3538 | { | |
3539 | struct iommu_dev_data *dev_data; | |
3540 | ||
3541 | if (!amd_iommu_v2_supported()) | |
3542 | return; | |
3543 | ||
3544 | dev_data = get_dev_data(&pdev->dev); | |
3545 | dev_data->errata |= (1 << erratum); | |
3546 | } | |
3547 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3548 | |
3549 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3550 | struct amd_iommu_device_info *info) | |
3551 | { | |
3552 | int max_pasids; | |
3553 | int pos; | |
3554 | ||
3555 | if (pdev == NULL || info == NULL) | |
3556 | return -EINVAL; | |
3557 | ||
3558 | if (!amd_iommu_v2_supported()) | |
3559 | return -EINVAL; | |
3560 | ||
3561 | memset(info, 0, sizeof(*info)); | |
3562 | ||
3563 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3564 | if (pos) | |
3565 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3566 | ||
3567 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3568 | if (pos) | |
3569 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3570 | ||
3571 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3572 | if (pos) { | |
3573 | int features; | |
3574 | ||
3575 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3576 | max_pasids = min(max_pasids, (1 << 20)); | |
3577 | ||
3578 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3579 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3580 | ||
3581 | features = pci_pasid_features(pdev); | |
3582 | if (features & PCI_PASID_CAP_EXEC) | |
3583 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3584 | if (features & PCI_PASID_CAP_PRIV) | |
3585 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3586 | } | |
3587 | ||
3588 | return 0; | |
3589 | } | |
3590 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3591 | |
3592 | #ifdef CONFIG_IRQ_REMAP | |
3593 | ||
3594 | /***************************************************************************** | |
3595 | * | |
3596 | * Interrupt Remapping Implementation | |
3597 | * | |
3598 | *****************************************************************************/ | |
3599 | ||
3600 | union irte { | |
3601 | u32 val; | |
3602 | struct { | |
3603 | u32 valid : 1, | |
3604 | no_fault : 1, | |
3605 | int_type : 3, | |
3606 | rq_eoi : 1, | |
3607 | dm : 1, | |
3608 | rsvd_1 : 1, | |
3609 | destination : 8, | |
3610 | vector : 8, | |
3611 | rsvd_2 : 8; | |
3612 | } fields; | |
3613 | }; | |
3614 | ||
9c724966 JL |
3615 | struct irq_2_irte { |
3616 | u16 devid; /* Device ID for IRTE table */ | |
3617 | u16 index; /* Index into IRTE table*/ | |
3618 | }; | |
3619 | ||
7c71d306 JL |
3620 | struct amd_ir_data { |
3621 | struct irq_2_irte irq_2_irte; | |
3622 | union irte irte_entry; | |
3623 | union { | |
3624 | struct msi_msg msi_entry; | |
3625 | }; | |
3626 | }; | |
3627 | ||
3628 | static struct irq_chip amd_ir_chip; | |
3629 | ||
2b324506 JR |
3630 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3631 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3632 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3633 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3634 | ||
3635 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3636 | { | |
3637 | u64 dte; | |
3638 | ||
3639 | dte = amd_iommu_dev_table[devid].data[2]; | |
3640 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3641 | dte |= virt_to_phys(table->table); | |
3642 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3643 | dte |= DTE_IRQ_TABLE_LEN; | |
3644 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3645 | ||
3646 | amd_iommu_dev_table[devid].data[2] = dte; | |
3647 | } | |
3648 | ||
3649 | #define IRTE_ALLOCATED (~1U) | |
3650 | ||
3651 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3652 | { | |
3653 | struct irq_remap_table *table = NULL; | |
3654 | struct amd_iommu *iommu; | |
3655 | unsigned long flags; | |
3656 | u16 alias; | |
3657 | ||
3658 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3659 | ||
3660 | iommu = amd_iommu_rlookup_table[devid]; | |
3661 | if (!iommu) | |
3662 | goto out_unlock; | |
3663 | ||
3664 | table = irq_lookup_table[devid]; | |
3665 | if (table) | |
3666 | goto out; | |
3667 | ||
3668 | alias = amd_iommu_alias_table[devid]; | |
3669 | table = irq_lookup_table[alias]; | |
3670 | if (table) { | |
3671 | irq_lookup_table[devid] = table; | |
3672 | set_dte_irq_entry(devid, table); | |
3673 | iommu_flush_dte(iommu, devid); | |
3674 | goto out; | |
3675 | } | |
3676 | ||
3677 | /* Nothing there yet, allocate new irq remapping table */ | |
3678 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3679 | if (!table) | |
3680 | goto out; | |
3681 | ||
197887f0 JR |
3682 | /* Initialize table spin-lock */ |
3683 | spin_lock_init(&table->lock); | |
3684 | ||
2b324506 JR |
3685 | if (ioapic) |
3686 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3687 | table->min_index = 32; | |
3688 | ||
3689 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3690 | if (!table->table) { | |
3691 | kfree(table); | |
821f0f68 | 3692 | table = NULL; |
2b324506 JR |
3693 | goto out; |
3694 | } | |
3695 | ||
3696 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3697 | ||
3698 | if (ioapic) { | |
3699 | int i; | |
3700 | ||
3701 | for (i = 0; i < 32; ++i) | |
3702 | table->table[i] = IRTE_ALLOCATED; | |
3703 | } | |
3704 | ||
3705 | irq_lookup_table[devid] = table; | |
3706 | set_dte_irq_entry(devid, table); | |
3707 | iommu_flush_dte(iommu, devid); | |
3708 | if (devid != alias) { | |
3709 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3710 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3711 | iommu_flush_dte(iommu, alias); |
3712 | } | |
3713 | ||
3714 | out: | |
3715 | iommu_completion_wait(iommu); | |
3716 | ||
3717 | out_unlock: | |
3718 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3719 | ||
3720 | return table; | |
3721 | } | |
3722 | ||
3c3d4f90 | 3723 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3724 | { |
3725 | struct irq_remap_table *table; | |
3726 | unsigned long flags; | |
3727 | int index, c; | |
3728 | ||
3729 | table = get_irq_table(devid, false); | |
3730 | if (!table) | |
3731 | return -ENODEV; | |
3732 | ||
3733 | spin_lock_irqsave(&table->lock, flags); | |
3734 | ||
3735 | /* Scan table for free entries */ | |
3736 | for (c = 0, index = table->min_index; | |
3737 | index < MAX_IRQS_PER_TABLE; | |
3738 | ++index) { | |
3739 | if (table->table[index] == 0) | |
3740 | c += 1; | |
3741 | else | |
3742 | c = 0; | |
3743 | ||
3744 | if (c == count) { | |
2b324506 JR |
3745 | for (; c != 0; --c) |
3746 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3747 | ||
3748 | index -= count - 1; | |
2b324506 JR |
3749 | goto out; |
3750 | } | |
3751 | } | |
3752 | ||
3753 | index = -ENOSPC; | |
3754 | ||
3755 | out: | |
3756 | spin_unlock_irqrestore(&table->lock, flags); | |
3757 | ||
3758 | return index; | |
3759 | } | |
3760 | ||
2b324506 JR |
3761 | static int modify_irte(u16 devid, int index, union irte irte) |
3762 | { | |
3763 | struct irq_remap_table *table; | |
3764 | struct amd_iommu *iommu; | |
3765 | unsigned long flags; | |
3766 | ||
3767 | iommu = amd_iommu_rlookup_table[devid]; | |
3768 | if (iommu == NULL) | |
3769 | return -EINVAL; | |
3770 | ||
3771 | table = get_irq_table(devid, false); | |
3772 | if (!table) | |
3773 | return -ENOMEM; | |
3774 | ||
3775 | spin_lock_irqsave(&table->lock, flags); | |
3776 | table->table[index] = irte.val; | |
3777 | spin_unlock_irqrestore(&table->lock, flags); | |
3778 | ||
3779 | iommu_flush_irt(iommu, devid); | |
3780 | iommu_completion_wait(iommu); | |
3781 | ||
3782 | return 0; | |
3783 | } | |
3784 | ||
3785 | static void free_irte(u16 devid, int index) | |
3786 | { | |
3787 | struct irq_remap_table *table; | |
3788 | struct amd_iommu *iommu; | |
3789 | unsigned long flags; | |
3790 | ||
3791 | iommu = amd_iommu_rlookup_table[devid]; | |
3792 | if (iommu == NULL) | |
3793 | return; | |
3794 | ||
3795 | table = get_irq_table(devid, false); | |
3796 | if (!table) | |
3797 | return; | |
3798 | ||
3799 | spin_lock_irqsave(&table->lock, flags); | |
3800 | table->table[index] = 0; | |
3801 | spin_unlock_irqrestore(&table->lock, flags); | |
3802 | ||
3803 | iommu_flush_irt(iommu, devid); | |
3804 | iommu_completion_wait(iommu); | |
3805 | } | |
3806 | ||
7c71d306 | 3807 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3808 | { |
7c71d306 | 3809 | int devid = -1; |
5527de74 | 3810 | |
7c71d306 JL |
3811 | switch (info->type) { |
3812 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3813 | devid = get_ioapic_devid(info->ioapic_id); | |
3814 | break; | |
3815 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3816 | devid = get_hpet_devid(info->hpet_id); | |
3817 | break; | |
3818 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3819 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3820 | devid = get_device_id(&info->msi_dev->dev); | |
3821 | break; | |
3822 | default: | |
3823 | BUG_ON(1); | |
3824 | break; | |
3825 | } | |
5527de74 | 3826 | |
7c71d306 JL |
3827 | return devid; |
3828 | } | |
5527de74 | 3829 | |
7c71d306 JL |
3830 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3831 | { | |
3832 | struct amd_iommu *iommu; | |
3833 | int devid; | |
5527de74 | 3834 | |
7c71d306 JL |
3835 | if (!info) |
3836 | return NULL; | |
5527de74 | 3837 | |
7c71d306 JL |
3838 | devid = get_devid(info); |
3839 | if (devid >= 0) { | |
3840 | iommu = amd_iommu_rlookup_table[devid]; | |
3841 | if (iommu) | |
3842 | return iommu->ir_domain; | |
3843 | } | |
5527de74 | 3844 | |
7c71d306 | 3845 | return NULL; |
5527de74 JR |
3846 | } |
3847 | ||
7c71d306 | 3848 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3849 | { |
7c71d306 JL |
3850 | struct amd_iommu *iommu; |
3851 | int devid; | |
5527de74 | 3852 | |
7c71d306 JL |
3853 | if (!info) |
3854 | return NULL; | |
5527de74 | 3855 | |
7c71d306 JL |
3856 | switch (info->type) { |
3857 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3858 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3859 | devid = get_device_id(&info->msi_dev->dev); | |
1fb260bc DC |
3860 | iommu = amd_iommu_rlookup_table[devid]; |
3861 | if (iommu) | |
3862 | return iommu->msi_domain; | |
7c71d306 JL |
3863 | break; |
3864 | default: | |
3865 | break; | |
3866 | } | |
5527de74 | 3867 | |
7c71d306 JL |
3868 | return NULL; |
3869 | } | |
5527de74 | 3870 | |
6b474b82 | 3871 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3872 | .prepare = amd_iommu_prepare, |
3873 | .enable = amd_iommu_enable, | |
3874 | .disable = amd_iommu_disable, | |
3875 | .reenable = amd_iommu_reenable, | |
3876 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3877 | .get_ir_irq_domain = get_ir_irq_domain, |
3878 | .get_irq_domain = get_irq_domain, | |
3879 | }; | |
5527de74 | 3880 | |
7c71d306 JL |
3881 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3882 | struct irq_cfg *irq_cfg, | |
3883 | struct irq_alloc_info *info, | |
3884 | int devid, int index, int sub_handle) | |
3885 | { | |
3886 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3887 | struct msi_msg *msg = &data->msi_entry; | |
3888 | union irte *irte = &data->irte_entry; | |
3889 | struct IO_APIC_route_entry *entry; | |
5527de74 | 3890 | |
7c71d306 JL |
3891 | data->irq_2_irte.devid = devid; |
3892 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 3893 | |
7c71d306 JL |
3894 | /* Setup IRTE for IOMMU */ |
3895 | irte->val = 0; | |
3896 | irte->fields.vector = irq_cfg->vector; | |
3897 | irte->fields.int_type = apic->irq_delivery_mode; | |
3898 | irte->fields.destination = irq_cfg->dest_apicid; | |
3899 | irte->fields.dm = apic->irq_dest_mode; | |
3900 | irte->fields.valid = 1; | |
3901 | ||
3902 | switch (info->type) { | |
3903 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3904 | /* Setup IOAPIC entry */ | |
3905 | entry = info->ioapic_entry; | |
3906 | info->ioapic_entry = NULL; | |
3907 | memset(entry, 0, sizeof(*entry)); | |
3908 | entry->vector = index; | |
3909 | entry->mask = 0; | |
3910 | entry->trigger = info->ioapic_trigger; | |
3911 | entry->polarity = info->ioapic_polarity; | |
3912 | /* Mask level triggered irqs. */ | |
3913 | if (info->ioapic_trigger) | |
3914 | entry->mask = 1; | |
3915 | break; | |
5527de74 | 3916 | |
7c71d306 JL |
3917 | case X86_IRQ_ALLOC_TYPE_HPET: |
3918 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3919 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3920 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3921 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3922 | msg->data = irte_info->index; | |
3923 | break; | |
5527de74 | 3924 | |
7c71d306 JL |
3925 | default: |
3926 | BUG_ON(1); | |
3927 | break; | |
3928 | } | |
5527de74 JR |
3929 | } |
3930 | ||
7c71d306 JL |
3931 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3932 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3933 | { |
7c71d306 JL |
3934 | struct irq_alloc_info *info = arg; |
3935 | struct irq_data *irq_data; | |
3936 | struct amd_ir_data *data; | |
5527de74 | 3937 | struct irq_cfg *cfg; |
7c71d306 JL |
3938 | int i, ret, devid; |
3939 | int index = -1; | |
5527de74 | 3940 | |
7c71d306 JL |
3941 | if (!info) |
3942 | return -EINVAL; | |
3943 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
3944 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
3945 | return -EINVAL; |
3946 | ||
7c71d306 JL |
3947 | /* |
3948 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3949 | * to support multiple MSI interrupts. | |
3950 | */ | |
3951 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
3952 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 3953 | |
7c71d306 JL |
3954 | devid = get_devid(info); |
3955 | if (devid < 0) | |
3956 | return -EINVAL; | |
5527de74 | 3957 | |
7c71d306 JL |
3958 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3959 | if (ret < 0) | |
3960 | return ret; | |
0b4d48cb | 3961 | |
7c71d306 JL |
3962 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
3963 | if (get_irq_table(devid, true)) | |
3964 | index = info->ioapic_pin; | |
3965 | else | |
3966 | ret = -ENOMEM; | |
3967 | } else { | |
3c3d4f90 | 3968 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
3969 | } |
3970 | if (index < 0) { | |
3971 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
3972 | goto out_free_parent; |
3973 | } | |
0b4d48cb | 3974 | |
7c71d306 JL |
3975 | for (i = 0; i < nr_irqs; i++) { |
3976 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3977 | cfg = irqd_cfg(irq_data); | |
3978 | if (!irq_data || !cfg) { | |
3979 | ret = -EINVAL; | |
3980 | goto out_free_data; | |
3981 | } | |
0b4d48cb | 3982 | |
a130e69f JR |
3983 | ret = -ENOMEM; |
3984 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3985 | if (!data) | |
3986 | goto out_free_data; | |
3987 | ||
7c71d306 JL |
3988 | irq_data->hwirq = (devid << 16) + i; |
3989 | irq_data->chip_data = data; | |
3990 | irq_data->chip = &amd_ir_chip; | |
3991 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
3992 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
3993 | } | |
a130e69f | 3994 | |
7c71d306 | 3995 | return 0; |
0b4d48cb | 3996 | |
7c71d306 JL |
3997 | out_free_data: |
3998 | for (i--; i >= 0; i--) { | |
3999 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4000 | if (irq_data) | |
4001 | kfree(irq_data->chip_data); | |
4002 | } | |
4003 | for (i = 0; i < nr_irqs; i++) | |
4004 | free_irte(devid, index + i); | |
4005 | out_free_parent: | |
4006 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4007 | return ret; | |
0b4d48cb JR |
4008 | } |
4009 | ||
7c71d306 JL |
4010 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4011 | unsigned int nr_irqs) | |
0b4d48cb | 4012 | { |
7c71d306 JL |
4013 | struct irq_2_irte *irte_info; |
4014 | struct irq_data *irq_data; | |
4015 | struct amd_ir_data *data; | |
4016 | int i; | |
0b4d48cb | 4017 | |
7c71d306 JL |
4018 | for (i = 0; i < nr_irqs; i++) { |
4019 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4020 | if (irq_data && irq_data->chip_data) { | |
4021 | data = irq_data->chip_data; | |
4022 | irte_info = &data->irq_2_irte; | |
4023 | free_irte(irte_info->devid, irte_info->index); | |
4024 | kfree(data); | |
4025 | } | |
4026 | } | |
4027 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4028 | } | |
0b4d48cb | 4029 | |
7c71d306 JL |
4030 | static void irq_remapping_activate(struct irq_domain *domain, |
4031 | struct irq_data *irq_data) | |
4032 | { | |
4033 | struct amd_ir_data *data = irq_data->chip_data; | |
4034 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4035 | |
7c71d306 | 4036 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4037 | } |
4038 | ||
7c71d306 JL |
4039 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4040 | struct irq_data *irq_data) | |
0b4d48cb | 4041 | { |
7c71d306 JL |
4042 | struct amd_ir_data *data = irq_data->chip_data; |
4043 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4044 | union irte entry; | |
0b4d48cb | 4045 | |
7c71d306 JL |
4046 | entry.val = 0; |
4047 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4048 | } | |
0b4d48cb | 4049 | |
7c71d306 JL |
4050 | static struct irq_domain_ops amd_ir_domain_ops = { |
4051 | .alloc = irq_remapping_alloc, | |
4052 | .free = irq_remapping_free, | |
4053 | .activate = irq_remapping_activate, | |
4054 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4055 | }; |
0b4d48cb | 4056 | |
7c71d306 JL |
4057 | static int amd_ir_set_affinity(struct irq_data *data, |
4058 | const struct cpumask *mask, bool force) | |
4059 | { | |
4060 | struct amd_ir_data *ir_data = data->chip_data; | |
4061 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4062 | struct irq_cfg *cfg = irqd_cfg(data); | |
4063 | struct irq_data *parent = data->parent_data; | |
4064 | int ret; | |
0b4d48cb | 4065 | |
7c71d306 JL |
4066 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4067 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4068 | return ret; | |
0b4d48cb | 4069 | |
7c71d306 JL |
4070 | /* |
4071 | * Atomically updates the IRTE with the new destination, vector | |
4072 | * and flushes the interrupt entry cache. | |
4073 | */ | |
4074 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4075 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4076 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4077 | |
7c71d306 JL |
4078 | /* |
4079 | * After this point, all the interrupts will start arriving | |
4080 | * at the new destination. So, time to cleanup the previous | |
4081 | * vector allocation. | |
4082 | */ | |
c6c2002b | 4083 | send_cleanup_vector(cfg); |
7c71d306 JL |
4084 | |
4085 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4086 | } |
4087 | ||
7c71d306 | 4088 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4089 | { |
7c71d306 | 4090 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4091 | |
7c71d306 JL |
4092 | *msg = ir_data->msi_entry; |
4093 | } | |
d976195c | 4094 | |
7c71d306 JL |
4095 | static struct irq_chip amd_ir_chip = { |
4096 | .irq_ack = ir_ack_apic_edge, | |
4097 | .irq_set_affinity = amd_ir_set_affinity, | |
4098 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4099 | }; | |
d976195c | 4100 | |
7c71d306 JL |
4101 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4102 | { | |
4103 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4104 | if (!iommu->ir_domain) | |
4105 | return -ENOMEM; | |
d976195c | 4106 | |
7c71d306 JL |
4107 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4108 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4109 | |
4110 | return 0; | |
4111 | } | |
2b324506 | 4112 | #endif |