Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
7c71d306 | 37 | #include <linux/irqdomain.h> |
2b324506 JR |
38 | #include <asm/irq_remapping.h> |
39 | #include <asm/io_apic.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/hw_irq.h> | |
17f5b569 | 42 | #include <asm/msidef.h> |
b6c02715 | 43 | #include <asm/proto.h> |
46a7fa27 | 44 | #include <asm/iommu.h> |
1d9b16d1 | 45 | #include <asm/gart.h> |
27c2127a | 46 | #include <asm/dma.h> |
403f81d8 JR |
47 | |
48 | #include "amd_iommu_proto.h" | |
49 | #include "amd_iommu_types.h" | |
6b474b82 | 50 | #include "irq_remapping.h" |
b6c02715 JR |
51 | |
52 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
53 | ||
815b33fd | 54 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 55 | |
aa3de9c0 OBC |
56 | /* |
57 | * This bitmap is used to advertise the page sizes our hardware support | |
58 | * to the IOMMU core, which will then use this information to split | |
59 | * physically contiguous memory regions it is mapping into page sizes | |
60 | * that we support. | |
61 | * | |
954e3dd8 | 62 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 63 | */ |
954e3dd8 | 64 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 65 | |
b6c02715 JR |
66 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
67 | ||
8fa5f802 JR |
68 | /* List of all available dev_data structures */ |
69 | static LIST_HEAD(dev_data_list); | |
70 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
71 | ||
6efed63b JR |
72 | LIST_HEAD(ioapic_map); |
73 | LIST_HEAD(hpet_map); | |
74 | ||
0feae533 JR |
75 | /* |
76 | * Domain for untranslated devices - only allocated | |
77 | * if iommu=pt passed on kernel cmd line. | |
78 | */ | |
79 | static struct protection_domain *pt_domain; | |
80 | ||
b22f6434 | 81 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 82 | |
72e1dcc4 | 83 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 84 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 85 | |
ac1534a5 JR |
86 | static struct dma_map_ops amd_iommu_dma_ops; |
87 | ||
50917e26 JR |
88 | /* |
89 | * This struct contains device specific data for the IOMMU | |
90 | */ | |
91 | struct iommu_dev_data { | |
92 | struct list_head list; /* For domain->dev_list */ | |
93 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 94 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
95 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
96 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
97 | u16 devid; /* PCI Device ID */ |
98 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
99 | bool passthrough; /* Default for device is pt_domain */ | |
100 | struct { | |
101 | bool enabled; | |
102 | int qdep; | |
103 | } ats; /* ATS state */ | |
104 | bool pri_tlp; /* PASID TLB required for | |
105 | PPR completions */ | |
106 | u32 errata; /* Bitmap for errata to apply */ | |
107 | }; | |
108 | ||
431b2a20 JR |
109 | /* |
110 | * general struct to manage commands send to an IOMMU | |
111 | */ | |
d6449536 | 112 | struct iommu_cmd { |
b6c02715 JR |
113 | u32 data[4]; |
114 | }; | |
115 | ||
05152a04 JR |
116 | struct kmem_cache *amd_iommu_irq_cache; |
117 | ||
04bfdd84 | 118 | static void update_domain(struct protection_domain *domain); |
aafd8ba0 | 119 | static int alloc_passthrough_domain(void); |
7a5a566e | 120 | static int protection_domain_init(struct protection_domain *domain); |
c1eee67b | 121 | |
15898bbc JR |
122 | /**************************************************************************** |
123 | * | |
124 | * Helper functions | |
125 | * | |
126 | ****************************************************************************/ | |
127 | ||
3f4b87b9 JR |
128 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
129 | { | |
130 | return container_of(dom, struct protection_domain, domain); | |
131 | } | |
132 | ||
f62dda66 | 133 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
134 | { |
135 | struct iommu_dev_data *dev_data; | |
136 | unsigned long flags; | |
137 | ||
138 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
139 | if (!dev_data) | |
140 | return NULL; | |
141 | ||
f251e187 JR |
142 | INIT_LIST_HEAD(&dev_data->alias_list); |
143 | ||
f62dda66 | 144 | dev_data->devid = devid; |
8fa5f802 JR |
145 | |
146 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
147 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
148 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
149 | ||
150 | return dev_data; | |
151 | } | |
152 | ||
153 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
154 | { | |
155 | unsigned long flags; | |
156 | ||
157 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
158 | list_del(&dev_data->dev_data_list); | |
159 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
160 | ||
161 | kfree(dev_data); | |
162 | } | |
163 | ||
3b03bb74 JR |
164 | static struct iommu_dev_data *search_dev_data(u16 devid) |
165 | { | |
166 | struct iommu_dev_data *dev_data; | |
167 | unsigned long flags; | |
168 | ||
169 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
170 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
171 | if (dev_data->devid == devid) | |
172 | goto out_unlock; | |
173 | } | |
174 | ||
175 | dev_data = NULL; | |
176 | ||
177 | out_unlock: | |
178 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
179 | ||
180 | return dev_data; | |
181 | } | |
182 | ||
183 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
184 | { | |
185 | struct iommu_dev_data *dev_data; | |
186 | ||
187 | dev_data = search_dev_data(devid); | |
188 | ||
189 | if (dev_data == NULL) | |
190 | dev_data = alloc_dev_data(devid); | |
191 | ||
192 | return dev_data; | |
193 | } | |
194 | ||
15898bbc JR |
195 | static inline u16 get_device_id(struct device *dev) |
196 | { | |
197 | struct pci_dev *pdev = to_pci_dev(dev); | |
198 | ||
6f2729ba | 199 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
200 | } |
201 | ||
657cbb6b JR |
202 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
203 | { | |
204 | return dev->archdata.iommu; | |
205 | } | |
206 | ||
5abcdba4 JR |
207 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
208 | { | |
209 | static const int caps[] = { | |
210 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
211 | PCI_EXT_CAP_ID_PRI, |
212 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
213 | }; |
214 | int i, pos; | |
215 | ||
216 | for (i = 0; i < 3; ++i) { | |
217 | pos = pci_find_ext_capability(pdev, caps[i]); | |
218 | if (pos == 0) | |
219 | return false; | |
220 | } | |
221 | ||
222 | return true; | |
223 | } | |
224 | ||
6a113ddc JR |
225 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
226 | { | |
227 | struct iommu_dev_data *dev_data; | |
228 | ||
229 | dev_data = get_dev_data(&pdev->dev); | |
230 | ||
231 | return dev_data->errata & (1 << erratum) ? true : false; | |
232 | } | |
233 | ||
71c70984 | 234 | /* |
0bb6e243 JR |
235 | * This function actually applies the mapping to the page table of the |
236 | * dma_ops domain. | |
71c70984 | 237 | */ |
0bb6e243 JR |
238 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
239 | struct unity_map_entry *e) | |
71c70984 | 240 | { |
0bb6e243 | 241 | u64 addr; |
71c70984 | 242 | |
0bb6e243 JR |
243 | for (addr = e->address_start; addr < e->address_end; |
244 | addr += PAGE_SIZE) { | |
245 | if (addr < dma_dom->aperture_size) | |
246 | __set_bit(addr >> PAGE_SHIFT, | |
247 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 248 | } |
0bb6e243 | 249 | } |
71c70984 | 250 | |
0bb6e243 JR |
251 | /* |
252 | * Inits the unity mappings required for a specific device | |
253 | */ | |
254 | static void init_unity_mappings_for_device(struct device *dev, | |
255 | struct dma_ops_domain *dma_dom) | |
256 | { | |
257 | struct unity_map_entry *e; | |
258 | u16 devid; | |
71c70984 | 259 | |
0bb6e243 | 260 | devid = get_device_id(dev); |
71c70984 | 261 | |
0bb6e243 JR |
262 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
263 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
264 | continue; | |
265 | alloc_unity_mapping(dma_dom, e); | |
266 | } | |
71c70984 JR |
267 | } |
268 | ||
98fc5a69 JR |
269 | /* |
270 | * This function checks if the driver got a valid device from the caller to | |
271 | * avoid dereferencing invalid pointers. | |
272 | */ | |
273 | static bool check_device(struct device *dev) | |
274 | { | |
275 | u16 devid; | |
276 | ||
277 | if (!dev || !dev->dma_mask) | |
278 | return false; | |
279 | ||
b82a2272 YW |
280 | /* No PCI device */ |
281 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
282 | return false; |
283 | ||
284 | devid = get_device_id(dev); | |
285 | ||
286 | /* Out of our scope? */ | |
287 | if (devid > amd_iommu_last_bdf) | |
288 | return false; | |
289 | ||
290 | if (amd_iommu_rlookup_table[devid] == NULL) | |
291 | return false; | |
292 | ||
293 | return true; | |
294 | } | |
295 | ||
25b11ce2 | 296 | static void init_iommu_group(struct device *dev) |
2851db21 | 297 | { |
0bb6e243 JR |
298 | struct dma_ops_domain *dma_domain; |
299 | struct iommu_domain *domain; | |
2851db21 | 300 | struct iommu_group *group; |
2851db21 | 301 | |
65d5352f | 302 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
303 | if (IS_ERR(group)) |
304 | return; | |
305 | ||
306 | domain = iommu_group_default_domain(group); | |
307 | if (!domain) | |
308 | goto out; | |
309 | ||
310 | dma_domain = to_pdomain(domain)->priv; | |
311 | ||
312 | init_unity_mappings_for_device(dev, dma_domain); | |
313 | out: | |
314 | iommu_group_put(group); | |
eb9c9527 AW |
315 | } |
316 | ||
c1931090 AW |
317 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
318 | { | |
319 | *(u16 *)data = alias; | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static u16 get_alias(struct device *dev) | |
324 | { | |
325 | struct pci_dev *pdev = to_pci_dev(dev); | |
326 | u16 devid, ivrs_alias, pci_alias; | |
327 | ||
328 | devid = get_device_id(dev); | |
329 | ivrs_alias = amd_iommu_alias_table[devid]; | |
330 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
331 | ||
332 | if (ivrs_alias == pci_alias) | |
333 | return ivrs_alias; | |
334 | ||
335 | /* | |
336 | * DMA alias showdown | |
337 | * | |
338 | * The IVRS is fairly reliable in telling us about aliases, but it | |
339 | * can't know about every screwy device. If we don't have an IVRS | |
340 | * reported alias, use the PCI reported alias. In that case we may | |
341 | * still need to initialize the rlookup and dev_table entries if the | |
342 | * alias is to a non-existent device. | |
343 | */ | |
344 | if (ivrs_alias == devid) { | |
345 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
346 | amd_iommu_rlookup_table[pci_alias] = | |
347 | amd_iommu_rlookup_table[devid]; | |
348 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
349 | amd_iommu_dev_table[devid].data, | |
350 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
351 | } | |
352 | ||
353 | return pci_alias; | |
354 | } | |
355 | ||
356 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
357 | "for device %s[%04x:%04x], kernel reported alias " | |
358 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
359 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
360 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
361 | PCI_FUNC(pci_alias)); | |
362 | ||
363 | /* | |
364 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
365 | * bus, then the IVRS table may know about a quirk that we don't. | |
366 | */ | |
367 | if (pci_alias == devid && | |
368 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
369 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
370 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
371 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
372 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
373 | dev_name(dev)); | |
374 | } | |
375 | ||
376 | return ivrs_alias; | |
377 | } | |
378 | ||
eb9c9527 AW |
379 | static int iommu_init_device(struct device *dev) |
380 | { | |
381 | struct pci_dev *pdev = to_pci_dev(dev); | |
382 | struct iommu_dev_data *dev_data; | |
383 | u16 alias; | |
eb9c9527 AW |
384 | |
385 | if (dev->archdata.iommu) | |
386 | return 0; | |
387 | ||
388 | dev_data = find_dev_data(get_device_id(dev)); | |
389 | if (!dev_data) | |
390 | return -ENOMEM; | |
391 | ||
c1931090 AW |
392 | alias = get_alias(dev); |
393 | ||
eb9c9527 AW |
394 | if (alias != dev_data->devid) { |
395 | struct iommu_dev_data *alias_data; | |
396 | ||
397 | alias_data = find_dev_data(alias); | |
398 | if (alias_data == NULL) { | |
399 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
400 | dev_name(dev)); | |
401 | free_dev_data(dev_data); | |
402 | return -ENOTSUPP; | |
403 | } | |
404 | dev_data->alias_data = alias_data; | |
eb9c9527 | 405 | |
f251e187 JR |
406 | /* Add device to the alias_list */ |
407 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 408 | } |
9dcd6130 | 409 | |
5abcdba4 JR |
410 | if (pci_iommuv2_capable(pdev)) { |
411 | struct amd_iommu *iommu; | |
412 | ||
413 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
414 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
415 | } | |
416 | ||
657cbb6b JR |
417 | dev->archdata.iommu = dev_data; |
418 | ||
066f2e98 AW |
419 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
420 | dev); | |
421 | ||
657cbb6b JR |
422 | return 0; |
423 | } | |
424 | ||
26018874 JR |
425 | static void iommu_ignore_device(struct device *dev) |
426 | { | |
427 | u16 devid, alias; | |
428 | ||
429 | devid = get_device_id(dev); | |
430 | alias = amd_iommu_alias_table[devid]; | |
431 | ||
432 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
433 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
434 | ||
435 | amd_iommu_rlookup_table[devid] = NULL; | |
436 | amd_iommu_rlookup_table[alias] = NULL; | |
437 | } | |
438 | ||
657cbb6b JR |
439 | static void iommu_uninit_device(struct device *dev) |
440 | { | |
c1931090 AW |
441 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
442 | ||
443 | if (!dev_data) | |
444 | return; | |
445 | ||
066f2e98 AW |
446 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
447 | dev); | |
448 | ||
9dcd6130 AW |
449 | iommu_group_remove_device(dev); |
450 | ||
c1931090 AW |
451 | /* Unlink from alias, it may change if another device is re-plugged */ |
452 | dev_data->alias_data = NULL; | |
453 | ||
aafd8ba0 JR |
454 | /* Remove dma-ops */ |
455 | dev->archdata.dma_ops = NULL; | |
456 | ||
8fa5f802 | 457 | /* |
c1931090 AW |
458 | * We keep dev_data around for unplugged devices and reuse it when the |
459 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 460 | */ |
657cbb6b | 461 | } |
b7cc9554 | 462 | |
7f26508b JR |
463 | #ifdef CONFIG_AMD_IOMMU_STATS |
464 | ||
465 | /* | |
466 | * Initialization code for statistics collection | |
467 | */ | |
468 | ||
da49f6df | 469 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 470 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 471 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 472 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 473 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 474 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 475 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 476 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 477 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 478 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 479 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 480 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
481 | DECLARE_STATS_COUNTER(complete_ppr); |
482 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
483 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
484 | DECLARE_STATS_COUNTER(pri_requests); | |
485 | ||
7f26508b | 486 | static struct dentry *stats_dir; |
7f26508b JR |
487 | static struct dentry *de_fflush; |
488 | ||
489 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
490 | { | |
491 | if (stats_dir == NULL) | |
492 | return; | |
493 | ||
494 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
495 | &cnt->value); | |
496 | } | |
497 | ||
498 | static void amd_iommu_stats_init(void) | |
499 | { | |
500 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
501 | if (stats_dir == NULL) | |
502 | return; | |
503 | ||
7f26508b | 504 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 505 | &amd_iommu_unmap_flush); |
da49f6df JR |
506 | |
507 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 508 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 509 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 510 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 511 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 512 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 513 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 514 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 515 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 516 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 517 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 518 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
519 | amd_iommu_stats_add(&complete_ppr); |
520 | amd_iommu_stats_add(&invalidate_iotlb); | |
521 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
522 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
523 | } |
524 | ||
525 | #endif | |
526 | ||
a80dc3e0 JR |
527 | /**************************************************************************** |
528 | * | |
529 | * Interrupt handling functions | |
530 | * | |
531 | ****************************************************************************/ | |
532 | ||
e3e59876 JR |
533 | static void dump_dte_entry(u16 devid) |
534 | { | |
535 | int i; | |
536 | ||
ee6c2868 JR |
537 | for (i = 0; i < 4; ++i) |
538 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
539 | amd_iommu_dev_table[devid].data[i]); |
540 | } | |
541 | ||
945b4ac4 JR |
542 | static void dump_command(unsigned long phys_addr) |
543 | { | |
544 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
545 | int i; | |
546 | ||
547 | for (i = 0; i < 4; ++i) | |
548 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
549 | } | |
550 | ||
a345b23b | 551 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 552 | { |
3d06fca8 JR |
553 | int type, devid, domid, flags; |
554 | volatile u32 *event = __evt; | |
555 | int count = 0; | |
556 | u64 address; | |
557 | ||
558 | retry: | |
559 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
560 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
561 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
562 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
563 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
564 | ||
565 | if (type == 0) { | |
566 | /* Did we hit the erratum? */ | |
567 | if (++count == LOOP_TIMEOUT) { | |
568 | pr_err("AMD-Vi: No event written to event log\n"); | |
569 | return; | |
570 | } | |
571 | udelay(1); | |
572 | goto retry; | |
573 | } | |
90008ee4 | 574 | |
4c6f40d4 | 575 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
576 | |
577 | switch (type) { | |
578 | case EVENT_TYPE_ILL_DEV: | |
579 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
580 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 581 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 582 | address, flags); |
e3e59876 | 583 | dump_dte_entry(devid); |
90008ee4 JR |
584 | break; |
585 | case EVENT_TYPE_IO_FAULT: | |
586 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
587 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 588 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
589 | domid, address, flags); |
590 | break; | |
591 | case EVENT_TYPE_DEV_TAB_ERR: | |
592 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
593 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 594 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
595 | address, flags); |
596 | break; | |
597 | case EVENT_TYPE_PAGE_TAB_ERR: | |
598 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
599 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 600 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
601 | domid, address, flags); |
602 | break; | |
603 | case EVENT_TYPE_ILL_CMD: | |
604 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 605 | dump_command(address); |
90008ee4 JR |
606 | break; |
607 | case EVENT_TYPE_CMD_HARD_ERR: | |
608 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
609 | "flags=0x%04x]\n", address, flags); | |
610 | break; | |
611 | case EVENT_TYPE_IOTLB_INV_TO: | |
612 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
613 | "address=0x%016llx]\n", | |
c5081cd7 | 614 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
615 | address); |
616 | break; | |
617 | case EVENT_TYPE_INV_DEV_REQ: | |
618 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
619 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 620 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
621 | address, flags); |
622 | break; | |
623 | default: | |
624 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
625 | } | |
3d06fca8 JR |
626 | |
627 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
628 | } |
629 | ||
630 | static void iommu_poll_events(struct amd_iommu *iommu) | |
631 | { | |
632 | u32 head, tail; | |
90008ee4 JR |
633 | |
634 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
635 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
636 | ||
637 | while (head != tail) { | |
a345b23b | 638 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
639 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
640 | } | |
641 | ||
642 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
643 | } |
644 | ||
eee53537 | 645 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
646 | { |
647 | struct amd_iommu_fault fault; | |
72e1dcc4 | 648 | |
399be2f5 JR |
649 | INC_STATS_COUNTER(pri_requests); |
650 | ||
72e1dcc4 JR |
651 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
652 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
653 | return; | |
654 | } | |
655 | ||
656 | fault.address = raw[1]; | |
657 | fault.pasid = PPR_PASID(raw[0]); | |
658 | fault.device_id = PPR_DEVID(raw[0]); | |
659 | fault.tag = PPR_TAG(raw[0]); | |
660 | fault.flags = PPR_FLAGS(raw[0]); | |
661 | ||
72e1dcc4 JR |
662 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
663 | } | |
664 | ||
665 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
666 | { | |
72e1dcc4 JR |
667 | u32 head, tail; |
668 | ||
669 | if (iommu->ppr_log == NULL) | |
670 | return; | |
671 | ||
72e1dcc4 JR |
672 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
673 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
674 | ||
675 | while (head != tail) { | |
eee53537 JR |
676 | volatile u64 *raw; |
677 | u64 entry[2]; | |
678 | int i; | |
679 | ||
680 | raw = (u64 *)(iommu->ppr_log + head); | |
681 | ||
682 | /* | |
683 | * Hardware bug: Interrupt may arrive before the entry is | |
684 | * written to memory. If this happens we need to wait for the | |
685 | * entry to arrive. | |
686 | */ | |
687 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
688 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
689 | break; | |
690 | udelay(1); | |
691 | } | |
72e1dcc4 | 692 | |
eee53537 JR |
693 | /* Avoid memcpy function-call overhead */ |
694 | entry[0] = raw[0]; | |
695 | entry[1] = raw[1]; | |
72e1dcc4 | 696 | |
eee53537 JR |
697 | /* |
698 | * To detect the hardware bug we need to clear the entry | |
699 | * back to zero. | |
700 | */ | |
701 | raw[0] = raw[1] = 0UL; | |
702 | ||
703 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
704 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
705 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 706 | |
eee53537 JR |
707 | /* Handle PPR entry */ |
708 | iommu_handle_ppr_entry(iommu, entry); | |
709 | ||
eee53537 JR |
710 | /* Refresh ring-buffer information */ |
711 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
712 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
713 | } | |
72e1dcc4 JR |
714 | } |
715 | ||
72fe00f0 | 716 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 717 | { |
3f398bc7 SS |
718 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
719 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 720 | |
3f398bc7 SS |
721 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
722 | /* Enable EVT and PPR interrupts again */ | |
723 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
724 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 725 | |
3f398bc7 SS |
726 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
727 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
728 | iommu_poll_events(iommu); | |
729 | } | |
90008ee4 | 730 | |
3f398bc7 SS |
731 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
732 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
733 | iommu_poll_ppr_log(iommu); | |
734 | } | |
90008ee4 | 735 | |
3f398bc7 SS |
736 | /* |
737 | * Hardware bug: ERBT1312 | |
738 | * When re-enabling interrupt (by writing 1 | |
739 | * to clear the bit), the hardware might also try to set | |
740 | * the interrupt bit in the event status register. | |
741 | * In this scenario, the bit will be set, and disable | |
742 | * subsequent interrupts. | |
743 | * | |
744 | * Workaround: The IOMMU driver should read back the | |
745 | * status register and check if the interrupt bits are cleared. | |
746 | * If not, driver will need to go through the interrupt handler | |
747 | * again and re-clear the bits | |
748 | */ | |
749 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
750 | } | |
90008ee4 | 751 | return IRQ_HANDLED; |
a80dc3e0 JR |
752 | } |
753 | ||
72fe00f0 JR |
754 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
755 | { | |
756 | return IRQ_WAKE_THREAD; | |
757 | } | |
758 | ||
431b2a20 JR |
759 | /**************************************************************************** |
760 | * | |
761 | * IOMMU command queuing functions | |
762 | * | |
763 | ****************************************************************************/ | |
764 | ||
ac0ea6e9 JR |
765 | static int wait_on_sem(volatile u64 *sem) |
766 | { | |
767 | int i = 0; | |
768 | ||
769 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
770 | udelay(1); | |
771 | i += 1; | |
772 | } | |
773 | ||
774 | if (i == LOOP_TIMEOUT) { | |
775 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
776 | return -EIO; | |
777 | } | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
782 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
783 | struct iommu_cmd *cmd, | |
784 | u32 tail) | |
a19ae1ec | 785 | { |
a19ae1ec JR |
786 | u8 *target; |
787 | ||
8a7c5ef3 | 788 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
789 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
790 | ||
791 | /* Copy command to buffer */ | |
792 | memcpy(target, cmd, sizeof(*cmd)); | |
793 | ||
794 | /* Tell the IOMMU about it */ | |
a19ae1ec | 795 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 796 | } |
a19ae1ec | 797 | |
815b33fd | 798 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 799 | { |
815b33fd JR |
800 | WARN_ON(address & 0x7ULL); |
801 | ||
ded46737 | 802 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
803 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
804 | cmd->data[1] = upper_32_bits(__pa(address)); | |
805 | cmd->data[2] = 1; | |
ded46737 JR |
806 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
807 | } | |
808 | ||
94fe79e2 JR |
809 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
810 | { | |
811 | memset(cmd, 0, sizeof(*cmd)); | |
812 | cmd->data[0] = devid; | |
813 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
814 | } | |
815 | ||
11b6402c JR |
816 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
817 | size_t size, u16 domid, int pde) | |
818 | { | |
819 | u64 pages; | |
ae0cbbb1 | 820 | bool s; |
11b6402c JR |
821 | |
822 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 823 | s = false; |
11b6402c JR |
824 | |
825 | if (pages > 1) { | |
826 | /* | |
827 | * If we have to flush more than one page, flush all | |
828 | * TLB entries for this domain | |
829 | */ | |
830 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 831 | s = true; |
11b6402c JR |
832 | } |
833 | ||
834 | address &= PAGE_MASK; | |
835 | ||
836 | memset(cmd, 0, sizeof(*cmd)); | |
837 | cmd->data[1] |= domid; | |
838 | cmd->data[2] = lower_32_bits(address); | |
839 | cmd->data[3] = upper_32_bits(address); | |
840 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
841 | if (s) /* size bit - we flush more than one 4kb page */ | |
842 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 843 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
844 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
845 | } | |
846 | ||
cb41ed85 JR |
847 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
848 | u64 address, size_t size) | |
849 | { | |
850 | u64 pages; | |
ae0cbbb1 | 851 | bool s; |
cb41ed85 JR |
852 | |
853 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 854 | s = false; |
cb41ed85 JR |
855 | |
856 | if (pages > 1) { | |
857 | /* | |
858 | * If we have to flush more than one page, flush all | |
859 | * TLB entries for this domain | |
860 | */ | |
861 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 862 | s = true; |
cb41ed85 JR |
863 | } |
864 | ||
865 | address &= PAGE_MASK; | |
866 | ||
867 | memset(cmd, 0, sizeof(*cmd)); | |
868 | cmd->data[0] = devid; | |
869 | cmd->data[0] |= (qdep & 0xff) << 24; | |
870 | cmd->data[1] = devid; | |
871 | cmd->data[2] = lower_32_bits(address); | |
872 | cmd->data[3] = upper_32_bits(address); | |
873 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
874 | if (s) | |
875 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
876 | } | |
877 | ||
22e266c7 JR |
878 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
879 | u64 address, bool size) | |
880 | { | |
881 | memset(cmd, 0, sizeof(*cmd)); | |
882 | ||
883 | address &= ~(0xfffULL); | |
884 | ||
a919a018 | 885 | cmd->data[0] = pasid; |
22e266c7 JR |
886 | cmd->data[1] = domid; |
887 | cmd->data[2] = lower_32_bits(address); | |
888 | cmd->data[3] = upper_32_bits(address); | |
889 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
890 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
891 | if (size) | |
892 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
893 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
894 | } | |
895 | ||
896 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
897 | int qdep, u64 address, bool size) | |
898 | { | |
899 | memset(cmd, 0, sizeof(*cmd)); | |
900 | ||
901 | address &= ~(0xfffULL); | |
902 | ||
903 | cmd->data[0] = devid; | |
e8d2d82d | 904 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
905 | cmd->data[0] |= (qdep & 0xff) << 24; |
906 | cmd->data[1] = devid; | |
e8d2d82d | 907 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
908 | cmd->data[2] = lower_32_bits(address); |
909 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
910 | cmd->data[3] = upper_32_bits(address); | |
911 | if (size) | |
912 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
913 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
914 | } | |
915 | ||
c99afa25 JR |
916 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
917 | int status, int tag, bool gn) | |
918 | { | |
919 | memset(cmd, 0, sizeof(*cmd)); | |
920 | ||
921 | cmd->data[0] = devid; | |
922 | if (gn) { | |
a919a018 | 923 | cmd->data[1] = pasid; |
c99afa25 JR |
924 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
925 | } | |
926 | cmd->data[3] = tag & 0x1ff; | |
927 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
928 | ||
929 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
930 | } | |
931 | ||
58fc7f14 JR |
932 | static void build_inv_all(struct iommu_cmd *cmd) |
933 | { | |
934 | memset(cmd, 0, sizeof(*cmd)); | |
935 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
936 | } |
937 | ||
7ef2798d JR |
938 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
939 | { | |
940 | memset(cmd, 0, sizeof(*cmd)); | |
941 | cmd->data[0] = devid; | |
942 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
943 | } | |
944 | ||
431b2a20 | 945 | /* |
431b2a20 | 946 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 947 | * hardware about the new command. |
431b2a20 | 948 | */ |
f1ca1512 JR |
949 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
950 | struct iommu_cmd *cmd, | |
951 | bool sync) | |
a19ae1ec | 952 | { |
ac0ea6e9 | 953 | u32 left, tail, head, next_tail; |
a19ae1ec | 954 | unsigned long flags; |
a19ae1ec | 955 | |
549c90dc | 956 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
957 | |
958 | again: | |
a19ae1ec | 959 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 960 | |
ac0ea6e9 JR |
961 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
962 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
963 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
964 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 965 | |
ac0ea6e9 JR |
966 | if (left <= 2) { |
967 | struct iommu_cmd sync_cmd; | |
968 | volatile u64 sem = 0; | |
969 | int ret; | |
8d201968 | 970 | |
ac0ea6e9 JR |
971 | build_completion_wait(&sync_cmd, (u64)&sem); |
972 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 973 | |
ac0ea6e9 JR |
974 | spin_unlock_irqrestore(&iommu->lock, flags); |
975 | ||
976 | if ((ret = wait_on_sem(&sem)) != 0) | |
977 | return ret; | |
978 | ||
979 | goto again; | |
8d201968 JR |
980 | } |
981 | ||
ac0ea6e9 JR |
982 | copy_cmd_to_buffer(iommu, cmd, tail); |
983 | ||
984 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 985 | iommu->need_sync = sync; |
ac0ea6e9 | 986 | |
a19ae1ec | 987 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 988 | |
815b33fd | 989 | return 0; |
8d201968 JR |
990 | } |
991 | ||
f1ca1512 JR |
992 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
993 | { | |
994 | return iommu_queue_command_sync(iommu, cmd, true); | |
995 | } | |
996 | ||
8d201968 JR |
997 | /* |
998 | * This function queues a completion wait command into the command | |
999 | * buffer of an IOMMU | |
1000 | */ | |
a19ae1ec | 1001 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1002 | { |
1003 | struct iommu_cmd cmd; | |
815b33fd | 1004 | volatile u64 sem = 0; |
ac0ea6e9 | 1005 | int ret; |
8d201968 | 1006 | |
09ee17eb | 1007 | if (!iommu->need_sync) |
815b33fd | 1008 | return 0; |
09ee17eb | 1009 | |
815b33fd | 1010 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1011 | |
f1ca1512 | 1012 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1013 | if (ret) |
815b33fd | 1014 | return ret; |
8d201968 | 1015 | |
ac0ea6e9 | 1016 | return wait_on_sem(&sem); |
8d201968 JR |
1017 | } |
1018 | ||
d8c13085 | 1019 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1020 | { |
d8c13085 | 1021 | struct iommu_cmd cmd; |
a19ae1ec | 1022 | |
d8c13085 | 1023 | build_inv_dte(&cmd, devid); |
7e4f88da | 1024 | |
d8c13085 JR |
1025 | return iommu_queue_command(iommu, &cmd); |
1026 | } | |
09ee17eb | 1027 | |
7d0c5cc5 JR |
1028 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1029 | { | |
1030 | u32 devid; | |
09ee17eb | 1031 | |
7d0c5cc5 JR |
1032 | for (devid = 0; devid <= 0xffff; ++devid) |
1033 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1034 | |
7d0c5cc5 JR |
1035 | iommu_completion_wait(iommu); |
1036 | } | |
84df8175 | 1037 | |
7d0c5cc5 JR |
1038 | /* |
1039 | * This function uses heavy locking and may disable irqs for some time. But | |
1040 | * this is no issue because it is only called during resume. | |
1041 | */ | |
1042 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1043 | { | |
1044 | u32 dom_id; | |
a19ae1ec | 1045 | |
7d0c5cc5 JR |
1046 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1047 | struct iommu_cmd cmd; | |
1048 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1049 | dom_id, 1); | |
1050 | iommu_queue_command(iommu, &cmd); | |
1051 | } | |
8eed9833 | 1052 | |
7d0c5cc5 | 1053 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1054 | } |
1055 | ||
58fc7f14 | 1056 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1057 | { |
58fc7f14 | 1058 | struct iommu_cmd cmd; |
0518a3a4 | 1059 | |
58fc7f14 | 1060 | build_inv_all(&cmd); |
0518a3a4 | 1061 | |
58fc7f14 JR |
1062 | iommu_queue_command(iommu, &cmd); |
1063 | iommu_completion_wait(iommu); | |
1064 | } | |
1065 | ||
7ef2798d JR |
1066 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1067 | { | |
1068 | struct iommu_cmd cmd; | |
1069 | ||
1070 | build_inv_irt(&cmd, devid); | |
1071 | ||
1072 | iommu_queue_command(iommu, &cmd); | |
1073 | } | |
1074 | ||
1075 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1076 | { | |
1077 | u32 devid; | |
1078 | ||
1079 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1080 | iommu_flush_irt(iommu, devid); | |
1081 | ||
1082 | iommu_completion_wait(iommu); | |
1083 | } | |
1084 | ||
7d0c5cc5 JR |
1085 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1086 | { | |
58fc7f14 JR |
1087 | if (iommu_feature(iommu, FEATURE_IA)) { |
1088 | iommu_flush_all(iommu); | |
1089 | } else { | |
1090 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1091 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1092 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1093 | } |
1094 | } | |
1095 | ||
431b2a20 | 1096 | /* |
cb41ed85 | 1097 | * Command send function for flushing on-device TLB |
431b2a20 | 1098 | */ |
6c542047 JR |
1099 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1100 | u64 address, size_t size) | |
3fa43655 JR |
1101 | { |
1102 | struct amd_iommu *iommu; | |
b00d3bcf | 1103 | struct iommu_cmd cmd; |
cb41ed85 | 1104 | int qdep; |
3fa43655 | 1105 | |
ea61cddb JR |
1106 | qdep = dev_data->ats.qdep; |
1107 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1108 | |
ea61cddb | 1109 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1110 | |
1111 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1112 | } |
1113 | ||
431b2a20 | 1114 | /* |
431b2a20 | 1115 | * Command send function for invalidating a device table entry |
431b2a20 | 1116 | */ |
6c542047 | 1117 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1118 | { |
3fa43655 | 1119 | struct amd_iommu *iommu; |
ee2fa743 | 1120 | int ret; |
a19ae1ec | 1121 | |
6c542047 | 1122 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1123 | |
f62dda66 | 1124 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1125 | if (ret) |
1126 | return ret; | |
1127 | ||
ea61cddb | 1128 | if (dev_data->ats.enabled) |
6c542047 | 1129 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1130 | |
ee2fa743 | 1131 | return ret; |
a19ae1ec JR |
1132 | } |
1133 | ||
431b2a20 JR |
1134 | /* |
1135 | * TLB invalidation function which is called from the mapping functions. | |
1136 | * It invalidates a single PTE if the range to flush is within a single | |
1137 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1138 | */ | |
17b124bf JR |
1139 | static void __domain_flush_pages(struct protection_domain *domain, |
1140 | u64 address, size_t size, int pde) | |
a19ae1ec | 1141 | { |
cb41ed85 | 1142 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1143 | struct iommu_cmd cmd; |
1144 | int ret = 0, i; | |
a19ae1ec | 1145 | |
11b6402c | 1146 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1147 | |
6de8ad9b JR |
1148 | for (i = 0; i < amd_iommus_present; ++i) { |
1149 | if (!domain->dev_iommu[i]) | |
1150 | continue; | |
1151 | ||
1152 | /* | |
1153 | * Devices of this domain are behind this IOMMU | |
1154 | * We need a TLB flush | |
1155 | */ | |
11b6402c | 1156 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1157 | } |
1158 | ||
cb41ed85 | 1159 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1160 | |
ea61cddb | 1161 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1162 | continue; |
1163 | ||
6c542047 | 1164 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1165 | } |
1166 | ||
11b6402c | 1167 | WARN_ON(ret); |
6de8ad9b JR |
1168 | } |
1169 | ||
17b124bf JR |
1170 | static void domain_flush_pages(struct protection_domain *domain, |
1171 | u64 address, size_t size) | |
6de8ad9b | 1172 | { |
17b124bf | 1173 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1174 | } |
b6c02715 | 1175 | |
1c655773 | 1176 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1177 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1178 | { |
17b124bf | 1179 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1180 | } |
1181 | ||
42a49f96 | 1182 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1183 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1184 | { |
17b124bf | 1185 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1186 | } |
1187 | ||
17b124bf | 1188 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1189 | { |
17b124bf | 1190 | int i; |
18811f55 | 1191 | |
17b124bf JR |
1192 | for (i = 0; i < amd_iommus_present; ++i) { |
1193 | if (!domain->dev_iommu[i]) | |
1194 | continue; | |
bfd1be18 | 1195 | |
17b124bf JR |
1196 | /* |
1197 | * Devices of this domain are behind this IOMMU | |
1198 | * We need to wait for completion of all commands. | |
1199 | */ | |
1200 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1201 | } |
e394d72a JR |
1202 | } |
1203 | ||
b00d3bcf | 1204 | |
09b42804 | 1205 | /* |
b00d3bcf | 1206 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1207 | */ |
17b124bf | 1208 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1209 | { |
b00d3bcf | 1210 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1211 | |
b00d3bcf | 1212 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1213 | device_flush_dte(dev_data); |
a345b23b JR |
1214 | } |
1215 | ||
431b2a20 JR |
1216 | /**************************************************************************** |
1217 | * | |
1218 | * The functions below are used the create the page table mappings for | |
1219 | * unity mapped regions. | |
1220 | * | |
1221 | ****************************************************************************/ | |
1222 | ||
308973d3 JR |
1223 | /* |
1224 | * This function is used to add another level to an IO page table. Adding | |
1225 | * another level increases the size of the address space by 9 bits to a size up | |
1226 | * to 64 bits. | |
1227 | */ | |
1228 | static bool increase_address_space(struct protection_domain *domain, | |
1229 | gfp_t gfp) | |
1230 | { | |
1231 | u64 *pte; | |
1232 | ||
1233 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1234 | /* address space already 64 bit large */ | |
1235 | return false; | |
1236 | ||
1237 | pte = (void *)get_zeroed_page(gfp); | |
1238 | if (!pte) | |
1239 | return false; | |
1240 | ||
1241 | *pte = PM_LEVEL_PDE(domain->mode, | |
1242 | virt_to_phys(domain->pt_root)); | |
1243 | domain->pt_root = pte; | |
1244 | domain->mode += 1; | |
1245 | domain->updated = true; | |
1246 | ||
1247 | return true; | |
1248 | } | |
1249 | ||
1250 | static u64 *alloc_pte(struct protection_domain *domain, | |
1251 | unsigned long address, | |
cbb9d729 | 1252 | unsigned long page_size, |
308973d3 JR |
1253 | u64 **pte_page, |
1254 | gfp_t gfp) | |
1255 | { | |
cbb9d729 | 1256 | int level, end_lvl; |
308973d3 | 1257 | u64 *pte, *page; |
cbb9d729 JR |
1258 | |
1259 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1260 | |
1261 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1262 | increase_address_space(domain, gfp); | |
1263 | ||
cbb9d729 JR |
1264 | level = domain->mode - 1; |
1265 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1266 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1267 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1268 | |
1269 | while (level > end_lvl) { | |
1270 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1271 | page = (u64 *)get_zeroed_page(gfp); | |
1272 | if (!page) | |
1273 | return NULL; | |
1274 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1275 | } | |
1276 | ||
cbb9d729 JR |
1277 | /* No level skipping support yet */ |
1278 | if (PM_PTE_LEVEL(*pte) != level) | |
1279 | return NULL; | |
1280 | ||
308973d3 JR |
1281 | level -= 1; |
1282 | ||
1283 | pte = IOMMU_PTE_PAGE(*pte); | |
1284 | ||
1285 | if (pte_page && level == end_lvl) | |
1286 | *pte_page = pte; | |
1287 | ||
1288 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1289 | } | |
1290 | ||
1291 | return pte; | |
1292 | } | |
1293 | ||
1294 | /* | |
1295 | * This function checks if there is a PTE for a given dma address. If | |
1296 | * there is one, it returns the pointer to it. | |
1297 | */ | |
3039ca1b JR |
1298 | static u64 *fetch_pte(struct protection_domain *domain, |
1299 | unsigned long address, | |
1300 | unsigned long *page_size) | |
308973d3 JR |
1301 | { |
1302 | int level; | |
1303 | u64 *pte; | |
1304 | ||
24cd7723 JR |
1305 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1306 | return NULL; | |
1307 | ||
3039ca1b JR |
1308 | level = domain->mode - 1; |
1309 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1310 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1311 | |
24cd7723 JR |
1312 | while (level > 0) { |
1313 | ||
1314 | /* Not Present */ | |
308973d3 JR |
1315 | if (!IOMMU_PTE_PRESENT(*pte)) |
1316 | return NULL; | |
1317 | ||
24cd7723 | 1318 | /* Large PTE */ |
3039ca1b JR |
1319 | if (PM_PTE_LEVEL(*pte) == 7 || |
1320 | PM_PTE_LEVEL(*pte) == 0) | |
1321 | break; | |
24cd7723 JR |
1322 | |
1323 | /* No level skipping support yet */ | |
1324 | if (PM_PTE_LEVEL(*pte) != level) | |
1325 | return NULL; | |
1326 | ||
308973d3 JR |
1327 | level -= 1; |
1328 | ||
24cd7723 | 1329 | /* Walk to the next level */ |
3039ca1b JR |
1330 | pte = IOMMU_PTE_PAGE(*pte); |
1331 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1332 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1333 | } | |
1334 | ||
1335 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1336 | unsigned long pte_mask; | |
1337 | ||
1338 | /* | |
1339 | * If we have a series of large PTEs, make | |
1340 | * sure to return a pointer to the first one. | |
1341 | */ | |
1342 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1343 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1344 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1345 | } |
1346 | ||
1347 | return pte; | |
1348 | } | |
1349 | ||
431b2a20 JR |
1350 | /* |
1351 | * Generic mapping functions. It maps a physical address into a DMA | |
1352 | * address space. It allocates the page table pages if necessary. | |
1353 | * In the future it can be extended to a generic mapping function | |
1354 | * supporting all features of AMD IOMMU page tables like level skipping | |
1355 | * and full 64 bit address spaces. | |
1356 | */ | |
38e817fe JR |
1357 | static int iommu_map_page(struct protection_domain *dom, |
1358 | unsigned long bus_addr, | |
1359 | unsigned long phys_addr, | |
abdc5eb3 | 1360 | int prot, |
cbb9d729 | 1361 | unsigned long page_size) |
bd0e5211 | 1362 | { |
8bda3092 | 1363 | u64 __pte, *pte; |
cbb9d729 | 1364 | int i, count; |
abdc5eb3 | 1365 | |
d4b03664 JR |
1366 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1367 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1368 | ||
bad1cac2 | 1369 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1370 | return -EINVAL; |
1371 | ||
d4b03664 JR |
1372 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1373 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1374 | |
63eaa75e ML |
1375 | if (!pte) |
1376 | return -ENOMEM; | |
1377 | ||
cbb9d729 JR |
1378 | for (i = 0; i < count; ++i) |
1379 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1380 | return -EBUSY; | |
bd0e5211 | 1381 | |
d4b03664 | 1382 | if (count > 1) { |
cbb9d729 JR |
1383 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1384 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1385 | } else | |
1386 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1387 | |
bd0e5211 JR |
1388 | if (prot & IOMMU_PROT_IR) |
1389 | __pte |= IOMMU_PTE_IR; | |
1390 | if (prot & IOMMU_PROT_IW) | |
1391 | __pte |= IOMMU_PTE_IW; | |
1392 | ||
cbb9d729 JR |
1393 | for (i = 0; i < count; ++i) |
1394 | pte[i] = __pte; | |
bd0e5211 | 1395 | |
04bfdd84 JR |
1396 | update_domain(dom); |
1397 | ||
bd0e5211 JR |
1398 | return 0; |
1399 | } | |
1400 | ||
24cd7723 JR |
1401 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1402 | unsigned long bus_addr, | |
1403 | unsigned long page_size) | |
eb74ff6c | 1404 | { |
71b390e9 JR |
1405 | unsigned long long unmapped; |
1406 | unsigned long unmap_size; | |
24cd7723 JR |
1407 | u64 *pte; |
1408 | ||
1409 | BUG_ON(!is_power_of_2(page_size)); | |
1410 | ||
1411 | unmapped = 0; | |
eb74ff6c | 1412 | |
24cd7723 JR |
1413 | while (unmapped < page_size) { |
1414 | ||
71b390e9 JR |
1415 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1416 | ||
1417 | if (pte) { | |
1418 | int i, count; | |
1419 | ||
1420 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1421 | for (i = 0; i < count; i++) |
1422 | pte[i] = 0ULL; | |
1423 | } | |
1424 | ||
1425 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1426 | unmapped += unmap_size; | |
1427 | } | |
1428 | ||
60d0ca3c | 1429 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1430 | |
24cd7723 | 1431 | return unmapped; |
eb74ff6c | 1432 | } |
eb74ff6c | 1433 | |
431b2a20 JR |
1434 | /**************************************************************************** |
1435 | * | |
1436 | * The next functions belong to the address allocator for the dma_ops | |
1437 | * interface functions. They work like the allocators in the other IOMMU | |
1438 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1439 | * the aperture. Maybe it could be enhanced in the future to a more | |
1440 | * efficient allocator. | |
1441 | * | |
1442 | ****************************************************************************/ | |
d3086444 | 1443 | |
431b2a20 | 1444 | /* |
384de729 | 1445 | * The address allocator core functions. |
431b2a20 JR |
1446 | * |
1447 | * called with domain->lock held | |
1448 | */ | |
384de729 | 1449 | |
171e7b37 JR |
1450 | /* |
1451 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1452 | * ranges. | |
1453 | */ | |
1454 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1455 | unsigned long start_page, | |
1456 | unsigned int pages) | |
1457 | { | |
1458 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1459 | ||
1460 | if (start_page + pages > last_page) | |
1461 | pages = last_page - start_page; | |
1462 | ||
1463 | for (i = start_page; i < start_page + pages; ++i) { | |
1464 | int index = i / APERTURE_RANGE_PAGES; | |
1465 | int page = i % APERTURE_RANGE_PAGES; | |
1466 | __set_bit(page, dom->aperture[index]->bitmap); | |
1467 | } | |
1468 | } | |
1469 | ||
9cabe89b JR |
1470 | /* |
1471 | * This function is used to add a new aperture range to an existing | |
1472 | * aperture in case of dma_ops domain allocation or address allocation | |
1473 | * failure. | |
1474 | */ | |
576175c2 | 1475 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1476 | bool populate, gfp_t gfp) |
1477 | { | |
1478 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1479 | struct amd_iommu *iommu; |
5d7c94c3 | 1480 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1481 | |
f5e9705c JR |
1482 | #ifdef CONFIG_IOMMU_STRESS |
1483 | populate = false; | |
1484 | #endif | |
1485 | ||
9cabe89b JR |
1486 | if (index >= APERTURE_MAX_RANGES) |
1487 | return -ENOMEM; | |
1488 | ||
1489 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1490 | if (!dma_dom->aperture[index]) | |
1491 | return -ENOMEM; | |
1492 | ||
1493 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1494 | if (!dma_dom->aperture[index]->bitmap) | |
1495 | goto out_free; | |
1496 | ||
1497 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1498 | ||
1499 | if (populate) { | |
1500 | unsigned long address = dma_dom->aperture_size; | |
1501 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1502 | u64 *pte, *pte_page; | |
1503 | ||
1504 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1505 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1506 | &pte_page, gfp); |
1507 | if (!pte) | |
1508 | goto out_free; | |
1509 | ||
1510 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1511 | ||
1512 | address += APERTURE_RANGE_SIZE / 64; | |
1513 | } | |
1514 | } | |
1515 | ||
17f5b569 | 1516 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1517 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1518 | ||
17f5b569 JR |
1519 | /* Reserve address range used for MSI messages */ |
1520 | if (old_size < MSI_ADDR_BASE_LO && | |
1521 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1522 | unsigned long spage; | |
1523 | int pages; | |
1524 | ||
1525 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1526 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1527 | ||
1528 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1529 | } | |
1530 | ||
b595076a | 1531 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1532 | for_each_iommu(iommu) { |
1533 | if (iommu->exclusion_start && | |
1534 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1535 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1536 | unsigned long startpage; | |
1537 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1538 | iommu->exclusion_length, | |
1539 | PAGE_SIZE); | |
1540 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1541 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1542 | } | |
00cd122a JR |
1543 | } |
1544 | ||
1545 | /* | |
1546 | * Check for areas already mapped as present in the new aperture | |
1547 | * range and mark those pages as reserved in the allocator. Such | |
1548 | * mappings may already exist as a result of requested unity | |
1549 | * mappings for devices. | |
1550 | */ | |
1551 | for (i = dma_dom->aperture[index]->offset; | |
1552 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1553 | i += pte_pgsize) { |
3039ca1b | 1554 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1555 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1556 | continue; | |
1557 | ||
5d7c94c3 JR |
1558 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1559 | pte_pgsize >> 12); | |
00cd122a JR |
1560 | } |
1561 | ||
04bfdd84 JR |
1562 | update_domain(&dma_dom->domain); |
1563 | ||
9cabe89b JR |
1564 | return 0; |
1565 | ||
1566 | out_free: | |
04bfdd84 JR |
1567 | update_domain(&dma_dom->domain); |
1568 | ||
9cabe89b JR |
1569 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1570 | ||
1571 | kfree(dma_dom->aperture[index]); | |
1572 | dma_dom->aperture[index] = NULL; | |
1573 | ||
1574 | return -ENOMEM; | |
1575 | } | |
1576 | ||
384de729 JR |
1577 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1578 | struct dma_ops_domain *dom, | |
1579 | unsigned int pages, | |
1580 | unsigned long align_mask, | |
1581 | u64 dma_mask, | |
1582 | unsigned long start) | |
1583 | { | |
803b8cb4 | 1584 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1585 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1586 | int i = start >> APERTURE_RANGE_SHIFT; | |
e6aabee0 | 1587 | unsigned long boundary_size, mask; |
384de729 JR |
1588 | unsigned long address = -1; |
1589 | unsigned long limit; | |
1590 | ||
803b8cb4 JR |
1591 | next_bit >>= PAGE_SHIFT; |
1592 | ||
e6aabee0 JR |
1593 | mask = dma_get_seg_boundary(dev); |
1594 | ||
1595 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
1596 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 JR |
1597 | |
1598 | for (;i < max_index; ++i) { | |
1599 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1600 | ||
1601 | if (dom->aperture[i]->offset >= dma_mask) | |
1602 | break; | |
1603 | ||
1604 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1605 | dma_mask >> PAGE_SHIFT); | |
1606 | ||
1607 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1608 | limit, next_bit, pages, 0, | |
1609 | boundary_size, align_mask); | |
1610 | if (address != -1) { | |
1611 | address = dom->aperture[i]->offset + | |
1612 | (address << PAGE_SHIFT); | |
803b8cb4 | 1613 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1614 | break; |
1615 | } | |
1616 | ||
1617 | next_bit = 0; | |
1618 | } | |
1619 | ||
1620 | return address; | |
1621 | } | |
1622 | ||
d3086444 JR |
1623 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1624 | struct dma_ops_domain *dom, | |
6d4f343f | 1625 | unsigned int pages, |
832a90c3 JR |
1626 | unsigned long align_mask, |
1627 | u64 dma_mask) | |
d3086444 | 1628 | { |
d3086444 | 1629 | unsigned long address; |
d3086444 | 1630 | |
fe16f088 JR |
1631 | #ifdef CONFIG_IOMMU_STRESS |
1632 | dom->next_address = 0; | |
1633 | dom->need_flush = true; | |
1634 | #endif | |
d3086444 | 1635 | |
384de729 | 1636 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1637 | dma_mask, dom->next_address); |
d3086444 | 1638 | |
1c655773 | 1639 | if (address == -1) { |
803b8cb4 | 1640 | dom->next_address = 0; |
384de729 JR |
1641 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1642 | dma_mask, 0); | |
1c655773 JR |
1643 | dom->need_flush = true; |
1644 | } | |
d3086444 | 1645 | |
384de729 | 1646 | if (unlikely(address == -1)) |
8fd524b3 | 1647 | address = DMA_ERROR_CODE; |
d3086444 JR |
1648 | |
1649 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1650 | ||
1651 | return address; | |
1652 | } | |
1653 | ||
431b2a20 JR |
1654 | /* |
1655 | * The address free function. | |
1656 | * | |
1657 | * called with domain->lock held | |
1658 | */ | |
d3086444 JR |
1659 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1660 | unsigned long address, | |
1661 | unsigned int pages) | |
1662 | { | |
384de729 JR |
1663 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1664 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1665 | |
384de729 JR |
1666 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1667 | ||
47bccd6b JR |
1668 | #ifdef CONFIG_IOMMU_STRESS |
1669 | if (i < 4) | |
1670 | return; | |
1671 | #endif | |
80be308d | 1672 | |
803b8cb4 | 1673 | if (address >= dom->next_address) |
80be308d | 1674 | dom->need_flush = true; |
384de729 JR |
1675 | |
1676 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1677 | |
a66022c4 | 1678 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1679 | |
d3086444 JR |
1680 | } |
1681 | ||
431b2a20 JR |
1682 | /**************************************************************************** |
1683 | * | |
1684 | * The next functions belong to the domain allocation. A domain is | |
1685 | * allocated for every IOMMU as the default domain. If device isolation | |
1686 | * is enabled, every device get its own domain. The most important thing | |
1687 | * about domains is the page table mapping the DMA address space they | |
1688 | * contain. | |
1689 | * | |
1690 | ****************************************************************************/ | |
1691 | ||
aeb26f55 JR |
1692 | /* |
1693 | * This function adds a protection domain to the global protection domain list | |
1694 | */ | |
1695 | static void add_domain_to_list(struct protection_domain *domain) | |
1696 | { | |
1697 | unsigned long flags; | |
1698 | ||
1699 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1700 | list_add(&domain->list, &amd_iommu_pd_list); | |
1701 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * This function removes a protection domain to the global | |
1706 | * protection domain list | |
1707 | */ | |
1708 | static void del_domain_from_list(struct protection_domain *domain) | |
1709 | { | |
1710 | unsigned long flags; | |
1711 | ||
1712 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1713 | list_del(&domain->list); | |
1714 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1715 | } | |
1716 | ||
ec487d1a JR |
1717 | static u16 domain_id_alloc(void) |
1718 | { | |
1719 | unsigned long flags; | |
1720 | int id; | |
1721 | ||
1722 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1723 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1724 | BUG_ON(id == 0); | |
1725 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1726 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1727 | else | |
1728 | id = 0; | |
1729 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1730 | ||
1731 | return id; | |
1732 | } | |
1733 | ||
a2acfb75 JR |
1734 | static void domain_id_free(int id) |
1735 | { | |
1736 | unsigned long flags; | |
1737 | ||
1738 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1739 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1740 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1741 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1742 | } | |
a2acfb75 | 1743 | |
5c34c403 JR |
1744 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1745 | static void free_pt_##LVL (unsigned long __pt) \ | |
1746 | { \ | |
1747 | unsigned long p; \ | |
1748 | u64 *pt; \ | |
1749 | int i; \ | |
1750 | \ | |
1751 | pt = (u64 *)__pt; \ | |
1752 | \ | |
1753 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1754 | /* PTE present? */ \ |
5c34c403 JR |
1755 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1756 | continue; \ | |
1757 | \ | |
0b3fff54 JR |
1758 | /* Large PTE? */ \ |
1759 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1760 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1761 | continue; \ | |
1762 | \ | |
5c34c403 JR |
1763 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1764 | FN(p); \ | |
1765 | } \ | |
1766 | free_page((unsigned long)pt); \ | |
1767 | } | |
1768 | ||
1769 | DEFINE_FREE_PT_FN(l2, free_page) | |
1770 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1771 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1772 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1773 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1774 | ||
86db2e5d | 1775 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1776 | { |
5c34c403 | 1777 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1778 | |
5c34c403 JR |
1779 | switch (domain->mode) { |
1780 | case PAGE_MODE_NONE: | |
1781 | break; | |
1782 | case PAGE_MODE_1_LEVEL: | |
1783 | free_page(root); | |
1784 | break; | |
1785 | case PAGE_MODE_2_LEVEL: | |
1786 | free_pt_l2(root); | |
1787 | break; | |
1788 | case PAGE_MODE_3_LEVEL: | |
1789 | free_pt_l3(root); | |
1790 | break; | |
1791 | case PAGE_MODE_4_LEVEL: | |
1792 | free_pt_l4(root); | |
1793 | break; | |
1794 | case PAGE_MODE_5_LEVEL: | |
1795 | free_pt_l5(root); | |
1796 | break; | |
1797 | case PAGE_MODE_6_LEVEL: | |
1798 | free_pt_l6(root); | |
1799 | break; | |
1800 | default: | |
1801 | BUG(); | |
ec487d1a | 1802 | } |
ec487d1a JR |
1803 | } |
1804 | ||
b16137b1 JR |
1805 | static void free_gcr3_tbl_level1(u64 *tbl) |
1806 | { | |
1807 | u64 *ptr; | |
1808 | int i; | |
1809 | ||
1810 | for (i = 0; i < 512; ++i) { | |
1811 | if (!(tbl[i] & GCR3_VALID)) | |
1812 | continue; | |
1813 | ||
1814 | ptr = __va(tbl[i] & PAGE_MASK); | |
1815 | ||
1816 | free_page((unsigned long)ptr); | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1821 | { | |
1822 | u64 *ptr; | |
1823 | int i; | |
1824 | ||
1825 | for (i = 0; i < 512; ++i) { | |
1826 | if (!(tbl[i] & GCR3_VALID)) | |
1827 | continue; | |
1828 | ||
1829 | ptr = __va(tbl[i] & PAGE_MASK); | |
1830 | ||
1831 | free_gcr3_tbl_level1(ptr); | |
1832 | } | |
1833 | } | |
1834 | ||
52815b75 JR |
1835 | static void free_gcr3_table(struct protection_domain *domain) |
1836 | { | |
b16137b1 JR |
1837 | if (domain->glx == 2) |
1838 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1839 | else if (domain->glx == 1) | |
1840 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1841 | else if (domain->glx != 0) | |
1842 | BUG(); | |
1843 | ||
52815b75 JR |
1844 | free_page((unsigned long)domain->gcr3_tbl); |
1845 | } | |
1846 | ||
431b2a20 JR |
1847 | /* |
1848 | * Free a domain, only used if something went wrong in the | |
1849 | * allocation path and we need to free an already allocated page table | |
1850 | */ | |
ec487d1a JR |
1851 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1852 | { | |
384de729 JR |
1853 | int i; |
1854 | ||
ec487d1a JR |
1855 | if (!dom) |
1856 | return; | |
1857 | ||
aeb26f55 JR |
1858 | del_domain_from_list(&dom->domain); |
1859 | ||
86db2e5d | 1860 | free_pagetable(&dom->domain); |
ec487d1a | 1861 | |
384de729 JR |
1862 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1863 | if (!dom->aperture[i]) | |
1864 | continue; | |
1865 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1866 | kfree(dom->aperture[i]); | |
1867 | } | |
ec487d1a JR |
1868 | |
1869 | kfree(dom); | |
1870 | } | |
1871 | ||
431b2a20 JR |
1872 | /* |
1873 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1874 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1875 | * structures required for the dma_ops interface |
1876 | */ | |
87a64d52 | 1877 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1878 | { |
1879 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1880 | |
1881 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1882 | if (!dma_dom) | |
1883 | return NULL; | |
1884 | ||
7a5a566e | 1885 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1886 | goto free_dma_dom; |
7a5a566e | 1887 | |
8f7a017c | 1888 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1889 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1890 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1891 | dma_dom->domain.priv = dma_dom; |
1892 | if (!dma_dom->domain.pt_root) | |
1893 | goto free_dma_dom; | |
ec487d1a | 1894 | |
1c655773 JR |
1895 | dma_dom->need_flush = false; |
1896 | ||
aeb26f55 JR |
1897 | add_domain_to_list(&dma_dom->domain); |
1898 | ||
576175c2 | 1899 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1900 | goto free_dma_dom; |
ec487d1a | 1901 | |
431b2a20 | 1902 | /* |
ec487d1a JR |
1903 | * mark the first page as allocated so we never return 0 as |
1904 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1905 | */ |
384de729 | 1906 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1907 | dma_dom->next_address = 0; |
ec487d1a | 1908 | |
ec487d1a JR |
1909 | |
1910 | return dma_dom; | |
1911 | ||
1912 | free_dma_dom: | |
1913 | dma_ops_domain_free(dma_dom); | |
1914 | ||
1915 | return NULL; | |
1916 | } | |
1917 | ||
5b28df6f JR |
1918 | /* |
1919 | * little helper function to check whether a given protection domain is a | |
1920 | * dma_ops domain | |
1921 | */ | |
1922 | static bool dma_ops_domain(struct protection_domain *domain) | |
1923 | { | |
1924 | return domain->flags & PD_DMA_OPS_MASK; | |
1925 | } | |
1926 | ||
fd7b5535 | 1927 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1928 | { |
132bd68f | 1929 | u64 pte_root = 0; |
ee6c2868 | 1930 | u64 flags = 0; |
863c74eb | 1931 | |
132bd68f JR |
1932 | if (domain->mode != PAGE_MODE_NONE) |
1933 | pte_root = virt_to_phys(domain->pt_root); | |
1934 | ||
38ddf41b JR |
1935 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1936 | << DEV_ENTRY_MODE_SHIFT; | |
1937 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1938 | |
ee6c2868 JR |
1939 | flags = amd_iommu_dev_table[devid].data[1]; |
1940 | ||
fd7b5535 JR |
1941 | if (ats) |
1942 | flags |= DTE_FLAG_IOTLB; | |
1943 | ||
52815b75 JR |
1944 | if (domain->flags & PD_IOMMUV2_MASK) { |
1945 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1946 | u64 glx = domain->glx; | |
1947 | u64 tmp; | |
1948 | ||
1949 | pte_root |= DTE_FLAG_GV; | |
1950 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1951 | ||
1952 | /* First mask out possible old values for GCR3 table */ | |
1953 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1954 | flags &= ~tmp; | |
1955 | ||
1956 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1957 | flags &= ~tmp; | |
1958 | ||
1959 | /* Encode GCR3 table into DTE */ | |
1960 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1961 | pte_root |= tmp; | |
1962 | ||
1963 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1964 | flags |= tmp; | |
1965 | ||
1966 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1967 | flags |= tmp; | |
1968 | } | |
1969 | ||
ee6c2868 JR |
1970 | flags &= ~(0xffffUL); |
1971 | flags |= domain->id; | |
1972 | ||
1973 | amd_iommu_dev_table[devid].data[1] = flags; | |
1974 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1975 | } |
1976 | ||
1977 | static void clear_dte_entry(u16 devid) | |
1978 | { | |
15898bbc JR |
1979 | /* remove entry from the device table seen by the hardware */ |
1980 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1981 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1982 | |
1983 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1984 | } |
1985 | ||
ec9e79ef JR |
1986 | static void do_attach(struct iommu_dev_data *dev_data, |
1987 | struct protection_domain *domain) | |
7f760ddd | 1988 | { |
7f760ddd | 1989 | struct amd_iommu *iommu; |
ec9e79ef | 1990 | bool ats; |
fd7b5535 | 1991 | |
ec9e79ef JR |
1992 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1993 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1994 | |
1995 | /* Update data structures */ | |
1996 | dev_data->domain = domain; | |
1997 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1998 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1999 | |
2000 | /* Do reference counting */ | |
2001 | domain->dev_iommu[iommu->index] += 1; | |
2002 | domain->dev_cnt += 1; | |
2003 | ||
2004 | /* Flush the DTE entry */ | |
6c542047 | 2005 | device_flush_dte(dev_data); |
7f760ddd JR |
2006 | } |
2007 | ||
ec9e79ef | 2008 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2009 | { |
7f760ddd | 2010 | struct amd_iommu *iommu; |
7f760ddd | 2011 | |
ec9e79ef | 2012 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2013 | |
2014 | /* decrease reference counters */ | |
7f760ddd JR |
2015 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2016 | dev_data->domain->dev_cnt -= 1; | |
2017 | ||
2018 | /* Update data structures */ | |
2019 | dev_data->domain = NULL; | |
2020 | list_del(&dev_data->list); | |
f62dda66 | 2021 | clear_dte_entry(dev_data->devid); |
15898bbc | 2022 | |
7f760ddd | 2023 | /* Flush the DTE entry */ |
6c542047 | 2024 | device_flush_dte(dev_data); |
2b681faf JR |
2025 | } |
2026 | ||
2027 | /* | |
2028 | * If a device is not yet associated with a domain, this function does | |
2029 | * assigns it visible for the hardware | |
2030 | */ | |
ec9e79ef | 2031 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2032 | struct protection_domain *domain) |
2b681faf | 2033 | { |
397111ab | 2034 | struct iommu_dev_data *head, *entry; |
84fe6c19 | 2035 | int ret; |
657cbb6b | 2036 | |
2b681faf JR |
2037 | /* lock domain */ |
2038 | spin_lock(&domain->lock); | |
2039 | ||
397111ab | 2040 | head = dev_data; |
15898bbc | 2041 | |
397111ab JR |
2042 | if (head->alias_data != NULL) |
2043 | head = head->alias_data; | |
eba6ac60 | 2044 | |
397111ab | 2045 | /* Now we have the root of the alias group, if any */ |
15898bbc | 2046 | |
397111ab JR |
2047 | ret = -EBUSY; |
2048 | if (head->domain != NULL) | |
2049 | goto out_unlock; | |
15898bbc | 2050 | |
397111ab JR |
2051 | /* Attach alias group root */ |
2052 | do_attach(head, domain); | |
eba6ac60 | 2053 | |
397111ab JR |
2054 | /* Attach other devices in the alias group */ |
2055 | list_for_each_entry(entry, &head->alias_list, alias_list) | |
2056 | do_attach(entry, domain); | |
24100055 | 2057 | |
84fe6c19 JL |
2058 | ret = 0; |
2059 | ||
2060 | out_unlock: | |
2061 | ||
eba6ac60 JR |
2062 | /* ready */ |
2063 | spin_unlock(&domain->lock); | |
15898bbc | 2064 | |
84fe6c19 | 2065 | return ret; |
0feae533 | 2066 | } |
b20ac0d4 | 2067 | |
52815b75 JR |
2068 | |
2069 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2070 | { | |
2071 | pci_disable_ats(pdev); | |
2072 | pci_disable_pri(pdev); | |
2073 | pci_disable_pasid(pdev); | |
2074 | } | |
2075 | ||
6a113ddc JR |
2076 | /* FIXME: Change generic reset-function to do the same */ |
2077 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2078 | { | |
2079 | u16 control; | |
2080 | int pos; | |
2081 | ||
46277b75 | 2082 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2083 | if (!pos) |
2084 | return -EINVAL; | |
2085 | ||
46277b75 JR |
2086 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2087 | control |= PCI_PRI_CTRL_RESET; | |
2088 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2089 | |
2090 | return 0; | |
2091 | } | |
2092 | ||
52815b75 JR |
2093 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2094 | { | |
6a113ddc JR |
2095 | bool reset_enable; |
2096 | int reqs, ret; | |
2097 | ||
2098 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2099 | reqs = 32; | |
2100 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2101 | reqs = 1; | |
2102 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2103 | |
2104 | /* Only allow access to user-accessible pages */ | |
2105 | ret = pci_enable_pasid(pdev, 0); | |
2106 | if (ret) | |
2107 | goto out_err; | |
2108 | ||
2109 | /* First reset the PRI state of the device */ | |
2110 | ret = pci_reset_pri(pdev); | |
2111 | if (ret) | |
2112 | goto out_err; | |
2113 | ||
6a113ddc JR |
2114 | /* Enable PRI */ |
2115 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2116 | if (ret) |
2117 | goto out_err; | |
2118 | ||
6a113ddc JR |
2119 | if (reset_enable) { |
2120 | ret = pri_reset_while_enabled(pdev); | |
2121 | if (ret) | |
2122 | goto out_err; | |
2123 | } | |
2124 | ||
52815b75 JR |
2125 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2126 | if (ret) | |
2127 | goto out_err; | |
2128 | ||
2129 | return 0; | |
2130 | ||
2131 | out_err: | |
2132 | pci_disable_pri(pdev); | |
2133 | pci_disable_pasid(pdev); | |
2134 | ||
2135 | return ret; | |
2136 | } | |
2137 | ||
c99afa25 | 2138 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2139 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2140 | |
98f1ad25 | 2141 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2142 | { |
a3b93121 | 2143 | u16 status; |
c99afa25 JR |
2144 | int pos; |
2145 | ||
46277b75 | 2146 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2147 | if (!pos) |
2148 | return false; | |
2149 | ||
a3b93121 | 2150 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2151 | |
a3b93121 | 2152 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2153 | } |
2154 | ||
407d733e | 2155 | /* |
df805abb | 2156 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2157 | * assigns it visible for the hardware |
2158 | */ | |
15898bbc JR |
2159 | static int attach_device(struct device *dev, |
2160 | struct protection_domain *domain) | |
0feae533 | 2161 | { |
fd7b5535 | 2162 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2163 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2164 | unsigned long flags; |
15898bbc | 2165 | int ret; |
eba6ac60 | 2166 | |
ea61cddb JR |
2167 | dev_data = get_dev_data(dev); |
2168 | ||
52815b75 JR |
2169 | if (domain->flags & PD_IOMMUV2_MASK) { |
2170 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2171 | return -EINVAL; | |
2172 | ||
2173 | if (pdev_iommuv2_enable(pdev) != 0) | |
2174 | return -EINVAL; | |
2175 | ||
2176 | dev_data->ats.enabled = true; | |
2177 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2178 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2179 | } else if (amd_iommu_iotlb_sup && |
2180 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2181 | dev_data->ats.enabled = true; |
2182 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2183 | } | |
fd7b5535 | 2184 | |
eba6ac60 | 2185 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2186 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2187 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2188 | ||
0feae533 JR |
2189 | /* |
2190 | * We might boot into a crash-kernel here. The crashed kernel | |
2191 | * left the caches in the IOMMU dirty. So we have to flush | |
2192 | * here to evict all dirty stuff. | |
2193 | */ | |
17b124bf | 2194 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2195 | |
2196 | return ret; | |
b20ac0d4 JR |
2197 | } |
2198 | ||
355bf553 JR |
2199 | /* |
2200 | * Removes a device from a protection domain (unlocked) | |
2201 | */ | |
ec9e79ef | 2202 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2203 | { |
397111ab | 2204 | struct iommu_dev_data *head, *entry; |
2ca76279 | 2205 | struct protection_domain *domain; |
7c392cbe | 2206 | unsigned long flags; |
c4596114 | 2207 | |
7f760ddd | 2208 | BUG_ON(!dev_data->domain); |
355bf553 | 2209 | |
2ca76279 JR |
2210 | domain = dev_data->domain; |
2211 | ||
2212 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2213 | |
397111ab JR |
2214 | head = dev_data; |
2215 | if (head->alias_data != NULL) | |
2216 | head = head->alias_data; | |
71f77580 | 2217 | |
397111ab JR |
2218 | list_for_each_entry(entry, &head->alias_list, alias_list) |
2219 | do_detach(entry); | |
24100055 | 2220 | |
397111ab | 2221 | do_detach(head); |
7f760ddd | 2222 | |
2ca76279 | 2223 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2224 | |
2225 | /* | |
2226 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2227 | * passthrough domain if it is detached from any other domain. |
2228 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2229 | */ |
5abcdba4 | 2230 | if (dev_data->passthrough && |
d3ad9373 | 2231 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2232 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2233 | } |
2234 | ||
2235 | /* | |
2236 | * Removes a device from a protection domain (with devtable_lock held) | |
2237 | */ | |
15898bbc | 2238 | static void detach_device(struct device *dev) |
355bf553 | 2239 | { |
52815b75 | 2240 | struct protection_domain *domain; |
ea61cddb | 2241 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2242 | unsigned long flags; |
2243 | ||
ec9e79ef | 2244 | dev_data = get_dev_data(dev); |
52815b75 | 2245 | domain = dev_data->domain; |
ec9e79ef | 2246 | |
355bf553 JR |
2247 | /* lock device table */ |
2248 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2249 | __detach_device(dev_data); |
355bf553 | 2250 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2251 | |
52815b75 JR |
2252 | if (domain->flags & PD_IOMMUV2_MASK) |
2253 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2254 | else if (dev_data->ats.enabled) | |
ea61cddb | 2255 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2256 | |
2257 | dev_data->ats.enabled = false; | |
355bf553 | 2258 | } |
e275a2a0 | 2259 | |
aafd8ba0 | 2260 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2261 | { |
5abcdba4 | 2262 | struct iommu_dev_data *dev_data; |
07ee8694 | 2263 | struct iommu_domain *domain; |
e275a2a0 | 2264 | struct amd_iommu *iommu; |
5abcdba4 | 2265 | u16 devid; |
aafd8ba0 | 2266 | int ret; |
e275a2a0 | 2267 | |
aafd8ba0 | 2268 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2269 | return 0; |
e275a2a0 | 2270 | |
aafd8ba0 JR |
2271 | devid = get_device_id(dev); |
2272 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2273 | |
aafd8ba0 | 2274 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2275 | if (ret) { |
2276 | if (ret != -ENOTSUPP) | |
2277 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2278 | dev_name(dev)); | |
657cbb6b | 2279 | |
aafd8ba0 | 2280 | iommu_ignore_device(dev); |
343e9cac | 2281 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2282 | goto out; |
2283 | } | |
2284 | init_iommu_group(dev); | |
2c9195e9 | 2285 | |
07ee8694 | 2286 | dev_data = get_dev_data(dev); |
2c9195e9 | 2287 | |
4d58b8a6 | 2288 | BUG_ON(!dev_data); |
657cbb6b | 2289 | |
4d58b8a6 | 2290 | if (dev_data->iommu_v2) |
07ee8694 | 2291 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2292 | |
07ee8694 JR |
2293 | /* Domains are initialized for this device - have a look what we ended up with */ |
2294 | domain = iommu_get_domain_for_dev(dev); | |
2295 | if (domain->type == IOMMU_DOMAIN_IDENTITY) { | |
2296 | dev_data->passthrough = true; | |
2297 | dev->archdata.dma_ops = &nommu_dma_ops; | |
2298 | } else { | |
2c9195e9 | 2299 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 JR |
2300 | } |
2301 | ||
aafd8ba0 | 2302 | out: |
e275a2a0 JR |
2303 | iommu_completion_wait(iommu); |
2304 | ||
e275a2a0 JR |
2305 | return 0; |
2306 | } | |
2307 | ||
aafd8ba0 | 2308 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2309 | { |
aafd8ba0 JR |
2310 | struct amd_iommu *iommu; |
2311 | u16 devid; | |
2312 | ||
2313 | if (!check_device(dev)) | |
2314 | return; | |
2315 | ||
2316 | devid = get_device_id(dev); | |
2317 | iommu = amd_iommu_rlookup_table[devid]; | |
2318 | ||
2319 | iommu_uninit_device(dev); | |
2320 | iommu_completion_wait(iommu); | |
8638c491 JR |
2321 | } |
2322 | ||
431b2a20 JR |
2323 | /***************************************************************************** |
2324 | * | |
2325 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2326 | * | |
2327 | *****************************************************************************/ | |
2328 | ||
2329 | /* | |
2330 | * In the dma_ops path we only have the struct device. This function | |
2331 | * finds the corresponding IOMMU, the protection domain and the | |
2332 | * requestor id for a given device. | |
2333 | * If the device is not yet associated with a domain this is also done | |
2334 | * in this function. | |
2335 | */ | |
94f6d190 | 2336 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2337 | { |
94f6d190 | 2338 | struct protection_domain *domain; |
063071df | 2339 | struct iommu_domain *io_domain; |
b20ac0d4 | 2340 | |
f99c0f1c | 2341 | if (!check_device(dev)) |
94f6d190 | 2342 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2343 | |
063071df | 2344 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2345 | if (!io_domain) |
2346 | return NULL; | |
b20ac0d4 | 2347 | |
0bb6e243 JR |
2348 | domain = to_pdomain(io_domain); |
2349 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2350 | return ERR_PTR(-EBUSY); |
f91ba190 | 2351 | |
0bb6e243 | 2352 | return domain; |
b20ac0d4 JR |
2353 | } |
2354 | ||
04bfdd84 JR |
2355 | static void update_device_table(struct protection_domain *domain) |
2356 | { | |
492667da | 2357 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2358 | |
ea61cddb JR |
2359 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2360 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2361 | } |
2362 | ||
2363 | static void update_domain(struct protection_domain *domain) | |
2364 | { | |
2365 | if (!domain->updated) | |
2366 | return; | |
2367 | ||
2368 | update_device_table(domain); | |
17b124bf JR |
2369 | |
2370 | domain_flush_devices(domain); | |
2371 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2372 | |
2373 | domain->updated = false; | |
2374 | } | |
2375 | ||
8bda3092 JR |
2376 | /* |
2377 | * This function fetches the PTE for a given address in the aperture | |
2378 | */ | |
2379 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2380 | unsigned long address) | |
2381 | { | |
384de729 | 2382 | struct aperture_range *aperture; |
8bda3092 JR |
2383 | u64 *pte, *pte_page; |
2384 | ||
384de729 JR |
2385 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2386 | if (!aperture) | |
2387 | return NULL; | |
2388 | ||
2389 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2390 | if (!pte) { |
cbb9d729 | 2391 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2392 | GFP_ATOMIC); |
384de729 JR |
2393 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2394 | } else | |
8c8c143c | 2395 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2396 | |
04bfdd84 | 2397 | update_domain(&dom->domain); |
8bda3092 JR |
2398 | |
2399 | return pte; | |
2400 | } | |
2401 | ||
431b2a20 JR |
2402 | /* |
2403 | * This is the generic map function. It maps one 4kb page at paddr to | |
2404 | * the given address in the DMA address space for the domain. | |
2405 | */ | |
680525e0 | 2406 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2407 | unsigned long address, |
2408 | phys_addr_t paddr, | |
2409 | int direction) | |
2410 | { | |
2411 | u64 *pte, __pte; | |
2412 | ||
2413 | WARN_ON(address > dom->aperture_size); | |
2414 | ||
2415 | paddr &= PAGE_MASK; | |
2416 | ||
8bda3092 | 2417 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2418 | if (!pte) |
8fd524b3 | 2419 | return DMA_ERROR_CODE; |
cb76c322 JR |
2420 | |
2421 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2422 | ||
2423 | if (direction == DMA_TO_DEVICE) | |
2424 | __pte |= IOMMU_PTE_IR; | |
2425 | else if (direction == DMA_FROM_DEVICE) | |
2426 | __pte |= IOMMU_PTE_IW; | |
2427 | else if (direction == DMA_BIDIRECTIONAL) | |
2428 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2429 | ||
2430 | WARN_ON(*pte); | |
2431 | ||
2432 | *pte = __pte; | |
2433 | ||
2434 | return (dma_addr_t)address; | |
2435 | } | |
2436 | ||
431b2a20 JR |
2437 | /* |
2438 | * The generic unmapping function for on page in the DMA address space. | |
2439 | */ | |
680525e0 | 2440 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2441 | unsigned long address) |
2442 | { | |
384de729 | 2443 | struct aperture_range *aperture; |
cb76c322 JR |
2444 | u64 *pte; |
2445 | ||
2446 | if (address >= dom->aperture_size) | |
2447 | return; | |
2448 | ||
384de729 JR |
2449 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2450 | if (!aperture) | |
2451 | return; | |
2452 | ||
2453 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2454 | if (!pte) | |
2455 | return; | |
cb76c322 | 2456 | |
8c8c143c | 2457 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2458 | |
2459 | WARN_ON(!*pte); | |
2460 | ||
2461 | *pte = 0ULL; | |
2462 | } | |
2463 | ||
431b2a20 JR |
2464 | /* |
2465 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2466 | * contiguous memory region into DMA address space. It is used by all |
2467 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2468 | * Must be called with the domain lock held. |
2469 | */ | |
cb76c322 | 2470 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2471 | struct dma_ops_domain *dma_dom, |
2472 | phys_addr_t paddr, | |
2473 | size_t size, | |
6d4f343f | 2474 | int dir, |
832a90c3 JR |
2475 | bool align, |
2476 | u64 dma_mask) | |
cb76c322 JR |
2477 | { |
2478 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2479 | dma_addr_t address, start, ret; |
cb76c322 | 2480 | unsigned int pages; |
6d4f343f | 2481 | unsigned long align_mask = 0; |
cb76c322 JR |
2482 | int i; |
2483 | ||
e3c449f5 | 2484 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2485 | paddr &= PAGE_MASK; |
2486 | ||
8ecaf8f1 JR |
2487 | INC_STATS_COUNTER(total_map_requests); |
2488 | ||
c1858976 JR |
2489 | if (pages > 1) |
2490 | INC_STATS_COUNTER(cross_page); | |
2491 | ||
6d4f343f JR |
2492 | if (align) |
2493 | align_mask = (1UL << get_order(size)) - 1; | |
2494 | ||
11b83888 | 2495 | retry: |
832a90c3 JR |
2496 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2497 | dma_mask); | |
8fd524b3 | 2498 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2499 | /* |
2500 | * setting next_address here will let the address | |
2501 | * allocator only scan the new allocated range in the | |
2502 | * first run. This is a small optimization. | |
2503 | */ | |
2504 | dma_dom->next_address = dma_dom->aperture_size; | |
2505 | ||
576175c2 | 2506 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2507 | goto out; |
2508 | ||
2509 | /* | |
af901ca1 | 2510 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2511 | * allocation again |
2512 | */ | |
2513 | goto retry; | |
2514 | } | |
cb76c322 JR |
2515 | |
2516 | start = address; | |
2517 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2518 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2519 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2520 | goto out_unmap; |
2521 | ||
cb76c322 JR |
2522 | paddr += PAGE_SIZE; |
2523 | start += PAGE_SIZE; | |
2524 | } | |
2525 | address += offset; | |
2526 | ||
5774f7c5 JR |
2527 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2528 | ||
afa9fdc2 | 2529 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2530 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2531 | dma_dom->need_flush = false; |
318afd41 | 2532 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2533 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2534 | |
cb76c322 JR |
2535 | out: |
2536 | return address; | |
53812c11 JR |
2537 | |
2538 | out_unmap: | |
2539 | ||
2540 | for (--i; i >= 0; --i) { | |
2541 | start -= PAGE_SIZE; | |
680525e0 | 2542 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2543 | } |
2544 | ||
2545 | dma_ops_free_addresses(dma_dom, address, pages); | |
2546 | ||
8fd524b3 | 2547 | return DMA_ERROR_CODE; |
cb76c322 JR |
2548 | } |
2549 | ||
431b2a20 JR |
2550 | /* |
2551 | * Does the reverse of the __map_single function. Must be called with | |
2552 | * the domain lock held too | |
2553 | */ | |
cd8c82e8 | 2554 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2555 | dma_addr_t dma_addr, |
2556 | size_t size, | |
2557 | int dir) | |
2558 | { | |
04e0463e | 2559 | dma_addr_t flush_addr; |
cb76c322 JR |
2560 | dma_addr_t i, start; |
2561 | unsigned int pages; | |
2562 | ||
8fd524b3 | 2563 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2564 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2565 | return; |
2566 | ||
04e0463e | 2567 | flush_addr = dma_addr; |
e3c449f5 | 2568 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2569 | dma_addr &= PAGE_MASK; |
2570 | start = dma_addr; | |
2571 | ||
2572 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2573 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2574 | start += PAGE_SIZE; |
2575 | } | |
2576 | ||
5774f7c5 JR |
2577 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2578 | ||
cb76c322 | 2579 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2580 | |
80be308d | 2581 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2582 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2583 | dma_dom->need_flush = false; |
2584 | } | |
cb76c322 JR |
2585 | } |
2586 | ||
431b2a20 JR |
2587 | /* |
2588 | * The exported map_single function for dma_ops. | |
2589 | */ | |
51491367 FT |
2590 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2591 | unsigned long offset, size_t size, | |
2592 | enum dma_data_direction dir, | |
2593 | struct dma_attrs *attrs) | |
4da70b9e JR |
2594 | { |
2595 | unsigned long flags; | |
4da70b9e | 2596 | struct protection_domain *domain; |
4da70b9e | 2597 | dma_addr_t addr; |
832a90c3 | 2598 | u64 dma_mask; |
51491367 | 2599 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2600 | |
0f2a86f2 JR |
2601 | INC_STATS_COUNTER(cnt_map_single); |
2602 | ||
94f6d190 JR |
2603 | domain = get_domain(dev); |
2604 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2605 | return (dma_addr_t)paddr; |
94f6d190 JR |
2606 | else if (IS_ERR(domain)) |
2607 | return DMA_ERROR_CODE; | |
4da70b9e | 2608 | |
f99c0f1c JR |
2609 | dma_mask = *dev->dma_mask; |
2610 | ||
4da70b9e | 2611 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2612 | |
cd8c82e8 | 2613 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2614 | dma_mask); |
8fd524b3 | 2615 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2616 | goto out; |
2617 | ||
17b124bf | 2618 | domain_flush_complete(domain); |
4da70b9e JR |
2619 | |
2620 | out: | |
2621 | spin_unlock_irqrestore(&domain->lock, flags); | |
2622 | ||
2623 | return addr; | |
2624 | } | |
2625 | ||
431b2a20 JR |
2626 | /* |
2627 | * The exported unmap_single function for dma_ops. | |
2628 | */ | |
51491367 FT |
2629 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2630 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2631 | { |
2632 | unsigned long flags; | |
4da70b9e | 2633 | struct protection_domain *domain; |
4da70b9e | 2634 | |
146a6917 JR |
2635 | INC_STATS_COUNTER(cnt_unmap_single); |
2636 | ||
94f6d190 JR |
2637 | domain = get_domain(dev); |
2638 | if (IS_ERR(domain)) | |
5b28df6f JR |
2639 | return; |
2640 | ||
4da70b9e JR |
2641 | spin_lock_irqsave(&domain->lock, flags); |
2642 | ||
cd8c82e8 | 2643 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2644 | |
17b124bf | 2645 | domain_flush_complete(domain); |
4da70b9e JR |
2646 | |
2647 | spin_unlock_irqrestore(&domain->lock, flags); | |
2648 | } | |
2649 | ||
431b2a20 JR |
2650 | /* |
2651 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2652 | * lists). | |
2653 | */ | |
65b050ad | 2654 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2655 | int nelems, enum dma_data_direction dir, |
2656 | struct dma_attrs *attrs) | |
65b050ad JR |
2657 | { |
2658 | unsigned long flags; | |
65b050ad | 2659 | struct protection_domain *domain; |
65b050ad JR |
2660 | int i; |
2661 | struct scatterlist *s; | |
2662 | phys_addr_t paddr; | |
2663 | int mapped_elems = 0; | |
832a90c3 | 2664 | u64 dma_mask; |
65b050ad | 2665 | |
d03f067a JR |
2666 | INC_STATS_COUNTER(cnt_map_sg); |
2667 | ||
94f6d190 | 2668 | domain = get_domain(dev); |
a0e191b2 | 2669 | if (IS_ERR(domain)) |
94f6d190 | 2670 | return 0; |
dbcc112e | 2671 | |
832a90c3 | 2672 | dma_mask = *dev->dma_mask; |
65b050ad | 2673 | |
65b050ad JR |
2674 | spin_lock_irqsave(&domain->lock, flags); |
2675 | ||
2676 | for_each_sg(sglist, s, nelems, i) { | |
2677 | paddr = sg_phys(s); | |
2678 | ||
cd8c82e8 | 2679 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2680 | paddr, s->length, dir, false, |
2681 | dma_mask); | |
65b050ad JR |
2682 | |
2683 | if (s->dma_address) { | |
2684 | s->dma_length = s->length; | |
2685 | mapped_elems++; | |
2686 | } else | |
2687 | goto unmap; | |
65b050ad JR |
2688 | } |
2689 | ||
17b124bf | 2690 | domain_flush_complete(domain); |
65b050ad JR |
2691 | |
2692 | out: | |
2693 | spin_unlock_irqrestore(&domain->lock, flags); | |
2694 | ||
2695 | return mapped_elems; | |
2696 | unmap: | |
2697 | for_each_sg(sglist, s, mapped_elems, i) { | |
2698 | if (s->dma_address) | |
cd8c82e8 | 2699 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2700 | s->dma_length, dir); |
2701 | s->dma_address = s->dma_length = 0; | |
2702 | } | |
2703 | ||
2704 | mapped_elems = 0; | |
2705 | ||
2706 | goto out; | |
2707 | } | |
2708 | ||
431b2a20 JR |
2709 | /* |
2710 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2711 | * lists). | |
2712 | */ | |
65b050ad | 2713 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2714 | int nelems, enum dma_data_direction dir, |
2715 | struct dma_attrs *attrs) | |
65b050ad JR |
2716 | { |
2717 | unsigned long flags; | |
65b050ad JR |
2718 | struct protection_domain *domain; |
2719 | struct scatterlist *s; | |
65b050ad JR |
2720 | int i; |
2721 | ||
55877a6b JR |
2722 | INC_STATS_COUNTER(cnt_unmap_sg); |
2723 | ||
94f6d190 JR |
2724 | domain = get_domain(dev); |
2725 | if (IS_ERR(domain)) | |
5b28df6f JR |
2726 | return; |
2727 | ||
65b050ad JR |
2728 | spin_lock_irqsave(&domain->lock, flags); |
2729 | ||
2730 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2731 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2732 | s->dma_length, dir); |
65b050ad JR |
2733 | s->dma_address = s->dma_length = 0; |
2734 | } | |
2735 | ||
17b124bf | 2736 | domain_flush_complete(domain); |
65b050ad JR |
2737 | |
2738 | spin_unlock_irqrestore(&domain->lock, flags); | |
2739 | } | |
2740 | ||
431b2a20 JR |
2741 | /* |
2742 | * The exported alloc_coherent function for dma_ops. | |
2743 | */ | |
5d8b53cf | 2744 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2745 | dma_addr_t *dma_addr, gfp_t flag, |
2746 | struct dma_attrs *attrs) | |
5d8b53cf | 2747 | { |
832a90c3 | 2748 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2749 | struct protection_domain *domain; |
2750 | unsigned long flags; | |
2751 | struct page *page; | |
5d8b53cf | 2752 | |
c8f0fb36 JR |
2753 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2754 | ||
94f6d190 JR |
2755 | domain = get_domain(dev); |
2756 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2757 | page = alloc_pages(flag, get_order(size)); |
2758 | *dma_addr = page_to_phys(page); | |
2759 | return page_address(page); | |
94f6d190 JR |
2760 | } else if (IS_ERR(domain)) |
2761 | return NULL; | |
5d8b53cf | 2762 | |
3b839a57 | 2763 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2764 | dma_mask = dev->coherent_dma_mask; |
2765 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2766 | flag |= __GFP_ZERO; |
5d8b53cf | 2767 | |
3b839a57 JR |
2768 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2769 | if (!page) { | |
2770 | if (!(flag & __GFP_WAIT)) | |
2771 | return NULL; | |
5d8b53cf | 2772 | |
3b839a57 JR |
2773 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2774 | get_order(size)); | |
2775 | if (!page) | |
2776 | return NULL; | |
2777 | } | |
5d8b53cf | 2778 | |
832a90c3 JR |
2779 | if (!dma_mask) |
2780 | dma_mask = *dev->dma_mask; | |
2781 | ||
5d8b53cf JR |
2782 | spin_lock_irqsave(&domain->lock, flags); |
2783 | ||
3b839a57 | 2784 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2785 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2786 | |
8fd524b3 | 2787 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2788 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2789 | goto out_free; |
367d04c4 | 2790 | } |
5d8b53cf | 2791 | |
17b124bf | 2792 | domain_flush_complete(domain); |
5d8b53cf | 2793 | |
5d8b53cf JR |
2794 | spin_unlock_irqrestore(&domain->lock, flags); |
2795 | ||
3b839a57 | 2796 | return page_address(page); |
5b28df6f JR |
2797 | |
2798 | out_free: | |
2799 | ||
3b839a57 JR |
2800 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2801 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2802 | |
2803 | return NULL; | |
5d8b53cf JR |
2804 | } |
2805 | ||
431b2a20 JR |
2806 | /* |
2807 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2808 | */ |
5d8b53cf | 2809 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2810 | void *virt_addr, dma_addr_t dma_addr, |
2811 | struct dma_attrs *attrs) | |
5d8b53cf | 2812 | { |
5d8b53cf | 2813 | struct protection_domain *domain; |
3b839a57 JR |
2814 | unsigned long flags; |
2815 | struct page *page; | |
5d8b53cf | 2816 | |
5d31ee7e JR |
2817 | INC_STATS_COUNTER(cnt_free_coherent); |
2818 | ||
3b839a57 JR |
2819 | page = virt_to_page(virt_addr); |
2820 | size = PAGE_ALIGN(size); | |
2821 | ||
94f6d190 JR |
2822 | domain = get_domain(dev); |
2823 | if (IS_ERR(domain)) | |
5b28df6f JR |
2824 | goto free_mem; |
2825 | ||
5d8b53cf JR |
2826 | spin_lock_irqsave(&domain->lock, flags); |
2827 | ||
cd8c82e8 | 2828 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2829 | |
17b124bf | 2830 | domain_flush_complete(domain); |
5d8b53cf JR |
2831 | |
2832 | spin_unlock_irqrestore(&domain->lock, flags); | |
2833 | ||
2834 | free_mem: | |
3b839a57 JR |
2835 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2836 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2837 | } |
2838 | ||
b39ba6ad JR |
2839 | /* |
2840 | * This function is called by the DMA layer to find out if we can handle a | |
2841 | * particular device. It is part of the dma_ops. | |
2842 | */ | |
2843 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2844 | { | |
420aef8a | 2845 | return check_device(dev); |
b39ba6ad JR |
2846 | } |
2847 | ||
160c1d8e | 2848 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2849 | .alloc = alloc_coherent, |
2850 | .free = free_coherent, | |
51491367 FT |
2851 | .map_page = map_page, |
2852 | .unmap_page = unmap_page, | |
6631ee9d JR |
2853 | .map_sg = map_sg, |
2854 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2855 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2856 | }; |
2857 | ||
3a18404c | 2858 | int __init amd_iommu_init_api(void) |
27c2127a | 2859 | { |
3a18404c | 2860 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2861 | } |
2862 | ||
6631ee9d JR |
2863 | int __init amd_iommu_init_dma_ops(void) |
2864 | { | |
6631ee9d | 2865 | iommu_detected = 1; |
75f1cdf1 | 2866 | swiotlb = 0; |
6631ee9d | 2867 | |
7f26508b JR |
2868 | amd_iommu_stats_init(); |
2869 | ||
62410eeb JR |
2870 | if (amd_iommu_unmap_flush) |
2871 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2872 | else | |
2873 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2874 | ||
6631ee9d | 2875 | return 0; |
6631ee9d | 2876 | } |
6d98cd80 JR |
2877 | |
2878 | /***************************************************************************** | |
2879 | * | |
2880 | * The following functions belong to the exported interface of AMD IOMMU | |
2881 | * | |
2882 | * This interface allows access to lower level functions of the IOMMU | |
2883 | * like protection domain handling and assignement of devices to domains | |
2884 | * which is not possible with the dma_ops interface. | |
2885 | * | |
2886 | *****************************************************************************/ | |
2887 | ||
6d98cd80 JR |
2888 | static void cleanup_domain(struct protection_domain *domain) |
2889 | { | |
9b29d3c6 | 2890 | struct iommu_dev_data *entry; |
6d98cd80 | 2891 | unsigned long flags; |
6d98cd80 JR |
2892 | |
2893 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2894 | ||
9b29d3c6 JR |
2895 | while (!list_empty(&domain->dev_list)) { |
2896 | entry = list_first_entry(&domain->dev_list, | |
2897 | struct iommu_dev_data, list); | |
2898 | __detach_device(entry); | |
492667da | 2899 | } |
6d98cd80 JR |
2900 | |
2901 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2902 | } | |
2903 | ||
2650815f JR |
2904 | static void protection_domain_free(struct protection_domain *domain) |
2905 | { | |
2906 | if (!domain) | |
2907 | return; | |
2908 | ||
aeb26f55 JR |
2909 | del_domain_from_list(domain); |
2910 | ||
2650815f JR |
2911 | if (domain->id) |
2912 | domain_id_free(domain->id); | |
2913 | ||
2914 | kfree(domain); | |
2915 | } | |
2916 | ||
7a5a566e JR |
2917 | static int protection_domain_init(struct protection_domain *domain) |
2918 | { | |
2919 | spin_lock_init(&domain->lock); | |
2920 | mutex_init(&domain->api_lock); | |
2921 | domain->id = domain_id_alloc(); | |
2922 | if (!domain->id) | |
2923 | return -ENOMEM; | |
2924 | INIT_LIST_HEAD(&domain->dev_list); | |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
2650815f | 2929 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2930 | { |
2931 | struct protection_domain *domain; | |
2932 | ||
2933 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2934 | if (!domain) | |
2650815f | 2935 | return NULL; |
c156e347 | 2936 | |
7a5a566e | 2937 | if (protection_domain_init(domain)) |
2650815f JR |
2938 | goto out_err; |
2939 | ||
aeb26f55 JR |
2940 | add_domain_to_list(domain); |
2941 | ||
2650815f JR |
2942 | return domain; |
2943 | ||
2944 | out_err: | |
2945 | kfree(domain); | |
2946 | ||
2947 | return NULL; | |
2948 | } | |
2949 | ||
aafd8ba0 | 2950 | static int alloc_passthrough_domain(void) |
5abcdba4 JR |
2951 | { |
2952 | if (pt_domain != NULL) | |
2953 | return 0; | |
2954 | ||
2955 | /* allocate passthrough domain */ | |
2956 | pt_domain = protection_domain_alloc(); | |
2957 | if (!pt_domain) | |
2958 | return -ENOMEM; | |
2959 | ||
2960 | pt_domain->mode = PAGE_MODE_NONE; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
3f4b87b9 JR |
2964 | |
2965 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
2650815f | 2966 | { |
3f4b87b9 | 2967 | struct protection_domain *pdomain; |
0bb6e243 | 2968 | struct dma_ops_domain *dma_domain; |
2650815f | 2969 | |
0bb6e243 JR |
2970 | switch (type) { |
2971 | case IOMMU_DOMAIN_UNMANAGED: | |
2972 | pdomain = protection_domain_alloc(); | |
2973 | if (!pdomain) | |
2974 | return NULL; | |
c156e347 | 2975 | |
0bb6e243 JR |
2976 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2977 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2978 | if (!pdomain->pt_root) { | |
2979 | protection_domain_free(pdomain); | |
2980 | return NULL; | |
2981 | } | |
c156e347 | 2982 | |
0bb6e243 JR |
2983 | pdomain->domain.geometry.aperture_start = 0; |
2984 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2985 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2986 | |
0bb6e243 JR |
2987 | break; |
2988 | case IOMMU_DOMAIN_DMA: | |
2989 | dma_domain = dma_ops_domain_alloc(); | |
2990 | if (!dma_domain) { | |
2991 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2992 | return NULL; | |
2993 | } | |
2994 | pdomain = &dma_domain->domain; | |
2995 | break; | |
07f643a3 JR |
2996 | case IOMMU_DOMAIN_IDENTITY: |
2997 | pdomain = protection_domain_alloc(); | |
2998 | if (!pdomain) | |
2999 | return NULL; | |
c156e347 | 3000 | |
07f643a3 JR |
3001 | pdomain->mode = PAGE_MODE_NONE; |
3002 | break; | |
0bb6e243 JR |
3003 | default: |
3004 | return NULL; | |
3005 | } | |
c156e347 | 3006 | |
3f4b87b9 | 3007 | return &pdomain->domain; |
c156e347 JR |
3008 | } |
3009 | ||
3f4b87b9 | 3010 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3011 | { |
3f4b87b9 | 3012 | struct protection_domain *domain; |
98383fc3 | 3013 | |
3f4b87b9 | 3014 | if (!dom) |
98383fc3 JR |
3015 | return; |
3016 | ||
3f4b87b9 JR |
3017 | domain = to_pdomain(dom); |
3018 | ||
98383fc3 JR |
3019 | if (domain->dev_cnt > 0) |
3020 | cleanup_domain(domain); | |
3021 | ||
3022 | BUG_ON(domain->dev_cnt != 0); | |
3023 | ||
132bd68f JR |
3024 | if (domain->mode != PAGE_MODE_NONE) |
3025 | free_pagetable(domain); | |
98383fc3 | 3026 | |
52815b75 JR |
3027 | if (domain->flags & PD_IOMMUV2_MASK) |
3028 | free_gcr3_table(domain); | |
3029 | ||
8b408fe4 | 3030 | protection_domain_free(domain); |
98383fc3 JR |
3031 | } |
3032 | ||
684f2888 JR |
3033 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3034 | struct device *dev) | |
3035 | { | |
657cbb6b | 3036 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3037 | struct amd_iommu *iommu; |
684f2888 JR |
3038 | u16 devid; |
3039 | ||
98fc5a69 | 3040 | if (!check_device(dev)) |
684f2888 JR |
3041 | return; |
3042 | ||
98fc5a69 | 3043 | devid = get_device_id(dev); |
684f2888 | 3044 | |
657cbb6b | 3045 | if (dev_data->domain != NULL) |
15898bbc | 3046 | detach_device(dev); |
684f2888 JR |
3047 | |
3048 | iommu = amd_iommu_rlookup_table[devid]; | |
3049 | if (!iommu) | |
3050 | return; | |
3051 | ||
684f2888 JR |
3052 | iommu_completion_wait(iommu); |
3053 | } | |
3054 | ||
01106066 JR |
3055 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3056 | struct device *dev) | |
3057 | { | |
3f4b87b9 | 3058 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3059 | struct iommu_dev_data *dev_data; |
01106066 | 3060 | struct amd_iommu *iommu; |
15898bbc | 3061 | int ret; |
01106066 | 3062 | |
98fc5a69 | 3063 | if (!check_device(dev)) |
01106066 JR |
3064 | return -EINVAL; |
3065 | ||
657cbb6b JR |
3066 | dev_data = dev->archdata.iommu; |
3067 | ||
f62dda66 | 3068 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3069 | if (!iommu) |
3070 | return -EINVAL; | |
3071 | ||
657cbb6b | 3072 | if (dev_data->domain) |
15898bbc | 3073 | detach_device(dev); |
01106066 | 3074 | |
15898bbc | 3075 | ret = attach_device(dev, domain); |
01106066 JR |
3076 | |
3077 | iommu_completion_wait(iommu); | |
3078 | ||
15898bbc | 3079 | return ret; |
01106066 JR |
3080 | } |
3081 | ||
468e2366 | 3082 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3083 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3084 | { |
3f4b87b9 | 3085 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3086 | int prot = 0; |
3087 | int ret; | |
3088 | ||
132bd68f JR |
3089 | if (domain->mode == PAGE_MODE_NONE) |
3090 | return -EINVAL; | |
3091 | ||
c6229ca6 JR |
3092 | if (iommu_prot & IOMMU_READ) |
3093 | prot |= IOMMU_PROT_IR; | |
3094 | if (iommu_prot & IOMMU_WRITE) | |
3095 | prot |= IOMMU_PROT_IW; | |
3096 | ||
5d214fe6 | 3097 | mutex_lock(&domain->api_lock); |
795e74f7 | 3098 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3099 | mutex_unlock(&domain->api_lock); |
3100 | ||
795e74f7 | 3101 | return ret; |
c6229ca6 JR |
3102 | } |
3103 | ||
5009065d OBC |
3104 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3105 | size_t page_size) | |
eb74ff6c | 3106 | { |
3f4b87b9 | 3107 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3108 | size_t unmap_size; |
eb74ff6c | 3109 | |
132bd68f JR |
3110 | if (domain->mode == PAGE_MODE_NONE) |
3111 | return -EINVAL; | |
3112 | ||
5d214fe6 | 3113 | mutex_lock(&domain->api_lock); |
468e2366 | 3114 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3115 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3116 | |
17b124bf | 3117 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3118 | |
5009065d | 3119 | return unmap_size; |
eb74ff6c JR |
3120 | } |
3121 | ||
645c4c8d | 3122 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3123 | dma_addr_t iova) |
645c4c8d | 3124 | { |
3f4b87b9 | 3125 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3126 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3127 | u64 *pte, __pte; |
645c4c8d | 3128 | |
132bd68f JR |
3129 | if (domain->mode == PAGE_MODE_NONE) |
3130 | return iova; | |
3131 | ||
3039ca1b | 3132 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3133 | |
a6d41a40 | 3134 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3135 | return 0; |
3136 | ||
b24b1b63 JR |
3137 | offset_mask = pte_pgsize - 1; |
3138 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3139 | |
b24b1b63 | 3140 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3141 | } |
3142 | ||
ab636481 | 3143 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3144 | { |
80a506b8 JR |
3145 | switch (cap) { |
3146 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3147 | return true; |
bdddadcb | 3148 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3149 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3150 | case IOMMU_CAP_NOEXEC: |
3151 | return false; | |
80a506b8 JR |
3152 | } |
3153 | ||
ab636481 | 3154 | return false; |
dbb9fd86 SY |
3155 | } |
3156 | ||
35cf248f JR |
3157 | static void amd_iommu_get_dm_regions(struct device *dev, |
3158 | struct list_head *head) | |
3159 | { | |
3160 | struct unity_map_entry *entry; | |
3161 | u16 devid; | |
3162 | ||
3163 | devid = get_device_id(dev); | |
3164 | ||
3165 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3166 | struct iommu_dm_region *region; | |
3167 | ||
3168 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3169 | continue; | |
3170 | ||
3171 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3172 | if (!region) { | |
3173 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3174 | dev_name(dev)); | |
3175 | return; | |
3176 | } | |
3177 | ||
3178 | region->start = entry->address_start; | |
3179 | region->length = entry->address_end - entry->address_start; | |
3180 | if (entry->prot & IOMMU_PROT_IR) | |
3181 | region->prot |= IOMMU_READ; | |
3182 | if (entry->prot & IOMMU_PROT_IW) | |
3183 | region->prot |= IOMMU_WRITE; | |
3184 | ||
3185 | list_add_tail(®ion->list, head); | |
3186 | } | |
3187 | } | |
3188 | ||
3189 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3190 | struct list_head *head) | |
3191 | { | |
3192 | struct iommu_dm_region *entry, *next; | |
3193 | ||
3194 | list_for_each_entry_safe(entry, next, head, list) | |
3195 | kfree(entry); | |
3196 | } | |
3197 | ||
b22f6434 | 3198 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3199 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3200 | .domain_alloc = amd_iommu_domain_alloc, |
3201 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3202 | .attach_dev = amd_iommu_attach_device, |
3203 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3204 | .map = amd_iommu_map, |
3205 | .unmap = amd_iommu_unmap, | |
315786eb | 3206 | .map_sg = default_iommu_map_sg, |
26961efe | 3207 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3208 | .add_device = amd_iommu_add_device, |
3209 | .remove_device = amd_iommu_remove_device, | |
35cf248f JR |
3210 | .get_dm_regions = amd_iommu_get_dm_regions, |
3211 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3212 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3213 | }; |
3214 | ||
0feae533 JR |
3215 | /***************************************************************************** |
3216 | * | |
3217 | * The next functions do a basic initialization of IOMMU for pass through | |
3218 | * mode | |
3219 | * | |
3220 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3221 | * DMA-API translation. | |
3222 | * | |
3223 | *****************************************************************************/ | |
3224 | ||
3225 | int __init amd_iommu_init_passthrough(void) | |
3226 | { | |
5abcdba4 | 3227 | struct iommu_dev_data *dev_data; |
0feae533 | 3228 | struct pci_dev *dev = NULL; |
5abcdba4 | 3229 | int ret; |
0feae533 | 3230 | |
5abcdba4 JR |
3231 | ret = alloc_passthrough_domain(); |
3232 | if (ret) | |
3233 | return ret; | |
0feae533 | 3234 | |
6c54aabd | 3235 | for_each_pci_dev(dev) { |
98fc5a69 | 3236 | if (!check_device(&dev->dev)) |
0feae533 JR |
3237 | continue; |
3238 | ||
5abcdba4 JR |
3239 | dev_data = get_dev_data(&dev->dev); |
3240 | dev_data->passthrough = true; | |
3241 | ||
15898bbc | 3242 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3243 | } |
3244 | ||
2655d7a2 JR |
3245 | amd_iommu_stats_init(); |
3246 | ||
0feae533 JR |
3247 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3248 | ||
3249 | return 0; | |
3250 | } | |
72e1dcc4 JR |
3251 | |
3252 | /* IOMMUv2 specific functions */ | |
3253 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3254 | { | |
3255 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3256 | } | |
3257 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3258 | ||
3259 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3260 | { | |
3261 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3262 | } | |
3263 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3264 | |
3265 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3266 | { | |
3f4b87b9 | 3267 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3268 | unsigned long flags; |
3269 | ||
3270 | spin_lock_irqsave(&domain->lock, flags); | |
3271 | ||
3272 | /* Update data structure */ | |
3273 | domain->mode = PAGE_MODE_NONE; | |
3274 | domain->updated = true; | |
3275 | ||
3276 | /* Make changes visible to IOMMUs */ | |
3277 | update_domain(domain); | |
3278 | ||
3279 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3280 | free_pagetable(domain); | |
3281 | ||
3282 | spin_unlock_irqrestore(&domain->lock, flags); | |
3283 | } | |
3284 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3285 | |
3286 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3287 | { | |
3f4b87b9 | 3288 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3289 | unsigned long flags; |
3290 | int levels, ret; | |
3291 | ||
3292 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3293 | return -EINVAL; | |
3294 | ||
3295 | /* Number of GCR3 table levels required */ | |
3296 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3297 | levels += 1; | |
3298 | ||
3299 | if (levels > amd_iommu_max_glx_val) | |
3300 | return -EINVAL; | |
3301 | ||
3302 | spin_lock_irqsave(&domain->lock, flags); | |
3303 | ||
3304 | /* | |
3305 | * Save us all sanity checks whether devices already in the | |
3306 | * domain support IOMMUv2. Just force that the domain has no | |
3307 | * devices attached when it is switched into IOMMUv2 mode. | |
3308 | */ | |
3309 | ret = -EBUSY; | |
3310 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3311 | goto out; | |
3312 | ||
3313 | ret = -ENOMEM; | |
3314 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3315 | if (domain->gcr3_tbl == NULL) | |
3316 | goto out; | |
3317 | ||
3318 | domain->glx = levels; | |
3319 | domain->flags |= PD_IOMMUV2_MASK; | |
3320 | domain->updated = true; | |
3321 | ||
3322 | update_domain(domain); | |
3323 | ||
3324 | ret = 0; | |
3325 | ||
3326 | out: | |
3327 | spin_unlock_irqrestore(&domain->lock, flags); | |
3328 | ||
3329 | return ret; | |
3330 | } | |
3331 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3332 | |
3333 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3334 | u64 address, bool size) | |
3335 | { | |
3336 | struct iommu_dev_data *dev_data; | |
3337 | struct iommu_cmd cmd; | |
3338 | int i, ret; | |
3339 | ||
3340 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3341 | return -EINVAL; | |
3342 | ||
3343 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3344 | ||
3345 | /* | |
3346 | * IOMMU TLB needs to be flushed before Device TLB to | |
3347 | * prevent device TLB refill from IOMMU TLB | |
3348 | */ | |
3349 | for (i = 0; i < amd_iommus_present; ++i) { | |
3350 | if (domain->dev_iommu[i] == 0) | |
3351 | continue; | |
3352 | ||
3353 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3354 | if (ret != 0) | |
3355 | goto out; | |
3356 | } | |
3357 | ||
3358 | /* Wait until IOMMU TLB flushes are complete */ | |
3359 | domain_flush_complete(domain); | |
3360 | ||
3361 | /* Now flush device TLBs */ | |
3362 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3363 | struct amd_iommu *iommu; | |
3364 | int qdep; | |
3365 | ||
3366 | BUG_ON(!dev_data->ats.enabled); | |
3367 | ||
3368 | qdep = dev_data->ats.qdep; | |
3369 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3370 | ||
3371 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3372 | qdep, address, size); | |
3373 | ||
3374 | ret = iommu_queue_command(iommu, &cmd); | |
3375 | if (ret != 0) | |
3376 | goto out; | |
3377 | } | |
3378 | ||
3379 | /* Wait until all device TLBs are flushed */ | |
3380 | domain_flush_complete(domain); | |
3381 | ||
3382 | ret = 0; | |
3383 | ||
3384 | out: | |
3385 | ||
3386 | return ret; | |
3387 | } | |
3388 | ||
3389 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3390 | u64 address) | |
3391 | { | |
399be2f5 JR |
3392 | INC_STATS_COUNTER(invalidate_iotlb); |
3393 | ||
22e266c7 JR |
3394 | return __flush_pasid(domain, pasid, address, false); |
3395 | } | |
3396 | ||
3397 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3398 | u64 address) | |
3399 | { | |
3f4b87b9 | 3400 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3401 | unsigned long flags; |
3402 | int ret; | |
3403 | ||
3404 | spin_lock_irqsave(&domain->lock, flags); | |
3405 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3406 | spin_unlock_irqrestore(&domain->lock, flags); | |
3407 | ||
3408 | return ret; | |
3409 | } | |
3410 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3411 | ||
3412 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3413 | { | |
399be2f5 JR |
3414 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3415 | ||
22e266c7 JR |
3416 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3417 | true); | |
3418 | } | |
3419 | ||
3420 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3421 | { | |
3f4b87b9 | 3422 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3423 | unsigned long flags; |
3424 | int ret; | |
3425 | ||
3426 | spin_lock_irqsave(&domain->lock, flags); | |
3427 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3428 | spin_unlock_irqrestore(&domain->lock, flags); | |
3429 | ||
3430 | return ret; | |
3431 | } | |
3432 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3433 | ||
b16137b1 JR |
3434 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3435 | { | |
3436 | int index; | |
3437 | u64 *pte; | |
3438 | ||
3439 | while (true) { | |
3440 | ||
3441 | index = (pasid >> (9 * level)) & 0x1ff; | |
3442 | pte = &root[index]; | |
3443 | ||
3444 | if (level == 0) | |
3445 | break; | |
3446 | ||
3447 | if (!(*pte & GCR3_VALID)) { | |
3448 | if (!alloc) | |
3449 | return NULL; | |
3450 | ||
3451 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3452 | if (root == NULL) | |
3453 | return NULL; | |
3454 | ||
3455 | *pte = __pa(root) | GCR3_VALID; | |
3456 | } | |
3457 | ||
3458 | root = __va(*pte & PAGE_MASK); | |
3459 | ||
3460 | level -= 1; | |
3461 | } | |
3462 | ||
3463 | return pte; | |
3464 | } | |
3465 | ||
3466 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3467 | unsigned long cr3) | |
3468 | { | |
3469 | u64 *pte; | |
3470 | ||
3471 | if (domain->mode != PAGE_MODE_NONE) | |
3472 | return -EINVAL; | |
3473 | ||
3474 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3475 | if (pte == NULL) | |
3476 | return -ENOMEM; | |
3477 | ||
3478 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3479 | ||
3480 | return __amd_iommu_flush_tlb(domain, pasid); | |
3481 | } | |
3482 | ||
3483 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3484 | { | |
3485 | u64 *pte; | |
3486 | ||
3487 | if (domain->mode != PAGE_MODE_NONE) | |
3488 | return -EINVAL; | |
3489 | ||
3490 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3491 | if (pte == NULL) | |
3492 | return 0; | |
3493 | ||
3494 | *pte = 0; | |
3495 | ||
3496 | return __amd_iommu_flush_tlb(domain, pasid); | |
3497 | } | |
3498 | ||
3499 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3500 | unsigned long cr3) | |
3501 | { | |
3f4b87b9 | 3502 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3503 | unsigned long flags; |
3504 | int ret; | |
3505 | ||
3506 | spin_lock_irqsave(&domain->lock, flags); | |
3507 | ret = __set_gcr3(domain, pasid, cr3); | |
3508 | spin_unlock_irqrestore(&domain->lock, flags); | |
3509 | ||
3510 | return ret; | |
3511 | } | |
3512 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3513 | ||
3514 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3515 | { | |
3f4b87b9 | 3516 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3517 | unsigned long flags; |
3518 | int ret; | |
3519 | ||
3520 | spin_lock_irqsave(&domain->lock, flags); | |
3521 | ret = __clear_gcr3(domain, pasid); | |
3522 | spin_unlock_irqrestore(&domain->lock, flags); | |
3523 | ||
3524 | return ret; | |
3525 | } | |
3526 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3527 | |
3528 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3529 | int status, int tag) | |
3530 | { | |
3531 | struct iommu_dev_data *dev_data; | |
3532 | struct amd_iommu *iommu; | |
3533 | struct iommu_cmd cmd; | |
3534 | ||
399be2f5 JR |
3535 | INC_STATS_COUNTER(complete_ppr); |
3536 | ||
c99afa25 JR |
3537 | dev_data = get_dev_data(&pdev->dev); |
3538 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3539 | ||
3540 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3541 | tag, dev_data->pri_tlp); | |
3542 | ||
3543 | return iommu_queue_command(iommu, &cmd); | |
3544 | } | |
3545 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3546 | |
3547 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3548 | { | |
3f4b87b9 | 3549 | struct protection_domain *pdomain; |
f3572db8 | 3550 | |
3f4b87b9 JR |
3551 | pdomain = get_domain(&pdev->dev); |
3552 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3553 | return NULL; |
3554 | ||
3555 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3556 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3557 | return NULL; |
3558 | ||
3f4b87b9 | 3559 | return &pdomain->domain; |
f3572db8 JR |
3560 | } |
3561 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3562 | |
3563 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3564 | { | |
3565 | struct iommu_dev_data *dev_data; | |
3566 | ||
3567 | if (!amd_iommu_v2_supported()) | |
3568 | return; | |
3569 | ||
3570 | dev_data = get_dev_data(&pdev->dev); | |
3571 | dev_data->errata |= (1 << erratum); | |
3572 | } | |
3573 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3574 | |
3575 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3576 | struct amd_iommu_device_info *info) | |
3577 | { | |
3578 | int max_pasids; | |
3579 | int pos; | |
3580 | ||
3581 | if (pdev == NULL || info == NULL) | |
3582 | return -EINVAL; | |
3583 | ||
3584 | if (!amd_iommu_v2_supported()) | |
3585 | return -EINVAL; | |
3586 | ||
3587 | memset(info, 0, sizeof(*info)); | |
3588 | ||
3589 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3590 | if (pos) | |
3591 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3592 | ||
3593 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3594 | if (pos) | |
3595 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3596 | ||
3597 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3598 | if (pos) { | |
3599 | int features; | |
3600 | ||
3601 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3602 | max_pasids = min(max_pasids, (1 << 20)); | |
3603 | ||
3604 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3605 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3606 | ||
3607 | features = pci_pasid_features(pdev); | |
3608 | if (features & PCI_PASID_CAP_EXEC) | |
3609 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3610 | if (features & PCI_PASID_CAP_PRIV) | |
3611 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3612 | } | |
3613 | ||
3614 | return 0; | |
3615 | } | |
3616 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3617 | |
3618 | #ifdef CONFIG_IRQ_REMAP | |
3619 | ||
3620 | /***************************************************************************** | |
3621 | * | |
3622 | * Interrupt Remapping Implementation | |
3623 | * | |
3624 | *****************************************************************************/ | |
3625 | ||
3626 | union irte { | |
3627 | u32 val; | |
3628 | struct { | |
3629 | u32 valid : 1, | |
3630 | no_fault : 1, | |
3631 | int_type : 3, | |
3632 | rq_eoi : 1, | |
3633 | dm : 1, | |
3634 | rsvd_1 : 1, | |
3635 | destination : 8, | |
3636 | vector : 8, | |
3637 | rsvd_2 : 8; | |
3638 | } fields; | |
3639 | }; | |
3640 | ||
9c724966 JL |
3641 | struct irq_2_irte { |
3642 | u16 devid; /* Device ID for IRTE table */ | |
3643 | u16 index; /* Index into IRTE table*/ | |
3644 | }; | |
3645 | ||
7c71d306 JL |
3646 | struct amd_ir_data { |
3647 | struct irq_2_irte irq_2_irte; | |
3648 | union irte irte_entry; | |
3649 | union { | |
3650 | struct msi_msg msi_entry; | |
3651 | }; | |
3652 | }; | |
3653 | ||
3654 | static struct irq_chip amd_ir_chip; | |
3655 | ||
2b324506 JR |
3656 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3657 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3658 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3659 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3660 | ||
3661 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3662 | { | |
3663 | u64 dte; | |
3664 | ||
3665 | dte = amd_iommu_dev_table[devid].data[2]; | |
3666 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3667 | dte |= virt_to_phys(table->table); | |
3668 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3669 | dte |= DTE_IRQ_TABLE_LEN; | |
3670 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3671 | ||
3672 | amd_iommu_dev_table[devid].data[2] = dte; | |
3673 | } | |
3674 | ||
3675 | #define IRTE_ALLOCATED (~1U) | |
3676 | ||
3677 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3678 | { | |
3679 | struct irq_remap_table *table = NULL; | |
3680 | struct amd_iommu *iommu; | |
3681 | unsigned long flags; | |
3682 | u16 alias; | |
3683 | ||
3684 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3685 | ||
3686 | iommu = amd_iommu_rlookup_table[devid]; | |
3687 | if (!iommu) | |
3688 | goto out_unlock; | |
3689 | ||
3690 | table = irq_lookup_table[devid]; | |
3691 | if (table) | |
3692 | goto out; | |
3693 | ||
3694 | alias = amd_iommu_alias_table[devid]; | |
3695 | table = irq_lookup_table[alias]; | |
3696 | if (table) { | |
3697 | irq_lookup_table[devid] = table; | |
3698 | set_dte_irq_entry(devid, table); | |
3699 | iommu_flush_dte(iommu, devid); | |
3700 | goto out; | |
3701 | } | |
3702 | ||
3703 | /* Nothing there yet, allocate new irq remapping table */ | |
3704 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3705 | if (!table) | |
3706 | goto out; | |
3707 | ||
197887f0 JR |
3708 | /* Initialize table spin-lock */ |
3709 | spin_lock_init(&table->lock); | |
3710 | ||
2b324506 JR |
3711 | if (ioapic) |
3712 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3713 | table->min_index = 32; | |
3714 | ||
3715 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3716 | if (!table->table) { | |
3717 | kfree(table); | |
821f0f68 | 3718 | table = NULL; |
2b324506 JR |
3719 | goto out; |
3720 | } | |
3721 | ||
3722 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3723 | ||
3724 | if (ioapic) { | |
3725 | int i; | |
3726 | ||
3727 | for (i = 0; i < 32; ++i) | |
3728 | table->table[i] = IRTE_ALLOCATED; | |
3729 | } | |
3730 | ||
3731 | irq_lookup_table[devid] = table; | |
3732 | set_dte_irq_entry(devid, table); | |
3733 | iommu_flush_dte(iommu, devid); | |
3734 | if (devid != alias) { | |
3735 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3736 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3737 | iommu_flush_dte(iommu, alias); |
3738 | } | |
3739 | ||
3740 | out: | |
3741 | iommu_completion_wait(iommu); | |
3742 | ||
3743 | out_unlock: | |
3744 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3745 | ||
3746 | return table; | |
3747 | } | |
3748 | ||
3c3d4f90 | 3749 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3750 | { |
3751 | struct irq_remap_table *table; | |
3752 | unsigned long flags; | |
3753 | int index, c; | |
3754 | ||
3755 | table = get_irq_table(devid, false); | |
3756 | if (!table) | |
3757 | return -ENODEV; | |
3758 | ||
3759 | spin_lock_irqsave(&table->lock, flags); | |
3760 | ||
3761 | /* Scan table for free entries */ | |
3762 | for (c = 0, index = table->min_index; | |
3763 | index < MAX_IRQS_PER_TABLE; | |
3764 | ++index) { | |
3765 | if (table->table[index] == 0) | |
3766 | c += 1; | |
3767 | else | |
3768 | c = 0; | |
3769 | ||
3770 | if (c == count) { | |
2b324506 JR |
3771 | for (; c != 0; --c) |
3772 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3773 | ||
3774 | index -= count - 1; | |
2b324506 JR |
3775 | goto out; |
3776 | } | |
3777 | } | |
3778 | ||
3779 | index = -ENOSPC; | |
3780 | ||
3781 | out: | |
3782 | spin_unlock_irqrestore(&table->lock, flags); | |
3783 | ||
3784 | return index; | |
3785 | } | |
3786 | ||
2b324506 JR |
3787 | static int modify_irte(u16 devid, int index, union irte irte) |
3788 | { | |
3789 | struct irq_remap_table *table; | |
3790 | struct amd_iommu *iommu; | |
3791 | unsigned long flags; | |
3792 | ||
3793 | iommu = amd_iommu_rlookup_table[devid]; | |
3794 | if (iommu == NULL) | |
3795 | return -EINVAL; | |
3796 | ||
3797 | table = get_irq_table(devid, false); | |
3798 | if (!table) | |
3799 | return -ENOMEM; | |
3800 | ||
3801 | spin_lock_irqsave(&table->lock, flags); | |
3802 | table->table[index] = irte.val; | |
3803 | spin_unlock_irqrestore(&table->lock, flags); | |
3804 | ||
3805 | iommu_flush_irt(iommu, devid); | |
3806 | iommu_completion_wait(iommu); | |
3807 | ||
3808 | return 0; | |
3809 | } | |
3810 | ||
3811 | static void free_irte(u16 devid, int index) | |
3812 | { | |
3813 | struct irq_remap_table *table; | |
3814 | struct amd_iommu *iommu; | |
3815 | unsigned long flags; | |
3816 | ||
3817 | iommu = amd_iommu_rlookup_table[devid]; | |
3818 | if (iommu == NULL) | |
3819 | return; | |
3820 | ||
3821 | table = get_irq_table(devid, false); | |
3822 | if (!table) | |
3823 | return; | |
3824 | ||
3825 | spin_lock_irqsave(&table->lock, flags); | |
3826 | table->table[index] = 0; | |
3827 | spin_unlock_irqrestore(&table->lock, flags); | |
3828 | ||
3829 | iommu_flush_irt(iommu, devid); | |
3830 | iommu_completion_wait(iommu); | |
3831 | } | |
3832 | ||
7c71d306 | 3833 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3834 | { |
7c71d306 | 3835 | int devid = -1; |
5527de74 | 3836 | |
7c71d306 JL |
3837 | switch (info->type) { |
3838 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3839 | devid = get_ioapic_devid(info->ioapic_id); | |
3840 | break; | |
3841 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3842 | devid = get_hpet_devid(info->hpet_id); | |
3843 | break; | |
3844 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3845 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3846 | devid = get_device_id(&info->msi_dev->dev); | |
3847 | break; | |
3848 | default: | |
3849 | BUG_ON(1); | |
3850 | break; | |
3851 | } | |
5527de74 | 3852 | |
7c71d306 JL |
3853 | return devid; |
3854 | } | |
5527de74 | 3855 | |
7c71d306 JL |
3856 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3857 | { | |
3858 | struct amd_iommu *iommu; | |
3859 | int devid; | |
5527de74 | 3860 | |
7c71d306 JL |
3861 | if (!info) |
3862 | return NULL; | |
5527de74 | 3863 | |
7c71d306 JL |
3864 | devid = get_devid(info); |
3865 | if (devid >= 0) { | |
3866 | iommu = amd_iommu_rlookup_table[devid]; | |
3867 | if (iommu) | |
3868 | return iommu->ir_domain; | |
3869 | } | |
5527de74 | 3870 | |
7c71d306 | 3871 | return NULL; |
5527de74 JR |
3872 | } |
3873 | ||
7c71d306 | 3874 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3875 | { |
7c71d306 JL |
3876 | struct amd_iommu *iommu; |
3877 | int devid; | |
5527de74 | 3878 | |
7c71d306 JL |
3879 | if (!info) |
3880 | return NULL; | |
5527de74 | 3881 | |
7c71d306 JL |
3882 | switch (info->type) { |
3883 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3884 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3885 | devid = get_device_id(&info->msi_dev->dev); | |
3886 | if (devid >= 0) { | |
3887 | iommu = amd_iommu_rlookup_table[devid]; | |
3888 | if (iommu) | |
3889 | return iommu->msi_domain; | |
3890 | } | |
3891 | break; | |
3892 | default: | |
3893 | break; | |
3894 | } | |
5527de74 | 3895 | |
7c71d306 JL |
3896 | return NULL; |
3897 | } | |
5527de74 | 3898 | |
6b474b82 | 3899 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3900 | .prepare = amd_iommu_prepare, |
3901 | .enable = amd_iommu_enable, | |
3902 | .disable = amd_iommu_disable, | |
3903 | .reenable = amd_iommu_reenable, | |
3904 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3905 | .get_ir_irq_domain = get_ir_irq_domain, |
3906 | .get_irq_domain = get_irq_domain, | |
3907 | }; | |
5527de74 | 3908 | |
7c71d306 JL |
3909 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3910 | struct irq_cfg *irq_cfg, | |
3911 | struct irq_alloc_info *info, | |
3912 | int devid, int index, int sub_handle) | |
3913 | { | |
3914 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3915 | struct msi_msg *msg = &data->msi_entry; | |
3916 | union irte *irte = &data->irte_entry; | |
3917 | struct IO_APIC_route_entry *entry; | |
5527de74 | 3918 | |
7c71d306 JL |
3919 | data->irq_2_irte.devid = devid; |
3920 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 3921 | |
7c71d306 JL |
3922 | /* Setup IRTE for IOMMU */ |
3923 | irte->val = 0; | |
3924 | irte->fields.vector = irq_cfg->vector; | |
3925 | irte->fields.int_type = apic->irq_delivery_mode; | |
3926 | irte->fields.destination = irq_cfg->dest_apicid; | |
3927 | irte->fields.dm = apic->irq_dest_mode; | |
3928 | irte->fields.valid = 1; | |
3929 | ||
3930 | switch (info->type) { | |
3931 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3932 | /* Setup IOAPIC entry */ | |
3933 | entry = info->ioapic_entry; | |
3934 | info->ioapic_entry = NULL; | |
3935 | memset(entry, 0, sizeof(*entry)); | |
3936 | entry->vector = index; | |
3937 | entry->mask = 0; | |
3938 | entry->trigger = info->ioapic_trigger; | |
3939 | entry->polarity = info->ioapic_polarity; | |
3940 | /* Mask level triggered irqs. */ | |
3941 | if (info->ioapic_trigger) | |
3942 | entry->mask = 1; | |
3943 | break; | |
5527de74 | 3944 | |
7c71d306 JL |
3945 | case X86_IRQ_ALLOC_TYPE_HPET: |
3946 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3947 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3948 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3949 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3950 | msg->data = irte_info->index; | |
3951 | break; | |
5527de74 | 3952 | |
7c71d306 JL |
3953 | default: |
3954 | BUG_ON(1); | |
3955 | break; | |
3956 | } | |
5527de74 JR |
3957 | } |
3958 | ||
7c71d306 JL |
3959 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3960 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3961 | { |
7c71d306 JL |
3962 | struct irq_alloc_info *info = arg; |
3963 | struct irq_data *irq_data; | |
3964 | struct amd_ir_data *data; | |
5527de74 | 3965 | struct irq_cfg *cfg; |
7c71d306 JL |
3966 | int i, ret, devid; |
3967 | int index = -1; | |
5527de74 | 3968 | |
7c71d306 JL |
3969 | if (!info) |
3970 | return -EINVAL; | |
3971 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
3972 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
3973 | return -EINVAL; |
3974 | ||
7c71d306 JL |
3975 | /* |
3976 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3977 | * to support multiple MSI interrupts. | |
3978 | */ | |
3979 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
3980 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 3981 | |
7c71d306 JL |
3982 | devid = get_devid(info); |
3983 | if (devid < 0) | |
3984 | return -EINVAL; | |
5527de74 | 3985 | |
7c71d306 JL |
3986 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3987 | if (ret < 0) | |
3988 | return ret; | |
0b4d48cb | 3989 | |
7c71d306 JL |
3990 | ret = -ENOMEM; |
3991 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3992 | if (!data) | |
3993 | goto out_free_parent; | |
0b4d48cb | 3994 | |
7c71d306 JL |
3995 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
3996 | if (get_irq_table(devid, true)) | |
3997 | index = info->ioapic_pin; | |
3998 | else | |
3999 | ret = -ENOMEM; | |
4000 | } else { | |
3c3d4f90 | 4001 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4002 | } |
4003 | if (index < 0) { | |
4004 | pr_warn("Failed to allocate IRTE\n"); | |
4005 | kfree(data); | |
4006 | goto out_free_parent; | |
4007 | } | |
0b4d48cb | 4008 | |
7c71d306 JL |
4009 | for (i = 0; i < nr_irqs; i++) { |
4010 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4011 | cfg = irqd_cfg(irq_data); | |
4012 | if (!irq_data || !cfg) { | |
4013 | ret = -EINVAL; | |
4014 | goto out_free_data; | |
4015 | } | |
0b4d48cb | 4016 | |
7c71d306 JL |
4017 | if (i > 0) { |
4018 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4019 | if (!data) | |
4020 | goto out_free_data; | |
4021 | } | |
4022 | irq_data->hwirq = (devid << 16) + i; | |
4023 | irq_data->chip_data = data; | |
4024 | irq_data->chip = &amd_ir_chip; | |
4025 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4026 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4027 | } | |
4028 | return 0; | |
0b4d48cb | 4029 | |
7c71d306 JL |
4030 | out_free_data: |
4031 | for (i--; i >= 0; i--) { | |
4032 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4033 | if (irq_data) | |
4034 | kfree(irq_data->chip_data); | |
4035 | } | |
4036 | for (i = 0; i < nr_irqs; i++) | |
4037 | free_irte(devid, index + i); | |
4038 | out_free_parent: | |
4039 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4040 | return ret; | |
0b4d48cb JR |
4041 | } |
4042 | ||
7c71d306 JL |
4043 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4044 | unsigned int nr_irqs) | |
0b4d48cb | 4045 | { |
7c71d306 JL |
4046 | struct irq_2_irte *irte_info; |
4047 | struct irq_data *irq_data; | |
4048 | struct amd_ir_data *data; | |
4049 | int i; | |
0b4d48cb | 4050 | |
7c71d306 JL |
4051 | for (i = 0; i < nr_irqs; i++) { |
4052 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4053 | if (irq_data && irq_data->chip_data) { | |
4054 | data = irq_data->chip_data; | |
4055 | irte_info = &data->irq_2_irte; | |
4056 | free_irte(irte_info->devid, irte_info->index); | |
4057 | kfree(data); | |
4058 | } | |
4059 | } | |
4060 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4061 | } | |
0b4d48cb | 4062 | |
7c71d306 JL |
4063 | static void irq_remapping_activate(struct irq_domain *domain, |
4064 | struct irq_data *irq_data) | |
4065 | { | |
4066 | struct amd_ir_data *data = irq_data->chip_data; | |
4067 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4068 | |
7c71d306 | 4069 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4070 | } |
4071 | ||
7c71d306 JL |
4072 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4073 | struct irq_data *irq_data) | |
0b4d48cb | 4074 | { |
7c71d306 JL |
4075 | struct amd_ir_data *data = irq_data->chip_data; |
4076 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4077 | union irte entry; | |
0b4d48cb | 4078 | |
7c71d306 JL |
4079 | entry.val = 0; |
4080 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4081 | } | |
0b4d48cb | 4082 | |
7c71d306 JL |
4083 | static struct irq_domain_ops amd_ir_domain_ops = { |
4084 | .alloc = irq_remapping_alloc, | |
4085 | .free = irq_remapping_free, | |
4086 | .activate = irq_remapping_activate, | |
4087 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4088 | }; |
0b4d48cb | 4089 | |
7c71d306 JL |
4090 | static int amd_ir_set_affinity(struct irq_data *data, |
4091 | const struct cpumask *mask, bool force) | |
4092 | { | |
4093 | struct amd_ir_data *ir_data = data->chip_data; | |
4094 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4095 | struct irq_cfg *cfg = irqd_cfg(data); | |
4096 | struct irq_data *parent = data->parent_data; | |
4097 | int ret; | |
0b4d48cb | 4098 | |
7c71d306 JL |
4099 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4100 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4101 | return ret; | |
0b4d48cb | 4102 | |
7c71d306 JL |
4103 | /* |
4104 | * Atomically updates the IRTE with the new destination, vector | |
4105 | * and flushes the interrupt entry cache. | |
4106 | */ | |
4107 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4108 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4109 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4110 | |
7c71d306 JL |
4111 | /* |
4112 | * After this point, all the interrupts will start arriving | |
4113 | * at the new destination. So, time to cleanup the previous | |
4114 | * vector allocation. | |
4115 | */ | |
c6c2002b | 4116 | send_cleanup_vector(cfg); |
7c71d306 JL |
4117 | |
4118 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4119 | } |
4120 | ||
7c71d306 | 4121 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4122 | { |
7c71d306 | 4123 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4124 | |
7c71d306 JL |
4125 | *msg = ir_data->msi_entry; |
4126 | } | |
d976195c | 4127 | |
7c71d306 JL |
4128 | static struct irq_chip amd_ir_chip = { |
4129 | .irq_ack = ir_ack_apic_edge, | |
4130 | .irq_set_affinity = amd_ir_set_affinity, | |
4131 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4132 | }; | |
d976195c | 4133 | |
7c71d306 JL |
4134 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4135 | { | |
4136 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4137 | if (!iommu->ir_domain) | |
4138 | return -ENOMEM; | |
d976195c | 4139 | |
7c71d306 JL |
4140 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4141 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4142 | |
4143 | return 0; | |
4144 | } | |
2b324506 | 4145 | #endif |