projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iommu/amd: Re-enable IOMMU event log interrupt after handling.
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
b6c02715
JR		 3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
cb41ed85 22#include <linux/pci-ats.h>
a66022c4 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
7f26508b 25#include <linux/debugfs.h>
b6c02715 26#include <linux/scatterlist.h>
51491367 27#include <linux/dma-mapping.h>
b6c02715 28#include <linux/iommu-helper.h>
c156e347 29#include <linux/iommu.h>
815b33fd 30#include <linux/delay.h>
403f81d8 31#include <linux/amd-iommu.h>
72e1dcc4
JR		 32#include <linux/notifier.h>
33#include <linux/export.h>
2b324506
JR		 34#include <linux/irq.h>
35#include <linux/msi.h>
36#include <asm/irq_remapping.h>
37#include <asm/io_apic.h>
38#include <asm/apic.h>
39#include <asm/hw_irq.h>
17f5b569 40#include <asm/msidef.h>
b6c02715 41#include <asm/proto.h>
46a7fa27 42#include <asm/iommu.h>
1d9b16d1 43#include <asm/gart.h>
27c2127a 44#include <asm/dma.h>
403f81d8
JR		 45
46#include "amd_iommu_proto.h"
47#include "amd_iommu_types.h"
6b474b82 48#include "irq_remapping.h"
b6c02715
JR		 49
50#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
815b33fd 52#define LOOP_TIMEOUT 100000
136f78a1 53
aa3de9c0
OBC		 54/*
55 * This bitmap is used to advertise the page sizes our hardware support
56 * to the IOMMU core, which will then use this information to split
57 * physically contiguous memory regions it is mapping into page sizes
58 * that we support.
59 *
954e3dd8 60 * 512GB Pages are not supported due to a hardware bug
aa3de9c0 61 */
954e3dd8 62#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
aa3de9c0 63
b6c02715
JR		 64static DEFINE_RWLOCK(amd_iommu_devtable_lock);
65
bd60b735
JR		 66/* A list of preallocated protection domains */
67static LIST_HEAD(iommu_pd_list);
68static DEFINE_SPINLOCK(iommu_pd_list_lock);
69
8fa5f802
JR		 70/* List of all available dev_data structures */
71static LIST_HEAD(dev_data_list);
72static DEFINE_SPINLOCK(dev_data_list_lock);
73
6efed63b
JR		 74LIST_HEAD(ioapic_map);
75LIST_HEAD(hpet_map);
76
0feae533
JR		 77/*
78 * Domain for untranslated devices - only allocated
79 * if iommu=pt passed on kernel cmd line.
80 */
81static struct protection_domain *pt_domain;
82
26961efe 83static struct iommu_ops amd_iommu_ops;
26961efe 84
72e1dcc4 85static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 86int amd_iommu_max_glx_val = -1;
72e1dcc4 87
ac1534a5
JR		 88static struct dma_map_ops amd_iommu_dma_ops;
89
431b2a20
JR		 90/*
91 * general struct to manage commands send to an IOMMU
92 */
d6449536 93struct iommu_cmd {
b6c02715
JR		 94 u32 data[4];
95};
96
05152a04
JR		 97struct kmem_cache *amd_iommu_irq_cache;
98
04bfdd84 99static void update_domain(struct protection_domain *domain);
5abcdba4 100static int __init alloc_passthrough_domain(void);
c1eee67b 101
15898bbc
JR		 102/****************************************************************************
103 *
104 * Helper functions
105 *
106 ****************************************************************************/
107
f62dda66 108static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 109{
110 struct iommu_dev_data *dev_data;
111 unsigned long flags;
112
113 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
114 if (!dev_data)
115 return NULL;
116
f62dda66 117 dev_data->devid = devid;
8fa5f802
JR		 118 atomic_set(&dev_data->bind, 0);
119
120 spin_lock_irqsave(&dev_data_list_lock, flags);
121 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
122 spin_unlock_irqrestore(&dev_data_list_lock, flags);
123
124 return dev_data;
125}
126
127static void free_dev_data(struct iommu_dev_data *dev_data)
128{
129 unsigned long flags;
130
131 spin_lock_irqsave(&dev_data_list_lock, flags);
132 list_del(&dev_data->dev_data_list);
133 spin_unlock_irqrestore(&dev_data_list_lock, flags);
134
78bfa9f3
AW		 135 if (dev_data->group)
136 iommu_group_put(dev_data->group);
137
8fa5f802
JR		 138 kfree(dev_data);
139}
140
3b03bb74
JR		 141static struct iommu_dev_data *search_dev_data(u16 devid)
142{
143 struct iommu_dev_data *dev_data;
144 unsigned long flags;
145
146 spin_lock_irqsave(&dev_data_list_lock, flags);
147 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
148 if (dev_data->devid == devid)
149 goto out_unlock;
150 }
151
152 dev_data = NULL;
153
154out_unlock:
155 spin_unlock_irqrestore(&dev_data_list_lock, flags);
156
157 return dev_data;
158}
159
160static struct iommu_dev_data *find_dev_data(u16 devid)
161{
162 struct iommu_dev_data *dev_data;
163
164 dev_data = search_dev_data(devid);
165
166 if (dev_data == NULL)
167 dev_data = alloc_dev_data(devid);
168
169 return dev_data;
170}
171
15898bbc
JR		 172static inline u16 get_device_id(struct device *dev)
173{
174 struct pci_dev *pdev = to_pci_dev(dev);
175
176 return calc_devid(pdev->bus->number, pdev->devfn);
177}
178
657cbb6b
JR		 179static struct iommu_dev_data *get_dev_data(struct device *dev)
180{
181 return dev->archdata.iommu;
182}
183
5abcdba4
JR		 184static bool pci_iommuv2_capable(struct pci_dev *pdev)
185{
186 static const int caps[] = {
187 PCI_EXT_CAP_ID_ATS,
46277b75
JR		 188 PCI_EXT_CAP_ID_PRI,
189 PCI_EXT_CAP_ID_PASID,
5abcdba4
JR		 190 };
191 int i, pos;
192
193 for (i = 0; i < 3; ++i) {
194 pos = pci_find_ext_capability(pdev, caps[i]);
195 if (pos == 0)
196 return false;
197 }
198
199 return true;
200}
201
6a113ddc
JR		 202static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
203{
204 struct iommu_dev_data *dev_data;
205
206 dev_data = get_dev_data(&pdev->dev);
207
208 return dev_data->errata & (1 << erratum) ? true : false;
209}
210
71c70984
JR		 211/*
212 * In this function the list of preallocated protection domains is traversed to
213 * find the domain for a specific device
214 */
215static struct dma_ops_domain *find_protection_domain(u16 devid)
216{
217 struct dma_ops_domain *entry, *ret = NULL;
218 unsigned long flags;
219 u16 alias = amd_iommu_alias_table[devid];
220
221 if (list_empty(&iommu_pd_list))
222 return NULL;
223
224 spin_lock_irqsave(&iommu_pd_list_lock, flags);
225
226 list_for_each_entry(entry, &iommu_pd_list, list) {
227 if (entry->target_dev == devid ||
228 entry->target_dev == alias) {
229 ret = entry;
230 break;
231 }
232 }
233
234 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
235
236 return ret;
237}
238
98fc5a69
JR		 239/*
240 * This function checks if the driver got a valid device from the caller to
241 * avoid dereferencing invalid pointers.
242 */
243static bool check_device(struct device *dev)
244{
245 u16 devid;
246
247 if (!dev || !dev->dma_mask)
248 return false;
249
250 /* No device or no PCI device */
339d3261 251 if (dev->bus != &pci_bus_type)
98fc5a69
JR		 252 return false;
253
254 devid = get_device_id(dev);
255
256 /* Out of our scope? */
257 if (devid > amd_iommu_last_bdf)
258 return false;
259
260 if (amd_iommu_rlookup_table[devid] == NULL)
261 return false;
262
263 return true;
264}
265
664b6003
AW		 266static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
267{
268 pci_dev_put(*from);
269 *from = to;
270}
271
2bff6a50
AW		 272static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
273{
274 while (!bus->self) {
275 if (!pci_is_root_bus(bus))
276 bus = bus->parent;
277 else
278 return ERR_PTR(-ENODEV);
279 }
280
281 return bus;
282}
283
664b6003
AW		 284#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
285
2851db21 286static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
657cbb6b 287{
2851db21 288 struct pci_dev *dma_pdev = pdev;
9dcd6130 289
31fe9435 290 /* Account for quirked devices */
664b6003
AW		 291 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
292
31fe9435
AW		 293 /*
294 * If it's a multifunction device that does not support our
295 * required ACS flags, add to the same group as function 0.
296 */
664b6003
AW		 297 if (dma_pdev->multifunction &&
298 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
299 swap_pci_ref(&dma_pdev,
300 pci_get_slot(dma_pdev->bus,
301 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
302 0)));
303
31fe9435
AW		 304 /*
305 * Devices on the root bus go through the iommu. If that's not us,
306 * find the next upstream device and test ACS up to the root bus.
307 * Finding the next device may require skipping virtual buses.
308 */
664b6003 309 while (!pci_is_root_bus(dma_pdev->bus)) {
2bff6a50
AW		 310 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
311 if (IS_ERR(bus))
312 break;
31fe9435
AW		 313
314 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
664b6003
AW		 315 break;
316
31fe9435 317 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
664b6003
AW		 318 }
319
2851db21
AW		 320 return dma_pdev;
321}
322
ce7ac4ab
AW		 323static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev)
324{
325 struct iommu_group *group = iommu_group_get(&pdev->dev);
326 int ret;
327
328 if (!group) {
329 group = iommu_group_alloc();
330 if (IS_ERR(group))
331 return PTR_ERR(group);
332
333 WARN_ON(&pdev->dev != dev);
334 }
335
336 ret = iommu_group_add_device(group, dev);
337 iommu_group_put(group);
338 return ret;
339}
340
78bfa9f3
AW		 341static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data,
342 struct device *dev)
343{
344 if (!dev_data->group) {
345 struct iommu_group *group = iommu_group_alloc();
346 if (IS_ERR(group))
347 return PTR_ERR(group);
348
349 dev_data->group = group;
350 }
351
352 return iommu_group_add_device(dev_data->group, dev);
353}
354
2851db21
AW		 355static int init_iommu_group(struct device *dev)
356{
357 struct iommu_dev_data *dev_data;
358 struct iommu_group *group;
78bfa9f3 359 struct pci_dev *dma_pdev;
2851db21
AW		 360 int ret;
361
362 group = iommu_group_get(dev);
363 if (group) {
364 iommu_group_put(group);
365 return 0;
366 }
367
368 dev_data = find_dev_data(get_device_id(dev));
369 if (!dev_data)
370 return -ENOMEM;
371
372 if (dev_data->alias_data) {
373 u16 alias;
78bfa9f3
AW		 374 struct pci_bus *bus;
375
376 if (dev_data->alias_data->group)
377 goto use_group;
2851db21 378
78bfa9f3
AW		 379 /*
380 * If the alias device exists, it's effectively just a first
381 * level quirk for finding the DMA source.
382 */
2851db21
AW		 383 alias = amd_iommu_alias_table[dev_data->devid];
384 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
78bfa9f3
AW		 385 if (dma_pdev) {
386 dma_pdev = get_isolation_root(dma_pdev);
387 goto use_pdev;
388 }
2851db21 389
78bfa9f3
AW		 390 /*
391 * If the alias is virtual, try to find a parent device
392 * and test whether the IOMMU group is actualy rooted above
393 * the alias. Be careful to also test the parent device if
394 * we think the alias is the root of the group.
395 */
396 bus = pci_find_bus(0, alias >> 8);
397 if (!bus)
398 goto use_group;
399
400 bus = find_hosted_bus(bus);
401 if (IS_ERR(bus) || !bus->self)
402 goto use_group;
403
404 dma_pdev = get_isolation_root(pci_dev_get(bus->self));
405 if (dma_pdev != bus->self || (dma_pdev->multifunction &&
406 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)))
407 goto use_pdev;
408
409 pci_dev_put(dma_pdev);
410 goto use_group;
411 }
2851db21 412
78bfa9f3
AW		 413 dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev)));
414use_pdev:
ce7ac4ab 415 ret = use_pdev_iommu_group(dma_pdev, dev);
9dcd6130 416 pci_dev_put(dma_pdev);
eb9c9527 417 return ret;
78bfa9f3
AW		 418use_group:
419 return use_dev_data_iommu_group(dev_data->alias_data, dev);
eb9c9527
AW		 420}
421
422static int iommu_init_device(struct device *dev)
423{
424 struct pci_dev *pdev = to_pci_dev(dev);
425 struct iommu_dev_data *dev_data;
426 u16 alias;
427 int ret;
428
429 if (dev->archdata.iommu)
430 return 0;
431
432 dev_data = find_dev_data(get_device_id(dev));
433 if (!dev_data)
434 return -ENOMEM;
435
436 alias = amd_iommu_alias_table[dev_data->devid];
437 if (alias != dev_data->devid) {
438 struct iommu_dev_data *alias_data;
439
440 alias_data = find_dev_data(alias);
441 if (alias_data == NULL) {
442 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
443 dev_name(dev));
444 free_dev_data(dev_data);
445 return -ENOTSUPP;
446 }
447 dev_data->alias_data = alias_data;
448 }
449
450 ret = init_iommu_group(dev);
9dcd6130
AW		 451 if (ret)
452 return ret;
453
5abcdba4
JR		 454 if (pci_iommuv2_capable(pdev)) {
455 struct amd_iommu *iommu;
456
457 iommu = amd_iommu_rlookup_table[dev_data->devid];
458 dev_data->iommu_v2 = iommu->is_iommu_v2;
459 }
460
657cbb6b
JR		 461 dev->archdata.iommu = dev_data;
462
657cbb6b
JR		 463 return 0;
464}
465
26018874
JR		 466static void iommu_ignore_device(struct device *dev)
467{
468 u16 devid, alias;
469
470 devid = get_device_id(dev);
471 alias = amd_iommu_alias_table[devid];
472
473 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
474 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
475
476 amd_iommu_rlookup_table[devid] = NULL;
477 amd_iommu_rlookup_table[alias] = NULL;
478}
479
657cbb6b
JR		 480static void iommu_uninit_device(struct device *dev)
481{
9dcd6130
AW		 482 iommu_group_remove_device(dev);
483
8fa5f802
JR		 484 /*
485 * Nothing to do here - we keep dev_data around for unplugged devices
486 * and reuse it when the device is re-plugged - not doing so would
487 * introduce a ton of races.
488 */
657cbb6b 489}
b7cc9554
JR		 490
491void __init amd_iommu_uninit_devices(void)
492{
8fa5f802 493 struct iommu_dev_data *dev_data, *n;
b7cc9554
JR		 494 struct pci_dev *pdev = NULL;
495
496 for_each_pci_dev(pdev) {
497
498 if (!check_device(&pdev->dev))
499 continue;
500
501 iommu_uninit_device(&pdev->dev);
502 }
8fa5f802
JR		 503
504 /* Free all of our dev_data structures */
505 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
506 free_dev_data(dev_data);
b7cc9554
JR		 507}
508
509int __init amd_iommu_init_devices(void)
510{
511 struct pci_dev *pdev = NULL;
512 int ret = 0;
513
514 for_each_pci_dev(pdev) {
515
516 if (!check_device(&pdev->dev))
517 continue;
518
519 ret = iommu_init_device(&pdev->dev);
26018874
JR		 520 if (ret == -ENOTSUPP)
521 iommu_ignore_device(&pdev->dev);
522 else if (ret)
b7cc9554
JR		 523 goto out_free;
524 }
525
526 return 0;
527
528out_free:
529
530 amd_iommu_uninit_devices();
531
532 return ret;
533}
7f26508b
JR		 534#ifdef CONFIG_AMD_IOMMU_STATS
535
536/*
537 * Initialization code for statistics collection
538 */
539
da49f6df 540DECLARE_STATS_COUNTER(compl_wait);
0f2a86f2 541DECLARE_STATS_COUNTER(cnt_map_single);
146a6917 542DECLARE_STATS_COUNTER(cnt_unmap_single);
d03f067a 543DECLARE_STATS_COUNTER(cnt_map_sg);
55877a6b 544DECLARE_STATS_COUNTER(cnt_unmap_sg);
c8f0fb36 545DECLARE_STATS_COUNTER(cnt_alloc_coherent);
5d31ee7e 546DECLARE_STATS_COUNTER(cnt_free_coherent);
c1858976 547DECLARE_STATS_COUNTER(cross_page);
f57d98ae 548DECLARE_STATS_COUNTER(domain_flush_single);
18811f55 549DECLARE_STATS_COUNTER(domain_flush_all);
5774f7c5 550DECLARE_STATS_COUNTER(alloced_io_mem);
8ecaf8f1 551DECLARE_STATS_COUNTER(total_map_requests);
399be2f5
JR		 552DECLARE_STATS_COUNTER(complete_ppr);
553DECLARE_STATS_COUNTER(invalidate_iotlb);
554DECLARE_STATS_COUNTER(invalidate_iotlb_all);
555DECLARE_STATS_COUNTER(pri_requests);
556
7f26508b 557static struct dentry *stats_dir;
7f26508b
JR		 558static struct dentry *de_fflush;
559
560static void amd_iommu_stats_add(struct __iommu_counter *cnt)
561{
562 if (stats_dir == NULL)
563 return;
564
565 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
566 &cnt->value);
567}
568
569static void amd_iommu_stats_init(void)
570{
571 stats_dir = debugfs_create_dir("amd-iommu", NULL);
572 if (stats_dir == NULL)
573 return;
574
7f26508b 575 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
3775d481 576 &amd_iommu_unmap_flush);
da49f6df
JR		 577
578 amd_iommu_stats_add(&compl_wait);
0f2a86f2 579 amd_iommu_stats_add(&cnt_map_single);
146a6917 580 amd_iommu_stats_add(&cnt_unmap_single);
d03f067a 581 amd_iommu_stats_add(&cnt_map_sg);
55877a6b 582 amd_iommu_stats_add(&cnt_unmap_sg);
c8f0fb36 583 amd_iommu_stats_add(&cnt_alloc_coherent);
5d31ee7e 584 amd_iommu_stats_add(&cnt_free_coherent);
c1858976 585 amd_iommu_stats_add(&cross_page);
f57d98ae 586 amd_iommu_stats_add(&domain_flush_single);
18811f55 587 amd_iommu_stats_add(&domain_flush_all);
5774f7c5 588 amd_iommu_stats_add(&alloced_io_mem);
8ecaf8f1 589 amd_iommu_stats_add(&total_map_requests);
399be2f5
JR		 590 amd_iommu_stats_add(&complete_ppr);
591 amd_iommu_stats_add(&invalidate_iotlb);
592 amd_iommu_stats_add(&invalidate_iotlb_all);
593 amd_iommu_stats_add(&pri_requests);
7f26508b
JR		 594}
595
596#endif
597
a80dc3e0
JR		 598/****************************************************************************
599 *
600 * Interrupt handling functions
601 *
602 ****************************************************************************/
603
e3e59876
JR		 604static void dump_dte_entry(u16 devid)
605{
606 int i;
607
ee6c2868
JR		 608 for (i = 0; i < 4; ++i)
609 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 610 amd_iommu_dev_table[devid].data[i]);
611}
612
945b4ac4
JR		 613static void dump_command(unsigned long phys_addr)
614{
615 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
616 int i;
617
618 for (i = 0; i < 4; ++i)
619 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
620}
621
a345b23b 622static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4 623{
3d06fca8
JR		 624 int type, devid, domid, flags;
625 volatile u32 *event = __evt;
626 int count = 0;
627 u64 address;
628
629retry:
630 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
631 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
632 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
633 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
634 address = (u64)(((u64)event[3]) << 32) | event[2];
635
636 if (type == 0) {
637 /* Did we hit the erratum? */
638 if (++count == LOOP_TIMEOUT) {
639 pr_err("AMD-Vi: No event written to event log\n");
640 return;
641 }
642 udelay(1);
643 goto retry;
644 }
90008ee4 645
4c6f40d4 646 printk(KERN_ERR "AMD-Vi: Event logged [");
90008ee4
JR		 647
648 switch (type) {
649 case EVENT_TYPE_ILL_DEV:
650 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
651 "address=0x%016llx flags=0x%04x]\n",
652 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
653 address, flags);
e3e59876 654 dump_dte_entry(devid);
90008ee4
JR		 655 break;
656 case EVENT_TYPE_IO_FAULT:
657 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
658 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
659 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
660 domid, address, flags);
661 break;
662 case EVENT_TYPE_DEV_TAB_ERR:
663 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
664 "address=0x%016llx flags=0x%04x]\n",
665 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
666 address, flags);
667 break;
668 case EVENT_TYPE_PAGE_TAB_ERR:
669 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
670 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
671 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
672 domid, address, flags);
673 break;
674 case EVENT_TYPE_ILL_CMD:
675 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 676 dump_command(address);
90008ee4
JR		 677 break;
678 case EVENT_TYPE_CMD_HARD_ERR:
679 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
680 "flags=0x%04x]\n", address, flags);
681 break;
682 case EVENT_TYPE_IOTLB_INV_TO:
683 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
684 "address=0x%016llx]\n",
685 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
686 address);
687 break;
688 case EVENT_TYPE_INV_DEV_REQ:
689 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
690 "address=0x%016llx flags=0x%04x]\n",
691 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
692 address, flags);
693 break;
694 default:
695 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
696 }
3d06fca8
JR		 697
698 memset(__evt, 0, 4 * sizeof(u32));
90008ee4
JR		 699}
700
701static void iommu_poll_events(struct amd_iommu *iommu)
702{
703 u32 head, tail;
704 unsigned long flags;
705
925fe08b
SS		 706 /* enable event interrupts again */
707 writel(MMIO_STATUS_EVT_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
708
90008ee4
JR		 709 spin_lock_irqsave(&iommu->lock, flags);
710
711 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
712 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
713
714 while (head != tail) {
a345b23b 715 iommu_print_event(iommu, iommu->evt_buf + head);
90008ee4
JR		 716 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
717 }
718
719 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
720
721 spin_unlock_irqrestore(&iommu->lock, flags);
722}
723
eee53537 724static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
72e1dcc4
JR		 725{
726 struct amd_iommu_fault fault;
72e1dcc4 727
399be2f5
JR		 728 INC_STATS_COUNTER(pri_requests);
729
72e1dcc4
JR		 730 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
731 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
732 return;
733 }
734
735 fault.address = raw[1];
736 fault.pasid = PPR_PASID(raw[0]);
737 fault.device_id = PPR_DEVID(raw[0]);
738 fault.tag = PPR_TAG(raw[0]);
739 fault.flags = PPR_FLAGS(raw[0]);
740
72e1dcc4
JR		 741 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
742}
743
744static void iommu_poll_ppr_log(struct amd_iommu *iommu)
745{
746 unsigned long flags;
747 u32 head, tail;
748
749 if (iommu->ppr_log == NULL)
750 return;
751
eee53537
JR		 752 /* enable ppr interrupts again */
753 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
754
72e1dcc4
JR		 755 spin_lock_irqsave(&iommu->lock, flags);
756
757 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
758 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
759
760 while (head != tail) {
eee53537
JR		 761 volatile u64 *raw;
762 u64 entry[2];
763 int i;
764
765 raw = (u64 *)(iommu->ppr_log + head);
766
767 /*
768 * Hardware bug: Interrupt may arrive before the entry is
769 * written to memory. If this happens we need to wait for the
770 * entry to arrive.
771 */
772 for (i = 0; i < LOOP_TIMEOUT; ++i) {
773 if (PPR_REQ_TYPE(raw[0]) != 0)
774 break;
775 udelay(1);
776 }
72e1dcc4 777
eee53537
JR		 778 /* Avoid memcpy function-call overhead */
779 entry[0] = raw[0];
780 entry[1] = raw[1];
72e1dcc4 781
eee53537
JR		 782 /*
783 * To detect the hardware bug we need to clear the entry
784 * back to zero.
785 */
786 raw[0] = raw[1] = 0UL;
787
788 /* Update head pointer of hardware ring-buffer */
72e1dcc4
JR		 789 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
790 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
eee53537
JR		 791
792 /*
793 * Release iommu->lock because ppr-handling might need to
df805abb 794 * re-acquire it
eee53537
JR		 795 */
796 spin_unlock_irqrestore(&iommu->lock, flags);
797
798 /* Handle PPR entry */
799 iommu_handle_ppr_entry(iommu, entry);
800
801 spin_lock_irqsave(&iommu->lock, flags);
802
803 /* Refresh ring-buffer information */
804 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
72e1dcc4
JR		 805 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
806 }
807
72e1dcc4
JR		 808 spin_unlock_irqrestore(&iommu->lock, flags);
809}
810
72fe00f0 811irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 812{
90008ee4
JR		 813 struct amd_iommu *iommu;
814
72e1dcc4 815 for_each_iommu(iommu) {
90008ee4 816 iommu_poll_events(iommu);
72e1dcc4
JR		 817 iommu_poll_ppr_log(iommu);
818 }
90008ee4
JR		 819
820 return IRQ_HANDLED;
a80dc3e0
JR		 821}
822
72fe00f0
JR		 823irqreturn_t amd_iommu_int_handler(int irq, void *data)
824{
825 return IRQ_WAKE_THREAD;
826}
827
431b2a20
JR		 828/****************************************************************************
829 *
830 * IOMMU command queuing functions
831 *
832 ****************************************************************************/
833
ac0ea6e9
JR		 834static int wait_on_sem(volatile u64 *sem)
835{
836 int i = 0;
837
838 while (*sem == 0 && i < LOOP_TIMEOUT) {
839 udelay(1);
840 i += 1;
841 }
842
843 if (i == LOOP_TIMEOUT) {
844 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
845 return -EIO;
846 }
847
848 return 0;
849}
850
851static void copy_cmd_to_buffer(struct amd_iommu *iommu,
852 struct iommu_cmd *cmd,
853 u32 tail)
a19ae1ec 854{
a19ae1ec
JR		 855 u8 *target;
856
8a7c5ef3 857 target = iommu->cmd_buf + tail;
ac0ea6e9
JR		 858 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
859
860 /* Copy command to buffer */
861 memcpy(target, cmd, sizeof(*cmd));
862
863 /* Tell the IOMMU about it */
a19ae1ec 864 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 865}
a19ae1ec 866
815b33fd 867static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 868{
815b33fd
JR		 869 WARN_ON(address & 0x7ULL);
870
ded46737 871 memset(cmd, 0, sizeof(*cmd));
815b33fd
JR		 872 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
873 cmd->data[1] = upper_32_bits(__pa(address));
874 cmd->data[2] = 1;
ded46737
JR		 875 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
876}
877
94fe79e2
JR		 878static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
879{
880 memset(cmd, 0, sizeof(*cmd));
881 cmd->data[0] = devid;
882 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
883}
884
11b6402c
JR		 885static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
886 size_t size, u16 domid, int pde)
887{
888 u64 pages;
889 int s;
890
891 pages = iommu_num_pages(address, size, PAGE_SIZE);
892 s = 0;
893
894 if (pages > 1) {
895 /*
896 * If we have to flush more than one page, flush all
897 * TLB entries for this domain
898 */
899 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
900 s = 1;
901 }
902
903 address &= PAGE_MASK;
904
905 memset(cmd, 0, sizeof(*cmd));
906 cmd->data[1] |= domid;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[3] = upper_32_bits(address);
909 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
910 if (s) /* size bit - we flush more than one 4kb page */
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
df805abb 912 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
11b6402c
JR		 913 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
914}
915
cb41ed85
JR		 916static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
917 u64 address, size_t size)
918{
919 u64 pages;
920 int s;
921
922 pages = iommu_num_pages(address, size, PAGE_SIZE);
923 s = 0;
924
925 if (pages > 1) {
926 /*
927 * If we have to flush more than one page, flush all
928 * TLB entries for this domain
929 */
930 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
931 s = 1;
932 }
933
934 address &= PAGE_MASK;
935
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[0] = devid;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[3] = upper_32_bits(address);
942 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
943 if (s)
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
945}
946
22e266c7
JR		 947static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
948 u64 address, bool size)
949{
950 memset(cmd, 0, sizeof(*cmd));
951
952 address &= ~(0xfffULL);
953
954 cmd->data[0] = pasid & PASID_MASK;
955 cmd->data[1] = domid;
956 cmd->data[2] = lower_32_bits(address);
957 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
960 if (size)
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
963}
964
965static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int qdep, u64 address, bool size)
967{
968 memset(cmd, 0, sizeof(*cmd));
969
970 address &= ~(0xfffULL);
971
972 cmd->data[0] = devid;
973 cmd->data[0] |= (pasid & 0xff) << 16;
974 cmd->data[0] |= (qdep & 0xff) << 24;
975 cmd->data[1] = devid;
976 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
977 cmd->data[2] = lower_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
979 cmd->data[3] = upper_32_bits(address);
980 if (size)
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
982 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
983}
984
c99afa25
JR		 985static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
986 int status, int tag, bool gn)
987{
988 memset(cmd, 0, sizeof(*cmd));
989
990 cmd->data[0] = devid;
991 if (gn) {
992 cmd->data[1] = pasid & PASID_MASK;
993 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
994 }
995 cmd->data[3] = tag & 0x1ff;
996 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
997
998 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
999}
1000
58fc7f14
JR		 1001static void build_inv_all(struct iommu_cmd *cmd)
1002{
1003 memset(cmd, 0, sizeof(*cmd));
1004 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 1005}
1006
7ef2798d
JR		 1007static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1008{
1009 memset(cmd, 0, sizeof(*cmd));
1010 cmd->data[0] = devid;
1011 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1012}
1013
431b2a20 1014/*
431b2a20 1015 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 1016 * hardware about the new command.
431b2a20 1017 */
f1ca1512
JR		 1018static int iommu_queue_command_sync(struct amd_iommu *iommu,
1019 struct iommu_cmd *cmd,
1020 bool sync)
a19ae1ec 1021{
ac0ea6e9 1022 u32 left, tail, head, next_tail;
a19ae1ec 1023 unsigned long flags;
a19ae1ec 1024
549c90dc 1025 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
ac0ea6e9
JR		 1026
1027again:
a19ae1ec 1028 spin_lock_irqsave(&iommu->lock, flags);
a19ae1ec 1029
ac0ea6e9
JR		 1030 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1031 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1032 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
1033 left = (head - next_tail) % iommu->cmd_buf_size;
a19ae1ec 1034
ac0ea6e9
JR		 1035 if (left <= 2) {
1036 struct iommu_cmd sync_cmd;
1037 volatile u64 sem = 0;
1038 int ret;
8d201968 1039
ac0ea6e9
JR		 1040 build_completion_wait(&sync_cmd, (u64)&sem);
1041 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
da49f6df 1042
ac0ea6e9
JR		 1043 spin_unlock_irqrestore(&iommu->lock, flags);
1044
1045 if ((ret = wait_on_sem(&sem)) != 0)
1046 return ret;
1047
1048 goto again;
8d201968
JR		 1049 }
1050
ac0ea6e9
JR		 1051 copy_cmd_to_buffer(iommu, cmd, tail);
1052
1053 /* We need to sync now to make sure all commands are processed */
f1ca1512 1054 iommu->need_sync = sync;
ac0ea6e9 1055
a19ae1ec 1056 spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1057
815b33fd 1058 return 0;
8d201968
JR		 1059}
1060
f1ca1512
JR		 1061static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1062{
1063 return iommu_queue_command_sync(iommu, cmd, true);
1064}
1065
8d201968
JR		 1066/*
1067 * This function queues a completion wait command into the command
1068 * buffer of an IOMMU
1069 */
a19ae1ec 1070static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 1071{
1072 struct iommu_cmd cmd;
815b33fd 1073 volatile u64 sem = 0;
ac0ea6e9 1074 int ret;
8d201968 1075
09ee17eb 1076 if (!iommu->need_sync)
815b33fd 1077 return 0;
09ee17eb 1078
815b33fd 1079 build_completion_wait(&cmd, (u64)&sem);
a19ae1ec 1080
f1ca1512 1081 ret = iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 1082 if (ret)
815b33fd 1083 return ret;
8d201968 1084
ac0ea6e9 1085 return wait_on_sem(&sem);
8d201968
JR		 1086}
1087
d8c13085 1088static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 1089{
d8c13085 1090 struct iommu_cmd cmd;
a19ae1ec 1091
d8c13085 1092 build_inv_dte(&cmd, devid);
7e4f88da 1093
d8c13085
JR		 1094 return iommu_queue_command(iommu, &cmd);
1095}
09ee17eb 1096
7d0c5cc5
JR		 1097static void iommu_flush_dte_all(struct amd_iommu *iommu)
1098{
1099 u32 devid;
09ee17eb 1100
7d0c5cc5
JR		 1101 for (devid = 0; devid <= 0xffff; ++devid)
1102 iommu_flush_dte(iommu, devid);
a19ae1ec 1103
7d0c5cc5
JR		 1104 iommu_completion_wait(iommu);
1105}
84df8175 1106
7d0c5cc5
JR		 1107/*
1108 * This function uses heavy locking and may disable irqs for some time. But
1109 * this is no issue because it is only called during resume.
1110 */
1111static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1112{
1113 u32 dom_id;
a19ae1ec 1114
7d0c5cc5
JR		 1115 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1116 struct iommu_cmd cmd;
1117 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1118 dom_id, 1);
1119 iommu_queue_command(iommu, &cmd);
1120 }
8eed9833 1121
7d0c5cc5 1122 iommu_completion_wait(iommu);
a19ae1ec
JR		 1123}
1124
58fc7f14 1125static void iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 1126{
58fc7f14 1127 struct iommu_cmd cmd;
0518a3a4 1128
58fc7f14 1129 build_inv_all(&cmd);
0518a3a4 1130
58fc7f14
JR		 1131 iommu_queue_command(iommu, &cmd);
1132 iommu_completion_wait(iommu);
1133}
1134
7ef2798d
JR		 1135static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1136{
1137 struct iommu_cmd cmd;
1138
1139 build_inv_irt(&cmd, devid);
1140
1141 iommu_queue_command(iommu, &cmd);
1142}
1143
1144static void iommu_flush_irt_all(struct amd_iommu *iommu)
1145{
1146 u32 devid;
1147
1148 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1149 iommu_flush_irt(iommu, devid);
1150
1151 iommu_completion_wait(iommu);
1152}
1153
7d0c5cc5
JR		 1154void iommu_flush_all_caches(struct amd_iommu *iommu)
1155{
58fc7f14
JR		 1156 if (iommu_feature(iommu, FEATURE_IA)) {
1157 iommu_flush_all(iommu);
1158 } else {
1159 iommu_flush_dte_all(iommu);
7ef2798d 1160 iommu_flush_irt_all(iommu);
58fc7f14 1161 iommu_flush_tlb_all(iommu);
0518a3a4
JR		 1162 }
1163}
1164
431b2a20 1165/*
cb41ed85 1166 * Command send function for flushing on-device TLB
431b2a20 1167 */
6c542047
JR		 1168static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1169 u64 address, size_t size)
3fa43655
JR		 1170{
1171 struct amd_iommu *iommu;
b00d3bcf 1172 struct iommu_cmd cmd;
cb41ed85 1173 int qdep;
3fa43655 1174
ea61cddb
JR		 1175 qdep = dev_data->ats.qdep;
1176 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 1177
ea61cddb 1178 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 1179
1180 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 1181}
1182
431b2a20 1183/*
431b2a20 1184 * Command send function for invalidating a device table entry
431b2a20 1185 */
6c542047 1186static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 1187{
3fa43655 1188 struct amd_iommu *iommu;
ee2fa743 1189 int ret;
a19ae1ec 1190
6c542047 1191 iommu = amd_iommu_rlookup_table[dev_data->devid];
a19ae1ec 1192
f62dda66 1193 ret = iommu_flush_dte(iommu, dev_data->devid);
cb41ed85
JR		 1194 if (ret)
1195 return ret;
1196
ea61cddb 1197 if (dev_data->ats.enabled)
6c542047 1198 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 1199
ee2fa743 1200 return ret;
a19ae1ec
JR		 1201}
1202
431b2a20
JR		 1203/*
1204 * TLB invalidation function which is called from the mapping functions.
1205 * It invalidates a single PTE if the range to flush is within a single
1206 * page. Otherwise it flushes the whole TLB of the IOMMU.
1207 */
17b124bf
JR		 1208static void __domain_flush_pages(struct protection_domain *domain,
1209 u64 address, size_t size, int pde)
a19ae1ec 1210{
cb41ed85 1211 struct iommu_dev_data *dev_data;
11b6402c
JR		 1212 struct iommu_cmd cmd;
1213 int ret = 0, i;
a19ae1ec 1214
11b6402c 1215 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 1216
6de8ad9b
JR		 1217 for (i = 0; i < amd_iommus_present; ++i) {
1218 if (!domain->dev_iommu[i])
1219 continue;
1220
1221 /*
1222 * Devices of this domain are behind this IOMMU
1223 * We need a TLB flush
1224 */
11b6402c 1225 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 1226 }
1227
cb41ed85 1228 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 1229
ea61cddb 1230 if (!dev_data->ats.enabled)
cb41ed85
JR		 1231 continue;
1232
6c542047 1233 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 1234 }
1235
11b6402c 1236 WARN_ON(ret);
6de8ad9b
JR		 1237}
1238
17b124bf
JR		 1239static void domain_flush_pages(struct protection_domain *domain,
1240 u64 address, size_t size)
6de8ad9b 1241{
17b124bf 1242 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 1243}
b6c02715 1244
1c655773 1245/* Flush the whole IO/TLB for a given protection domain */
17b124bf 1246static void domain_flush_tlb(struct protection_domain *domain)
1c655773 1247{
17b124bf 1248 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 1249}
1250
42a49f96 1251/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 1252static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 1253{
17b124bf 1254 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 1255}
1256
17b124bf 1257static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 1258{
17b124bf 1259 int i;
18811f55 1260
17b124bf
JR		 1261 for (i = 0; i < amd_iommus_present; ++i) {
1262 if (!domain->dev_iommu[i])
1263 continue;
bfd1be18 1264
17b124bf
JR		 1265 /*
1266 * Devices of this domain are behind this IOMMU
1267 * We need to wait for completion of all commands.
1268 */
1269 iommu_completion_wait(amd_iommus[i]);
bfd1be18 1270 }
e394d72a
JR		 1271}
1272
b00d3bcf 1273
09b42804 1274/*
b00d3bcf 1275 * This function flushes the DTEs for all devices in domain
09b42804 1276 */
17b124bf 1277static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1278{
b00d3bcf 1279 struct iommu_dev_data *dev_data;
b26e81b8 1280
b00d3bcf 1281 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1282 device_flush_dte(dev_data);
a345b23b
JR		 1283}
1284
431b2a20
JR		 1285/****************************************************************************
1286 *
1287 * The functions below are used the create the page table mappings for
1288 * unity mapped regions.
1289 *
1290 ****************************************************************************/
1291
308973d3
JR		 1292/*
1293 * This function is used to add another level to an IO page table. Adding
1294 * another level increases the size of the address space by 9 bits to a size up
1295 * to 64 bits.
1296 */
1297static bool increase_address_space(struct protection_domain *domain,
1298 gfp_t gfp)
1299{
1300 u64 *pte;
1301
1302 if (domain->mode == PAGE_MODE_6_LEVEL)
1303 /* address space already 64 bit large */
1304 return false;
1305
1306 pte = (void *)get_zeroed_page(gfp);
1307 if (!pte)
1308 return false;
1309
1310 *pte = PM_LEVEL_PDE(domain->mode,
1311 virt_to_phys(domain->pt_root));
1312 domain->pt_root = pte;
1313 domain->mode += 1;
1314 domain->updated = true;
1315
1316 return true;
1317}
1318
1319static u64 *alloc_pte(struct protection_domain *domain,
1320 unsigned long address,
cbb9d729 1321 unsigned long page_size,
308973d3
JR		 1322 u64 **pte_page,
1323 gfp_t gfp)
1324{
cbb9d729 1325 int level, end_lvl;
308973d3 1326 u64 *pte, *page;
cbb9d729
JR		 1327
1328 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1329
1330 while (address > PM_LEVEL_SIZE(domain->mode))
1331 increase_address_space(domain, gfp);
1332
cbb9d729
JR		 1333 level = domain->mode - 1;
1334 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1335 address = PAGE_SIZE_ALIGN(address, page_size);
1336 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1337
1338 while (level > end_lvl) {
1339 if (!IOMMU_PTE_PRESENT(*pte)) {
1340 page = (u64 *)get_zeroed_page(gfp);
1341 if (!page)
1342 return NULL;
1343 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1344 }
1345
cbb9d729
JR		 1346 /* No level skipping support yet */
1347 if (PM_PTE_LEVEL(*pte) != level)
1348 return NULL;
1349
308973d3
JR		 1350 level -= 1;
1351
1352 pte = IOMMU_PTE_PAGE(*pte);
1353
1354 if (pte_page && level == end_lvl)
1355 *pte_page = pte;
1356
1357 pte = &pte[PM_LEVEL_INDEX(level, address)];
1358 }
1359
1360 return pte;
1361}
1362
1363/*
1364 * This function checks if there is a PTE for a given dma address. If
1365 * there is one, it returns the pointer to it.
1366 */
24cd7723 1367static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
308973d3
JR		 1368{
1369 int level;
1370 u64 *pte;
1371
24cd7723
JR		 1372 if (address > PM_LEVEL_SIZE(domain->mode))
1373 return NULL;
1374
1375 level = domain->mode - 1;
1376 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
308973d3 1377
24cd7723
JR		 1378 while (level > 0) {
1379
1380 /* Not Present */
308973d3
JR		 1381 if (!IOMMU_PTE_PRESENT(*pte))
1382 return NULL;
1383
24cd7723
JR		 1384 /* Large PTE */
1385 if (PM_PTE_LEVEL(*pte) == 0x07) {
1386 unsigned long pte_mask, __pte;
1387
1388 /*
1389 * If we have a series of large PTEs, make
1390 * sure to return a pointer to the first one.
1391 */
1392 pte_mask = PTE_PAGE_SIZE(*pte);
1393 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1394 __pte = ((unsigned long)pte) & pte_mask;
1395
1396 return (u64 *)__pte;
1397 }
1398
1399 /* No level skipping support yet */
1400 if (PM_PTE_LEVEL(*pte) != level)
1401 return NULL;
1402
308973d3
JR		 1403 level -= 1;
1404
24cd7723 1405 /* Walk to the next level */
308973d3
JR		 1406 pte = IOMMU_PTE_PAGE(*pte);
1407 pte = &pte[PM_LEVEL_INDEX(level, address)];
308973d3
JR		 1408 }
1409
1410 return pte;
1411}
1412
431b2a20
JR		 1413/*
1414 * Generic mapping functions. It maps a physical address into a DMA
1415 * address space. It allocates the page table pages if necessary.
1416 * In the future it can be extended to a generic mapping function
1417 * supporting all features of AMD IOMMU page tables like level skipping
1418 * and full 64 bit address spaces.
1419 */
38e817fe
JR		 1420static int iommu_map_page(struct protection_domain *dom,
1421 unsigned long bus_addr,
1422 unsigned long phys_addr,
abdc5eb3 1423 int prot,
cbb9d729 1424 unsigned long page_size)
bd0e5211 1425{
8bda3092 1426 u64 __pte, *pte;
cbb9d729 1427 int i, count;
abdc5eb3 1428
bad1cac2 1429 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1430 return -EINVAL;
1431
cbb9d729
JR		 1432 bus_addr = PAGE_ALIGN(bus_addr);
1433 phys_addr = PAGE_ALIGN(phys_addr);
1434 count = PAGE_SIZE_PTE_COUNT(page_size);
1435 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1436
1437 for (i = 0; i < count; ++i)
1438 if (IOMMU_PTE_PRESENT(pte[i]))
1439 return -EBUSY;
bd0e5211 1440
cbb9d729
JR		 1441 if (page_size > PAGE_SIZE) {
1442 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1443 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1444 } else
1445 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
bd0e5211 1446
bd0e5211
JR		 1447 if (prot & IOMMU_PROT_IR)
1448 __pte |= IOMMU_PTE_IR;
1449 if (prot & IOMMU_PROT_IW)
1450 __pte |= IOMMU_PTE_IW;
1451
cbb9d729
JR		 1452 for (i = 0; i < count; ++i)
1453 pte[i] = __pte;
bd0e5211 1454
04bfdd84
JR		 1455 update_domain(dom);
1456
bd0e5211
JR		 1457 return 0;
1458}
1459
24cd7723
JR		 1460static unsigned long iommu_unmap_page(struct protection_domain *dom,
1461 unsigned long bus_addr,
1462 unsigned long page_size)
eb74ff6c 1463{
24cd7723
JR		 1464 unsigned long long unmap_size, unmapped;
1465 u64 *pte;
1466
1467 BUG_ON(!is_power_of_2(page_size));
1468
1469 unmapped = 0;
eb74ff6c 1470
24cd7723
JR		 1471 while (unmapped < page_size) {
1472
1473 pte = fetch_pte(dom, bus_addr);
1474
1475 if (!pte) {
1476 /*
1477 * No PTE for this address
1478 * move forward in 4kb steps
1479 */
1480 unmap_size = PAGE_SIZE;
1481 } else if (PM_PTE_LEVEL(*pte) == 0) {
1482 /* 4kb PTE found for this address */
1483 unmap_size = PAGE_SIZE;
1484 *pte = 0ULL;
1485 } else {
1486 int count, i;
1487
1488 /* Large PTE found which maps this address */
1489 unmap_size = PTE_PAGE_SIZE(*pte);
1490 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1491 for (i = 0; i < count; i++)
1492 pte[i] = 0ULL;
1493 }
1494
1495 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1496 unmapped += unmap_size;
1497 }
1498
1499 BUG_ON(!is_power_of_2(unmapped));
eb74ff6c 1500
24cd7723 1501 return unmapped;
eb74ff6c 1502}
eb74ff6c 1503
431b2a20
JR		 1504/*
1505 * This function checks if a specific unity mapping entry is needed for
1506 * this specific IOMMU.
1507 */
bd0e5211
JR		 1508static int iommu_for_unity_map(struct amd_iommu *iommu,
1509 struct unity_map_entry *entry)
1510{
1511 u16 bdf, i;
1512
1513 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1514 bdf = amd_iommu_alias_table[i];
1515 if (amd_iommu_rlookup_table[bdf] == iommu)
1516 return 1;
1517 }
1518
1519 return 0;
1520}
1521
431b2a20
JR		 1522/*
1523 * This function actually applies the mapping to the page table of the
1524 * dma_ops domain.
1525 */
bd0e5211
JR		 1526static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1527 struct unity_map_entry *e)
1528{
1529 u64 addr;
1530 int ret;
1531
1532 for (addr = e->address_start; addr < e->address_end;
1533 addr += PAGE_SIZE) {
abdc5eb3 1534 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
cbb9d729 1535 PAGE_SIZE);
bd0e5211
JR		 1536 if (ret)
1537 return ret;
1538 /*
1539 * if unity mapping is in aperture range mark the page
1540 * as allocated in the aperture
1541 */
1542 if (addr < dma_dom->aperture_size)
c3239567 1543 __set_bit(addr >> PAGE_SHIFT,
384de729 1544 dma_dom->aperture[0]->bitmap);
bd0e5211
JR		 1545 }
1546
1547 return 0;
1548}
1549
171e7b37
JR		 1550/*
1551 * Init the unity mappings for a specific IOMMU in the system
1552 *
1553 * Basically iterates over all unity mapping entries and applies them to
1554 * the default domain DMA of that IOMMU if necessary.
1555 */
1556static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1557{
1558 struct unity_map_entry *entry;
1559 int ret;
1560
1561 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1562 if (!iommu_for_unity_map(iommu, entry))
1563 continue;
1564 ret = dma_ops_unity_map(iommu->default_dom, entry);
1565 if (ret)
1566 return ret;
1567 }
1568
1569 return 0;
1570}
1571
431b2a20
JR		 1572/*
1573 * Inits the unity mappings required for a specific device
1574 */
bd0e5211
JR		 1575static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1576 u16 devid)
1577{
1578 struct unity_map_entry *e;
1579 int ret;
1580
1581 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1582 if (!(devid >= e->devid_start && devid <= e->devid_end))
1583 continue;
1584 ret = dma_ops_unity_map(dma_dom, e);
1585 if (ret)
1586 return ret;
1587 }
1588
1589 return 0;
1590}
1591
431b2a20
JR		 1592/****************************************************************************
1593 *
1594 * The next functions belong to the address allocator for the dma_ops
1595 * interface functions. They work like the allocators in the other IOMMU
1596 * drivers. Its basically a bitmap which marks the allocated pages in
1597 * the aperture. Maybe it could be enhanced in the future to a more
1598 * efficient allocator.
1599 *
1600 ****************************************************************************/
d3086444 1601
431b2a20 1602/*
384de729 1603 * The address allocator core functions.
431b2a20
JR		 1604 *
1605 * called with domain->lock held
1606 */
384de729 1607
171e7b37
JR		 1608/*
1609 * Used to reserve address ranges in the aperture (e.g. for exclusion
1610 * ranges.
1611 */
1612static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1613 unsigned long start_page,
1614 unsigned int pages)
1615{
1616 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1617
1618 if (start_page + pages > last_page)
1619 pages = last_page - start_page;
1620
1621 for (i = start_page; i < start_page + pages; ++i) {
1622 int index = i / APERTURE_RANGE_PAGES;
1623 int page = i % APERTURE_RANGE_PAGES;
1624 __set_bit(page, dom->aperture[index]->bitmap);
1625 }
1626}
1627
9cabe89b
JR		 1628/*
1629 * This function is used to add a new aperture range to an existing
1630 * aperture in case of dma_ops domain allocation or address allocation
1631 * failure.
1632 */
576175c2 1633static int alloc_new_range(struct dma_ops_domain *dma_dom,
9cabe89b
JR		 1634 bool populate, gfp_t gfp)
1635{
1636 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
576175c2 1637 struct amd_iommu *iommu;
17f5b569 1638 unsigned long i, old_size;
9cabe89b 1639
f5e9705c
JR		 1640#ifdef CONFIG_IOMMU_STRESS
1641 populate = false;
1642#endif
1643
9cabe89b
JR		 1644 if (index >= APERTURE_MAX_RANGES)
1645 return -ENOMEM;
1646
1647 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1648 if (!dma_dom->aperture[index])
1649 return -ENOMEM;
1650
1651 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1652 if (!dma_dom->aperture[index]->bitmap)
1653 goto out_free;
1654
1655 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1656
1657 if (populate) {
1658 unsigned long address = dma_dom->aperture_size;
1659 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1660 u64 *pte, *pte_page;
1661
1662 for (i = 0; i < num_ptes; ++i) {
cbb9d729 1663 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
9cabe89b
JR		 1664 &pte_page, gfp);
1665 if (!pte)
1666 goto out_free;
1667
1668 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1669
1670 address += APERTURE_RANGE_SIZE / 64;
1671 }
1672 }
1673
17f5b569 1674 old_size = dma_dom->aperture_size;
9cabe89b
JR		 1675 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1676
17f5b569
JR		 1677 /* Reserve address range used for MSI messages */
1678 if (old_size < MSI_ADDR_BASE_LO &&
1679 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1680 unsigned long spage;
1681 int pages;
1682
1683 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1684 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1685
1686 dma_ops_reserve_addresses(dma_dom, spage, pages);
1687 }
1688
b595076a 1689 /* Initialize the exclusion range if necessary */
576175c2
JR		 1690 for_each_iommu(iommu) {
1691 if (iommu->exclusion_start &&
1692 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1693 && iommu->exclusion_start < dma_dom->aperture_size) {
1694 unsigned long startpage;
1695 int pages = iommu_num_pages(iommu->exclusion_start,
1696 iommu->exclusion_length,
1697 PAGE_SIZE);
1698 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1699 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1700 }
00cd122a
JR		 1701 }
1702
1703 /*
1704 * Check for areas already mapped as present in the new aperture
1705 * range and mark those pages as reserved in the allocator. Such
1706 * mappings may already exist as a result of requested unity
1707 * mappings for devices.
1708 */
1709 for (i = dma_dom->aperture[index]->offset;
1710 i < dma_dom->aperture_size;
1711 i += PAGE_SIZE) {
24cd7723 1712 u64 *pte = fetch_pte(&dma_dom->domain, i);
00cd122a
JR		 1713 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1714 continue;
1715
fcd0861d 1716 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
00cd122a
JR		 1717 }
1718
04bfdd84
JR		 1719 update_domain(&dma_dom->domain);
1720
9cabe89b
JR		 1721 return 0;
1722
1723out_free:
04bfdd84
JR		 1724 update_domain(&dma_dom->domain);
1725
9cabe89b
JR		 1726 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1727
1728 kfree(dma_dom->aperture[index]);
1729 dma_dom->aperture[index] = NULL;
1730
1731 return -ENOMEM;
1732}
1733
384de729
JR		 1734static unsigned long dma_ops_area_alloc(struct device *dev,
1735 struct dma_ops_domain *dom,
1736 unsigned int pages,
1737 unsigned long align_mask,
1738 u64 dma_mask,
1739 unsigned long start)
1740{
803b8cb4 1741 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
384de729
JR		 1742 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1743 int i = start >> APERTURE_RANGE_SHIFT;
1744 unsigned long boundary_size;
1745 unsigned long address = -1;
1746 unsigned long limit;
1747
803b8cb4
JR		 1748 next_bit >>= PAGE_SHIFT;
1749
384de729
JR		 1750 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1751 PAGE_SIZE) >> PAGE_SHIFT;
1752
1753 for (;i < max_index; ++i) {
1754 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1755
1756 if (dom->aperture[i]->offset >= dma_mask)
1757 break;
1758
1759 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1760 dma_mask >> PAGE_SHIFT);
1761
1762 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1763 limit, next_bit, pages, 0,
1764 boundary_size, align_mask);
1765 if (address != -1) {
1766 address = dom->aperture[i]->offset +
1767 (address << PAGE_SHIFT);
803b8cb4 1768 dom->next_address = address + (pages << PAGE_SHIFT);
384de729
JR		 1769 break;
1770 }
1771
1772 next_bit = 0;
1773 }
1774
1775 return address;
1776}
1777
d3086444
JR		 1778static unsigned long dma_ops_alloc_addresses(struct device *dev,
1779 struct dma_ops_domain *dom,
6d4f343f 1780 unsigned int pages,
832a90c3
JR		 1781 unsigned long align_mask,
1782 u64 dma_mask)
d3086444 1783{
d3086444 1784 unsigned long address;
d3086444 1785
fe16f088
JR		 1786#ifdef CONFIG_IOMMU_STRESS
1787 dom->next_address = 0;
1788 dom->need_flush = true;
1789#endif
d3086444 1790
384de729 1791 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
803b8cb4 1792 dma_mask, dom->next_address);
d3086444 1793
1c655773 1794 if (address == -1) {
803b8cb4 1795 dom->next_address = 0;
384de729
JR		 1796 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1797 dma_mask, 0);
1c655773
JR		 1798 dom->need_flush = true;
1799 }
d3086444 1800
384de729 1801 if (unlikely(address == -1))
8fd524b3 1802 address = DMA_ERROR_CODE;
d3086444
JR		 1803
1804 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1805
1806 return address;
1807}
1808
431b2a20
JR		 1809/*
1810 * The address free function.
1811 *
1812 * called with domain->lock held
1813 */
d3086444
JR		 1814static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1815 unsigned long address,
1816 unsigned int pages)
1817{
384de729
JR		 1818 unsigned i = address >> APERTURE_RANGE_SHIFT;
1819 struct aperture_range *range = dom->aperture[i];
80be308d 1820
384de729
JR		 1821 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1822
47bccd6b
JR		 1823#ifdef CONFIG_IOMMU_STRESS
1824 if (i < 4)
1825 return;
1826#endif
80be308d 1827
803b8cb4 1828 if (address >= dom->next_address)
80be308d 1829 dom->need_flush = true;
384de729
JR		 1830
1831 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
803b8cb4 1832
a66022c4 1833 bitmap_clear(range->bitmap, address, pages);
384de729 1834
d3086444
JR		 1835}
1836
431b2a20
JR		 1837/****************************************************************************
1838 *
1839 * The next functions belong to the domain allocation. A domain is
1840 * allocated for every IOMMU as the default domain. If device isolation
1841 * is enabled, every device get its own domain. The most important thing
1842 * about domains is the page table mapping the DMA address space they
1843 * contain.
1844 *
1845 ****************************************************************************/
1846
aeb26f55
JR		 1847/*
1848 * This function adds a protection domain to the global protection domain list
1849 */
1850static void add_domain_to_list(struct protection_domain *domain)
1851{
1852 unsigned long flags;
1853
1854 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1855 list_add(&domain->list, &amd_iommu_pd_list);
1856 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1857}
1858
1859/*
1860 * This function removes a protection domain to the global
1861 * protection domain list
1862 */
1863static void del_domain_from_list(struct protection_domain *domain)
1864{
1865 unsigned long flags;
1866
1867 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1868 list_del(&domain->list);
1869 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1870}
1871
ec487d1a
JR		 1872static u16 domain_id_alloc(void)
1873{
1874 unsigned long flags;
1875 int id;
1876
1877 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1878 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1879 BUG_ON(id == 0);
1880 if (id > 0 && id < MAX_DOMAIN_ID)
1881 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1882 else
1883 id = 0;
1884 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1885
1886 return id;
1887}
1888
a2acfb75
JR		 1889static void domain_id_free(int id)
1890{
1891 unsigned long flags;
1892
1893 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1894 if (id > 0 && id < MAX_DOMAIN_ID)
1895 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1896 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1897}
a2acfb75 1898
86db2e5d 1899static void free_pagetable(struct protection_domain *domain)
ec487d1a
JR		 1900{
1901 int i, j;
1902 u64 *p1, *p2, *p3;
1903
86db2e5d 1904 p1 = domain->pt_root;
ec487d1a
JR		 1905
1906 if (!p1)
1907 return;
1908
1909 for (i = 0; i < 512; ++i) {
1910 if (!IOMMU_PTE_PRESENT(p1[i]))
1911 continue;
1912
1913 p2 = IOMMU_PTE_PAGE(p1[i]);
3cc3d84b 1914 for (j = 0; j < 512; ++j) {
ec487d1a
JR		 1915 if (!IOMMU_PTE_PRESENT(p2[j]))
1916 continue;
1917 p3 = IOMMU_PTE_PAGE(p2[j]);
1918 free_page((unsigned long)p3);
1919 }
1920
1921 free_page((unsigned long)p2);
1922 }
1923
1924 free_page((unsigned long)p1);
86db2e5d
JR		 1925
1926 domain->pt_root = NULL;
ec487d1a
JR		 1927}
1928
b16137b1
JR		 1929static void free_gcr3_tbl_level1(u64 *tbl)
1930{
1931 u64 *ptr;
1932 int i;
1933
1934 for (i = 0; i < 512; ++i) {
1935 if (!(tbl[i] & GCR3_VALID))
1936 continue;
1937
1938 ptr = __va(tbl[i] & PAGE_MASK);
1939
1940 free_page((unsigned long)ptr);
1941 }
1942}
1943
1944static void free_gcr3_tbl_level2(u64 *tbl)
1945{
1946 u64 *ptr;
1947 int i;
1948
1949 for (i = 0; i < 512; ++i) {
1950 if (!(tbl[i] & GCR3_VALID))
1951 continue;
1952
1953 ptr = __va(tbl[i] & PAGE_MASK);
1954
1955 free_gcr3_tbl_level1(ptr);
1956 }
1957}
1958
52815b75
JR		 1959static void free_gcr3_table(struct protection_domain *domain)
1960{
b16137b1
JR		 1961 if (domain->glx == 2)
1962 free_gcr3_tbl_level2(domain->gcr3_tbl);
1963 else if (domain->glx == 1)
1964 free_gcr3_tbl_level1(domain->gcr3_tbl);
1965 else if (domain->glx != 0)
1966 BUG();
1967
52815b75
JR		 1968 free_page((unsigned long)domain->gcr3_tbl);
1969}
1970
431b2a20
JR		 1971/*
1972 * Free a domain, only used if something went wrong in the
1973 * allocation path and we need to free an already allocated page table
1974 */
ec487d1a
JR		 1975static void dma_ops_domain_free(struct dma_ops_domain *dom)
1976{
384de729
JR		 1977 int i;
1978
ec487d1a
JR		 1979 if (!dom)
1980 return;
1981
aeb26f55
JR		 1982 del_domain_from_list(&dom->domain);
1983
86db2e5d 1984 free_pagetable(&dom->domain);
ec487d1a 1985
384de729
JR		 1986 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1987 if (!dom->aperture[i])
1988 continue;
1989 free_page((unsigned long)dom->aperture[i]->bitmap);
1990 kfree(dom->aperture[i]);
1991 }
ec487d1a
JR		 1992
1993 kfree(dom);
1994}
1995
431b2a20
JR		 1996/*
1997 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1998 * It also initializes the page table and the address allocator data
431b2a20
JR		 1999 * structures required for the dma_ops interface
2000 */
87a64d52 2001static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 2002{
2003 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 2004
2005 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2006 if (!dma_dom)
2007 return NULL;
2008
2009 spin_lock_init(&dma_dom->domain.lock);
2010
2011 dma_dom->domain.id = domain_id_alloc();
2012 if (dma_dom->domain.id == 0)
2013 goto free_dma_dom;
7c392cbe 2014 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
8f7a017c 2015 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
ec487d1a 2016 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 2017 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 2018 dma_dom->domain.priv = dma_dom;
2019 if (!dma_dom->domain.pt_root)
2020 goto free_dma_dom;
ec487d1a 2021
1c655773 2022 dma_dom->need_flush = false;
bd60b735 2023 dma_dom->target_dev = 0xffff;
1c655773 2024
aeb26f55
JR		 2025 add_domain_to_list(&dma_dom->domain);
2026
576175c2 2027 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
ec487d1a 2028 goto free_dma_dom;
ec487d1a 2029
431b2a20 2030 /*
ec487d1a
JR		 2031 * mark the first page as allocated so we never return 0 as
2032 * a valid dma-address. So we can use 0 as error value
431b2a20 2033 */
384de729 2034 dma_dom->aperture[0]->bitmap[0] = 1;
803b8cb4 2035 dma_dom->next_address = 0;
ec487d1a 2036
ec487d1a
JR		 2037
2038 return dma_dom;
2039
2040free_dma_dom:
2041 dma_ops_domain_free(dma_dom);
2042
2043 return NULL;
2044}
2045
5b28df6f
JR		 2046/*
2047 * little helper function to check whether a given protection domain is a
2048 * dma_ops domain
2049 */
2050static bool dma_ops_domain(struct protection_domain *domain)
2051{
2052 return domain->flags & PD_DMA_OPS_MASK;
2053}
2054
fd7b5535 2055static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
b20ac0d4 2056{
132bd68f 2057 u64 pte_root = 0;
ee6c2868 2058 u64 flags = 0;
863c74eb 2059
132bd68f
JR		 2060 if (domain->mode != PAGE_MODE_NONE)
2061 pte_root = virt_to_phys(domain->pt_root);
2062
38ddf41b
JR		 2063 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2064 << DEV_ENTRY_MODE_SHIFT;
2065 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
b20ac0d4 2066
ee6c2868
JR		 2067 flags = amd_iommu_dev_table[devid].data[1];
2068
fd7b5535
JR		 2069 if (ats)
2070 flags |= DTE_FLAG_IOTLB;
2071
52815b75
JR		 2072 if (domain->flags & PD_IOMMUV2_MASK) {
2073 u64 gcr3 = __pa(domain->gcr3_tbl);
2074 u64 glx = domain->glx;
2075 u64 tmp;
2076
2077 pte_root |= DTE_FLAG_GV;
2078 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2079
2080 /* First mask out possible old values for GCR3 table */
2081 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2082 flags &= ~tmp;
2083
2084 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2085 flags &= ~tmp;
2086
2087 /* Encode GCR3 table into DTE */
2088 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2089 pte_root |= tmp;
2090
2091 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2092 flags |= tmp;
2093
2094 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2095 flags |= tmp;
2096 }
2097
ee6c2868
JR		 2098 flags &= ~(0xffffUL);
2099 flags |= domain->id;
2100
2101 amd_iommu_dev_table[devid].data[1] = flags;
2102 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 2103}
2104
2105static void clear_dte_entry(u16 devid)
2106{
15898bbc
JR		 2107 /* remove entry from the device table seen by the hardware */
2108 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2109 amd_iommu_dev_table[devid].data[1] = 0;
15898bbc
JR		 2110
2111 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 2112}
2113
ec9e79ef
JR		 2114static void do_attach(struct iommu_dev_data *dev_data,
2115 struct protection_domain *domain)
7f760ddd 2116{
7f760ddd 2117 struct amd_iommu *iommu;
ec9e79ef 2118 bool ats;
fd7b5535 2119
ec9e79ef
JR		 2120 iommu = amd_iommu_rlookup_table[dev_data->devid];
2121 ats = dev_data->ats.enabled;
7f760ddd
JR		 2122
2123 /* Update data structures */
2124 dev_data->domain = domain;
2125 list_add(&dev_data->list, &domain->dev_list);
f62dda66 2126 set_dte_entry(dev_data->devid, domain, ats);
7f760ddd
JR		 2127
2128 /* Do reference counting */
2129 domain->dev_iommu[iommu->index] += 1;
2130 domain->dev_cnt += 1;
2131
2132 /* Flush the DTE entry */
6c542047 2133 device_flush_dte(dev_data);
7f760ddd
JR		 2134}
2135
ec9e79ef 2136static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 2137{
7f760ddd 2138 struct amd_iommu *iommu;
7f760ddd 2139
ec9e79ef 2140 iommu = amd_iommu_rlookup_table[dev_data->devid];
15898bbc
JR		 2141
2142 /* decrease reference counters */
7f760ddd
JR		 2143 dev_data->domain->dev_iommu[iommu->index] -= 1;
2144 dev_data->domain->dev_cnt -= 1;
2145
2146 /* Update data structures */
2147 dev_data->domain = NULL;
2148 list_del(&dev_data->list);
f62dda66 2149 clear_dte_entry(dev_data->devid);
15898bbc 2150
7f760ddd 2151 /* Flush the DTE entry */
6c542047 2152 device_flush_dte(dev_data);
2b681faf
JR		 2153}
2154
2155/*
2156 * If a device is not yet associated with a domain, this function does
2157 * assigns it visible for the hardware
2158 */
ec9e79ef 2159static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 2160 struct protection_domain *domain)
2b681faf 2161{
84fe6c19 2162 int ret;
657cbb6b 2163
2b681faf
JR		 2164 /* lock domain */
2165 spin_lock(&domain->lock);
2166
71f77580
JR		 2167 if (dev_data->alias_data != NULL) {
2168 struct iommu_dev_data *alias_data = dev_data->alias_data;
15898bbc 2169
2b02b091
JR		 2170 /* Some sanity checks */
2171 ret = -EBUSY;
2172 if (alias_data->domain != NULL &&
2173 alias_data->domain != domain)
2174 goto out_unlock;
eba6ac60 2175
2b02b091
JR		 2176 if (dev_data->domain != NULL &&
2177 dev_data->domain != domain)
2178 goto out_unlock;
15898bbc 2179
2b02b091 2180 /* Do real assignment */
7f760ddd 2181 if (alias_data->domain == NULL)
ec9e79ef 2182 do_attach(alias_data, domain);
24100055
JR		 2183
2184 atomic_inc(&alias_data->bind);
657cbb6b 2185 }
15898bbc 2186
7f760ddd 2187 if (dev_data->domain == NULL)
ec9e79ef 2188 do_attach(dev_data, domain);
eba6ac60 2189
24100055
JR		 2190 atomic_inc(&dev_data->bind);
2191
84fe6c19
JL		 2192 ret = 0;
2193
2194out_unlock:
2195
eba6ac60
JR		 2196 /* ready */
2197 spin_unlock(&domain->lock);
15898bbc 2198
84fe6c19 2199 return ret;
0feae533 2200}
b20ac0d4 2201
52815b75
JR		 2202
2203static void pdev_iommuv2_disable(struct pci_dev *pdev)
2204{
2205 pci_disable_ats(pdev);
2206 pci_disable_pri(pdev);
2207 pci_disable_pasid(pdev);
2208}
2209
6a113ddc
JR		 2210/* FIXME: Change generic reset-function to do the same */
2211static int pri_reset_while_enabled(struct pci_dev *pdev)
2212{
2213 u16 control;
2214 int pos;
2215
46277b75 2216 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
6a113ddc
JR		 2217 if (!pos)
2218 return -EINVAL;
2219
46277b75
JR		 2220 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2221 control |= PCI_PRI_CTRL_RESET;
2222 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
6a113ddc
JR		 2223
2224 return 0;
2225}
2226
52815b75
JR		 2227static int pdev_iommuv2_enable(struct pci_dev *pdev)
2228{
6a113ddc
JR		 2229 bool reset_enable;
2230 int reqs, ret;
2231
2232 /* FIXME: Hardcode number of outstanding requests for now */
2233 reqs = 32;
2234 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2235 reqs = 1;
2236 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
52815b75
JR		 2237
2238 /* Only allow access to user-accessible pages */
2239 ret = pci_enable_pasid(pdev, 0);
2240 if (ret)
2241 goto out_err;
2242
2243 /* First reset the PRI state of the device */
2244 ret = pci_reset_pri(pdev);
2245 if (ret)
2246 goto out_err;
2247
6a113ddc
JR		 2248 /* Enable PRI */
2249 ret = pci_enable_pri(pdev, reqs);
52815b75
JR		 2250 if (ret)
2251 goto out_err;
2252
6a113ddc
JR		 2253 if (reset_enable) {
2254 ret = pri_reset_while_enabled(pdev);
2255 if (ret)
2256 goto out_err;
2257 }
2258
52815b75
JR		 2259 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2260 if (ret)
2261 goto out_err;
2262
2263 return 0;
2264
2265out_err:
2266 pci_disable_pri(pdev);
2267 pci_disable_pasid(pdev);
2268
2269 return ret;
2270}
2271
c99afa25 2272/* FIXME: Move this to PCI code */
a3b93121 2273#define PCI_PRI_TLP_OFF (1 << 15)
c99afa25 2274
98f1ad25 2275static bool pci_pri_tlp_required(struct pci_dev *pdev)
c99afa25 2276{
a3b93121 2277 u16 status;
c99afa25
JR		 2278 int pos;
2279
46277b75 2280 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c99afa25
JR		 2281 if (!pos)
2282 return false;
2283
a3b93121 2284 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
c99afa25 2285
a3b93121 2286 return (status & PCI_PRI_TLP_OFF) ? true : false;
c99afa25
JR		 2287}
2288
407d733e 2289/*
df805abb 2290 * If a device is not yet associated with a domain, this function
407d733e
JR		 2291 * assigns it visible for the hardware
2292 */
15898bbc
JR		 2293static int attach_device(struct device *dev,
2294 struct protection_domain *domain)
0feae533 2295{
fd7b5535 2296 struct pci_dev *pdev = to_pci_dev(dev);
ea61cddb 2297 struct iommu_dev_data *dev_data;
eba6ac60 2298 unsigned long flags;
15898bbc 2299 int ret;
eba6ac60 2300
ea61cddb
JR		 2301 dev_data = get_dev_data(dev);
2302
52815b75
JR		 2303 if (domain->flags & PD_IOMMUV2_MASK) {
2304 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2305 return -EINVAL;
2306
2307 if (pdev_iommuv2_enable(pdev) != 0)
2308 return -EINVAL;
2309
2310 dev_data->ats.enabled = true;
2311 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
c99afa25 2312 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
52815b75
JR		 2313 } else if (amd_iommu_iotlb_sup &&
2314 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2315 dev_data->ats.enabled = true;
2316 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2317 }
fd7b5535 2318
eba6ac60 2319 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2320 ret = __attach_device(dev_data, domain);
b20ac0d4
JR		 2321 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2322
0feae533
JR		 2323 /*
2324 * We might boot into a crash-kernel here. The crashed kernel
2325 * left the caches in the IOMMU dirty. So we have to flush
2326 * here to evict all dirty stuff.
2327 */
17b124bf 2328 domain_flush_tlb_pde(domain);
15898bbc
JR		 2329
2330 return ret;
b20ac0d4
JR		 2331}
2332
355bf553
JR		 2333/*
2334 * Removes a device from a protection domain (unlocked)
2335 */
ec9e79ef 2336static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2337{
2ca76279 2338 struct protection_domain *domain;
7c392cbe 2339 unsigned long flags;
c4596114 2340
7f760ddd 2341 BUG_ON(!dev_data->domain);
355bf553 2342
2ca76279
JR		 2343 domain = dev_data->domain;
2344
2345 spin_lock_irqsave(&domain->lock, flags);
24100055 2346
71f77580
JR		 2347 if (dev_data->alias_data != NULL) {
2348 struct iommu_dev_data *alias_data = dev_data->alias_data;
2349
7f760ddd 2350 if (atomic_dec_and_test(&alias_data->bind))
ec9e79ef 2351 do_detach(alias_data);
24100055
JR		 2352 }
2353
7f760ddd 2354 if (atomic_dec_and_test(&dev_data->bind))
ec9e79ef 2355 do_detach(dev_data);
7f760ddd 2356
2ca76279 2357 spin_unlock_irqrestore(&domain->lock, flags);
21129f78
JR		 2358
2359 /*
2360 * If we run in passthrough mode the device must be assigned to the
d3ad9373
JR		 2361 * passthrough domain if it is detached from any other domain.
2362 * Make sure we can deassign from the pt_domain itself.
21129f78 2363 */
5abcdba4 2364 if (dev_data->passthrough &&
d3ad9373 2365 (dev_data->domain == NULL && domain != pt_domain))
ec9e79ef 2366 __attach_device(dev_data, pt_domain);
355bf553
JR		 2367}
2368
2369/*
2370 * Removes a device from a protection domain (with devtable_lock held)
2371 */
15898bbc 2372static void detach_device(struct device *dev)
355bf553 2373{
52815b75 2374 struct protection_domain *domain;
ea61cddb 2375 struct iommu_dev_data *dev_data;
355bf553
JR		 2376 unsigned long flags;
2377
ec9e79ef 2378 dev_data = get_dev_data(dev);
52815b75 2379 domain = dev_data->domain;
ec9e79ef 2380
355bf553
JR		 2381 /* lock device table */
2382 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2383 __detach_device(dev_data);
355bf553 2384 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2385
52815b75
JR		 2386 if (domain->flags & PD_IOMMUV2_MASK)
2387 pdev_iommuv2_disable(to_pci_dev(dev));
2388 else if (dev_data->ats.enabled)
ea61cddb 2389 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2390
2391 dev_data->ats.enabled = false;
355bf553 2392}
e275a2a0 2393
15898bbc
JR		 2394/*
2395 * Find out the protection domain structure for a given PCI device. This
2396 * will give us the pointer to the page table root for example.
2397 */
2398static struct protection_domain *domain_for_device(struct device *dev)
2399{
71f77580 2400 struct iommu_dev_data *dev_data;
2b02b091 2401 struct protection_domain *dom = NULL;
15898bbc 2402 unsigned long flags;
15898bbc 2403
657cbb6b 2404 dev_data = get_dev_data(dev);
15898bbc 2405
2b02b091
JR		 2406 if (dev_data->domain)
2407 return dev_data->domain;
15898bbc 2408
71f77580
JR		 2409 if (dev_data->alias_data != NULL) {
2410 struct iommu_dev_data *alias_data = dev_data->alias_data;
2b02b091
JR		 2411
2412 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2413 if (alias_data->domain != NULL) {
2414 __attach_device(dev_data, alias_data->domain);
2415 dom = alias_data->domain;
2416 }
2417 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2418 }
15898bbc
JR		 2419
2420 return dom;
2421}
2422
e275a2a0
JR		 2423static int device_change_notifier(struct notifier_block *nb,
2424 unsigned long action, void *data)
2425{
e275a2a0 2426 struct dma_ops_domain *dma_domain;
5abcdba4
JR		 2427 struct protection_domain *domain;
2428 struct iommu_dev_data *dev_data;
2429 struct device *dev = data;
e275a2a0 2430 struct amd_iommu *iommu;
1ac4cbbc 2431 unsigned long flags;
5abcdba4 2432 u16 devid;
e275a2a0 2433
98fc5a69
JR		 2434 if (!check_device(dev))
2435 return 0;
e275a2a0 2436
5abcdba4
JR		 2437 devid = get_device_id(dev);
2438 iommu = amd_iommu_rlookup_table[devid];
2439 dev_data = get_dev_data(dev);
e275a2a0
JR		 2440
2441 switch (action) {
c1eee67b 2442 case BUS_NOTIFY_UNBOUND_DRIVER:
657cbb6b
JR		 2443
2444 domain = domain_for_device(dev);
2445
e275a2a0
JR		 2446 if (!domain)
2447 goto out;
5abcdba4 2448 if (dev_data->passthrough)
a1ca331c 2449 break;
15898bbc 2450 detach_device(dev);
1ac4cbbc
JR		 2451 break;
2452 case BUS_NOTIFY_ADD_DEVICE:
657cbb6b
JR		 2453
2454 iommu_init_device(dev);
2455
2c9195e9
JR		 2456 /*
2457 * dev_data is still NULL and
2458 * got initialized in iommu_init_device
2459 */
2460 dev_data = get_dev_data(dev);
2461
2462 if (iommu_pass_through || dev_data->iommu_v2) {
2463 dev_data->passthrough = true;
2464 attach_device(dev, pt_domain);
2465 break;
2466 }
2467
657cbb6b
JR		 2468 domain = domain_for_device(dev);
2469
1ac4cbbc
JR		 2470 /* allocate a protection domain if a device is added */
2471 dma_domain = find_protection_domain(devid);
c2a2876e
JR		 2472 if (!dma_domain) {
2473 dma_domain = dma_ops_domain_alloc();
2474 if (!dma_domain)
2475 goto out;
2476 dma_domain->target_dev = devid;
2477
2478 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2479 list_add_tail(&dma_domain->list, &iommu_pd_list);
2480 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2481 }
ac1534a5 2482
2c9195e9 2483 dev->archdata.dma_ops = &amd_iommu_dma_ops;
ac1534a5 2484
e275a2a0 2485 break;
657cbb6b
JR		 2486 case BUS_NOTIFY_DEL_DEVICE:
2487
2488 iommu_uninit_device(dev);
2489
e275a2a0
JR		 2490 default:
2491 goto out;
2492 }
2493
e275a2a0
JR		 2494 iommu_completion_wait(iommu);
2495
2496out:
2497 return 0;
2498}
2499
b25ae679 2500static struct notifier_block device_nb = {
e275a2a0
JR		 2501 .notifier_call = device_change_notifier,
2502};
355bf553 2503
8638c491
JR		 2504void amd_iommu_init_notifier(void)
2505{
2506 bus_register_notifier(&pci_bus_type, &device_nb);
2507}
2508
431b2a20
JR		 2509/*****************************************************************************
2510 *
2511 * The next functions belong to the dma_ops mapping/unmapping code.
2512 *
2513 *****************************************************************************/
2514
2515/*
2516 * In the dma_ops path we only have the struct device. This function
2517 * finds the corresponding IOMMU, the protection domain and the
2518 * requestor id for a given device.
2519 * If the device is not yet associated with a domain this is also done
2520 * in this function.
2521 */
94f6d190 2522static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2523{
94f6d190 2524 struct protection_domain *domain;
b20ac0d4 2525 struct dma_ops_domain *dma_dom;
94f6d190 2526 u16 devid = get_device_id(dev);
b20ac0d4 2527
f99c0f1c 2528 if (!check_device(dev))
94f6d190 2529 return ERR_PTR(-EINVAL);
b20ac0d4 2530
94f6d190
JR		 2531 domain = domain_for_device(dev);
2532 if (domain != NULL && !dma_ops_domain(domain))
2533 return ERR_PTR(-EBUSY);
f99c0f1c 2534
94f6d190
JR		 2535 if (domain != NULL)
2536 return domain;
b20ac0d4 2537
df805abb 2538 /* Device not bound yet - bind it */
94f6d190 2539 dma_dom = find_protection_domain(devid);
15898bbc 2540 if (!dma_dom)
94f6d190
JR		 2541 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2542 attach_device(dev, &dma_dom->domain);
15898bbc 2543 DUMP_printk("Using protection domain %d for device %s\n",
94f6d190 2544 dma_dom->domain.id, dev_name(dev));
f91ba190 2545
94f6d190 2546 return &dma_dom->domain;
b20ac0d4
JR		 2547}
2548
04bfdd84
JR		 2549static void update_device_table(struct protection_domain *domain)
2550{
492667da 2551 struct iommu_dev_data *dev_data;
04bfdd84 2552
ea61cddb
JR		 2553 list_for_each_entry(dev_data, &domain->dev_list, list)
2554 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
04bfdd84
JR		 2555}
2556
2557static void update_domain(struct protection_domain *domain)
2558{
2559 if (!domain->updated)
2560 return;
2561
2562 update_device_table(domain);
17b124bf
JR		 2563
2564 domain_flush_devices(domain);
2565 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2566
2567 domain->updated = false;
2568}
2569
8bda3092
JR		 2570/*
2571 * This function fetches the PTE for a given address in the aperture
2572 */
2573static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2574 unsigned long address)
2575{
384de729 2576 struct aperture_range *aperture;
8bda3092
JR		 2577 u64 *pte, *pte_page;
2578
384de729
JR		 2579 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2580 if (!aperture)
2581 return NULL;
2582
2583 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
8bda3092 2584 if (!pte) {
cbb9d729 2585 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
abdc5eb3 2586 GFP_ATOMIC);
384de729
JR		 2587 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2588 } else
8c8c143c 2589 pte += PM_LEVEL_INDEX(0, address);
8bda3092 2590
04bfdd84 2591 update_domain(&dom->domain);
8bda3092
JR		 2592
2593 return pte;
2594}
2595
431b2a20
JR		 2596/*
2597 * This is the generic map function. It maps one 4kb page at paddr to
2598 * the given address in the DMA address space for the domain.
2599 */
680525e0 2600static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
cb76c322
JR		 2601 unsigned long address,
2602 phys_addr_t paddr,
2603 int direction)
2604{
2605 u64 *pte, __pte;
2606
2607 WARN_ON(address > dom->aperture_size);
2608
2609 paddr &= PAGE_MASK;
2610
8bda3092 2611 pte = dma_ops_get_pte(dom, address);
53812c11 2612 if (!pte)
8fd524b3 2613 return DMA_ERROR_CODE;
cb76c322
JR		 2614
2615 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2616
2617 if (direction == DMA_TO_DEVICE)
2618 __pte |= IOMMU_PTE_IR;
2619 else if (direction == DMA_FROM_DEVICE)
2620 __pte |= IOMMU_PTE_IW;
2621 else if (direction == DMA_BIDIRECTIONAL)
2622 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2623
2624 WARN_ON(*pte);
2625
2626 *pte = __pte;
2627
2628 return (dma_addr_t)address;
2629}
2630
431b2a20
JR		 2631/*
2632 * The generic unmapping function for on page in the DMA address space.
2633 */
680525e0 2634static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
cb76c322
JR		 2635 unsigned long address)
2636{
384de729 2637 struct aperture_range *aperture;
cb76c322
JR		 2638 u64 *pte;
2639
2640 if (address >= dom->aperture_size)
2641 return;
2642
384de729
JR		 2643 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2644 if (!aperture)
2645 return;
2646
2647 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2648 if (!pte)
2649 return;
cb76c322 2650
8c8c143c 2651 pte += PM_LEVEL_INDEX(0, address);
cb76c322
JR		 2652
2653 WARN_ON(!*pte);
2654
2655 *pte = 0ULL;
2656}
2657
431b2a20
JR		 2658/*
2659 * This function contains common code for mapping of a physically
24f81160
JR		 2660 * contiguous memory region into DMA address space. It is used by all
2661 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2662 * Must be called with the domain lock held.
2663 */
cb76c322 2664static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2665 struct dma_ops_domain *dma_dom,
2666 phys_addr_t paddr,
2667 size_t size,
6d4f343f 2668 int dir,
832a90c3
JR		 2669 bool align,
2670 u64 dma_mask)
cb76c322
JR		 2671{
2672 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2673 dma_addr_t address, start, ret;
cb76c322 2674 unsigned int pages;
6d4f343f 2675 unsigned long align_mask = 0;
cb76c322
JR		 2676 int i;
2677
e3c449f5 2678 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2679 paddr &= PAGE_MASK;
2680
8ecaf8f1
JR		 2681 INC_STATS_COUNTER(total_map_requests);
2682
c1858976
JR		 2683 if (pages > 1)
2684 INC_STATS_COUNTER(cross_page);
2685
6d4f343f
JR		 2686 if (align)
2687 align_mask = (1UL << get_order(size)) - 1;
2688
11b83888 2689retry:
832a90c3
JR		 2690 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2691 dma_mask);
8fd524b3 2692 if (unlikely(address == DMA_ERROR_CODE)) {
11b83888
JR		 2693 /*
2694 * setting next_address here will let the address
2695 * allocator only scan the new allocated range in the
2696 * first run. This is a small optimization.
2697 */
2698 dma_dom->next_address = dma_dom->aperture_size;
2699
576175c2 2700 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
11b83888
JR		 2701 goto out;
2702
2703 /*
af901ca1 2704 * aperture was successfully enlarged by 128 MB, try
11b83888
JR		 2705 * allocation again
2706 */
2707 goto retry;
2708 }
cb76c322
JR		 2709
2710 start = address;
2711 for (i = 0; i < pages; ++i) {
680525e0 2712 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
8fd524b3 2713 if (ret == DMA_ERROR_CODE)
53812c11
JR		 2714 goto out_unmap;
2715
cb76c322
JR		 2716 paddr += PAGE_SIZE;
2717 start += PAGE_SIZE;
2718 }
2719 address += offset;
2720
5774f7c5
JR		 2721 ADD_STATS_COUNTER(alloced_io_mem, size);
2722
afa9fdc2 2723 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
17b124bf 2724 domain_flush_tlb(&dma_dom->domain);
1c655773 2725 dma_dom->need_flush = false;
318afd41 2726 } else if (unlikely(amd_iommu_np_cache))
17b124bf 2727 domain_flush_pages(&dma_dom->domain, address, size);
270cab24 2728
cb76c322
JR		 2729out:
2730 return address;
53812c11
JR		 2731
2732out_unmap:
2733
2734 for (--i; i >= 0; --i) {
2735 start -= PAGE_SIZE;
680525e0 2736 dma_ops_domain_unmap(dma_dom, start);
53812c11
JR		 2737 }
2738
2739 dma_ops_free_addresses(dma_dom, address, pages);
2740
8fd524b3 2741 return DMA_ERROR_CODE;
cb76c322
JR		 2742}
2743
431b2a20
JR		 2744/*
2745 * Does the reverse of the __map_single function. Must be called with
2746 * the domain lock held too
2747 */
cd8c82e8 2748static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2749 dma_addr_t dma_addr,
2750 size_t size,
2751 int dir)
2752{
04e0463e 2753 dma_addr_t flush_addr;
cb76c322
JR		 2754 dma_addr_t i, start;
2755 unsigned int pages;
2756
8fd524b3 2757 if ((dma_addr == DMA_ERROR_CODE) ||
b8d9905d 2758 (dma_addr + size > dma_dom->aperture_size))
cb76c322
JR		 2759 return;
2760
04e0463e 2761 flush_addr = dma_addr;
e3c449f5 2762 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2763 dma_addr &= PAGE_MASK;
2764 start = dma_addr;
2765
2766 for (i = 0; i < pages; ++i) {
680525e0 2767 dma_ops_domain_unmap(dma_dom, start);
cb76c322
JR		 2768 start += PAGE_SIZE;
2769 }
2770
5774f7c5
JR		 2771 SUB_STATS_COUNTER(alloced_io_mem, size);
2772
cb76c322 2773 dma_ops_free_addresses(dma_dom, dma_addr, pages);
270cab24 2774
80be308d 2775 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
17b124bf 2776 domain_flush_pages(&dma_dom->domain, flush_addr, size);
80be308d
JR		 2777 dma_dom->need_flush = false;
2778 }
cb76c322
JR		 2779}
2780
431b2a20
JR		 2781/*
2782 * The exported map_single function for dma_ops.
2783 */
51491367
FT		 2784static dma_addr_t map_page(struct device *dev, struct page *page,
2785 unsigned long offset, size_t size,
2786 enum dma_data_direction dir,
2787 struct dma_attrs *attrs)
4da70b9e
JR		 2788{
2789 unsigned long flags;
4da70b9e 2790 struct protection_domain *domain;
4da70b9e 2791 dma_addr_t addr;
832a90c3 2792 u64 dma_mask;
51491367 2793 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2794
0f2a86f2
JR		 2795 INC_STATS_COUNTER(cnt_map_single);
2796
94f6d190
JR		 2797 domain = get_domain(dev);
2798 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2799 return (dma_addr_t)paddr;
94f6d190
JR		 2800 else if (IS_ERR(domain))
2801 return DMA_ERROR_CODE;
4da70b9e 2802
f99c0f1c
JR		 2803 dma_mask = *dev->dma_mask;
2804
4da70b9e 2805 spin_lock_irqsave(&domain->lock, flags);
94f6d190 2806
cd8c82e8 2807 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
832a90c3 2808 dma_mask);
8fd524b3 2809 if (addr == DMA_ERROR_CODE)
4da70b9e
JR		 2810 goto out;
2811
17b124bf 2812 domain_flush_complete(domain);
4da70b9e
JR		 2813
2814out:
2815 spin_unlock_irqrestore(&domain->lock, flags);
2816
2817 return addr;
2818}
2819
431b2a20
JR		 2820/*
2821 * The exported unmap_single function for dma_ops.
2822 */
51491367
FT		 2823static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2824 enum dma_data_direction dir, struct dma_attrs *attrs)
4da70b9e
JR		 2825{
2826 unsigned long flags;
4da70b9e 2827 struct protection_domain *domain;
4da70b9e 2828
146a6917
JR		 2829 INC_STATS_COUNTER(cnt_unmap_single);
2830
94f6d190
JR		 2831 domain = get_domain(dev);
2832 if (IS_ERR(domain))
5b28df6f
JR		 2833 return;
2834
4da70b9e
JR		 2835 spin_lock_irqsave(&domain->lock, flags);
2836
cd8c82e8 2837 __unmap_single(domain->priv, dma_addr, size, dir);
4da70b9e 2838
17b124bf 2839 domain_flush_complete(domain);
4da70b9e
JR		 2840
2841 spin_unlock_irqrestore(&domain->lock, flags);
2842}
2843
431b2a20
JR		 2844/*
2845 * This is a special map_sg function which is used if we should map a
2846 * device which is not handled by an AMD IOMMU in the system.
2847 */
65b050ad
JR		 2848static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2849 int nelems, int dir)
2850{
2851 struct scatterlist *s;
2852 int i;
2853
2854 for_each_sg(sglist, s, nelems, i) {
2855 s->dma_address = (dma_addr_t)sg_phys(s);
2856 s->dma_length = s->length;
2857 }
2858
2859 return nelems;
2860}
2861
431b2a20
JR		 2862/*
2863 * The exported map_sg function for dma_ops (handles scatter-gather
2864 * lists).
2865 */
65b050ad 2866static int map_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2867 int nelems, enum dma_data_direction dir,
2868 struct dma_attrs *attrs)
65b050ad
JR		 2869{
2870 unsigned long flags;
65b050ad 2871 struct protection_domain *domain;
65b050ad
JR		 2872 int i;
2873 struct scatterlist *s;
2874 phys_addr_t paddr;
2875 int mapped_elems = 0;
832a90c3 2876 u64 dma_mask;
65b050ad 2877
d03f067a
JR		 2878 INC_STATS_COUNTER(cnt_map_sg);
2879
94f6d190
JR		 2880 domain = get_domain(dev);
2881 if (PTR_ERR(domain) == -EINVAL)
f99c0f1c 2882 return map_sg_no_iommu(dev, sglist, nelems, dir);
94f6d190
JR		 2883 else if (IS_ERR(domain))
2884 return 0;
dbcc112e 2885
832a90c3 2886 dma_mask = *dev->dma_mask;
65b050ad 2887
65b050ad
JR		 2888 spin_lock_irqsave(&domain->lock, flags);
2889
2890 for_each_sg(sglist, s, nelems, i) {
2891 paddr = sg_phys(s);
2892
cd8c82e8 2893 s->dma_address = __map_single(dev, domain->priv,
832a90c3
JR		 2894 paddr, s->length, dir, false,
2895 dma_mask);
65b050ad
JR		 2896
2897 if (s->dma_address) {
2898 s->dma_length = s->length;
2899 mapped_elems++;
2900 } else
2901 goto unmap;
65b050ad
JR		 2902 }
2903
17b124bf 2904 domain_flush_complete(domain);
65b050ad
JR		 2905
2906out:
2907 spin_unlock_irqrestore(&domain->lock, flags);
2908
2909 return mapped_elems;
2910unmap:
2911 for_each_sg(sglist, s, mapped_elems, i) {
2912 if (s->dma_address)
cd8c82e8 2913 __unmap_single(domain->priv, s->dma_address,
65b050ad
JR		 2914 s->dma_length, dir);
2915 s->dma_address = s->dma_length = 0;
2916 }
2917
2918 mapped_elems = 0;
2919
2920 goto out;
2921}
2922
431b2a20
JR		 2923/*
2924 * The exported map_sg function for dma_ops (handles scatter-gather
2925 * lists).
2926 */
65b050ad 2927static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2928 int nelems, enum dma_data_direction dir,
2929 struct dma_attrs *attrs)
65b050ad
JR		 2930{
2931 unsigned long flags;
65b050ad
JR		 2932 struct protection_domain *domain;
2933 struct scatterlist *s;
65b050ad
JR		 2934 int i;
2935
55877a6b
JR		 2936 INC_STATS_COUNTER(cnt_unmap_sg);
2937
94f6d190
JR		 2938 domain = get_domain(dev);
2939 if (IS_ERR(domain))
5b28df6f
JR		 2940 return;
2941
65b050ad
JR		 2942 spin_lock_irqsave(&domain->lock, flags);
2943
2944 for_each_sg(sglist, s, nelems, i) {
cd8c82e8 2945 __unmap_single(domain->priv, s->dma_address,
65b050ad 2946 s->dma_length, dir);
65b050ad
JR		 2947 s->dma_address = s->dma_length = 0;
2948 }
2949
17b124bf 2950 domain_flush_complete(domain);
65b050ad
JR		 2951
2952 spin_unlock_irqrestore(&domain->lock, flags);
2953}
2954
431b2a20
JR		 2955/*
2956 * The exported alloc_coherent function for dma_ops.
2957 */
5d8b53cf 2958static void *alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 2959 dma_addr_t *dma_addr, gfp_t flag,
2960 struct dma_attrs *attrs)
5d8b53cf
JR		 2961{
2962 unsigned long flags;
2963 void *virt_addr;
5d8b53cf 2964 struct protection_domain *domain;
5d8b53cf 2965 phys_addr_t paddr;
832a90c3 2966 u64 dma_mask = dev->coherent_dma_mask;
5d8b53cf 2967
c8f0fb36
JR		 2968 INC_STATS_COUNTER(cnt_alloc_coherent);
2969
94f6d190
JR		 2970 domain = get_domain(dev);
2971 if (PTR_ERR(domain) == -EINVAL) {
f99c0f1c
JR		 2972 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2973 *dma_addr = __pa(virt_addr);
2974 return virt_addr;
94f6d190
JR		 2975 } else if (IS_ERR(domain))
2976 return NULL;
5d8b53cf 2977
f99c0f1c
JR		 2978 dma_mask = dev->coherent_dma_mask;
2979 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2980 flag |= __GFP_ZERO;
5d8b53cf
JR		 2981
2982 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2983 if (!virt_addr)
b25ae679 2984 return NULL;
5d8b53cf 2985
5d8b53cf
JR		 2986 paddr = virt_to_phys(virt_addr);
2987
832a90c3
JR		 2988 if (!dma_mask)
2989 dma_mask = *dev->dma_mask;
2990
5d8b53cf
JR		 2991 spin_lock_irqsave(&domain->lock, flags);
2992
cd8c82e8 2993 *dma_addr = __map_single(dev, domain->priv, paddr,
832a90c3 2994 size, DMA_BIDIRECTIONAL, true, dma_mask);
5d8b53cf 2995
8fd524b3 2996 if (*dma_addr == DMA_ERROR_CODE) {
367d04c4 2997 spin_unlock_irqrestore(&domain->lock, flags);
5b28df6f 2998 goto out_free;
367d04c4 2999 }
5d8b53cf 3000
17b124bf 3001 domain_flush_complete(domain);
5d8b53cf 3002
5d8b53cf
JR		 3003 spin_unlock_irqrestore(&domain->lock, flags);
3004
3005 return virt_addr;
5b28df6f
JR		 3006
3007out_free:
3008
3009 free_pages((unsigned long)virt_addr, get_order(size));
3010
3011 return NULL;
5d8b53cf
JR		 3012}
3013
431b2a20
JR		 3014/*
3015 * The exported free_coherent function for dma_ops.
431b2a20 3016 */
5d8b53cf 3017static void free_coherent(struct device *dev, size_t size,
baa676fc
AP		 3018 void *virt_addr, dma_addr_t dma_addr,
3019 struct dma_attrs *attrs)
5d8b53cf
JR		 3020{
3021 unsigned long flags;
5d8b53cf 3022 struct protection_domain *domain;
5d8b53cf 3023
5d31ee7e
JR		 3024 INC_STATS_COUNTER(cnt_free_coherent);
3025
94f6d190
JR		 3026 domain = get_domain(dev);
3027 if (IS_ERR(domain))
5b28df6f
JR		 3028 goto free_mem;
3029
5d8b53cf
JR		 3030 spin_lock_irqsave(&domain->lock, flags);
3031
cd8c82e8 3032 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 3033
17b124bf 3034 domain_flush_complete(domain);
5d8b53cf
JR		 3035
3036 spin_unlock_irqrestore(&domain->lock, flags);
3037
3038free_mem:
3039 free_pages((unsigned long)virt_addr, get_order(size));
3040}
3041
b39ba6ad
JR		 3042/*
3043 * This function is called by the DMA layer to find out if we can handle a
3044 * particular device. It is part of the dma_ops.
3045 */
3046static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3047{
420aef8a 3048 return check_device(dev);
b39ba6ad
JR		 3049}
3050
c432f3df 3051/*
431b2a20
JR		 3052 * The function for pre-allocating protection domains.
3053 *
c432f3df
JR		 3054 * If the driver core informs the DMA layer if a driver grabs a device
3055 * we don't need to preallocate the protection domains anymore.
3056 * For now we have to.
3057 */
943bc7e1 3058static void __init prealloc_protection_domains(void)
c432f3df 3059{
5abcdba4 3060 struct iommu_dev_data *dev_data;
c432f3df 3061 struct dma_ops_domain *dma_dom;
5abcdba4 3062 struct pci_dev *dev = NULL;
98fc5a69 3063 u16 devid;
c432f3df 3064
d18c69d3 3065 for_each_pci_dev(dev) {
98fc5a69
JR		 3066
3067 /* Do we handle this device? */
3068 if (!check_device(&dev->dev))
c432f3df 3069 continue;
98fc5a69 3070
5abcdba4
JR		 3071 dev_data = get_dev_data(&dev->dev);
3072 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3073 /* Make sure passthrough domain is allocated */
3074 alloc_passthrough_domain();
3075 dev_data->passthrough = true;
3076 attach_device(&dev->dev, pt_domain);
df805abb 3077 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
5abcdba4
JR		 3078 dev_name(&dev->dev));
3079 }
3080
98fc5a69 3081 /* Is there already any domain for it? */
15898bbc 3082 if (domain_for_device(&dev->dev))
c432f3df 3083 continue;
98fc5a69
JR		 3084
3085 devid = get_device_id(&dev->dev);
3086
87a64d52 3087 dma_dom = dma_ops_domain_alloc();
c432f3df
JR		 3088 if (!dma_dom)
3089 continue;
3090 init_unity_mappings_for_device(dma_dom, devid);
bd60b735
JR		 3091 dma_dom->target_dev = devid;
3092
15898bbc 3093 attach_device(&dev->dev, &dma_dom->domain);
be831297 3094
bd60b735 3095 list_add_tail(&dma_dom->list, &iommu_pd_list);
c432f3df
JR		 3096 }
3097}
3098
160c1d8e 3099static struct dma_map_ops amd_iommu_dma_ops = {
baa676fc
AP		 3100 .alloc = alloc_coherent,
3101 .free = free_coherent,
51491367
FT		 3102 .map_page = map_page,
3103 .unmap_page = unmap_page,
6631ee9d
JR		 3104 .map_sg = map_sg,
3105 .unmap_sg = unmap_sg,
b39ba6ad 3106 .dma_supported = amd_iommu_dma_supported,
6631ee9d
JR		 3107};
3108
27c2127a
JR		 3109static unsigned device_dma_ops_init(void)
3110{
5abcdba4 3111 struct iommu_dev_data *dev_data;
27c2127a
JR		 3112 struct pci_dev *pdev = NULL;
3113 unsigned unhandled = 0;
3114
3115 for_each_pci_dev(pdev) {
3116 if (!check_device(&pdev->dev)) {
af1be049
JR		 3117
3118 iommu_ignore_device(&pdev->dev);
3119
27c2127a
JR		 3120 unhandled += 1;
3121 continue;
3122 }
3123
5abcdba4
JR		 3124 dev_data = get_dev_data(&pdev->dev);
3125
3126 if (!dev_data->passthrough)
3127 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3128 else
3129 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
27c2127a
JR		 3130 }
3131
3132 return unhandled;
3133}
3134
431b2a20
JR		 3135/*
3136 * The function which clues the AMD IOMMU driver into dma_ops.
3137 */
f5325094
JR		 3138
3139void __init amd_iommu_init_api(void)
3140{
2cc21c42 3141 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
f5325094
JR		 3142}
3143
6631ee9d
JR		 3144int __init amd_iommu_init_dma_ops(void)
3145{
3146 struct amd_iommu *iommu;
27c2127a 3147 int ret, unhandled;
6631ee9d 3148
431b2a20
JR		 3149 /*
3150 * first allocate a default protection domain for every IOMMU we
3151 * found in the system. Devices not assigned to any other
3152 * protection domain will be assigned to the default one.
3153 */
3bd22172 3154 for_each_iommu(iommu) {
87a64d52 3155 iommu->default_dom = dma_ops_domain_alloc();
6631ee9d
JR		 3156 if (iommu->default_dom == NULL)
3157 return -ENOMEM;
e2dc14a2 3158 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
6631ee9d
JR		 3159 ret = iommu_init_unity_mappings(iommu);
3160 if (ret)
3161 goto free_domains;
3162 }
3163
431b2a20 3164 /*
8793abeb 3165 * Pre-allocate the protection domains for each device.
431b2a20 3166 */
8793abeb 3167 prealloc_protection_domains();
6631ee9d
JR		 3168
3169 iommu_detected = 1;
75f1cdf1 3170 swiotlb = 0;
6631ee9d 3171
431b2a20 3172 /* Make the driver finally visible to the drivers */
27c2127a
JR		 3173 unhandled = device_dma_ops_init();
3174 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3175 /* There are unhandled devices - initialize swiotlb for them */
3176 swiotlb = 1;
3177 }
6631ee9d 3178
7f26508b
JR		 3179 amd_iommu_stats_init();
3180
62410eeb
JR		 3181 if (amd_iommu_unmap_flush)
3182 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3183 else
3184 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3185
6631ee9d
JR		 3186 return 0;
3187
3188free_domains:
3189
3bd22172 3190 for_each_iommu(iommu) {
91457df7 3191 dma_ops_domain_free(iommu->default_dom);
6631ee9d
JR		 3192 }
3193
3194 return ret;
3195}
6d98cd80
JR		 3196
3197/*****************************************************************************
3198 *
3199 * The following functions belong to the exported interface of AMD IOMMU
3200 *
3201 * This interface allows access to lower level functions of the IOMMU
3202 * like protection domain handling and assignement of devices to domains
3203 * which is not possible with the dma_ops interface.
3204 *
3205 *****************************************************************************/
3206
6d98cd80
JR		 3207static void cleanup_domain(struct protection_domain *domain)
3208{
492667da 3209 struct iommu_dev_data *dev_data, *next;
6d98cd80 3210 unsigned long flags;
6d98cd80
JR		 3211
3212 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3213
492667da 3214 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
ec9e79ef 3215 __detach_device(dev_data);
492667da
JR		 3216 atomic_set(&dev_data->bind, 0);
3217 }
6d98cd80
JR		 3218
3219 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3220}
3221
2650815f
JR		 3222static void protection_domain_free(struct protection_domain *domain)
3223{
3224 if (!domain)
3225 return;
3226
aeb26f55
JR		 3227 del_domain_from_list(domain);
3228
2650815f
JR		 3229 if (domain->id)
3230 domain_id_free(domain->id);
3231
3232 kfree(domain);
3233}
3234
3235static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 3236{
3237 struct protection_domain *domain;
3238
3239 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3240 if (!domain)
2650815f 3241 return NULL;
c156e347
JR		 3242
3243 spin_lock_init(&domain->lock);
5d214fe6 3244 mutex_init(&domain->api_lock);
c156e347
JR		 3245 domain->id = domain_id_alloc();
3246 if (!domain->id)
2650815f 3247 goto out_err;
7c392cbe 3248 INIT_LIST_HEAD(&domain->dev_list);
2650815f 3249
aeb26f55
JR		 3250 add_domain_to_list(domain);
3251
2650815f
JR		 3252 return domain;
3253
3254out_err:
3255 kfree(domain);
3256
3257 return NULL;
3258}
3259
5abcdba4
JR		 3260static int __init alloc_passthrough_domain(void)
3261{
3262 if (pt_domain != NULL)
3263 return 0;
3264
3265 /* allocate passthrough domain */
3266 pt_domain = protection_domain_alloc();
3267 if (!pt_domain)
3268 return -ENOMEM;
3269
3270 pt_domain->mode = PAGE_MODE_NONE;
3271
3272 return 0;
3273}
2650815f
JR		 3274static int amd_iommu_domain_init(struct iommu_domain *dom)
3275{
3276 struct protection_domain *domain;
3277
3278 domain = protection_domain_alloc();
3279 if (!domain)
c156e347 3280 goto out_free;
2650815f
JR		 3281
3282 domain->mode = PAGE_MODE_3_LEVEL;
c156e347
JR		 3283 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3284 if (!domain->pt_root)
3285 goto out_free;
3286
f3572db8
JR		 3287 domain->iommu_domain = dom;
3288
c156e347
JR		 3289 dom->priv = domain;
3290
0ff64f80
JR		 3291 dom->geometry.aperture_start = 0;
3292 dom->geometry.aperture_end = ~0ULL;
3293 dom->geometry.force_aperture = true;
3294
c156e347
JR		 3295 return 0;
3296
3297out_free:
2650815f 3298 protection_domain_free(domain);
c156e347
JR		 3299
3300 return -ENOMEM;
3301}
3302
98383fc3
JR		 3303static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3304{
3305 struct protection_domain *domain = dom->priv;
3306
3307 if (!domain)
3308 return;
3309
3310 if (domain->dev_cnt > 0)
3311 cleanup_domain(domain);
3312
3313 BUG_ON(domain->dev_cnt != 0);
3314
132bd68f
JR		 3315 if (domain->mode != PAGE_MODE_NONE)
3316 free_pagetable(domain);
98383fc3 3317
52815b75
JR		 3318 if (domain->flags & PD_IOMMUV2_MASK)
3319 free_gcr3_table(domain);
3320
8b408fe4 3321 protection_domain_free(domain);
98383fc3
JR		 3322
3323 dom->priv = NULL;
3324}
3325
684f2888
JR		 3326static void amd_iommu_detach_device(struct iommu_domain *dom,
3327 struct device *dev)
3328{
657cbb6b 3329 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 3330 struct amd_iommu *iommu;
684f2888
JR		 3331 u16 devid;
3332
98fc5a69 3333 if (!check_device(dev))
684f2888
JR		 3334 return;
3335
98fc5a69 3336 devid = get_device_id(dev);
684f2888 3337
657cbb6b 3338 if (dev_data->domain != NULL)
15898bbc 3339 detach_device(dev);
684f2888
JR		 3340
3341 iommu = amd_iommu_rlookup_table[devid];
3342 if (!iommu)
3343 return;
3344
684f2888
JR		 3345 iommu_completion_wait(iommu);
3346}
3347
01106066
JR		 3348static int amd_iommu_attach_device(struct iommu_domain *dom,
3349 struct device *dev)
3350{
3351 struct protection_domain *domain = dom->priv;
657cbb6b 3352 struct iommu_dev_data *dev_data;
01106066 3353 struct amd_iommu *iommu;
15898bbc 3354 int ret;
01106066 3355
98fc5a69 3356 if (!check_device(dev))
01106066
JR		 3357 return -EINVAL;
3358
657cbb6b
JR		 3359 dev_data = dev->archdata.iommu;
3360
f62dda66 3361 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 3362 if (!iommu)
3363 return -EINVAL;
3364
657cbb6b 3365 if (dev_data->domain)
15898bbc 3366 detach_device(dev);
01106066 3367
15898bbc 3368 ret = attach_device(dev, domain);
01106066
JR		 3369
3370 iommu_completion_wait(iommu);
3371
15898bbc 3372 return ret;
01106066
JR		 3373}
3374
468e2366 3375static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
5009065d 3376 phys_addr_t paddr, size_t page_size, int iommu_prot)
c6229ca6
JR		 3377{
3378 struct protection_domain *domain = dom->priv;
c6229ca6
JR		 3379 int prot = 0;
3380 int ret;
3381
132bd68f
JR		 3382 if (domain->mode == PAGE_MODE_NONE)
3383 return -EINVAL;
3384
c6229ca6
JR		 3385 if (iommu_prot & IOMMU_READ)
3386 prot |= IOMMU_PROT_IR;
3387 if (iommu_prot & IOMMU_WRITE)
3388 prot |= IOMMU_PROT_IW;
3389
5d214fe6 3390 mutex_lock(&domain->api_lock);
795e74f7 3391 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
5d214fe6
JR		 3392 mutex_unlock(&domain->api_lock);
3393
795e74f7 3394 return ret;
c6229ca6
JR		 3395}
3396
5009065d
OBC		 3397static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3398 size_t page_size)
eb74ff6c 3399{
eb74ff6c 3400 struct protection_domain *domain = dom->priv;
5009065d 3401 size_t unmap_size;
eb74ff6c 3402
132bd68f
JR		 3403 if (domain->mode == PAGE_MODE_NONE)
3404 return -EINVAL;
3405
5d214fe6 3406 mutex_lock(&domain->api_lock);
468e2366 3407 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3408 mutex_unlock(&domain->api_lock);
eb74ff6c 3409
17b124bf 3410 domain_flush_tlb_pde(domain);
5d214fe6 3411
5009065d 3412 return unmap_size;
eb74ff6c
JR		 3413}
3414
645c4c8d
JR		 3415static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3416 unsigned long iova)
3417{
3418 struct protection_domain *domain = dom->priv;
f03152bb 3419 unsigned long offset_mask;
645c4c8d 3420 phys_addr_t paddr;
f03152bb 3421 u64 *pte, __pte;
645c4c8d 3422
132bd68f
JR		 3423 if (domain->mode == PAGE_MODE_NONE)
3424 return iova;
3425
24cd7723 3426 pte = fetch_pte(domain, iova);
645c4c8d 3427
a6d41a40 3428 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3429 return 0;
3430
f03152bb
JR		 3431 if (PM_PTE_LEVEL(*pte) == 0)
3432 offset_mask = PAGE_SIZE - 1;
3433 else
3434 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3435
3436 __pte = *pte & PM_ADDR_MASK;
3437 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3438
3439 return paddr;
3440}
3441
dbb9fd86
SY		 3442static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3443 unsigned long cap)
3444{
80a506b8
JR		 3445 switch (cap) {
3446 case IOMMU_CAP_CACHE_COHERENCY:
3447 return 1;
bdddadcb
JR		 3448 case IOMMU_CAP_INTR_REMAP:
3449 return irq_remapping_enabled;
80a506b8
JR		 3450 }
3451
dbb9fd86
SY		 3452 return 0;
3453}
3454
26961efe
JR		 3455static struct iommu_ops amd_iommu_ops = {
3456 .domain_init = amd_iommu_domain_init,
3457 .domain_destroy = amd_iommu_domain_destroy,
3458 .attach_dev = amd_iommu_attach_device,
3459 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3460 .map = amd_iommu_map,
3461 .unmap = amd_iommu_unmap,
26961efe 3462 .iova_to_phys = amd_iommu_iova_to_phys,
dbb9fd86 3463 .domain_has_cap = amd_iommu_domain_has_cap,
aa3de9c0 3464 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
26961efe
JR		 3465};
3466
0feae533
JR		 3467/*****************************************************************************
3468 *
3469 * The next functions do a basic initialization of IOMMU for pass through
3470 * mode
3471 *
3472 * In passthrough mode the IOMMU is initialized and enabled but not used for
3473 * DMA-API translation.
3474 *
3475 *****************************************************************************/
3476
3477int __init amd_iommu_init_passthrough(void)
3478{
5abcdba4 3479 struct iommu_dev_data *dev_data;
0feae533 3480 struct pci_dev *dev = NULL;
5abcdba4 3481 struct amd_iommu *iommu;
15898bbc 3482 u16 devid;
5abcdba4 3483 int ret;
0feae533 3484
5abcdba4
JR		 3485 ret = alloc_passthrough_domain();
3486 if (ret)
3487 return ret;
0feae533 3488
6c54aabd 3489 for_each_pci_dev(dev) {
98fc5a69 3490 if (!check_device(&dev->dev))
0feae533
JR		 3491 continue;
3492
5abcdba4
JR		 3493 dev_data = get_dev_data(&dev->dev);
3494 dev_data->passthrough = true;
3495
98fc5a69
JR		 3496 devid = get_device_id(&dev->dev);
3497
15898bbc 3498 iommu = amd_iommu_rlookup_table[devid];
0feae533
JR		 3499 if (!iommu)
3500 continue;
3501
15898bbc 3502 attach_device(&dev->dev, pt_domain);
0feae533
JR		 3503 }
3504
2655d7a2
JR		 3505 amd_iommu_stats_init();
3506
0feae533
JR		 3507 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3508
3509 return 0;
3510}
72e1dcc4
JR		 3511
3512/* IOMMUv2 specific functions */
3513int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3514{
3515 return atomic_notifier_chain_register(&ppr_notifier, nb);
3516}
3517EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3518
3519int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3520{
3521 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3522}
3523EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3524
3525void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3526{
3527 struct protection_domain *domain = dom->priv;
3528 unsigned long flags;
3529
3530 spin_lock_irqsave(&domain->lock, flags);
3531
3532 /* Update data structure */
3533 domain->mode = PAGE_MODE_NONE;
3534 domain->updated = true;
3535
3536 /* Make changes visible to IOMMUs */
3537 update_domain(domain);
3538
3539 /* Page-table is not visible to IOMMU anymore, so free it */
3540 free_pagetable(domain);
3541
3542 spin_unlock_irqrestore(&domain->lock, flags);
3543}
3544EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3545
3546int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3547{
3548 struct protection_domain *domain = dom->priv;
3549 unsigned long flags;
3550 int levels, ret;
3551
3552 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3553 return -EINVAL;
3554
3555 /* Number of GCR3 table levels required */
3556 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3557 levels += 1;
3558
3559 if (levels > amd_iommu_max_glx_val)
3560 return -EINVAL;
3561
3562 spin_lock_irqsave(&domain->lock, flags);
3563
3564 /*
3565 * Save us all sanity checks whether devices already in the
3566 * domain support IOMMUv2. Just force that the domain has no
3567 * devices attached when it is switched into IOMMUv2 mode.
3568 */
3569 ret = -EBUSY;
3570 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3571 goto out;
3572
3573 ret = -ENOMEM;
3574 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3575 if (domain->gcr3_tbl == NULL)
3576 goto out;
3577
3578 domain->glx = levels;
3579 domain->flags |= PD_IOMMUV2_MASK;
3580 domain->updated = true;
3581
3582 update_domain(domain);
3583
3584 ret = 0;
3585
3586out:
3587 spin_unlock_irqrestore(&domain->lock, flags);
3588
3589 return ret;
3590}
3591EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3592
3593static int __flush_pasid(struct protection_domain *domain, int pasid,
3594 u64 address, bool size)
3595{
3596 struct iommu_dev_data *dev_data;
3597 struct iommu_cmd cmd;
3598 int i, ret;
3599
3600 if (!(domain->flags & PD_IOMMUV2_MASK))
3601 return -EINVAL;
3602
3603 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3604
3605 /*
3606 * IOMMU TLB needs to be flushed before Device TLB to
3607 * prevent device TLB refill from IOMMU TLB
3608 */
3609 for (i = 0; i < amd_iommus_present; ++i) {
3610 if (domain->dev_iommu[i] == 0)
3611 continue;
3612
3613 ret = iommu_queue_command(amd_iommus[i], &cmd);
3614 if (ret != 0)
3615 goto out;
3616 }
3617
3618 /* Wait until IOMMU TLB flushes are complete */
3619 domain_flush_complete(domain);
3620
3621 /* Now flush device TLBs */
3622 list_for_each_entry(dev_data, &domain->dev_list, list) {
3623 struct amd_iommu *iommu;
3624 int qdep;
3625
3626 BUG_ON(!dev_data->ats.enabled);
3627
3628 qdep = dev_data->ats.qdep;
3629 iommu = amd_iommu_rlookup_table[dev_data->devid];
3630
3631 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3632 qdep, address, size);
3633
3634 ret = iommu_queue_command(iommu, &cmd);
3635 if (ret != 0)
3636 goto out;
3637 }
3638
3639 /* Wait until all device TLBs are flushed */
3640 domain_flush_complete(domain);
3641
3642 ret = 0;
3643
3644out:
3645
3646 return ret;
3647}
3648
3649static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3650 u64 address)
3651{
399be2f5
JR		 3652 INC_STATS_COUNTER(invalidate_iotlb);
3653
22e266c7
JR		 3654 return __flush_pasid(domain, pasid, address, false);
3655}
3656
3657int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3658 u64 address)
3659{
3660 struct protection_domain *domain = dom->priv;
3661 unsigned long flags;
3662 int ret;
3663
3664 spin_lock_irqsave(&domain->lock, flags);
3665 ret = __amd_iommu_flush_page(domain, pasid, address);
3666 spin_unlock_irqrestore(&domain->lock, flags);
3667
3668 return ret;
3669}
3670EXPORT_SYMBOL(amd_iommu_flush_page);
3671
3672static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3673{
399be2f5
JR		 3674 INC_STATS_COUNTER(invalidate_iotlb_all);
3675
22e266c7
JR		 3676 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3677 true);
3678}
3679
3680int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3681{
3682 struct protection_domain *domain = dom->priv;
3683 unsigned long flags;
3684 int ret;
3685
3686 spin_lock_irqsave(&domain->lock, flags);
3687 ret = __amd_iommu_flush_tlb(domain, pasid);
3688 spin_unlock_irqrestore(&domain->lock, flags);
3689
3690 return ret;
3691}
3692EXPORT_SYMBOL(amd_iommu_flush_tlb);
3693
b16137b1
JR		 3694static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3695{
3696 int index;
3697 u64 *pte;
3698
3699 while (true) {
3700
3701 index = (pasid >> (9 * level)) & 0x1ff;
3702 pte = &root[index];
3703
3704 if (level == 0)
3705 break;
3706
3707 if (!(*pte & GCR3_VALID)) {
3708 if (!alloc)
3709 return NULL;
3710
3711 root = (void *)get_zeroed_page(GFP_ATOMIC);
3712 if (root == NULL)
3713 return NULL;
3714
3715 *pte = __pa(root) | GCR3_VALID;
3716 }
3717
3718 root = __va(*pte & PAGE_MASK);
3719
3720 level -= 1;
3721 }
3722
3723 return pte;
3724}
3725
3726static int __set_gcr3(struct protection_domain *domain, int pasid,
3727 unsigned long cr3)
3728{
3729 u64 *pte;
3730
3731 if (domain->mode != PAGE_MODE_NONE)
3732 return -EINVAL;
3733
3734 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3735 if (pte == NULL)
3736 return -ENOMEM;
3737
3738 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3739
3740 return __amd_iommu_flush_tlb(domain, pasid);
3741}
3742
3743static int __clear_gcr3(struct protection_domain *domain, int pasid)
3744{
3745 u64 *pte;
3746
3747 if (domain->mode != PAGE_MODE_NONE)
3748 return -EINVAL;
3749
3750 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3751 if (pte == NULL)
3752 return 0;
3753
3754 *pte = 0;
3755
3756 return __amd_iommu_flush_tlb(domain, pasid);
3757}
3758
3759int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3760 unsigned long cr3)
3761{
3762 struct protection_domain *domain = dom->priv;
3763 unsigned long flags;
3764 int ret;
3765
3766 spin_lock_irqsave(&domain->lock, flags);
3767 ret = __set_gcr3(domain, pasid, cr3);
3768 spin_unlock_irqrestore(&domain->lock, flags);
3769
3770 return ret;
3771}
3772EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3773
3774int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3775{
3776 struct protection_domain *domain = dom->priv;
3777 unsigned long flags;
3778 int ret;
3779
3780 spin_lock_irqsave(&domain->lock, flags);
3781 ret = __clear_gcr3(domain, pasid);
3782 spin_unlock_irqrestore(&domain->lock, flags);
3783
3784 return ret;
3785}
3786EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3787
3788int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3789 int status, int tag)
3790{
3791 struct iommu_dev_data *dev_data;
3792 struct amd_iommu *iommu;
3793 struct iommu_cmd cmd;
3794
399be2f5
JR		 3795 INC_STATS_COUNTER(complete_ppr);
3796
c99afa25
JR		 3797 dev_data = get_dev_data(&pdev->dev);
3798 iommu = amd_iommu_rlookup_table[dev_data->devid];
3799
3800 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3801 tag, dev_data->pri_tlp);
3802
3803 return iommu_queue_command(iommu, &cmd);
3804}
3805EXPORT_SYMBOL(amd_iommu_complete_ppr);
f3572db8
JR		 3806
3807struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3808{
3809 struct protection_domain *domain;
3810
3811 domain = get_domain(&pdev->dev);
3812 if (IS_ERR(domain))
3813 return NULL;
3814
3815 /* Only return IOMMUv2 domains */
3816 if (!(domain->flags & PD_IOMMUV2_MASK))
3817 return NULL;
3818
3819 return domain->iommu_domain;
3820}
3821EXPORT_SYMBOL(amd_iommu_get_v2_domain);
6a113ddc
JR		 3822
3823void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3824{
3825 struct iommu_dev_data *dev_data;
3826
3827 if (!amd_iommu_v2_supported())
3828 return;
3829
3830 dev_data = get_dev_data(&pdev->dev);
3831 dev_data->errata |= (1 << erratum);
3832}
3833EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
52efdb89
JR		 3834
3835int amd_iommu_device_info(struct pci_dev *pdev,
3836 struct amd_iommu_device_info *info)
3837{
3838 int max_pasids;
3839 int pos;
3840
3841 if (pdev == NULL || info == NULL)
3842 return -EINVAL;
3843
3844 if (!amd_iommu_v2_supported())
3845 return -EINVAL;
3846
3847 memset(info, 0, sizeof(*info));
3848
3849 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3850 if (pos)
3851 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3852
3853 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3854 if (pos)
3855 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3856
3857 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3858 if (pos) {
3859 int features;
3860
3861 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3862 max_pasids = min(max_pasids, (1 << 20));
3863
3864 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3865 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3866
3867 features = pci_pasid_features(pdev);
3868 if (features & PCI_PASID_CAP_EXEC)
3869 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3870 if (features & PCI_PASID_CAP_PRIV)
3871 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3872 }
3873
3874 return 0;
3875}
3876EXPORT_SYMBOL(amd_iommu_device_info);
2b324506
JR		 3877
3878#ifdef CONFIG_IRQ_REMAP
3879
3880/*****************************************************************************
3881 *
3882 * Interrupt Remapping Implementation
3883 *
3884 *****************************************************************************/
3885
3886union irte {
3887 u32 val;
3888 struct {
3889 u32 valid : 1,
3890 no_fault : 1,
3891 int_type : 3,
3892 rq_eoi : 1,
3893 dm : 1,
3894 rsvd_1 : 1,
3895 destination : 8,
3896 vector : 8,
3897 rsvd_2 : 8;
3898 } fields;
3899};
3900
3901#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3902#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3903#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3904#define DTE_IRQ_REMAP_ENABLE 1ULL
3905
3906static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3907{
3908 u64 dte;
3909
3910 dte = amd_iommu_dev_table[devid].data[2];
3911 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3912 dte |= virt_to_phys(table->table);
3913 dte |= DTE_IRQ_REMAP_INTCTL;
3914 dte |= DTE_IRQ_TABLE_LEN;
3915 dte |= DTE_IRQ_REMAP_ENABLE;
3916
3917 amd_iommu_dev_table[devid].data[2] = dte;
3918}
3919
3920#define IRTE_ALLOCATED (~1U)
3921
3922static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3923{
3924 struct irq_remap_table *table = NULL;
3925 struct amd_iommu *iommu;
3926 unsigned long flags;
3927 u16 alias;
3928
3929 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3930
3931 iommu = amd_iommu_rlookup_table[devid];
3932 if (!iommu)
3933 goto out_unlock;
3934
3935 table = irq_lookup_table[devid];
3936 if (table)
3937 goto out;
3938
3939 alias = amd_iommu_alias_table[devid];
3940 table = irq_lookup_table[alias];
3941 if (table) {
3942 irq_lookup_table[devid] = table;
3943 set_dte_irq_entry(devid, table);
3944 iommu_flush_dte(iommu, devid);
3945 goto out;
3946 }
3947
3948 /* Nothing there yet, allocate new irq remapping table */
3949 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3950 if (!table)
3951 goto out;
3952
3953 if (ioapic)
3954 /* Keep the first 32 indexes free for IOAPIC interrupts */
3955 table->min_index = 32;
3956
3957 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3958 if (!table->table) {
3959 kfree(table);
821f0f68 3960 table = NULL;
2b324506
JR		 3961 goto out;
3962 }
3963
3964 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3965
3966 if (ioapic) {
3967 int i;
3968
3969 for (i = 0; i < 32; ++i)
3970 table->table[i] = IRTE_ALLOCATED;
3971 }
3972
3973 irq_lookup_table[devid] = table;
3974 set_dte_irq_entry(devid, table);
3975 iommu_flush_dte(iommu, devid);
3976 if (devid != alias) {
3977 irq_lookup_table[alias] = table;
3978 set_dte_irq_entry(devid, table);
3979 iommu_flush_dte(iommu, alias);
3980 }
3981
3982out:
3983 iommu_completion_wait(iommu);
3984
3985out_unlock:
3986 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3987
3988 return table;
3989}
3990
3991static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3992{
3993 struct irq_remap_table *table;
3994 unsigned long flags;
3995 int index, c;
3996
3997 table = get_irq_table(devid, false);
3998 if (!table)
3999 return -ENODEV;
4000
4001 spin_lock_irqsave(&table->lock, flags);
4002
4003 /* Scan table for free entries */
4004 for (c = 0, index = table->min_index;
4005 index < MAX_IRQS_PER_TABLE;
4006 ++index) {
4007 if (table->table[index] == 0)
4008 c += 1;
4009 else
4010 c = 0;
4011
4012 if (c == count) {
4013 struct irq_2_iommu *irte_info;
4014
4015 for (; c != 0; --c)
4016 table->table[index - c + 1] = IRTE_ALLOCATED;
4017
4018 index -= count - 1;
4019
9b1b0e42 4020 cfg->remapped = 1;
2b324506
JR		 4021 irte_info = &cfg->irq_2_iommu;
4022 irte_info->sub_handle = devid;
4023 irte_info->irte_index = index;
2b324506
JR		 4024
4025 goto out;
4026 }
4027 }
4028
4029 index = -ENOSPC;
4030
4031out:
4032 spin_unlock_irqrestore(&table->lock, flags);
4033
4034 return index;
4035}
4036
4037static int get_irte(u16 devid, int index, union irte *irte)
4038{
4039 struct irq_remap_table *table;
4040 unsigned long flags;
4041
4042 table = get_irq_table(devid, false);
4043 if (!table)
4044 return -ENOMEM;
4045
4046 spin_lock_irqsave(&table->lock, flags);
4047 irte->val = table->table[index];
4048 spin_unlock_irqrestore(&table->lock, flags);
4049
4050 return 0;
4051}
4052
4053static int modify_irte(u16 devid, int index, union irte irte)
4054{
4055 struct irq_remap_table *table;
4056 struct amd_iommu *iommu;
4057 unsigned long flags;
4058
4059 iommu = amd_iommu_rlookup_table[devid];
4060 if (iommu == NULL)
4061 return -EINVAL;
4062
4063 table = get_irq_table(devid, false);
4064 if (!table)
4065 return -ENOMEM;
4066
4067 spin_lock_irqsave(&table->lock, flags);
4068 table->table[index] = irte.val;
4069 spin_unlock_irqrestore(&table->lock, flags);
4070
4071 iommu_flush_irt(iommu, devid);
4072 iommu_completion_wait(iommu);
4073
4074 return 0;
4075}
4076
4077static void free_irte(u16 devid, int index)
4078{
4079 struct irq_remap_table *table;
4080 struct amd_iommu *iommu;
4081 unsigned long flags;
4082
4083 iommu = amd_iommu_rlookup_table[devid];
4084 if (iommu == NULL)
4085 return;
4086
4087 table = get_irq_table(devid, false);
4088 if (!table)
4089 return;
4090
4091 spin_lock_irqsave(&table->lock, flags);
4092 table->table[index] = 0;
4093 spin_unlock_irqrestore(&table->lock, flags);
4094
4095 iommu_flush_irt(iommu, devid);
4096 iommu_completion_wait(iommu);
4097}
4098
5527de74
JR		 4099static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4100 unsigned int destination, int vector,
4101 struct io_apic_irq_attr *attr)
4102{
4103 struct irq_remap_table *table;
4104 struct irq_2_iommu *irte_info;
4105 struct irq_cfg *cfg;
4106 union irte irte;
4107 int ioapic_id;
4108 int index;
4109 int devid;
4110 int ret;
4111
4112 cfg = irq_get_chip_data(irq);
4113 if (!cfg)
4114 return -EINVAL;
4115
4116 irte_info = &cfg->irq_2_iommu;
4117 ioapic_id = mpc_ioapic_id(attr->ioapic);
4118 devid = get_ioapic_devid(ioapic_id);
4119
4120 if (devid < 0)
4121 return devid;
4122
4123 table = get_irq_table(devid, true);
4124 if (table == NULL)
4125 return -ENOMEM;
4126
4127 index = attr->ioapic_pin;
4128
4129 /* Setup IRQ remapping info */
9b1b0e42 4130 cfg->remapped = 1;
5527de74
JR		 4131 irte_info->sub_handle = devid;
4132 irte_info->irte_index = index;
5527de74
JR		 4133
4134 /* Setup IRTE for IOMMU */
4135 irte.val = 0;
4136 irte.fields.vector = vector;
4137 irte.fields.int_type = apic->irq_delivery_mode;
4138 irte.fields.destination = destination;
4139 irte.fields.dm = apic->irq_dest_mode;
4140 irte.fields.valid = 1;
4141
4142 ret = modify_irte(devid, index, irte);
4143 if (ret)
4144 return ret;
4145
4146 /* Setup IOAPIC entry */
4147 memset(entry, 0, sizeof(*entry));
4148
4149 entry->vector = index;
4150 entry->mask = 0;
4151 entry->trigger = attr->trigger;
4152 entry->polarity = attr->polarity;
4153
4154 /*
4155 * Mask level triggered irqs.
5527de74
JR		 4156 */
4157 if (attr->trigger)
4158 entry->mask = 1;
4159
4160 return 0;
4161}
4162
4163static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4164 bool force)
4165{
4166 struct irq_2_iommu *irte_info;
4167 unsigned int dest, irq;
4168 struct irq_cfg *cfg;
4169 union irte irte;
4170 int err;
4171
4172 if (!config_enabled(CONFIG_SMP))
4173 return -1;
4174
4175 cfg = data->chip_data;
4176 irq = data->irq;
4177 irte_info = &cfg->irq_2_iommu;
4178
4179 if (!cpumask_intersects(mask, cpu_online_mask))
4180 return -EINVAL;
4181
4182 if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte))
4183 return -EBUSY;
4184
4185 if (assign_irq_vector(irq, cfg, mask))
4186 return -EBUSY;
4187
4188 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4189 if (err) {
4190 if (assign_irq_vector(irq, cfg, data->affinity))
4191 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4192 return err;
4193 }
4194
4195 irte.fields.vector = cfg->vector;
4196 irte.fields.destination = dest;
4197
4198 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4199
4200 if (cfg->move_in_progress)
4201 send_cleanup_vector(cfg);
4202
4203 cpumask_copy(data->affinity, mask);
4204
4205 return 0;
4206}
4207
4208static int free_irq(int irq)
4209{
4210 struct irq_2_iommu *irte_info;
4211 struct irq_cfg *cfg;
4212
4213 cfg = irq_get_chip_data(irq);
4214 if (!cfg)
4215 return -EINVAL;
4216
4217 irte_info = &cfg->irq_2_iommu;
4218
4219 free_irte(irte_info->sub_handle, irte_info->irte_index);
4220
4221 return 0;
4222}
4223
0b4d48cb
JR		 4224static void compose_msi_msg(struct pci_dev *pdev,
4225 unsigned int irq, unsigned int dest,
4226 struct msi_msg *msg, u8 hpet_id)
4227{
4228 struct irq_2_iommu *irte_info;
4229 struct irq_cfg *cfg;
4230 union irte irte;
4231
4232 cfg = irq_get_chip_data(irq);
4233 if (!cfg)
4234 return;
4235
4236 irte_info = &cfg->irq_2_iommu;
4237
4238 irte.val = 0;
4239 irte.fields.vector = cfg->vector;
4240 irte.fields.int_type = apic->irq_delivery_mode;
4241 irte.fields.destination = dest;
4242 irte.fields.dm = apic->irq_dest_mode;
4243 irte.fields.valid = 1;
4244
4245 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4246
4247 msg->address_hi = MSI_ADDR_BASE_HI;
4248 msg->address_lo = MSI_ADDR_BASE_LO;
4249 msg->data = irte_info->irte_index;
4250}
4251
4252static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4253{
4254 struct irq_cfg *cfg;
4255 int index;
4256 u16 devid;
4257
4258 if (!pdev)
4259 return -EINVAL;
4260
4261 cfg = irq_get_chip_data(irq);
4262 if (!cfg)
4263 return -EINVAL;
4264
4265 devid = get_device_id(&pdev->dev);
4266 index = alloc_irq_index(cfg, devid, nvec);
4267
4268 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4269}
4270
4271static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4272 int index, int offset)
4273{
4274 struct irq_2_iommu *irte_info;
4275 struct irq_cfg *cfg;
4276 u16 devid;
4277
4278 if (!pdev)
4279 return -EINVAL;
4280
4281 cfg = irq_get_chip_data(irq);
4282 if (!cfg)
4283 return -EINVAL;
4284
4285 if (index >= MAX_IRQS_PER_TABLE)
4286 return 0;
4287
4288 devid = get_device_id(&pdev->dev);
4289 irte_info = &cfg->irq_2_iommu;
4290
9b1b0e42 4291 cfg->remapped = 1;
0b4d48cb
JR		 4292 irte_info->sub_handle = devid;
4293 irte_info->irte_index = index + offset;
0b4d48cb
JR		 4294
4295 return 0;
4296}
4297
d976195c
JR		 4298static int setup_hpet_msi(unsigned int irq, unsigned int id)
4299{
4300 struct irq_2_iommu *irte_info;
4301 struct irq_cfg *cfg;
4302 int index, devid;
4303
4304 cfg = irq_get_chip_data(irq);
4305 if (!cfg)
4306 return -EINVAL;
4307
4308 irte_info = &cfg->irq_2_iommu;
4309 devid = get_hpet_devid(id);
4310 if (devid < 0)
4311 return devid;
4312
4313 index = alloc_irq_index(cfg, devid, 1);
4314 if (index < 0)
4315 return index;
4316
9b1b0e42 4317 cfg->remapped = 1;
d976195c
JR		 4318 irte_info->sub_handle = devid;
4319 irte_info->irte_index = index;
d976195c
JR		 4320
4321 return 0;
4322}
4323
6b474b82
JR		 4324struct irq_remap_ops amd_iommu_irq_ops = {
4325 .supported = amd_iommu_supported,
4326 .prepare = amd_iommu_prepare,
4327 .enable = amd_iommu_enable,
4328 .disable = amd_iommu_disable,
4329 .reenable = amd_iommu_reenable,
4330 .enable_faulting = amd_iommu_enable_faulting,
4331 .setup_ioapic_entry = setup_ioapic_entry,
4332 .set_affinity = set_affinity,
4333 .free_irq = free_irq,
4334 .compose_msi_msg = compose_msi_msg,
4335 .msi_alloc_irq = msi_alloc_irq,
4336 .msi_setup_irq = msi_setup_irq,
4337 .setup_hpet_msi = setup_hpet_msi,
4338};
2b324506 4339#endif
Linux kernel - Deliverables
This page took 0.736669 seconds and 5 git commands to generate.