Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
7c71d306 | 37 | #include <linux/irqdomain.h> |
2b324506 JR |
38 | #include <asm/irq_remapping.h> |
39 | #include <asm/io_apic.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/hw_irq.h> | |
17f5b569 | 42 | #include <asm/msidef.h> |
b6c02715 | 43 | #include <asm/proto.h> |
46a7fa27 | 44 | #include <asm/iommu.h> |
1d9b16d1 | 45 | #include <asm/gart.h> |
27c2127a | 46 | #include <asm/dma.h> |
403f81d8 JR |
47 | |
48 | #include "amd_iommu_proto.h" | |
49 | #include "amd_iommu_types.h" | |
6b474b82 | 50 | #include "irq_remapping.h" |
b6c02715 JR |
51 | |
52 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
53 | ||
815b33fd | 54 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 55 | |
aa3de9c0 OBC |
56 | /* |
57 | * This bitmap is used to advertise the page sizes our hardware support | |
58 | * to the IOMMU core, which will then use this information to split | |
59 | * physically contiguous memory regions it is mapping into page sizes | |
60 | * that we support. | |
61 | * | |
954e3dd8 | 62 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 63 | */ |
954e3dd8 | 64 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 65 | |
b6c02715 JR |
66 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
67 | ||
bd60b735 JR |
68 | /* A list of preallocated protection domains */ |
69 | static LIST_HEAD(iommu_pd_list); | |
70 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
71 | ||
8fa5f802 JR |
72 | /* List of all available dev_data structures */ |
73 | static LIST_HEAD(dev_data_list); | |
74 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
75 | ||
6efed63b JR |
76 | LIST_HEAD(ioapic_map); |
77 | LIST_HEAD(hpet_map); | |
78 | ||
0feae533 JR |
79 | /* |
80 | * Domain for untranslated devices - only allocated | |
81 | * if iommu=pt passed on kernel cmd line. | |
82 | */ | |
83 | static struct protection_domain *pt_domain; | |
84 | ||
b22f6434 | 85 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 86 | |
72e1dcc4 | 87 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 88 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 89 | |
ac1534a5 JR |
90 | static struct dma_map_ops amd_iommu_dma_ops; |
91 | ||
50917e26 JR |
92 | /* |
93 | * This struct contains device specific data for the IOMMU | |
94 | */ | |
95 | struct iommu_dev_data { | |
96 | struct list_head list; /* For domain->dev_list */ | |
97 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 98 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
99 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
100 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
101 | u16 devid; /* PCI Device ID */ |
102 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
103 | bool passthrough; /* Default for device is pt_domain */ | |
104 | struct { | |
105 | bool enabled; | |
106 | int qdep; | |
107 | } ats; /* ATS state */ | |
108 | bool pri_tlp; /* PASID TLB required for | |
109 | PPR completions */ | |
110 | u32 errata; /* Bitmap for errata to apply */ | |
111 | }; | |
112 | ||
431b2a20 JR |
113 | /* |
114 | * general struct to manage commands send to an IOMMU | |
115 | */ | |
d6449536 | 116 | struct iommu_cmd { |
b6c02715 JR |
117 | u32 data[4]; |
118 | }; | |
119 | ||
05152a04 JR |
120 | struct kmem_cache *amd_iommu_irq_cache; |
121 | ||
04bfdd84 | 122 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 123 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 124 | |
15898bbc JR |
125 | /**************************************************************************** |
126 | * | |
127 | * Helper functions | |
128 | * | |
129 | ****************************************************************************/ | |
130 | ||
3f4b87b9 JR |
131 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
132 | { | |
133 | return container_of(dom, struct protection_domain, domain); | |
134 | } | |
135 | ||
f62dda66 | 136 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
137 | { |
138 | struct iommu_dev_data *dev_data; | |
139 | unsigned long flags; | |
140 | ||
141 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
142 | if (!dev_data) | |
143 | return NULL; | |
144 | ||
f251e187 JR |
145 | INIT_LIST_HEAD(&dev_data->alias_list); |
146 | ||
f62dda66 | 147 | dev_data->devid = devid; |
8fa5f802 JR |
148 | |
149 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
150 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
151 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
152 | ||
153 | return dev_data; | |
154 | } | |
155 | ||
156 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
157 | { | |
158 | unsigned long flags; | |
159 | ||
160 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
161 | list_del(&dev_data->dev_data_list); | |
162 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
163 | ||
164 | kfree(dev_data); | |
165 | } | |
166 | ||
3b03bb74 JR |
167 | static struct iommu_dev_data *search_dev_data(u16 devid) |
168 | { | |
169 | struct iommu_dev_data *dev_data; | |
170 | unsigned long flags; | |
171 | ||
172 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
173 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
174 | if (dev_data->devid == devid) | |
175 | goto out_unlock; | |
176 | } | |
177 | ||
178 | dev_data = NULL; | |
179 | ||
180 | out_unlock: | |
181 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
182 | ||
183 | return dev_data; | |
184 | } | |
185 | ||
186 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
187 | { | |
188 | struct iommu_dev_data *dev_data; | |
189 | ||
190 | dev_data = search_dev_data(devid); | |
191 | ||
192 | if (dev_data == NULL) | |
193 | dev_data = alloc_dev_data(devid); | |
194 | ||
195 | return dev_data; | |
196 | } | |
197 | ||
15898bbc JR |
198 | static inline u16 get_device_id(struct device *dev) |
199 | { | |
200 | struct pci_dev *pdev = to_pci_dev(dev); | |
201 | ||
6f2729ba | 202 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
203 | } |
204 | ||
657cbb6b JR |
205 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
206 | { | |
207 | return dev->archdata.iommu; | |
208 | } | |
209 | ||
5abcdba4 JR |
210 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
211 | { | |
212 | static const int caps[] = { | |
213 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
214 | PCI_EXT_CAP_ID_PRI, |
215 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
216 | }; |
217 | int i, pos; | |
218 | ||
219 | for (i = 0; i < 3; ++i) { | |
220 | pos = pci_find_ext_capability(pdev, caps[i]); | |
221 | if (pos == 0) | |
222 | return false; | |
223 | } | |
224 | ||
225 | return true; | |
226 | } | |
227 | ||
6a113ddc JR |
228 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
229 | { | |
230 | struct iommu_dev_data *dev_data; | |
231 | ||
232 | dev_data = get_dev_data(&pdev->dev); | |
233 | ||
234 | return dev_data->errata & (1 << erratum) ? true : false; | |
235 | } | |
236 | ||
71c70984 JR |
237 | /* |
238 | * In this function the list of preallocated protection domains is traversed to | |
239 | * find the domain for a specific device | |
240 | */ | |
241 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
242 | { | |
243 | struct dma_ops_domain *entry, *ret = NULL; | |
244 | unsigned long flags; | |
245 | u16 alias = amd_iommu_alias_table[devid]; | |
246 | ||
247 | if (list_empty(&iommu_pd_list)) | |
248 | return NULL; | |
249 | ||
250 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
251 | ||
252 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
253 | if (entry->target_dev == devid || | |
254 | entry->target_dev == alias) { | |
255 | ret = entry; | |
256 | break; | |
257 | } | |
258 | } | |
259 | ||
260 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
98fc5a69 JR |
265 | /* |
266 | * This function checks if the driver got a valid device from the caller to | |
267 | * avoid dereferencing invalid pointers. | |
268 | */ | |
269 | static bool check_device(struct device *dev) | |
270 | { | |
271 | u16 devid; | |
272 | ||
273 | if (!dev || !dev->dma_mask) | |
274 | return false; | |
275 | ||
b82a2272 YW |
276 | /* No PCI device */ |
277 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
278 | return false; |
279 | ||
280 | devid = get_device_id(dev); | |
281 | ||
282 | /* Out of our scope? */ | |
283 | if (devid > amd_iommu_last_bdf) | |
284 | return false; | |
285 | ||
286 | if (amd_iommu_rlookup_table[devid] == NULL) | |
287 | return false; | |
288 | ||
289 | return true; | |
290 | } | |
291 | ||
25b11ce2 | 292 | static void init_iommu_group(struct device *dev) |
2851db21 | 293 | { |
2851db21 | 294 | struct iommu_group *group; |
2851db21 | 295 | |
65d5352f | 296 | group = iommu_group_get_for_dev(dev); |
25b11ce2 AW |
297 | if (!IS_ERR(group)) |
298 | iommu_group_put(group); | |
eb9c9527 AW |
299 | } |
300 | ||
c1931090 AW |
301 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
302 | { | |
303 | *(u16 *)data = alias; | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static u16 get_alias(struct device *dev) | |
308 | { | |
309 | struct pci_dev *pdev = to_pci_dev(dev); | |
310 | u16 devid, ivrs_alias, pci_alias; | |
311 | ||
312 | devid = get_device_id(dev); | |
313 | ivrs_alias = amd_iommu_alias_table[devid]; | |
314 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
315 | ||
316 | if (ivrs_alias == pci_alias) | |
317 | return ivrs_alias; | |
318 | ||
319 | /* | |
320 | * DMA alias showdown | |
321 | * | |
322 | * The IVRS is fairly reliable in telling us about aliases, but it | |
323 | * can't know about every screwy device. If we don't have an IVRS | |
324 | * reported alias, use the PCI reported alias. In that case we may | |
325 | * still need to initialize the rlookup and dev_table entries if the | |
326 | * alias is to a non-existent device. | |
327 | */ | |
328 | if (ivrs_alias == devid) { | |
329 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
330 | amd_iommu_rlookup_table[pci_alias] = | |
331 | amd_iommu_rlookup_table[devid]; | |
332 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
333 | amd_iommu_dev_table[devid].data, | |
334 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
335 | } | |
336 | ||
337 | return pci_alias; | |
338 | } | |
339 | ||
340 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
341 | "for device %s[%04x:%04x], kernel reported alias " | |
342 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
343 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
344 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
345 | PCI_FUNC(pci_alias)); | |
346 | ||
347 | /* | |
348 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
349 | * bus, then the IVRS table may know about a quirk that we don't. | |
350 | */ | |
351 | if (pci_alias == devid && | |
352 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
353 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
354 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
355 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
356 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
357 | dev_name(dev)); | |
358 | } | |
359 | ||
360 | return ivrs_alias; | |
361 | } | |
362 | ||
eb9c9527 AW |
363 | static int iommu_init_device(struct device *dev) |
364 | { | |
365 | struct pci_dev *pdev = to_pci_dev(dev); | |
366 | struct iommu_dev_data *dev_data; | |
367 | u16 alias; | |
eb9c9527 AW |
368 | |
369 | if (dev->archdata.iommu) | |
370 | return 0; | |
371 | ||
372 | dev_data = find_dev_data(get_device_id(dev)); | |
373 | if (!dev_data) | |
374 | return -ENOMEM; | |
375 | ||
c1931090 AW |
376 | alias = get_alias(dev); |
377 | ||
eb9c9527 AW |
378 | if (alias != dev_data->devid) { |
379 | struct iommu_dev_data *alias_data; | |
380 | ||
381 | alias_data = find_dev_data(alias); | |
382 | if (alias_data == NULL) { | |
383 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
384 | dev_name(dev)); | |
385 | free_dev_data(dev_data); | |
386 | return -ENOTSUPP; | |
387 | } | |
388 | dev_data->alias_data = alias_data; | |
eb9c9527 | 389 | |
f251e187 JR |
390 | /* Add device to the alias_list */ |
391 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 392 | } |
9dcd6130 | 393 | |
5abcdba4 JR |
394 | if (pci_iommuv2_capable(pdev)) { |
395 | struct amd_iommu *iommu; | |
396 | ||
397 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
398 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
399 | } | |
400 | ||
657cbb6b JR |
401 | dev->archdata.iommu = dev_data; |
402 | ||
066f2e98 AW |
403 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
404 | dev); | |
405 | ||
657cbb6b JR |
406 | return 0; |
407 | } | |
408 | ||
26018874 JR |
409 | static void iommu_ignore_device(struct device *dev) |
410 | { | |
411 | u16 devid, alias; | |
412 | ||
413 | devid = get_device_id(dev); | |
414 | alias = amd_iommu_alias_table[devid]; | |
415 | ||
416 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
417 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
418 | ||
419 | amd_iommu_rlookup_table[devid] = NULL; | |
420 | amd_iommu_rlookup_table[alias] = NULL; | |
421 | } | |
422 | ||
657cbb6b JR |
423 | static void iommu_uninit_device(struct device *dev) |
424 | { | |
c1931090 AW |
425 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
426 | ||
427 | if (!dev_data) | |
428 | return; | |
429 | ||
066f2e98 AW |
430 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
431 | dev); | |
432 | ||
9dcd6130 AW |
433 | iommu_group_remove_device(dev); |
434 | ||
c1931090 AW |
435 | /* Unlink from alias, it may change if another device is re-plugged */ |
436 | dev_data->alias_data = NULL; | |
437 | ||
8fa5f802 | 438 | /* |
c1931090 AW |
439 | * We keep dev_data around for unplugged devices and reuse it when the |
440 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 441 | */ |
657cbb6b | 442 | } |
b7cc9554 JR |
443 | |
444 | void __init amd_iommu_uninit_devices(void) | |
445 | { | |
8fa5f802 | 446 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
447 | struct pci_dev *pdev = NULL; |
448 | ||
449 | for_each_pci_dev(pdev) { | |
450 | ||
451 | if (!check_device(&pdev->dev)) | |
452 | continue; | |
453 | ||
454 | iommu_uninit_device(&pdev->dev); | |
455 | } | |
8fa5f802 JR |
456 | |
457 | /* Free all of our dev_data structures */ | |
458 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
459 | free_dev_data(dev_data); | |
b7cc9554 JR |
460 | } |
461 | ||
462 | int __init amd_iommu_init_devices(void) | |
463 | { | |
464 | struct pci_dev *pdev = NULL; | |
465 | int ret = 0; | |
466 | ||
467 | for_each_pci_dev(pdev) { | |
468 | ||
469 | if (!check_device(&pdev->dev)) | |
470 | continue; | |
471 | ||
472 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
473 | if (ret == -ENOTSUPP) |
474 | iommu_ignore_device(&pdev->dev); | |
475 | else if (ret) | |
b7cc9554 JR |
476 | goto out_free; |
477 | } | |
478 | ||
25b11ce2 AW |
479 | /* |
480 | * Initialize IOMMU groups only after iommu_init_device() has | |
481 | * had a chance to populate any IVRS defined aliases. | |
482 | */ | |
483 | for_each_pci_dev(pdev) { | |
484 | if (check_device(&pdev->dev)) | |
485 | init_iommu_group(&pdev->dev); | |
486 | } | |
487 | ||
b7cc9554 JR |
488 | return 0; |
489 | ||
490 | out_free: | |
491 | ||
492 | amd_iommu_uninit_devices(); | |
493 | ||
494 | return ret; | |
495 | } | |
7f26508b JR |
496 | #ifdef CONFIG_AMD_IOMMU_STATS |
497 | ||
498 | /* | |
499 | * Initialization code for statistics collection | |
500 | */ | |
501 | ||
da49f6df | 502 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 503 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 504 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 505 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 506 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 507 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 508 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 509 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 510 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 511 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 512 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 513 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
514 | DECLARE_STATS_COUNTER(complete_ppr); |
515 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
516 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
517 | DECLARE_STATS_COUNTER(pri_requests); | |
518 | ||
7f26508b | 519 | static struct dentry *stats_dir; |
7f26508b JR |
520 | static struct dentry *de_fflush; |
521 | ||
522 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
523 | { | |
524 | if (stats_dir == NULL) | |
525 | return; | |
526 | ||
527 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
528 | &cnt->value); | |
529 | } | |
530 | ||
531 | static void amd_iommu_stats_init(void) | |
532 | { | |
533 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
534 | if (stats_dir == NULL) | |
535 | return; | |
536 | ||
7f26508b | 537 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 538 | &amd_iommu_unmap_flush); |
da49f6df JR |
539 | |
540 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 541 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 542 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 543 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 544 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 545 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 546 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 547 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 548 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 549 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 550 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 551 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
552 | amd_iommu_stats_add(&complete_ppr); |
553 | amd_iommu_stats_add(&invalidate_iotlb); | |
554 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
555 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
556 | } |
557 | ||
558 | #endif | |
559 | ||
a80dc3e0 JR |
560 | /**************************************************************************** |
561 | * | |
562 | * Interrupt handling functions | |
563 | * | |
564 | ****************************************************************************/ | |
565 | ||
e3e59876 JR |
566 | static void dump_dte_entry(u16 devid) |
567 | { | |
568 | int i; | |
569 | ||
ee6c2868 JR |
570 | for (i = 0; i < 4; ++i) |
571 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
572 | amd_iommu_dev_table[devid].data[i]); |
573 | } | |
574 | ||
945b4ac4 JR |
575 | static void dump_command(unsigned long phys_addr) |
576 | { | |
577 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
578 | int i; | |
579 | ||
580 | for (i = 0; i < 4; ++i) | |
581 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
582 | } | |
583 | ||
a345b23b | 584 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 585 | { |
3d06fca8 JR |
586 | int type, devid, domid, flags; |
587 | volatile u32 *event = __evt; | |
588 | int count = 0; | |
589 | u64 address; | |
590 | ||
591 | retry: | |
592 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
593 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
594 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
595 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
596 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
597 | ||
598 | if (type == 0) { | |
599 | /* Did we hit the erratum? */ | |
600 | if (++count == LOOP_TIMEOUT) { | |
601 | pr_err("AMD-Vi: No event written to event log\n"); | |
602 | return; | |
603 | } | |
604 | udelay(1); | |
605 | goto retry; | |
606 | } | |
90008ee4 | 607 | |
4c6f40d4 | 608 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
609 | |
610 | switch (type) { | |
611 | case EVENT_TYPE_ILL_DEV: | |
612 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
613 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 614 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 615 | address, flags); |
e3e59876 | 616 | dump_dte_entry(devid); |
90008ee4 JR |
617 | break; |
618 | case EVENT_TYPE_IO_FAULT: | |
619 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
620 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 621 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
622 | domid, address, flags); |
623 | break; | |
624 | case EVENT_TYPE_DEV_TAB_ERR: | |
625 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
626 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 627 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
628 | address, flags); |
629 | break; | |
630 | case EVENT_TYPE_PAGE_TAB_ERR: | |
631 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
632 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 633 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
634 | domid, address, flags); |
635 | break; | |
636 | case EVENT_TYPE_ILL_CMD: | |
637 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 638 | dump_command(address); |
90008ee4 JR |
639 | break; |
640 | case EVENT_TYPE_CMD_HARD_ERR: | |
641 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
642 | "flags=0x%04x]\n", address, flags); | |
643 | break; | |
644 | case EVENT_TYPE_IOTLB_INV_TO: | |
645 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
646 | "address=0x%016llx]\n", | |
c5081cd7 | 647 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
648 | address); |
649 | break; | |
650 | case EVENT_TYPE_INV_DEV_REQ: | |
651 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
652 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 653 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
654 | address, flags); |
655 | break; | |
656 | default: | |
657 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
658 | } | |
3d06fca8 JR |
659 | |
660 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
661 | } |
662 | ||
663 | static void iommu_poll_events(struct amd_iommu *iommu) | |
664 | { | |
665 | u32 head, tail; | |
90008ee4 JR |
666 | |
667 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
668 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
669 | ||
670 | while (head != tail) { | |
a345b23b | 671 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
672 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
673 | } | |
674 | ||
675 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
676 | } |
677 | ||
eee53537 | 678 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
679 | { |
680 | struct amd_iommu_fault fault; | |
72e1dcc4 | 681 | |
399be2f5 JR |
682 | INC_STATS_COUNTER(pri_requests); |
683 | ||
72e1dcc4 JR |
684 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
685 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
686 | return; | |
687 | } | |
688 | ||
689 | fault.address = raw[1]; | |
690 | fault.pasid = PPR_PASID(raw[0]); | |
691 | fault.device_id = PPR_DEVID(raw[0]); | |
692 | fault.tag = PPR_TAG(raw[0]); | |
693 | fault.flags = PPR_FLAGS(raw[0]); | |
694 | ||
72e1dcc4 JR |
695 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
696 | } | |
697 | ||
698 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
699 | { | |
72e1dcc4 JR |
700 | u32 head, tail; |
701 | ||
702 | if (iommu->ppr_log == NULL) | |
703 | return; | |
704 | ||
72e1dcc4 JR |
705 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
706 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
707 | ||
708 | while (head != tail) { | |
eee53537 JR |
709 | volatile u64 *raw; |
710 | u64 entry[2]; | |
711 | int i; | |
712 | ||
713 | raw = (u64 *)(iommu->ppr_log + head); | |
714 | ||
715 | /* | |
716 | * Hardware bug: Interrupt may arrive before the entry is | |
717 | * written to memory. If this happens we need to wait for the | |
718 | * entry to arrive. | |
719 | */ | |
720 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
721 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
722 | break; | |
723 | udelay(1); | |
724 | } | |
72e1dcc4 | 725 | |
eee53537 JR |
726 | /* Avoid memcpy function-call overhead */ |
727 | entry[0] = raw[0]; | |
728 | entry[1] = raw[1]; | |
72e1dcc4 | 729 | |
eee53537 JR |
730 | /* |
731 | * To detect the hardware bug we need to clear the entry | |
732 | * back to zero. | |
733 | */ | |
734 | raw[0] = raw[1] = 0UL; | |
735 | ||
736 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
737 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
738 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 739 | |
eee53537 JR |
740 | /* Handle PPR entry */ |
741 | iommu_handle_ppr_entry(iommu, entry); | |
742 | ||
eee53537 JR |
743 | /* Refresh ring-buffer information */ |
744 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
745 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
746 | } | |
72e1dcc4 JR |
747 | } |
748 | ||
72fe00f0 | 749 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 750 | { |
3f398bc7 SS |
751 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
752 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 753 | |
3f398bc7 SS |
754 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
755 | /* Enable EVT and PPR interrupts again */ | |
756 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
757 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 758 | |
3f398bc7 SS |
759 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
760 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
761 | iommu_poll_events(iommu); | |
762 | } | |
90008ee4 | 763 | |
3f398bc7 SS |
764 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
765 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
766 | iommu_poll_ppr_log(iommu); | |
767 | } | |
90008ee4 | 768 | |
3f398bc7 SS |
769 | /* |
770 | * Hardware bug: ERBT1312 | |
771 | * When re-enabling interrupt (by writing 1 | |
772 | * to clear the bit), the hardware might also try to set | |
773 | * the interrupt bit in the event status register. | |
774 | * In this scenario, the bit will be set, and disable | |
775 | * subsequent interrupts. | |
776 | * | |
777 | * Workaround: The IOMMU driver should read back the | |
778 | * status register and check if the interrupt bits are cleared. | |
779 | * If not, driver will need to go through the interrupt handler | |
780 | * again and re-clear the bits | |
781 | */ | |
782 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
783 | } | |
90008ee4 | 784 | return IRQ_HANDLED; |
a80dc3e0 JR |
785 | } |
786 | ||
72fe00f0 JR |
787 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
788 | { | |
789 | return IRQ_WAKE_THREAD; | |
790 | } | |
791 | ||
431b2a20 JR |
792 | /**************************************************************************** |
793 | * | |
794 | * IOMMU command queuing functions | |
795 | * | |
796 | ****************************************************************************/ | |
797 | ||
ac0ea6e9 JR |
798 | static int wait_on_sem(volatile u64 *sem) |
799 | { | |
800 | int i = 0; | |
801 | ||
802 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
803 | udelay(1); | |
804 | i += 1; | |
805 | } | |
806 | ||
807 | if (i == LOOP_TIMEOUT) { | |
808 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
809 | return -EIO; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
816 | struct iommu_cmd *cmd, | |
817 | u32 tail) | |
a19ae1ec | 818 | { |
a19ae1ec JR |
819 | u8 *target; |
820 | ||
8a7c5ef3 | 821 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
822 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
823 | ||
824 | /* Copy command to buffer */ | |
825 | memcpy(target, cmd, sizeof(*cmd)); | |
826 | ||
827 | /* Tell the IOMMU about it */ | |
a19ae1ec | 828 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 829 | } |
a19ae1ec | 830 | |
815b33fd | 831 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 832 | { |
815b33fd JR |
833 | WARN_ON(address & 0x7ULL); |
834 | ||
ded46737 | 835 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
836 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
837 | cmd->data[1] = upper_32_bits(__pa(address)); | |
838 | cmd->data[2] = 1; | |
ded46737 JR |
839 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
840 | } | |
841 | ||
94fe79e2 JR |
842 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
843 | { | |
844 | memset(cmd, 0, sizeof(*cmd)); | |
845 | cmd->data[0] = devid; | |
846 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
847 | } | |
848 | ||
11b6402c JR |
849 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
850 | size_t size, u16 domid, int pde) | |
851 | { | |
852 | u64 pages; | |
ae0cbbb1 | 853 | bool s; |
11b6402c JR |
854 | |
855 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 856 | s = false; |
11b6402c JR |
857 | |
858 | if (pages > 1) { | |
859 | /* | |
860 | * If we have to flush more than one page, flush all | |
861 | * TLB entries for this domain | |
862 | */ | |
863 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 864 | s = true; |
11b6402c JR |
865 | } |
866 | ||
867 | address &= PAGE_MASK; | |
868 | ||
869 | memset(cmd, 0, sizeof(*cmd)); | |
870 | cmd->data[1] |= domid; | |
871 | cmd->data[2] = lower_32_bits(address); | |
872 | cmd->data[3] = upper_32_bits(address); | |
873 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
874 | if (s) /* size bit - we flush more than one 4kb page */ | |
875 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 876 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
877 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
878 | } | |
879 | ||
cb41ed85 JR |
880 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
881 | u64 address, size_t size) | |
882 | { | |
883 | u64 pages; | |
ae0cbbb1 | 884 | bool s; |
cb41ed85 JR |
885 | |
886 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 887 | s = false; |
cb41ed85 JR |
888 | |
889 | if (pages > 1) { | |
890 | /* | |
891 | * If we have to flush more than one page, flush all | |
892 | * TLB entries for this domain | |
893 | */ | |
894 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 895 | s = true; |
cb41ed85 JR |
896 | } |
897 | ||
898 | address &= PAGE_MASK; | |
899 | ||
900 | memset(cmd, 0, sizeof(*cmd)); | |
901 | cmd->data[0] = devid; | |
902 | cmd->data[0] |= (qdep & 0xff) << 24; | |
903 | cmd->data[1] = devid; | |
904 | cmd->data[2] = lower_32_bits(address); | |
905 | cmd->data[3] = upper_32_bits(address); | |
906 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
907 | if (s) | |
908 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
909 | } | |
910 | ||
22e266c7 JR |
911 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
912 | u64 address, bool size) | |
913 | { | |
914 | memset(cmd, 0, sizeof(*cmd)); | |
915 | ||
916 | address &= ~(0xfffULL); | |
917 | ||
a919a018 | 918 | cmd->data[0] = pasid; |
22e266c7 JR |
919 | cmd->data[1] = domid; |
920 | cmd->data[2] = lower_32_bits(address); | |
921 | cmd->data[3] = upper_32_bits(address); | |
922 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
923 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
924 | if (size) | |
925 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
926 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
927 | } | |
928 | ||
929 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
930 | int qdep, u64 address, bool size) | |
931 | { | |
932 | memset(cmd, 0, sizeof(*cmd)); | |
933 | ||
934 | address &= ~(0xfffULL); | |
935 | ||
936 | cmd->data[0] = devid; | |
e8d2d82d | 937 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
938 | cmd->data[0] |= (qdep & 0xff) << 24; |
939 | cmd->data[1] = devid; | |
e8d2d82d | 940 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
941 | cmd->data[2] = lower_32_bits(address); |
942 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
943 | cmd->data[3] = upper_32_bits(address); | |
944 | if (size) | |
945 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
946 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
947 | } | |
948 | ||
c99afa25 JR |
949 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
950 | int status, int tag, bool gn) | |
951 | { | |
952 | memset(cmd, 0, sizeof(*cmd)); | |
953 | ||
954 | cmd->data[0] = devid; | |
955 | if (gn) { | |
a919a018 | 956 | cmd->data[1] = pasid; |
c99afa25 JR |
957 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
958 | } | |
959 | cmd->data[3] = tag & 0x1ff; | |
960 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
961 | ||
962 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
963 | } | |
964 | ||
58fc7f14 JR |
965 | static void build_inv_all(struct iommu_cmd *cmd) |
966 | { | |
967 | memset(cmd, 0, sizeof(*cmd)); | |
968 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
969 | } |
970 | ||
7ef2798d JR |
971 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
972 | { | |
973 | memset(cmd, 0, sizeof(*cmd)); | |
974 | cmd->data[0] = devid; | |
975 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
976 | } | |
977 | ||
431b2a20 | 978 | /* |
431b2a20 | 979 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 980 | * hardware about the new command. |
431b2a20 | 981 | */ |
f1ca1512 JR |
982 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
983 | struct iommu_cmd *cmd, | |
984 | bool sync) | |
a19ae1ec | 985 | { |
ac0ea6e9 | 986 | u32 left, tail, head, next_tail; |
a19ae1ec | 987 | unsigned long flags; |
a19ae1ec | 988 | |
549c90dc | 989 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
990 | |
991 | again: | |
a19ae1ec | 992 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 993 | |
ac0ea6e9 JR |
994 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
995 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
996 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
997 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 998 | |
ac0ea6e9 JR |
999 | if (left <= 2) { |
1000 | struct iommu_cmd sync_cmd; | |
1001 | volatile u64 sem = 0; | |
1002 | int ret; | |
8d201968 | 1003 | |
ac0ea6e9 JR |
1004 | build_completion_wait(&sync_cmd, (u64)&sem); |
1005 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1006 | |
ac0ea6e9 JR |
1007 | spin_unlock_irqrestore(&iommu->lock, flags); |
1008 | ||
1009 | if ((ret = wait_on_sem(&sem)) != 0) | |
1010 | return ret; | |
1011 | ||
1012 | goto again; | |
8d201968 JR |
1013 | } |
1014 | ||
ac0ea6e9 JR |
1015 | copy_cmd_to_buffer(iommu, cmd, tail); |
1016 | ||
1017 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1018 | iommu->need_sync = sync; |
ac0ea6e9 | 1019 | |
a19ae1ec | 1020 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1021 | |
815b33fd | 1022 | return 0; |
8d201968 JR |
1023 | } |
1024 | ||
f1ca1512 JR |
1025 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1026 | { | |
1027 | return iommu_queue_command_sync(iommu, cmd, true); | |
1028 | } | |
1029 | ||
8d201968 JR |
1030 | /* |
1031 | * This function queues a completion wait command into the command | |
1032 | * buffer of an IOMMU | |
1033 | */ | |
a19ae1ec | 1034 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1035 | { |
1036 | struct iommu_cmd cmd; | |
815b33fd | 1037 | volatile u64 sem = 0; |
ac0ea6e9 | 1038 | int ret; |
8d201968 | 1039 | |
09ee17eb | 1040 | if (!iommu->need_sync) |
815b33fd | 1041 | return 0; |
09ee17eb | 1042 | |
815b33fd | 1043 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1044 | |
f1ca1512 | 1045 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1046 | if (ret) |
815b33fd | 1047 | return ret; |
8d201968 | 1048 | |
ac0ea6e9 | 1049 | return wait_on_sem(&sem); |
8d201968 JR |
1050 | } |
1051 | ||
d8c13085 | 1052 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1053 | { |
d8c13085 | 1054 | struct iommu_cmd cmd; |
a19ae1ec | 1055 | |
d8c13085 | 1056 | build_inv_dte(&cmd, devid); |
7e4f88da | 1057 | |
d8c13085 JR |
1058 | return iommu_queue_command(iommu, &cmd); |
1059 | } | |
09ee17eb | 1060 | |
7d0c5cc5 JR |
1061 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1062 | { | |
1063 | u32 devid; | |
09ee17eb | 1064 | |
7d0c5cc5 JR |
1065 | for (devid = 0; devid <= 0xffff; ++devid) |
1066 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1067 | |
7d0c5cc5 JR |
1068 | iommu_completion_wait(iommu); |
1069 | } | |
84df8175 | 1070 | |
7d0c5cc5 JR |
1071 | /* |
1072 | * This function uses heavy locking and may disable irqs for some time. But | |
1073 | * this is no issue because it is only called during resume. | |
1074 | */ | |
1075 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1076 | { | |
1077 | u32 dom_id; | |
a19ae1ec | 1078 | |
7d0c5cc5 JR |
1079 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1080 | struct iommu_cmd cmd; | |
1081 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1082 | dom_id, 1); | |
1083 | iommu_queue_command(iommu, &cmd); | |
1084 | } | |
8eed9833 | 1085 | |
7d0c5cc5 | 1086 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1087 | } |
1088 | ||
58fc7f14 | 1089 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1090 | { |
58fc7f14 | 1091 | struct iommu_cmd cmd; |
0518a3a4 | 1092 | |
58fc7f14 | 1093 | build_inv_all(&cmd); |
0518a3a4 | 1094 | |
58fc7f14 JR |
1095 | iommu_queue_command(iommu, &cmd); |
1096 | iommu_completion_wait(iommu); | |
1097 | } | |
1098 | ||
7ef2798d JR |
1099 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1100 | { | |
1101 | struct iommu_cmd cmd; | |
1102 | ||
1103 | build_inv_irt(&cmd, devid); | |
1104 | ||
1105 | iommu_queue_command(iommu, &cmd); | |
1106 | } | |
1107 | ||
1108 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1109 | { | |
1110 | u32 devid; | |
1111 | ||
1112 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1113 | iommu_flush_irt(iommu, devid); | |
1114 | ||
1115 | iommu_completion_wait(iommu); | |
1116 | } | |
1117 | ||
7d0c5cc5 JR |
1118 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1119 | { | |
58fc7f14 JR |
1120 | if (iommu_feature(iommu, FEATURE_IA)) { |
1121 | iommu_flush_all(iommu); | |
1122 | } else { | |
1123 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1124 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1125 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1126 | } |
1127 | } | |
1128 | ||
431b2a20 | 1129 | /* |
cb41ed85 | 1130 | * Command send function for flushing on-device TLB |
431b2a20 | 1131 | */ |
6c542047 JR |
1132 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1133 | u64 address, size_t size) | |
3fa43655 JR |
1134 | { |
1135 | struct amd_iommu *iommu; | |
b00d3bcf | 1136 | struct iommu_cmd cmd; |
cb41ed85 | 1137 | int qdep; |
3fa43655 | 1138 | |
ea61cddb JR |
1139 | qdep = dev_data->ats.qdep; |
1140 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1141 | |
ea61cddb | 1142 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1143 | |
1144 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1145 | } |
1146 | ||
431b2a20 | 1147 | /* |
431b2a20 | 1148 | * Command send function for invalidating a device table entry |
431b2a20 | 1149 | */ |
6c542047 | 1150 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1151 | { |
3fa43655 | 1152 | struct amd_iommu *iommu; |
ee2fa743 | 1153 | int ret; |
a19ae1ec | 1154 | |
6c542047 | 1155 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1156 | |
f62dda66 | 1157 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1158 | if (ret) |
1159 | return ret; | |
1160 | ||
ea61cddb | 1161 | if (dev_data->ats.enabled) |
6c542047 | 1162 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1163 | |
ee2fa743 | 1164 | return ret; |
a19ae1ec JR |
1165 | } |
1166 | ||
431b2a20 JR |
1167 | /* |
1168 | * TLB invalidation function which is called from the mapping functions. | |
1169 | * It invalidates a single PTE if the range to flush is within a single | |
1170 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1171 | */ | |
17b124bf JR |
1172 | static void __domain_flush_pages(struct protection_domain *domain, |
1173 | u64 address, size_t size, int pde) | |
a19ae1ec | 1174 | { |
cb41ed85 | 1175 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1176 | struct iommu_cmd cmd; |
1177 | int ret = 0, i; | |
a19ae1ec | 1178 | |
11b6402c | 1179 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1180 | |
6de8ad9b JR |
1181 | for (i = 0; i < amd_iommus_present; ++i) { |
1182 | if (!domain->dev_iommu[i]) | |
1183 | continue; | |
1184 | ||
1185 | /* | |
1186 | * Devices of this domain are behind this IOMMU | |
1187 | * We need a TLB flush | |
1188 | */ | |
11b6402c | 1189 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1190 | } |
1191 | ||
cb41ed85 | 1192 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1193 | |
ea61cddb | 1194 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1195 | continue; |
1196 | ||
6c542047 | 1197 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1198 | } |
1199 | ||
11b6402c | 1200 | WARN_ON(ret); |
6de8ad9b JR |
1201 | } |
1202 | ||
17b124bf JR |
1203 | static void domain_flush_pages(struct protection_domain *domain, |
1204 | u64 address, size_t size) | |
6de8ad9b | 1205 | { |
17b124bf | 1206 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1207 | } |
b6c02715 | 1208 | |
1c655773 | 1209 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1210 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1211 | { |
17b124bf | 1212 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1213 | } |
1214 | ||
42a49f96 | 1215 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1216 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1217 | { |
17b124bf | 1218 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1219 | } |
1220 | ||
17b124bf | 1221 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1222 | { |
17b124bf | 1223 | int i; |
18811f55 | 1224 | |
17b124bf JR |
1225 | for (i = 0; i < amd_iommus_present; ++i) { |
1226 | if (!domain->dev_iommu[i]) | |
1227 | continue; | |
bfd1be18 | 1228 | |
17b124bf JR |
1229 | /* |
1230 | * Devices of this domain are behind this IOMMU | |
1231 | * We need to wait for completion of all commands. | |
1232 | */ | |
1233 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1234 | } |
e394d72a JR |
1235 | } |
1236 | ||
b00d3bcf | 1237 | |
09b42804 | 1238 | /* |
b00d3bcf | 1239 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1240 | */ |
17b124bf | 1241 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1242 | { |
b00d3bcf | 1243 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1244 | |
b00d3bcf | 1245 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1246 | device_flush_dte(dev_data); |
a345b23b JR |
1247 | } |
1248 | ||
431b2a20 JR |
1249 | /**************************************************************************** |
1250 | * | |
1251 | * The functions below are used the create the page table mappings for | |
1252 | * unity mapped regions. | |
1253 | * | |
1254 | ****************************************************************************/ | |
1255 | ||
308973d3 JR |
1256 | /* |
1257 | * This function is used to add another level to an IO page table. Adding | |
1258 | * another level increases the size of the address space by 9 bits to a size up | |
1259 | * to 64 bits. | |
1260 | */ | |
1261 | static bool increase_address_space(struct protection_domain *domain, | |
1262 | gfp_t gfp) | |
1263 | { | |
1264 | u64 *pte; | |
1265 | ||
1266 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1267 | /* address space already 64 bit large */ | |
1268 | return false; | |
1269 | ||
1270 | pte = (void *)get_zeroed_page(gfp); | |
1271 | if (!pte) | |
1272 | return false; | |
1273 | ||
1274 | *pte = PM_LEVEL_PDE(domain->mode, | |
1275 | virt_to_phys(domain->pt_root)); | |
1276 | domain->pt_root = pte; | |
1277 | domain->mode += 1; | |
1278 | domain->updated = true; | |
1279 | ||
1280 | return true; | |
1281 | } | |
1282 | ||
1283 | static u64 *alloc_pte(struct protection_domain *domain, | |
1284 | unsigned long address, | |
cbb9d729 | 1285 | unsigned long page_size, |
308973d3 JR |
1286 | u64 **pte_page, |
1287 | gfp_t gfp) | |
1288 | { | |
cbb9d729 | 1289 | int level, end_lvl; |
308973d3 | 1290 | u64 *pte, *page; |
cbb9d729 JR |
1291 | |
1292 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1293 | |
1294 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1295 | increase_address_space(domain, gfp); | |
1296 | ||
cbb9d729 JR |
1297 | level = domain->mode - 1; |
1298 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1299 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1300 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1301 | |
1302 | while (level > end_lvl) { | |
1303 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1304 | page = (u64 *)get_zeroed_page(gfp); | |
1305 | if (!page) | |
1306 | return NULL; | |
1307 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1308 | } | |
1309 | ||
cbb9d729 JR |
1310 | /* No level skipping support yet */ |
1311 | if (PM_PTE_LEVEL(*pte) != level) | |
1312 | return NULL; | |
1313 | ||
308973d3 JR |
1314 | level -= 1; |
1315 | ||
1316 | pte = IOMMU_PTE_PAGE(*pte); | |
1317 | ||
1318 | if (pte_page && level == end_lvl) | |
1319 | *pte_page = pte; | |
1320 | ||
1321 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1322 | } | |
1323 | ||
1324 | return pte; | |
1325 | } | |
1326 | ||
1327 | /* | |
1328 | * This function checks if there is a PTE for a given dma address. If | |
1329 | * there is one, it returns the pointer to it. | |
1330 | */ | |
3039ca1b JR |
1331 | static u64 *fetch_pte(struct protection_domain *domain, |
1332 | unsigned long address, | |
1333 | unsigned long *page_size) | |
308973d3 JR |
1334 | { |
1335 | int level; | |
1336 | u64 *pte; | |
1337 | ||
24cd7723 JR |
1338 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1339 | return NULL; | |
1340 | ||
3039ca1b JR |
1341 | level = domain->mode - 1; |
1342 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1343 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1344 | |
24cd7723 JR |
1345 | while (level > 0) { |
1346 | ||
1347 | /* Not Present */ | |
308973d3 JR |
1348 | if (!IOMMU_PTE_PRESENT(*pte)) |
1349 | return NULL; | |
1350 | ||
24cd7723 | 1351 | /* Large PTE */ |
3039ca1b JR |
1352 | if (PM_PTE_LEVEL(*pte) == 7 || |
1353 | PM_PTE_LEVEL(*pte) == 0) | |
1354 | break; | |
24cd7723 JR |
1355 | |
1356 | /* No level skipping support yet */ | |
1357 | if (PM_PTE_LEVEL(*pte) != level) | |
1358 | return NULL; | |
1359 | ||
308973d3 JR |
1360 | level -= 1; |
1361 | ||
24cd7723 | 1362 | /* Walk to the next level */ |
3039ca1b JR |
1363 | pte = IOMMU_PTE_PAGE(*pte); |
1364 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1365 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1366 | } | |
1367 | ||
1368 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1369 | unsigned long pte_mask; | |
1370 | ||
1371 | /* | |
1372 | * If we have a series of large PTEs, make | |
1373 | * sure to return a pointer to the first one. | |
1374 | */ | |
1375 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1376 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1377 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1378 | } |
1379 | ||
1380 | return pte; | |
1381 | } | |
1382 | ||
431b2a20 JR |
1383 | /* |
1384 | * Generic mapping functions. It maps a physical address into a DMA | |
1385 | * address space. It allocates the page table pages if necessary. | |
1386 | * In the future it can be extended to a generic mapping function | |
1387 | * supporting all features of AMD IOMMU page tables like level skipping | |
1388 | * and full 64 bit address spaces. | |
1389 | */ | |
38e817fe JR |
1390 | static int iommu_map_page(struct protection_domain *dom, |
1391 | unsigned long bus_addr, | |
1392 | unsigned long phys_addr, | |
abdc5eb3 | 1393 | int prot, |
cbb9d729 | 1394 | unsigned long page_size) |
bd0e5211 | 1395 | { |
8bda3092 | 1396 | u64 __pte, *pte; |
cbb9d729 | 1397 | int i, count; |
abdc5eb3 | 1398 | |
d4b03664 JR |
1399 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1400 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1401 | ||
bad1cac2 | 1402 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1403 | return -EINVAL; |
1404 | ||
d4b03664 JR |
1405 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1406 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1407 | |
63eaa75e ML |
1408 | if (!pte) |
1409 | return -ENOMEM; | |
1410 | ||
cbb9d729 JR |
1411 | for (i = 0; i < count; ++i) |
1412 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1413 | return -EBUSY; | |
bd0e5211 | 1414 | |
d4b03664 | 1415 | if (count > 1) { |
cbb9d729 JR |
1416 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1417 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1418 | } else | |
1419 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1420 | |
bd0e5211 JR |
1421 | if (prot & IOMMU_PROT_IR) |
1422 | __pte |= IOMMU_PTE_IR; | |
1423 | if (prot & IOMMU_PROT_IW) | |
1424 | __pte |= IOMMU_PTE_IW; | |
1425 | ||
cbb9d729 JR |
1426 | for (i = 0; i < count; ++i) |
1427 | pte[i] = __pte; | |
bd0e5211 | 1428 | |
04bfdd84 JR |
1429 | update_domain(dom); |
1430 | ||
bd0e5211 JR |
1431 | return 0; |
1432 | } | |
1433 | ||
24cd7723 JR |
1434 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1435 | unsigned long bus_addr, | |
1436 | unsigned long page_size) | |
eb74ff6c | 1437 | { |
71b390e9 JR |
1438 | unsigned long long unmapped; |
1439 | unsigned long unmap_size; | |
24cd7723 JR |
1440 | u64 *pte; |
1441 | ||
1442 | BUG_ON(!is_power_of_2(page_size)); | |
1443 | ||
1444 | unmapped = 0; | |
eb74ff6c | 1445 | |
24cd7723 JR |
1446 | while (unmapped < page_size) { |
1447 | ||
71b390e9 JR |
1448 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1449 | ||
1450 | if (pte) { | |
1451 | int i, count; | |
1452 | ||
1453 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1454 | for (i = 0; i < count; i++) |
1455 | pte[i] = 0ULL; | |
1456 | } | |
1457 | ||
1458 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1459 | unmapped += unmap_size; | |
1460 | } | |
1461 | ||
60d0ca3c | 1462 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1463 | |
24cd7723 | 1464 | return unmapped; |
eb74ff6c | 1465 | } |
eb74ff6c | 1466 | |
431b2a20 JR |
1467 | /* |
1468 | * This function checks if a specific unity mapping entry is needed for | |
1469 | * this specific IOMMU. | |
1470 | */ | |
bd0e5211 JR |
1471 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1472 | struct unity_map_entry *entry) | |
1473 | { | |
1474 | u16 bdf, i; | |
1475 | ||
1476 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1477 | bdf = amd_iommu_alias_table[i]; | |
1478 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1479 | return 1; | |
1480 | } | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
431b2a20 JR |
1485 | /* |
1486 | * This function actually applies the mapping to the page table of the | |
1487 | * dma_ops domain. | |
1488 | */ | |
bd0e5211 JR |
1489 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1490 | struct unity_map_entry *e) | |
1491 | { | |
1492 | u64 addr; | |
1493 | int ret; | |
1494 | ||
1495 | for (addr = e->address_start; addr < e->address_end; | |
1496 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1497 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1498 | PAGE_SIZE); |
bd0e5211 JR |
1499 | if (ret) |
1500 | return ret; | |
1501 | /* | |
1502 | * if unity mapping is in aperture range mark the page | |
1503 | * as allocated in the aperture | |
1504 | */ | |
1505 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1506 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1507 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1508 | } |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
171e7b37 JR |
1513 | /* |
1514 | * Init the unity mappings for a specific IOMMU in the system | |
1515 | * | |
1516 | * Basically iterates over all unity mapping entries and applies them to | |
1517 | * the default domain DMA of that IOMMU if necessary. | |
1518 | */ | |
1519 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1520 | { | |
1521 | struct unity_map_entry *entry; | |
1522 | int ret; | |
1523 | ||
1524 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1525 | if (!iommu_for_unity_map(iommu, entry)) | |
1526 | continue; | |
1527 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1528 | if (ret) | |
1529 | return ret; | |
1530 | } | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
431b2a20 JR |
1535 | /* |
1536 | * Inits the unity mappings required for a specific device | |
1537 | */ | |
bd0e5211 JR |
1538 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1539 | u16 devid) | |
1540 | { | |
1541 | struct unity_map_entry *e; | |
1542 | int ret; | |
1543 | ||
1544 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1545 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1546 | continue; | |
1547 | ret = dma_ops_unity_map(dma_dom, e); | |
1548 | if (ret) | |
1549 | return ret; | |
1550 | } | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
431b2a20 JR |
1555 | /**************************************************************************** |
1556 | * | |
1557 | * The next functions belong to the address allocator for the dma_ops | |
1558 | * interface functions. They work like the allocators in the other IOMMU | |
1559 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1560 | * the aperture. Maybe it could be enhanced in the future to a more | |
1561 | * efficient allocator. | |
1562 | * | |
1563 | ****************************************************************************/ | |
d3086444 | 1564 | |
431b2a20 | 1565 | /* |
384de729 | 1566 | * The address allocator core functions. |
431b2a20 JR |
1567 | * |
1568 | * called with domain->lock held | |
1569 | */ | |
384de729 | 1570 | |
171e7b37 JR |
1571 | /* |
1572 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1573 | * ranges. | |
1574 | */ | |
1575 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1576 | unsigned long start_page, | |
1577 | unsigned int pages) | |
1578 | { | |
1579 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1580 | ||
1581 | if (start_page + pages > last_page) | |
1582 | pages = last_page - start_page; | |
1583 | ||
1584 | for (i = start_page; i < start_page + pages; ++i) { | |
1585 | int index = i / APERTURE_RANGE_PAGES; | |
1586 | int page = i % APERTURE_RANGE_PAGES; | |
1587 | __set_bit(page, dom->aperture[index]->bitmap); | |
1588 | } | |
1589 | } | |
1590 | ||
9cabe89b JR |
1591 | /* |
1592 | * This function is used to add a new aperture range to an existing | |
1593 | * aperture in case of dma_ops domain allocation or address allocation | |
1594 | * failure. | |
1595 | */ | |
576175c2 | 1596 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1597 | bool populate, gfp_t gfp) |
1598 | { | |
1599 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1600 | struct amd_iommu *iommu; |
5d7c94c3 | 1601 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1602 | |
f5e9705c JR |
1603 | #ifdef CONFIG_IOMMU_STRESS |
1604 | populate = false; | |
1605 | #endif | |
1606 | ||
9cabe89b JR |
1607 | if (index >= APERTURE_MAX_RANGES) |
1608 | return -ENOMEM; | |
1609 | ||
1610 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1611 | if (!dma_dom->aperture[index]) | |
1612 | return -ENOMEM; | |
1613 | ||
1614 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1615 | if (!dma_dom->aperture[index]->bitmap) | |
1616 | goto out_free; | |
1617 | ||
1618 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1619 | ||
1620 | if (populate) { | |
1621 | unsigned long address = dma_dom->aperture_size; | |
1622 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1623 | u64 *pte, *pte_page; | |
1624 | ||
1625 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1626 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1627 | &pte_page, gfp); |
1628 | if (!pte) | |
1629 | goto out_free; | |
1630 | ||
1631 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1632 | ||
1633 | address += APERTURE_RANGE_SIZE / 64; | |
1634 | } | |
1635 | } | |
1636 | ||
17f5b569 | 1637 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1638 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1639 | ||
17f5b569 JR |
1640 | /* Reserve address range used for MSI messages */ |
1641 | if (old_size < MSI_ADDR_BASE_LO && | |
1642 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1643 | unsigned long spage; | |
1644 | int pages; | |
1645 | ||
1646 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1647 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1648 | ||
1649 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1650 | } | |
1651 | ||
b595076a | 1652 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1653 | for_each_iommu(iommu) { |
1654 | if (iommu->exclusion_start && | |
1655 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1656 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1657 | unsigned long startpage; | |
1658 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1659 | iommu->exclusion_length, | |
1660 | PAGE_SIZE); | |
1661 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1662 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1663 | } | |
00cd122a JR |
1664 | } |
1665 | ||
1666 | /* | |
1667 | * Check for areas already mapped as present in the new aperture | |
1668 | * range and mark those pages as reserved in the allocator. Such | |
1669 | * mappings may already exist as a result of requested unity | |
1670 | * mappings for devices. | |
1671 | */ | |
1672 | for (i = dma_dom->aperture[index]->offset; | |
1673 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1674 | i += pte_pgsize) { |
3039ca1b | 1675 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1676 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1677 | continue; | |
1678 | ||
5d7c94c3 JR |
1679 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1680 | pte_pgsize >> 12); | |
00cd122a JR |
1681 | } |
1682 | ||
04bfdd84 JR |
1683 | update_domain(&dma_dom->domain); |
1684 | ||
9cabe89b JR |
1685 | return 0; |
1686 | ||
1687 | out_free: | |
04bfdd84 JR |
1688 | update_domain(&dma_dom->domain); |
1689 | ||
9cabe89b JR |
1690 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1691 | ||
1692 | kfree(dma_dom->aperture[index]); | |
1693 | dma_dom->aperture[index] = NULL; | |
1694 | ||
1695 | return -ENOMEM; | |
1696 | } | |
1697 | ||
384de729 JR |
1698 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1699 | struct dma_ops_domain *dom, | |
1700 | unsigned int pages, | |
1701 | unsigned long align_mask, | |
1702 | u64 dma_mask, | |
1703 | unsigned long start) | |
1704 | { | |
803b8cb4 | 1705 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1706 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1707 | int i = start >> APERTURE_RANGE_SHIFT; | |
1708 | unsigned long boundary_size; | |
1709 | unsigned long address = -1; | |
1710 | unsigned long limit; | |
1711 | ||
803b8cb4 JR |
1712 | next_bit >>= PAGE_SHIFT; |
1713 | ||
384de729 JR |
1714 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1715 | PAGE_SIZE) >> PAGE_SHIFT; | |
1716 | ||
1717 | for (;i < max_index; ++i) { | |
1718 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1719 | ||
1720 | if (dom->aperture[i]->offset >= dma_mask) | |
1721 | break; | |
1722 | ||
1723 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1724 | dma_mask >> PAGE_SHIFT); | |
1725 | ||
1726 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1727 | limit, next_bit, pages, 0, | |
1728 | boundary_size, align_mask); | |
1729 | if (address != -1) { | |
1730 | address = dom->aperture[i]->offset + | |
1731 | (address << PAGE_SHIFT); | |
803b8cb4 | 1732 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1733 | break; |
1734 | } | |
1735 | ||
1736 | next_bit = 0; | |
1737 | } | |
1738 | ||
1739 | return address; | |
1740 | } | |
1741 | ||
d3086444 JR |
1742 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1743 | struct dma_ops_domain *dom, | |
6d4f343f | 1744 | unsigned int pages, |
832a90c3 JR |
1745 | unsigned long align_mask, |
1746 | u64 dma_mask) | |
d3086444 | 1747 | { |
d3086444 | 1748 | unsigned long address; |
d3086444 | 1749 | |
fe16f088 JR |
1750 | #ifdef CONFIG_IOMMU_STRESS |
1751 | dom->next_address = 0; | |
1752 | dom->need_flush = true; | |
1753 | #endif | |
d3086444 | 1754 | |
384de729 | 1755 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1756 | dma_mask, dom->next_address); |
d3086444 | 1757 | |
1c655773 | 1758 | if (address == -1) { |
803b8cb4 | 1759 | dom->next_address = 0; |
384de729 JR |
1760 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1761 | dma_mask, 0); | |
1c655773 JR |
1762 | dom->need_flush = true; |
1763 | } | |
d3086444 | 1764 | |
384de729 | 1765 | if (unlikely(address == -1)) |
8fd524b3 | 1766 | address = DMA_ERROR_CODE; |
d3086444 JR |
1767 | |
1768 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1769 | ||
1770 | return address; | |
1771 | } | |
1772 | ||
431b2a20 JR |
1773 | /* |
1774 | * The address free function. | |
1775 | * | |
1776 | * called with domain->lock held | |
1777 | */ | |
d3086444 JR |
1778 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1779 | unsigned long address, | |
1780 | unsigned int pages) | |
1781 | { | |
384de729 JR |
1782 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1783 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1784 | |
384de729 JR |
1785 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1786 | ||
47bccd6b JR |
1787 | #ifdef CONFIG_IOMMU_STRESS |
1788 | if (i < 4) | |
1789 | return; | |
1790 | #endif | |
80be308d | 1791 | |
803b8cb4 | 1792 | if (address >= dom->next_address) |
80be308d | 1793 | dom->need_flush = true; |
384de729 JR |
1794 | |
1795 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1796 | |
a66022c4 | 1797 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1798 | |
d3086444 JR |
1799 | } |
1800 | ||
431b2a20 JR |
1801 | /**************************************************************************** |
1802 | * | |
1803 | * The next functions belong to the domain allocation. A domain is | |
1804 | * allocated for every IOMMU as the default domain. If device isolation | |
1805 | * is enabled, every device get its own domain. The most important thing | |
1806 | * about domains is the page table mapping the DMA address space they | |
1807 | * contain. | |
1808 | * | |
1809 | ****************************************************************************/ | |
1810 | ||
aeb26f55 JR |
1811 | /* |
1812 | * This function adds a protection domain to the global protection domain list | |
1813 | */ | |
1814 | static void add_domain_to_list(struct protection_domain *domain) | |
1815 | { | |
1816 | unsigned long flags; | |
1817 | ||
1818 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1819 | list_add(&domain->list, &amd_iommu_pd_list); | |
1820 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1821 | } | |
1822 | ||
1823 | /* | |
1824 | * This function removes a protection domain to the global | |
1825 | * protection domain list | |
1826 | */ | |
1827 | static void del_domain_from_list(struct protection_domain *domain) | |
1828 | { | |
1829 | unsigned long flags; | |
1830 | ||
1831 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1832 | list_del(&domain->list); | |
1833 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1834 | } | |
1835 | ||
ec487d1a JR |
1836 | static u16 domain_id_alloc(void) |
1837 | { | |
1838 | unsigned long flags; | |
1839 | int id; | |
1840 | ||
1841 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1842 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1843 | BUG_ON(id == 0); | |
1844 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1845 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1846 | else | |
1847 | id = 0; | |
1848 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1849 | ||
1850 | return id; | |
1851 | } | |
1852 | ||
a2acfb75 JR |
1853 | static void domain_id_free(int id) |
1854 | { | |
1855 | unsigned long flags; | |
1856 | ||
1857 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1858 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1859 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1860 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1861 | } | |
a2acfb75 | 1862 | |
5c34c403 JR |
1863 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1864 | static void free_pt_##LVL (unsigned long __pt) \ | |
1865 | { \ | |
1866 | unsigned long p; \ | |
1867 | u64 *pt; \ | |
1868 | int i; \ | |
1869 | \ | |
1870 | pt = (u64 *)__pt; \ | |
1871 | \ | |
1872 | for (i = 0; i < 512; ++i) { \ | |
1873 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1874 | continue; \ | |
1875 | \ | |
1876 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1877 | FN(p); \ | |
1878 | } \ | |
1879 | free_page((unsigned long)pt); \ | |
1880 | } | |
1881 | ||
1882 | DEFINE_FREE_PT_FN(l2, free_page) | |
1883 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1884 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1885 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1886 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1887 | ||
86db2e5d | 1888 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1889 | { |
5c34c403 | 1890 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1891 | |
5c34c403 JR |
1892 | switch (domain->mode) { |
1893 | case PAGE_MODE_NONE: | |
1894 | break; | |
1895 | case PAGE_MODE_1_LEVEL: | |
1896 | free_page(root); | |
1897 | break; | |
1898 | case PAGE_MODE_2_LEVEL: | |
1899 | free_pt_l2(root); | |
1900 | break; | |
1901 | case PAGE_MODE_3_LEVEL: | |
1902 | free_pt_l3(root); | |
1903 | break; | |
1904 | case PAGE_MODE_4_LEVEL: | |
1905 | free_pt_l4(root); | |
1906 | break; | |
1907 | case PAGE_MODE_5_LEVEL: | |
1908 | free_pt_l5(root); | |
1909 | break; | |
1910 | case PAGE_MODE_6_LEVEL: | |
1911 | free_pt_l6(root); | |
1912 | break; | |
1913 | default: | |
1914 | BUG(); | |
ec487d1a | 1915 | } |
ec487d1a JR |
1916 | } |
1917 | ||
b16137b1 JR |
1918 | static void free_gcr3_tbl_level1(u64 *tbl) |
1919 | { | |
1920 | u64 *ptr; | |
1921 | int i; | |
1922 | ||
1923 | for (i = 0; i < 512; ++i) { | |
1924 | if (!(tbl[i] & GCR3_VALID)) | |
1925 | continue; | |
1926 | ||
1927 | ptr = __va(tbl[i] & PAGE_MASK); | |
1928 | ||
1929 | free_page((unsigned long)ptr); | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1934 | { | |
1935 | u64 *ptr; | |
1936 | int i; | |
1937 | ||
1938 | for (i = 0; i < 512; ++i) { | |
1939 | if (!(tbl[i] & GCR3_VALID)) | |
1940 | continue; | |
1941 | ||
1942 | ptr = __va(tbl[i] & PAGE_MASK); | |
1943 | ||
1944 | free_gcr3_tbl_level1(ptr); | |
1945 | } | |
1946 | } | |
1947 | ||
52815b75 JR |
1948 | static void free_gcr3_table(struct protection_domain *domain) |
1949 | { | |
b16137b1 JR |
1950 | if (domain->glx == 2) |
1951 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1952 | else if (domain->glx == 1) | |
1953 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1954 | else if (domain->glx != 0) | |
1955 | BUG(); | |
1956 | ||
52815b75 JR |
1957 | free_page((unsigned long)domain->gcr3_tbl); |
1958 | } | |
1959 | ||
431b2a20 JR |
1960 | /* |
1961 | * Free a domain, only used if something went wrong in the | |
1962 | * allocation path and we need to free an already allocated page table | |
1963 | */ | |
ec487d1a JR |
1964 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1965 | { | |
384de729 JR |
1966 | int i; |
1967 | ||
ec487d1a JR |
1968 | if (!dom) |
1969 | return; | |
1970 | ||
aeb26f55 JR |
1971 | del_domain_from_list(&dom->domain); |
1972 | ||
86db2e5d | 1973 | free_pagetable(&dom->domain); |
ec487d1a | 1974 | |
384de729 JR |
1975 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1976 | if (!dom->aperture[i]) | |
1977 | continue; | |
1978 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1979 | kfree(dom->aperture[i]); | |
1980 | } | |
ec487d1a JR |
1981 | |
1982 | kfree(dom); | |
1983 | } | |
1984 | ||
431b2a20 JR |
1985 | /* |
1986 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1987 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1988 | * structures required for the dma_ops interface |
1989 | */ | |
87a64d52 | 1990 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1991 | { |
1992 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1993 | |
1994 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1995 | if (!dma_dom) | |
1996 | return NULL; | |
1997 | ||
1998 | spin_lock_init(&dma_dom->domain.lock); | |
1999 | ||
2000 | dma_dom->domain.id = domain_id_alloc(); | |
2001 | if (dma_dom->domain.id == 0) | |
2002 | goto free_dma_dom; | |
7c392cbe | 2003 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 2004 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2005 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2006 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2007 | dma_dom->domain.priv = dma_dom; |
2008 | if (!dma_dom->domain.pt_root) | |
2009 | goto free_dma_dom; | |
ec487d1a | 2010 | |
1c655773 | 2011 | dma_dom->need_flush = false; |
bd60b735 | 2012 | dma_dom->target_dev = 0xffff; |
1c655773 | 2013 | |
aeb26f55 JR |
2014 | add_domain_to_list(&dma_dom->domain); |
2015 | ||
576175c2 | 2016 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2017 | goto free_dma_dom; |
ec487d1a | 2018 | |
431b2a20 | 2019 | /* |
ec487d1a JR |
2020 | * mark the first page as allocated so we never return 0 as |
2021 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2022 | */ |
384de729 | 2023 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 2024 | dma_dom->next_address = 0; |
ec487d1a | 2025 | |
ec487d1a JR |
2026 | |
2027 | return dma_dom; | |
2028 | ||
2029 | free_dma_dom: | |
2030 | dma_ops_domain_free(dma_dom); | |
2031 | ||
2032 | return NULL; | |
2033 | } | |
2034 | ||
5b28df6f JR |
2035 | /* |
2036 | * little helper function to check whether a given protection domain is a | |
2037 | * dma_ops domain | |
2038 | */ | |
2039 | static bool dma_ops_domain(struct protection_domain *domain) | |
2040 | { | |
2041 | return domain->flags & PD_DMA_OPS_MASK; | |
2042 | } | |
2043 | ||
fd7b5535 | 2044 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2045 | { |
132bd68f | 2046 | u64 pte_root = 0; |
ee6c2868 | 2047 | u64 flags = 0; |
863c74eb | 2048 | |
132bd68f JR |
2049 | if (domain->mode != PAGE_MODE_NONE) |
2050 | pte_root = virt_to_phys(domain->pt_root); | |
2051 | ||
38ddf41b JR |
2052 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2053 | << DEV_ENTRY_MODE_SHIFT; | |
2054 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2055 | |
ee6c2868 JR |
2056 | flags = amd_iommu_dev_table[devid].data[1]; |
2057 | ||
fd7b5535 JR |
2058 | if (ats) |
2059 | flags |= DTE_FLAG_IOTLB; | |
2060 | ||
52815b75 JR |
2061 | if (domain->flags & PD_IOMMUV2_MASK) { |
2062 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2063 | u64 glx = domain->glx; | |
2064 | u64 tmp; | |
2065 | ||
2066 | pte_root |= DTE_FLAG_GV; | |
2067 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2068 | ||
2069 | /* First mask out possible old values for GCR3 table */ | |
2070 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2071 | flags &= ~tmp; | |
2072 | ||
2073 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2074 | flags &= ~tmp; | |
2075 | ||
2076 | /* Encode GCR3 table into DTE */ | |
2077 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2078 | pte_root |= tmp; | |
2079 | ||
2080 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2081 | flags |= tmp; | |
2082 | ||
2083 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2084 | flags |= tmp; | |
2085 | } | |
2086 | ||
ee6c2868 JR |
2087 | flags &= ~(0xffffUL); |
2088 | flags |= domain->id; | |
2089 | ||
2090 | amd_iommu_dev_table[devid].data[1] = flags; | |
2091 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2092 | } |
2093 | ||
2094 | static void clear_dte_entry(u16 devid) | |
2095 | { | |
15898bbc JR |
2096 | /* remove entry from the device table seen by the hardware */ |
2097 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2098 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2099 | |
2100 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2101 | } |
2102 | ||
ec9e79ef JR |
2103 | static void do_attach(struct iommu_dev_data *dev_data, |
2104 | struct protection_domain *domain) | |
7f760ddd | 2105 | { |
7f760ddd | 2106 | struct amd_iommu *iommu; |
ec9e79ef | 2107 | bool ats; |
fd7b5535 | 2108 | |
ec9e79ef JR |
2109 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2110 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2111 | |
2112 | /* Update data structures */ | |
2113 | dev_data->domain = domain; | |
2114 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2115 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2116 | |
2117 | /* Do reference counting */ | |
2118 | domain->dev_iommu[iommu->index] += 1; | |
2119 | domain->dev_cnt += 1; | |
2120 | ||
2121 | /* Flush the DTE entry */ | |
6c542047 | 2122 | device_flush_dte(dev_data); |
7f760ddd JR |
2123 | } |
2124 | ||
ec9e79ef | 2125 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2126 | { |
7f760ddd | 2127 | struct amd_iommu *iommu; |
7f760ddd | 2128 | |
ec9e79ef | 2129 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2130 | |
2131 | /* decrease reference counters */ | |
7f760ddd JR |
2132 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2133 | dev_data->domain->dev_cnt -= 1; | |
2134 | ||
2135 | /* Update data structures */ | |
2136 | dev_data->domain = NULL; | |
2137 | list_del(&dev_data->list); | |
f62dda66 | 2138 | clear_dte_entry(dev_data->devid); |
15898bbc | 2139 | |
7f760ddd | 2140 | /* Flush the DTE entry */ |
6c542047 | 2141 | device_flush_dte(dev_data); |
2b681faf JR |
2142 | } |
2143 | ||
2144 | /* | |
2145 | * If a device is not yet associated with a domain, this function does | |
2146 | * assigns it visible for the hardware | |
2147 | */ | |
ec9e79ef | 2148 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2149 | struct protection_domain *domain) |
2b681faf | 2150 | { |
397111ab | 2151 | struct iommu_dev_data *head, *entry; |
84fe6c19 | 2152 | int ret; |
657cbb6b | 2153 | |
2b681faf JR |
2154 | /* lock domain */ |
2155 | spin_lock(&domain->lock); | |
2156 | ||
397111ab | 2157 | head = dev_data; |
15898bbc | 2158 | |
397111ab JR |
2159 | if (head->alias_data != NULL) |
2160 | head = head->alias_data; | |
eba6ac60 | 2161 | |
397111ab | 2162 | /* Now we have the root of the alias group, if any */ |
15898bbc | 2163 | |
397111ab JR |
2164 | ret = -EBUSY; |
2165 | if (head->domain != NULL) | |
2166 | goto out_unlock; | |
15898bbc | 2167 | |
397111ab JR |
2168 | /* Attach alias group root */ |
2169 | do_attach(head, domain); | |
eba6ac60 | 2170 | |
397111ab JR |
2171 | /* Attach other devices in the alias group */ |
2172 | list_for_each_entry(entry, &head->alias_list, alias_list) | |
2173 | do_attach(entry, domain); | |
24100055 | 2174 | |
84fe6c19 JL |
2175 | ret = 0; |
2176 | ||
2177 | out_unlock: | |
2178 | ||
eba6ac60 JR |
2179 | /* ready */ |
2180 | spin_unlock(&domain->lock); | |
15898bbc | 2181 | |
84fe6c19 | 2182 | return ret; |
0feae533 | 2183 | } |
b20ac0d4 | 2184 | |
52815b75 JR |
2185 | |
2186 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2187 | { | |
2188 | pci_disable_ats(pdev); | |
2189 | pci_disable_pri(pdev); | |
2190 | pci_disable_pasid(pdev); | |
2191 | } | |
2192 | ||
6a113ddc JR |
2193 | /* FIXME: Change generic reset-function to do the same */ |
2194 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2195 | { | |
2196 | u16 control; | |
2197 | int pos; | |
2198 | ||
46277b75 | 2199 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2200 | if (!pos) |
2201 | return -EINVAL; | |
2202 | ||
46277b75 JR |
2203 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2204 | control |= PCI_PRI_CTRL_RESET; | |
2205 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2206 | |
2207 | return 0; | |
2208 | } | |
2209 | ||
52815b75 JR |
2210 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2211 | { | |
6a113ddc JR |
2212 | bool reset_enable; |
2213 | int reqs, ret; | |
2214 | ||
2215 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2216 | reqs = 32; | |
2217 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2218 | reqs = 1; | |
2219 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2220 | |
2221 | /* Only allow access to user-accessible pages */ | |
2222 | ret = pci_enable_pasid(pdev, 0); | |
2223 | if (ret) | |
2224 | goto out_err; | |
2225 | ||
2226 | /* First reset the PRI state of the device */ | |
2227 | ret = pci_reset_pri(pdev); | |
2228 | if (ret) | |
2229 | goto out_err; | |
2230 | ||
6a113ddc JR |
2231 | /* Enable PRI */ |
2232 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2233 | if (ret) |
2234 | goto out_err; | |
2235 | ||
6a113ddc JR |
2236 | if (reset_enable) { |
2237 | ret = pri_reset_while_enabled(pdev); | |
2238 | if (ret) | |
2239 | goto out_err; | |
2240 | } | |
2241 | ||
52815b75 JR |
2242 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2243 | if (ret) | |
2244 | goto out_err; | |
2245 | ||
2246 | return 0; | |
2247 | ||
2248 | out_err: | |
2249 | pci_disable_pri(pdev); | |
2250 | pci_disable_pasid(pdev); | |
2251 | ||
2252 | return ret; | |
2253 | } | |
2254 | ||
c99afa25 | 2255 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2256 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2257 | |
98f1ad25 | 2258 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2259 | { |
a3b93121 | 2260 | u16 status; |
c99afa25 JR |
2261 | int pos; |
2262 | ||
46277b75 | 2263 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2264 | if (!pos) |
2265 | return false; | |
2266 | ||
a3b93121 | 2267 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2268 | |
a3b93121 | 2269 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2270 | } |
2271 | ||
407d733e | 2272 | /* |
df805abb | 2273 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2274 | * assigns it visible for the hardware |
2275 | */ | |
15898bbc JR |
2276 | static int attach_device(struct device *dev, |
2277 | struct protection_domain *domain) | |
0feae533 | 2278 | { |
fd7b5535 | 2279 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2280 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2281 | unsigned long flags; |
15898bbc | 2282 | int ret; |
eba6ac60 | 2283 | |
ea61cddb JR |
2284 | dev_data = get_dev_data(dev); |
2285 | ||
52815b75 JR |
2286 | if (domain->flags & PD_IOMMUV2_MASK) { |
2287 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2288 | return -EINVAL; | |
2289 | ||
2290 | if (pdev_iommuv2_enable(pdev) != 0) | |
2291 | return -EINVAL; | |
2292 | ||
2293 | dev_data->ats.enabled = true; | |
2294 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2295 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2296 | } else if (amd_iommu_iotlb_sup && |
2297 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2298 | dev_data->ats.enabled = true; |
2299 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2300 | } | |
fd7b5535 | 2301 | |
eba6ac60 | 2302 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2303 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2304 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2305 | ||
0feae533 JR |
2306 | /* |
2307 | * We might boot into a crash-kernel here. The crashed kernel | |
2308 | * left the caches in the IOMMU dirty. So we have to flush | |
2309 | * here to evict all dirty stuff. | |
2310 | */ | |
17b124bf | 2311 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2312 | |
2313 | return ret; | |
b20ac0d4 JR |
2314 | } |
2315 | ||
355bf553 JR |
2316 | /* |
2317 | * Removes a device from a protection domain (unlocked) | |
2318 | */ | |
ec9e79ef | 2319 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2320 | { |
397111ab | 2321 | struct iommu_dev_data *head, *entry; |
2ca76279 | 2322 | struct protection_domain *domain; |
7c392cbe | 2323 | unsigned long flags; |
c4596114 | 2324 | |
7f760ddd | 2325 | BUG_ON(!dev_data->domain); |
355bf553 | 2326 | |
2ca76279 JR |
2327 | domain = dev_data->domain; |
2328 | ||
2329 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2330 | |
397111ab JR |
2331 | head = dev_data; |
2332 | if (head->alias_data != NULL) | |
2333 | head = head->alias_data; | |
71f77580 | 2334 | |
397111ab JR |
2335 | list_for_each_entry(entry, &head->alias_list, alias_list) |
2336 | do_detach(entry); | |
24100055 | 2337 | |
397111ab | 2338 | do_detach(head); |
7f760ddd | 2339 | |
2ca76279 | 2340 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2341 | |
2342 | /* | |
2343 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2344 | * passthrough domain if it is detached from any other domain. |
2345 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2346 | */ |
5abcdba4 | 2347 | if (dev_data->passthrough && |
d3ad9373 | 2348 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2349 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2350 | } |
2351 | ||
2352 | /* | |
2353 | * Removes a device from a protection domain (with devtable_lock held) | |
2354 | */ | |
15898bbc | 2355 | static void detach_device(struct device *dev) |
355bf553 | 2356 | { |
52815b75 | 2357 | struct protection_domain *domain; |
ea61cddb | 2358 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2359 | unsigned long flags; |
2360 | ||
ec9e79ef | 2361 | dev_data = get_dev_data(dev); |
52815b75 | 2362 | domain = dev_data->domain; |
ec9e79ef | 2363 | |
355bf553 JR |
2364 | /* lock device table */ |
2365 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2366 | __detach_device(dev_data); |
355bf553 | 2367 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2368 | |
52815b75 JR |
2369 | if (domain->flags & PD_IOMMUV2_MASK) |
2370 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2371 | else if (dev_data->ats.enabled) | |
ea61cddb | 2372 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2373 | |
2374 | dev_data->ats.enabled = false; | |
355bf553 | 2375 | } |
e275a2a0 | 2376 | |
15898bbc JR |
2377 | /* |
2378 | * Find out the protection domain structure for a given PCI device. This | |
2379 | * will give us the pointer to the page table root for example. | |
2380 | */ | |
2381 | static struct protection_domain *domain_for_device(struct device *dev) | |
2382 | { | |
71f77580 | 2383 | struct iommu_dev_data *dev_data; |
2b02b091 | 2384 | struct protection_domain *dom = NULL; |
15898bbc | 2385 | unsigned long flags; |
15898bbc | 2386 | |
657cbb6b | 2387 | dev_data = get_dev_data(dev); |
15898bbc | 2388 | |
2b02b091 JR |
2389 | if (dev_data->domain) |
2390 | return dev_data->domain; | |
15898bbc | 2391 | |
71f77580 JR |
2392 | if (dev_data->alias_data != NULL) { |
2393 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2394 | |
2395 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2396 | if (alias_data->domain != NULL) { | |
2397 | __attach_device(dev_data, alias_data->domain); | |
2398 | dom = alias_data->domain; | |
2399 | } | |
2400 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2401 | } | |
15898bbc JR |
2402 | |
2403 | return dom; | |
2404 | } | |
2405 | ||
e275a2a0 JR |
2406 | static int device_change_notifier(struct notifier_block *nb, |
2407 | unsigned long action, void *data) | |
2408 | { | |
e275a2a0 | 2409 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2410 | struct protection_domain *domain; |
2411 | struct iommu_dev_data *dev_data; | |
2412 | struct device *dev = data; | |
e275a2a0 | 2413 | struct amd_iommu *iommu; |
1ac4cbbc | 2414 | unsigned long flags; |
5abcdba4 | 2415 | u16 devid; |
e275a2a0 | 2416 | |
98fc5a69 JR |
2417 | if (!check_device(dev)) |
2418 | return 0; | |
e275a2a0 | 2419 | |
5abcdba4 JR |
2420 | devid = get_device_id(dev); |
2421 | iommu = amd_iommu_rlookup_table[devid]; | |
2422 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2423 | |
2424 | switch (action) { | |
1ac4cbbc | 2425 | case BUS_NOTIFY_ADD_DEVICE: |
657cbb6b JR |
2426 | |
2427 | iommu_init_device(dev); | |
25b11ce2 | 2428 | init_iommu_group(dev); |
657cbb6b | 2429 | |
2c9195e9 JR |
2430 | /* |
2431 | * dev_data is still NULL and | |
2432 | * got initialized in iommu_init_device | |
2433 | */ | |
2434 | dev_data = get_dev_data(dev); | |
2435 | ||
2436 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2437 | dev_data->passthrough = true; | |
2438 | attach_device(dev, pt_domain); | |
2439 | break; | |
2440 | } | |
2441 | ||
657cbb6b JR |
2442 | domain = domain_for_device(dev); |
2443 | ||
1ac4cbbc JR |
2444 | /* allocate a protection domain if a device is added */ |
2445 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2446 | if (!dma_domain) { |
2447 | dma_domain = dma_ops_domain_alloc(); | |
2448 | if (!dma_domain) | |
2449 | goto out; | |
2450 | dma_domain->target_dev = devid; | |
2451 | ||
2452 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2453 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2454 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2455 | } | |
ac1534a5 | 2456 | |
2c9195e9 | 2457 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2458 | |
e275a2a0 | 2459 | break; |
6c5cc801 | 2460 | case BUS_NOTIFY_REMOVED_DEVICE: |
657cbb6b JR |
2461 | |
2462 | iommu_uninit_device(dev); | |
2463 | ||
e275a2a0 JR |
2464 | default: |
2465 | goto out; | |
2466 | } | |
2467 | ||
e275a2a0 JR |
2468 | iommu_completion_wait(iommu); |
2469 | ||
2470 | out: | |
2471 | return 0; | |
2472 | } | |
2473 | ||
b25ae679 | 2474 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2475 | .notifier_call = device_change_notifier, |
2476 | }; | |
355bf553 | 2477 | |
8638c491 JR |
2478 | void amd_iommu_init_notifier(void) |
2479 | { | |
2480 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2481 | } | |
2482 | ||
431b2a20 JR |
2483 | /***************************************************************************** |
2484 | * | |
2485 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2486 | * | |
2487 | *****************************************************************************/ | |
2488 | ||
2489 | /* | |
2490 | * In the dma_ops path we only have the struct device. This function | |
2491 | * finds the corresponding IOMMU, the protection domain and the | |
2492 | * requestor id for a given device. | |
2493 | * If the device is not yet associated with a domain this is also done | |
2494 | * in this function. | |
2495 | */ | |
94f6d190 | 2496 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2497 | { |
94f6d190 | 2498 | struct protection_domain *domain; |
b20ac0d4 | 2499 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2500 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2501 | |
f99c0f1c | 2502 | if (!check_device(dev)) |
94f6d190 | 2503 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2504 | |
94f6d190 JR |
2505 | domain = domain_for_device(dev); |
2506 | if (domain != NULL && !dma_ops_domain(domain)) | |
2507 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2508 | |
94f6d190 JR |
2509 | if (domain != NULL) |
2510 | return domain; | |
b20ac0d4 | 2511 | |
df805abb | 2512 | /* Device not bound yet - bind it */ |
94f6d190 | 2513 | dma_dom = find_protection_domain(devid); |
15898bbc | 2514 | if (!dma_dom) |
94f6d190 JR |
2515 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2516 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2517 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2518 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2519 | |
94f6d190 | 2520 | return &dma_dom->domain; |
b20ac0d4 JR |
2521 | } |
2522 | ||
04bfdd84 JR |
2523 | static void update_device_table(struct protection_domain *domain) |
2524 | { | |
492667da | 2525 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2526 | |
ea61cddb JR |
2527 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2528 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2529 | } |
2530 | ||
2531 | static void update_domain(struct protection_domain *domain) | |
2532 | { | |
2533 | if (!domain->updated) | |
2534 | return; | |
2535 | ||
2536 | update_device_table(domain); | |
17b124bf JR |
2537 | |
2538 | domain_flush_devices(domain); | |
2539 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2540 | |
2541 | domain->updated = false; | |
2542 | } | |
2543 | ||
8bda3092 JR |
2544 | /* |
2545 | * This function fetches the PTE for a given address in the aperture | |
2546 | */ | |
2547 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2548 | unsigned long address) | |
2549 | { | |
384de729 | 2550 | struct aperture_range *aperture; |
8bda3092 JR |
2551 | u64 *pte, *pte_page; |
2552 | ||
384de729 JR |
2553 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2554 | if (!aperture) | |
2555 | return NULL; | |
2556 | ||
2557 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2558 | if (!pte) { |
cbb9d729 | 2559 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2560 | GFP_ATOMIC); |
384de729 JR |
2561 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2562 | } else | |
8c8c143c | 2563 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2564 | |
04bfdd84 | 2565 | update_domain(&dom->domain); |
8bda3092 JR |
2566 | |
2567 | return pte; | |
2568 | } | |
2569 | ||
431b2a20 JR |
2570 | /* |
2571 | * This is the generic map function. It maps one 4kb page at paddr to | |
2572 | * the given address in the DMA address space for the domain. | |
2573 | */ | |
680525e0 | 2574 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2575 | unsigned long address, |
2576 | phys_addr_t paddr, | |
2577 | int direction) | |
2578 | { | |
2579 | u64 *pte, __pte; | |
2580 | ||
2581 | WARN_ON(address > dom->aperture_size); | |
2582 | ||
2583 | paddr &= PAGE_MASK; | |
2584 | ||
8bda3092 | 2585 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2586 | if (!pte) |
8fd524b3 | 2587 | return DMA_ERROR_CODE; |
cb76c322 JR |
2588 | |
2589 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2590 | ||
2591 | if (direction == DMA_TO_DEVICE) | |
2592 | __pte |= IOMMU_PTE_IR; | |
2593 | else if (direction == DMA_FROM_DEVICE) | |
2594 | __pte |= IOMMU_PTE_IW; | |
2595 | else if (direction == DMA_BIDIRECTIONAL) | |
2596 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2597 | ||
2598 | WARN_ON(*pte); | |
2599 | ||
2600 | *pte = __pte; | |
2601 | ||
2602 | return (dma_addr_t)address; | |
2603 | } | |
2604 | ||
431b2a20 JR |
2605 | /* |
2606 | * The generic unmapping function for on page in the DMA address space. | |
2607 | */ | |
680525e0 | 2608 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2609 | unsigned long address) |
2610 | { | |
384de729 | 2611 | struct aperture_range *aperture; |
cb76c322 JR |
2612 | u64 *pte; |
2613 | ||
2614 | if (address >= dom->aperture_size) | |
2615 | return; | |
2616 | ||
384de729 JR |
2617 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2618 | if (!aperture) | |
2619 | return; | |
2620 | ||
2621 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2622 | if (!pte) | |
2623 | return; | |
cb76c322 | 2624 | |
8c8c143c | 2625 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2626 | |
2627 | WARN_ON(!*pte); | |
2628 | ||
2629 | *pte = 0ULL; | |
2630 | } | |
2631 | ||
431b2a20 JR |
2632 | /* |
2633 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2634 | * contiguous memory region into DMA address space. It is used by all |
2635 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2636 | * Must be called with the domain lock held. |
2637 | */ | |
cb76c322 | 2638 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2639 | struct dma_ops_domain *dma_dom, |
2640 | phys_addr_t paddr, | |
2641 | size_t size, | |
6d4f343f | 2642 | int dir, |
832a90c3 JR |
2643 | bool align, |
2644 | u64 dma_mask) | |
cb76c322 JR |
2645 | { |
2646 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2647 | dma_addr_t address, start, ret; |
cb76c322 | 2648 | unsigned int pages; |
6d4f343f | 2649 | unsigned long align_mask = 0; |
cb76c322 JR |
2650 | int i; |
2651 | ||
e3c449f5 | 2652 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2653 | paddr &= PAGE_MASK; |
2654 | ||
8ecaf8f1 JR |
2655 | INC_STATS_COUNTER(total_map_requests); |
2656 | ||
c1858976 JR |
2657 | if (pages > 1) |
2658 | INC_STATS_COUNTER(cross_page); | |
2659 | ||
6d4f343f JR |
2660 | if (align) |
2661 | align_mask = (1UL << get_order(size)) - 1; | |
2662 | ||
11b83888 | 2663 | retry: |
832a90c3 JR |
2664 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2665 | dma_mask); | |
8fd524b3 | 2666 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2667 | /* |
2668 | * setting next_address here will let the address | |
2669 | * allocator only scan the new allocated range in the | |
2670 | * first run. This is a small optimization. | |
2671 | */ | |
2672 | dma_dom->next_address = dma_dom->aperture_size; | |
2673 | ||
576175c2 | 2674 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2675 | goto out; |
2676 | ||
2677 | /* | |
af901ca1 | 2678 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2679 | * allocation again |
2680 | */ | |
2681 | goto retry; | |
2682 | } | |
cb76c322 JR |
2683 | |
2684 | start = address; | |
2685 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2686 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2687 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2688 | goto out_unmap; |
2689 | ||
cb76c322 JR |
2690 | paddr += PAGE_SIZE; |
2691 | start += PAGE_SIZE; | |
2692 | } | |
2693 | address += offset; | |
2694 | ||
5774f7c5 JR |
2695 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2696 | ||
afa9fdc2 | 2697 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2698 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2699 | dma_dom->need_flush = false; |
318afd41 | 2700 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2701 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2702 | |
cb76c322 JR |
2703 | out: |
2704 | return address; | |
53812c11 JR |
2705 | |
2706 | out_unmap: | |
2707 | ||
2708 | for (--i; i >= 0; --i) { | |
2709 | start -= PAGE_SIZE; | |
680525e0 | 2710 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2711 | } |
2712 | ||
2713 | dma_ops_free_addresses(dma_dom, address, pages); | |
2714 | ||
8fd524b3 | 2715 | return DMA_ERROR_CODE; |
cb76c322 JR |
2716 | } |
2717 | ||
431b2a20 JR |
2718 | /* |
2719 | * Does the reverse of the __map_single function. Must be called with | |
2720 | * the domain lock held too | |
2721 | */ | |
cd8c82e8 | 2722 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2723 | dma_addr_t dma_addr, |
2724 | size_t size, | |
2725 | int dir) | |
2726 | { | |
04e0463e | 2727 | dma_addr_t flush_addr; |
cb76c322 JR |
2728 | dma_addr_t i, start; |
2729 | unsigned int pages; | |
2730 | ||
8fd524b3 | 2731 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2732 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2733 | return; |
2734 | ||
04e0463e | 2735 | flush_addr = dma_addr; |
e3c449f5 | 2736 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2737 | dma_addr &= PAGE_MASK; |
2738 | start = dma_addr; | |
2739 | ||
2740 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2741 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2742 | start += PAGE_SIZE; |
2743 | } | |
2744 | ||
5774f7c5 JR |
2745 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2746 | ||
cb76c322 | 2747 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2748 | |
80be308d | 2749 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2750 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2751 | dma_dom->need_flush = false; |
2752 | } | |
cb76c322 JR |
2753 | } |
2754 | ||
431b2a20 JR |
2755 | /* |
2756 | * The exported map_single function for dma_ops. | |
2757 | */ | |
51491367 FT |
2758 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2759 | unsigned long offset, size_t size, | |
2760 | enum dma_data_direction dir, | |
2761 | struct dma_attrs *attrs) | |
4da70b9e JR |
2762 | { |
2763 | unsigned long flags; | |
4da70b9e | 2764 | struct protection_domain *domain; |
4da70b9e | 2765 | dma_addr_t addr; |
832a90c3 | 2766 | u64 dma_mask; |
51491367 | 2767 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2768 | |
0f2a86f2 JR |
2769 | INC_STATS_COUNTER(cnt_map_single); |
2770 | ||
94f6d190 JR |
2771 | domain = get_domain(dev); |
2772 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2773 | return (dma_addr_t)paddr; |
94f6d190 JR |
2774 | else if (IS_ERR(domain)) |
2775 | return DMA_ERROR_CODE; | |
4da70b9e | 2776 | |
f99c0f1c JR |
2777 | dma_mask = *dev->dma_mask; |
2778 | ||
4da70b9e | 2779 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2780 | |
cd8c82e8 | 2781 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2782 | dma_mask); |
8fd524b3 | 2783 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2784 | goto out; |
2785 | ||
17b124bf | 2786 | domain_flush_complete(domain); |
4da70b9e JR |
2787 | |
2788 | out: | |
2789 | spin_unlock_irqrestore(&domain->lock, flags); | |
2790 | ||
2791 | return addr; | |
2792 | } | |
2793 | ||
431b2a20 JR |
2794 | /* |
2795 | * The exported unmap_single function for dma_ops. | |
2796 | */ | |
51491367 FT |
2797 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2798 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2799 | { |
2800 | unsigned long flags; | |
4da70b9e | 2801 | struct protection_domain *domain; |
4da70b9e | 2802 | |
146a6917 JR |
2803 | INC_STATS_COUNTER(cnt_unmap_single); |
2804 | ||
94f6d190 JR |
2805 | domain = get_domain(dev); |
2806 | if (IS_ERR(domain)) | |
5b28df6f JR |
2807 | return; |
2808 | ||
4da70b9e JR |
2809 | spin_lock_irqsave(&domain->lock, flags); |
2810 | ||
cd8c82e8 | 2811 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2812 | |
17b124bf | 2813 | domain_flush_complete(domain); |
4da70b9e JR |
2814 | |
2815 | spin_unlock_irqrestore(&domain->lock, flags); | |
2816 | } | |
2817 | ||
431b2a20 JR |
2818 | /* |
2819 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2820 | * lists). | |
2821 | */ | |
65b050ad | 2822 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2823 | int nelems, enum dma_data_direction dir, |
2824 | struct dma_attrs *attrs) | |
65b050ad JR |
2825 | { |
2826 | unsigned long flags; | |
65b050ad | 2827 | struct protection_domain *domain; |
65b050ad JR |
2828 | int i; |
2829 | struct scatterlist *s; | |
2830 | phys_addr_t paddr; | |
2831 | int mapped_elems = 0; | |
832a90c3 | 2832 | u64 dma_mask; |
65b050ad | 2833 | |
d03f067a JR |
2834 | INC_STATS_COUNTER(cnt_map_sg); |
2835 | ||
94f6d190 | 2836 | domain = get_domain(dev); |
a0e191b2 | 2837 | if (IS_ERR(domain)) |
94f6d190 | 2838 | return 0; |
dbcc112e | 2839 | |
832a90c3 | 2840 | dma_mask = *dev->dma_mask; |
65b050ad | 2841 | |
65b050ad JR |
2842 | spin_lock_irqsave(&domain->lock, flags); |
2843 | ||
2844 | for_each_sg(sglist, s, nelems, i) { | |
2845 | paddr = sg_phys(s); | |
2846 | ||
cd8c82e8 | 2847 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2848 | paddr, s->length, dir, false, |
2849 | dma_mask); | |
65b050ad JR |
2850 | |
2851 | if (s->dma_address) { | |
2852 | s->dma_length = s->length; | |
2853 | mapped_elems++; | |
2854 | } else | |
2855 | goto unmap; | |
65b050ad JR |
2856 | } |
2857 | ||
17b124bf | 2858 | domain_flush_complete(domain); |
65b050ad JR |
2859 | |
2860 | out: | |
2861 | spin_unlock_irqrestore(&domain->lock, flags); | |
2862 | ||
2863 | return mapped_elems; | |
2864 | unmap: | |
2865 | for_each_sg(sglist, s, mapped_elems, i) { | |
2866 | if (s->dma_address) | |
cd8c82e8 | 2867 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2868 | s->dma_length, dir); |
2869 | s->dma_address = s->dma_length = 0; | |
2870 | } | |
2871 | ||
2872 | mapped_elems = 0; | |
2873 | ||
2874 | goto out; | |
2875 | } | |
2876 | ||
431b2a20 JR |
2877 | /* |
2878 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2879 | * lists). | |
2880 | */ | |
65b050ad | 2881 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2882 | int nelems, enum dma_data_direction dir, |
2883 | struct dma_attrs *attrs) | |
65b050ad JR |
2884 | { |
2885 | unsigned long flags; | |
65b050ad JR |
2886 | struct protection_domain *domain; |
2887 | struct scatterlist *s; | |
65b050ad JR |
2888 | int i; |
2889 | ||
55877a6b JR |
2890 | INC_STATS_COUNTER(cnt_unmap_sg); |
2891 | ||
94f6d190 JR |
2892 | domain = get_domain(dev); |
2893 | if (IS_ERR(domain)) | |
5b28df6f JR |
2894 | return; |
2895 | ||
65b050ad JR |
2896 | spin_lock_irqsave(&domain->lock, flags); |
2897 | ||
2898 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2899 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2900 | s->dma_length, dir); |
65b050ad JR |
2901 | s->dma_address = s->dma_length = 0; |
2902 | } | |
2903 | ||
17b124bf | 2904 | domain_flush_complete(domain); |
65b050ad JR |
2905 | |
2906 | spin_unlock_irqrestore(&domain->lock, flags); | |
2907 | } | |
2908 | ||
431b2a20 JR |
2909 | /* |
2910 | * The exported alloc_coherent function for dma_ops. | |
2911 | */ | |
5d8b53cf | 2912 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2913 | dma_addr_t *dma_addr, gfp_t flag, |
2914 | struct dma_attrs *attrs) | |
5d8b53cf | 2915 | { |
832a90c3 | 2916 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2917 | struct protection_domain *domain; |
2918 | unsigned long flags; | |
2919 | struct page *page; | |
5d8b53cf | 2920 | |
c8f0fb36 JR |
2921 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2922 | ||
94f6d190 JR |
2923 | domain = get_domain(dev); |
2924 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2925 | page = alloc_pages(flag, get_order(size)); |
2926 | *dma_addr = page_to_phys(page); | |
2927 | return page_address(page); | |
94f6d190 JR |
2928 | } else if (IS_ERR(domain)) |
2929 | return NULL; | |
5d8b53cf | 2930 | |
3b839a57 | 2931 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2932 | dma_mask = dev->coherent_dma_mask; |
2933 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2934 | flag |= __GFP_ZERO; |
5d8b53cf | 2935 | |
3b839a57 JR |
2936 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2937 | if (!page) { | |
2938 | if (!(flag & __GFP_WAIT)) | |
2939 | return NULL; | |
5d8b53cf | 2940 | |
3b839a57 JR |
2941 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2942 | get_order(size)); | |
2943 | if (!page) | |
2944 | return NULL; | |
2945 | } | |
5d8b53cf | 2946 | |
832a90c3 JR |
2947 | if (!dma_mask) |
2948 | dma_mask = *dev->dma_mask; | |
2949 | ||
5d8b53cf JR |
2950 | spin_lock_irqsave(&domain->lock, flags); |
2951 | ||
3b839a57 | 2952 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2953 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2954 | |
8fd524b3 | 2955 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2956 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2957 | goto out_free; |
367d04c4 | 2958 | } |
5d8b53cf | 2959 | |
17b124bf | 2960 | domain_flush_complete(domain); |
5d8b53cf | 2961 | |
5d8b53cf JR |
2962 | spin_unlock_irqrestore(&domain->lock, flags); |
2963 | ||
3b839a57 | 2964 | return page_address(page); |
5b28df6f JR |
2965 | |
2966 | out_free: | |
2967 | ||
3b839a57 JR |
2968 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2969 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2970 | |
2971 | return NULL; | |
5d8b53cf JR |
2972 | } |
2973 | ||
431b2a20 JR |
2974 | /* |
2975 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2976 | */ |
5d8b53cf | 2977 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2978 | void *virt_addr, dma_addr_t dma_addr, |
2979 | struct dma_attrs *attrs) | |
5d8b53cf | 2980 | { |
5d8b53cf | 2981 | struct protection_domain *domain; |
3b839a57 JR |
2982 | unsigned long flags; |
2983 | struct page *page; | |
5d8b53cf | 2984 | |
5d31ee7e JR |
2985 | INC_STATS_COUNTER(cnt_free_coherent); |
2986 | ||
3b839a57 JR |
2987 | page = virt_to_page(virt_addr); |
2988 | size = PAGE_ALIGN(size); | |
2989 | ||
94f6d190 JR |
2990 | domain = get_domain(dev); |
2991 | if (IS_ERR(domain)) | |
5b28df6f JR |
2992 | goto free_mem; |
2993 | ||
5d8b53cf JR |
2994 | spin_lock_irqsave(&domain->lock, flags); |
2995 | ||
cd8c82e8 | 2996 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2997 | |
17b124bf | 2998 | domain_flush_complete(domain); |
5d8b53cf JR |
2999 | |
3000 | spin_unlock_irqrestore(&domain->lock, flags); | |
3001 | ||
3002 | free_mem: | |
3b839a57 JR |
3003 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
3004 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
3005 | } |
3006 | ||
b39ba6ad JR |
3007 | /* |
3008 | * This function is called by the DMA layer to find out if we can handle a | |
3009 | * particular device. It is part of the dma_ops. | |
3010 | */ | |
3011 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
3012 | { | |
420aef8a | 3013 | return check_device(dev); |
b39ba6ad JR |
3014 | } |
3015 | ||
c432f3df | 3016 | /* |
431b2a20 JR |
3017 | * The function for pre-allocating protection domains. |
3018 | * | |
c432f3df JR |
3019 | * If the driver core informs the DMA layer if a driver grabs a device |
3020 | * we don't need to preallocate the protection domains anymore. | |
3021 | * For now we have to. | |
3022 | */ | |
943bc7e1 | 3023 | static void __init prealloc_protection_domains(void) |
c432f3df | 3024 | { |
5abcdba4 | 3025 | struct iommu_dev_data *dev_data; |
c432f3df | 3026 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3027 | struct pci_dev *dev = NULL; |
98fc5a69 | 3028 | u16 devid; |
c432f3df | 3029 | |
d18c69d3 | 3030 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3031 | |
3032 | /* Do we handle this device? */ | |
3033 | if (!check_device(&dev->dev)) | |
c432f3df | 3034 | continue; |
98fc5a69 | 3035 | |
5abcdba4 JR |
3036 | dev_data = get_dev_data(&dev->dev); |
3037 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3038 | /* Make sure passthrough domain is allocated */ | |
3039 | alloc_passthrough_domain(); | |
3040 | dev_data->passthrough = true; | |
3041 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3042 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3043 | dev_name(&dev->dev)); |
3044 | } | |
3045 | ||
98fc5a69 | 3046 | /* Is there already any domain for it? */ |
15898bbc | 3047 | if (domain_for_device(&dev->dev)) |
c432f3df | 3048 | continue; |
98fc5a69 JR |
3049 | |
3050 | devid = get_device_id(&dev->dev); | |
3051 | ||
87a64d52 | 3052 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3053 | if (!dma_dom) |
3054 | continue; | |
3055 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3056 | dma_dom->target_dev = devid; |
3057 | ||
15898bbc | 3058 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3059 | |
bd60b735 | 3060 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3061 | } |
3062 | } | |
3063 | ||
160c1d8e | 3064 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3065 | .alloc = alloc_coherent, |
3066 | .free = free_coherent, | |
51491367 FT |
3067 | .map_page = map_page, |
3068 | .unmap_page = unmap_page, | |
6631ee9d JR |
3069 | .map_sg = map_sg, |
3070 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3071 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3072 | }; |
3073 | ||
27c2127a JR |
3074 | static unsigned device_dma_ops_init(void) |
3075 | { | |
5abcdba4 | 3076 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3077 | struct pci_dev *pdev = NULL; |
3078 | unsigned unhandled = 0; | |
3079 | ||
3080 | for_each_pci_dev(pdev) { | |
3081 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3082 | |
3083 | iommu_ignore_device(&pdev->dev); | |
3084 | ||
27c2127a JR |
3085 | unhandled += 1; |
3086 | continue; | |
3087 | } | |
3088 | ||
5abcdba4 JR |
3089 | dev_data = get_dev_data(&pdev->dev); |
3090 | ||
3091 | if (!dev_data->passthrough) | |
3092 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3093 | else | |
3094 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3095 | } |
3096 | ||
3097 | return unhandled; | |
3098 | } | |
3099 | ||
431b2a20 JR |
3100 | /* |
3101 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3102 | */ | |
f5325094 JR |
3103 | |
3104 | void __init amd_iommu_init_api(void) | |
3105 | { | |
2cc21c42 | 3106 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3107 | } |
3108 | ||
6631ee9d JR |
3109 | int __init amd_iommu_init_dma_ops(void) |
3110 | { | |
3111 | struct amd_iommu *iommu; | |
27c2127a | 3112 | int ret, unhandled; |
6631ee9d | 3113 | |
431b2a20 JR |
3114 | /* |
3115 | * first allocate a default protection domain for every IOMMU we | |
3116 | * found in the system. Devices not assigned to any other | |
3117 | * protection domain will be assigned to the default one. | |
3118 | */ | |
3bd22172 | 3119 | for_each_iommu(iommu) { |
87a64d52 | 3120 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3121 | if (iommu->default_dom == NULL) |
3122 | return -ENOMEM; | |
e2dc14a2 | 3123 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3124 | ret = iommu_init_unity_mappings(iommu); |
3125 | if (ret) | |
3126 | goto free_domains; | |
3127 | } | |
3128 | ||
431b2a20 | 3129 | /* |
8793abeb | 3130 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3131 | */ |
8793abeb | 3132 | prealloc_protection_domains(); |
6631ee9d JR |
3133 | |
3134 | iommu_detected = 1; | |
75f1cdf1 | 3135 | swiotlb = 0; |
6631ee9d | 3136 | |
431b2a20 | 3137 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3138 | unhandled = device_dma_ops_init(); |
3139 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3140 | /* There are unhandled devices - initialize swiotlb for them */ | |
3141 | swiotlb = 1; | |
3142 | } | |
6631ee9d | 3143 | |
7f26508b JR |
3144 | amd_iommu_stats_init(); |
3145 | ||
62410eeb JR |
3146 | if (amd_iommu_unmap_flush) |
3147 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3148 | else | |
3149 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3150 | ||
6631ee9d JR |
3151 | return 0; |
3152 | ||
3153 | free_domains: | |
3154 | ||
3bd22172 | 3155 | for_each_iommu(iommu) { |
91457df7 | 3156 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3157 | } |
3158 | ||
3159 | return ret; | |
3160 | } | |
6d98cd80 JR |
3161 | |
3162 | /***************************************************************************** | |
3163 | * | |
3164 | * The following functions belong to the exported interface of AMD IOMMU | |
3165 | * | |
3166 | * This interface allows access to lower level functions of the IOMMU | |
3167 | * like protection domain handling and assignement of devices to domains | |
3168 | * which is not possible with the dma_ops interface. | |
3169 | * | |
3170 | *****************************************************************************/ | |
3171 | ||
6d98cd80 JR |
3172 | static void cleanup_domain(struct protection_domain *domain) |
3173 | { | |
9b29d3c6 | 3174 | struct iommu_dev_data *entry; |
6d98cd80 | 3175 | unsigned long flags; |
6d98cd80 JR |
3176 | |
3177 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3178 | ||
9b29d3c6 JR |
3179 | while (!list_empty(&domain->dev_list)) { |
3180 | entry = list_first_entry(&domain->dev_list, | |
3181 | struct iommu_dev_data, list); | |
3182 | __detach_device(entry); | |
492667da | 3183 | } |
6d98cd80 JR |
3184 | |
3185 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3186 | } | |
3187 | ||
2650815f JR |
3188 | static void protection_domain_free(struct protection_domain *domain) |
3189 | { | |
3190 | if (!domain) | |
3191 | return; | |
3192 | ||
aeb26f55 JR |
3193 | del_domain_from_list(domain); |
3194 | ||
2650815f JR |
3195 | if (domain->id) |
3196 | domain_id_free(domain->id); | |
3197 | ||
3198 | kfree(domain); | |
3199 | } | |
3200 | ||
3201 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3202 | { |
3203 | struct protection_domain *domain; | |
3204 | ||
3205 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3206 | if (!domain) | |
2650815f | 3207 | return NULL; |
c156e347 JR |
3208 | |
3209 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3210 | mutex_init(&domain->api_lock); |
c156e347 JR |
3211 | domain->id = domain_id_alloc(); |
3212 | if (!domain->id) | |
2650815f | 3213 | goto out_err; |
7c392cbe | 3214 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3215 | |
aeb26f55 JR |
3216 | add_domain_to_list(domain); |
3217 | ||
2650815f JR |
3218 | return domain; |
3219 | ||
3220 | out_err: | |
3221 | kfree(domain); | |
3222 | ||
3223 | return NULL; | |
3224 | } | |
3225 | ||
5abcdba4 JR |
3226 | static int __init alloc_passthrough_domain(void) |
3227 | { | |
3228 | if (pt_domain != NULL) | |
3229 | return 0; | |
3230 | ||
3231 | /* allocate passthrough domain */ | |
3232 | pt_domain = protection_domain_alloc(); | |
3233 | if (!pt_domain) | |
3234 | return -ENOMEM; | |
3235 | ||
3236 | pt_domain->mode = PAGE_MODE_NONE; | |
3237 | ||
3238 | return 0; | |
3239 | } | |
3f4b87b9 JR |
3240 | |
3241 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
2650815f | 3242 | { |
3f4b87b9 | 3243 | struct protection_domain *pdomain; |
2650815f | 3244 | |
3f4b87b9 JR |
3245 | /* We only support unmanaged domains for now */ |
3246 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
3247 | return NULL; | |
2650815f | 3248 | |
3f4b87b9 JR |
3249 | pdomain = protection_domain_alloc(); |
3250 | if (!pdomain) | |
c156e347 JR |
3251 | goto out_free; |
3252 | ||
3f4b87b9 JR |
3253 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3254 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3255 | if (!pdomain->pt_root) | |
3256 | goto out_free; | |
c156e347 | 3257 | |
3f4b87b9 JR |
3258 | pdomain->domain.geometry.aperture_start = 0; |
3259 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3260 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3261 | |
3f4b87b9 | 3262 | return &pdomain->domain; |
c156e347 JR |
3263 | |
3264 | out_free: | |
3f4b87b9 | 3265 | protection_domain_free(pdomain); |
c156e347 | 3266 | |
3f4b87b9 | 3267 | return NULL; |
c156e347 JR |
3268 | } |
3269 | ||
3f4b87b9 | 3270 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3271 | { |
3f4b87b9 | 3272 | struct protection_domain *domain; |
98383fc3 | 3273 | |
3f4b87b9 | 3274 | if (!dom) |
98383fc3 JR |
3275 | return; |
3276 | ||
3f4b87b9 JR |
3277 | domain = to_pdomain(dom); |
3278 | ||
98383fc3 JR |
3279 | if (domain->dev_cnt > 0) |
3280 | cleanup_domain(domain); | |
3281 | ||
3282 | BUG_ON(domain->dev_cnt != 0); | |
3283 | ||
132bd68f JR |
3284 | if (domain->mode != PAGE_MODE_NONE) |
3285 | free_pagetable(domain); | |
98383fc3 | 3286 | |
52815b75 JR |
3287 | if (domain->flags & PD_IOMMUV2_MASK) |
3288 | free_gcr3_table(domain); | |
3289 | ||
8b408fe4 | 3290 | protection_domain_free(domain); |
98383fc3 JR |
3291 | } |
3292 | ||
684f2888 JR |
3293 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3294 | struct device *dev) | |
3295 | { | |
657cbb6b | 3296 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3297 | struct amd_iommu *iommu; |
684f2888 JR |
3298 | u16 devid; |
3299 | ||
98fc5a69 | 3300 | if (!check_device(dev)) |
684f2888 JR |
3301 | return; |
3302 | ||
98fc5a69 | 3303 | devid = get_device_id(dev); |
684f2888 | 3304 | |
657cbb6b | 3305 | if (dev_data->domain != NULL) |
15898bbc | 3306 | detach_device(dev); |
684f2888 JR |
3307 | |
3308 | iommu = amd_iommu_rlookup_table[devid]; | |
3309 | if (!iommu) | |
3310 | return; | |
3311 | ||
684f2888 JR |
3312 | iommu_completion_wait(iommu); |
3313 | } | |
3314 | ||
01106066 JR |
3315 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3316 | struct device *dev) | |
3317 | { | |
3f4b87b9 | 3318 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3319 | struct iommu_dev_data *dev_data; |
01106066 | 3320 | struct amd_iommu *iommu; |
15898bbc | 3321 | int ret; |
01106066 | 3322 | |
98fc5a69 | 3323 | if (!check_device(dev)) |
01106066 JR |
3324 | return -EINVAL; |
3325 | ||
657cbb6b JR |
3326 | dev_data = dev->archdata.iommu; |
3327 | ||
f62dda66 | 3328 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3329 | if (!iommu) |
3330 | return -EINVAL; | |
3331 | ||
657cbb6b | 3332 | if (dev_data->domain) |
15898bbc | 3333 | detach_device(dev); |
01106066 | 3334 | |
15898bbc | 3335 | ret = attach_device(dev, domain); |
01106066 JR |
3336 | |
3337 | iommu_completion_wait(iommu); | |
3338 | ||
15898bbc | 3339 | return ret; |
01106066 JR |
3340 | } |
3341 | ||
468e2366 | 3342 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3343 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3344 | { |
3f4b87b9 | 3345 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3346 | int prot = 0; |
3347 | int ret; | |
3348 | ||
132bd68f JR |
3349 | if (domain->mode == PAGE_MODE_NONE) |
3350 | return -EINVAL; | |
3351 | ||
c6229ca6 JR |
3352 | if (iommu_prot & IOMMU_READ) |
3353 | prot |= IOMMU_PROT_IR; | |
3354 | if (iommu_prot & IOMMU_WRITE) | |
3355 | prot |= IOMMU_PROT_IW; | |
3356 | ||
5d214fe6 | 3357 | mutex_lock(&domain->api_lock); |
795e74f7 | 3358 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3359 | mutex_unlock(&domain->api_lock); |
3360 | ||
795e74f7 | 3361 | return ret; |
c6229ca6 JR |
3362 | } |
3363 | ||
5009065d OBC |
3364 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3365 | size_t page_size) | |
eb74ff6c | 3366 | { |
3f4b87b9 | 3367 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3368 | size_t unmap_size; |
eb74ff6c | 3369 | |
132bd68f JR |
3370 | if (domain->mode == PAGE_MODE_NONE) |
3371 | return -EINVAL; | |
3372 | ||
5d214fe6 | 3373 | mutex_lock(&domain->api_lock); |
468e2366 | 3374 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3375 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3376 | |
17b124bf | 3377 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3378 | |
5009065d | 3379 | return unmap_size; |
eb74ff6c JR |
3380 | } |
3381 | ||
645c4c8d | 3382 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3383 | dma_addr_t iova) |
645c4c8d | 3384 | { |
3f4b87b9 | 3385 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3386 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3387 | u64 *pte, __pte; |
645c4c8d | 3388 | |
132bd68f JR |
3389 | if (domain->mode == PAGE_MODE_NONE) |
3390 | return iova; | |
3391 | ||
3039ca1b | 3392 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3393 | |
a6d41a40 | 3394 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3395 | return 0; |
3396 | ||
b24b1b63 JR |
3397 | offset_mask = pte_pgsize - 1; |
3398 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3399 | |
b24b1b63 | 3400 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3401 | } |
3402 | ||
ab636481 | 3403 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3404 | { |
80a506b8 JR |
3405 | switch (cap) { |
3406 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3407 | return true; |
bdddadcb | 3408 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3409 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3410 | case IOMMU_CAP_NOEXEC: |
3411 | return false; | |
80a506b8 JR |
3412 | } |
3413 | ||
ab636481 | 3414 | return false; |
dbb9fd86 SY |
3415 | } |
3416 | ||
b22f6434 | 3417 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3418 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3419 | .domain_alloc = amd_iommu_domain_alloc, |
3420 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3421 | .attach_dev = amd_iommu_attach_device, |
3422 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3423 | .map = amd_iommu_map, |
3424 | .unmap = amd_iommu_unmap, | |
315786eb | 3425 | .map_sg = default_iommu_map_sg, |
26961efe | 3426 | .iova_to_phys = amd_iommu_iova_to_phys, |
aa3de9c0 | 3427 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3428 | }; |
3429 | ||
0feae533 JR |
3430 | /***************************************************************************** |
3431 | * | |
3432 | * The next functions do a basic initialization of IOMMU for pass through | |
3433 | * mode | |
3434 | * | |
3435 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3436 | * DMA-API translation. | |
3437 | * | |
3438 | *****************************************************************************/ | |
3439 | ||
3440 | int __init amd_iommu_init_passthrough(void) | |
3441 | { | |
5abcdba4 | 3442 | struct iommu_dev_data *dev_data; |
0feae533 | 3443 | struct pci_dev *dev = NULL; |
5abcdba4 | 3444 | int ret; |
0feae533 | 3445 | |
5abcdba4 JR |
3446 | ret = alloc_passthrough_domain(); |
3447 | if (ret) | |
3448 | return ret; | |
0feae533 | 3449 | |
6c54aabd | 3450 | for_each_pci_dev(dev) { |
98fc5a69 | 3451 | if (!check_device(&dev->dev)) |
0feae533 JR |
3452 | continue; |
3453 | ||
5abcdba4 JR |
3454 | dev_data = get_dev_data(&dev->dev); |
3455 | dev_data->passthrough = true; | |
3456 | ||
15898bbc | 3457 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3458 | } |
3459 | ||
2655d7a2 JR |
3460 | amd_iommu_stats_init(); |
3461 | ||
0feae533 JR |
3462 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3463 | ||
3464 | return 0; | |
3465 | } | |
72e1dcc4 JR |
3466 | |
3467 | /* IOMMUv2 specific functions */ | |
3468 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3469 | { | |
3470 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3471 | } | |
3472 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3473 | ||
3474 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3475 | { | |
3476 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3477 | } | |
3478 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3479 | |
3480 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3481 | { | |
3f4b87b9 | 3482 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3483 | unsigned long flags; |
3484 | ||
3485 | spin_lock_irqsave(&domain->lock, flags); | |
3486 | ||
3487 | /* Update data structure */ | |
3488 | domain->mode = PAGE_MODE_NONE; | |
3489 | domain->updated = true; | |
3490 | ||
3491 | /* Make changes visible to IOMMUs */ | |
3492 | update_domain(domain); | |
3493 | ||
3494 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3495 | free_pagetable(domain); | |
3496 | ||
3497 | spin_unlock_irqrestore(&domain->lock, flags); | |
3498 | } | |
3499 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3500 | |
3501 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3502 | { | |
3f4b87b9 | 3503 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3504 | unsigned long flags; |
3505 | int levels, ret; | |
3506 | ||
3507 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3508 | return -EINVAL; | |
3509 | ||
3510 | /* Number of GCR3 table levels required */ | |
3511 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3512 | levels += 1; | |
3513 | ||
3514 | if (levels > amd_iommu_max_glx_val) | |
3515 | return -EINVAL; | |
3516 | ||
3517 | spin_lock_irqsave(&domain->lock, flags); | |
3518 | ||
3519 | /* | |
3520 | * Save us all sanity checks whether devices already in the | |
3521 | * domain support IOMMUv2. Just force that the domain has no | |
3522 | * devices attached when it is switched into IOMMUv2 mode. | |
3523 | */ | |
3524 | ret = -EBUSY; | |
3525 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3526 | goto out; | |
3527 | ||
3528 | ret = -ENOMEM; | |
3529 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3530 | if (domain->gcr3_tbl == NULL) | |
3531 | goto out; | |
3532 | ||
3533 | domain->glx = levels; | |
3534 | domain->flags |= PD_IOMMUV2_MASK; | |
3535 | domain->updated = true; | |
3536 | ||
3537 | update_domain(domain); | |
3538 | ||
3539 | ret = 0; | |
3540 | ||
3541 | out: | |
3542 | spin_unlock_irqrestore(&domain->lock, flags); | |
3543 | ||
3544 | return ret; | |
3545 | } | |
3546 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3547 | |
3548 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3549 | u64 address, bool size) | |
3550 | { | |
3551 | struct iommu_dev_data *dev_data; | |
3552 | struct iommu_cmd cmd; | |
3553 | int i, ret; | |
3554 | ||
3555 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3556 | return -EINVAL; | |
3557 | ||
3558 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3559 | ||
3560 | /* | |
3561 | * IOMMU TLB needs to be flushed before Device TLB to | |
3562 | * prevent device TLB refill from IOMMU TLB | |
3563 | */ | |
3564 | for (i = 0; i < amd_iommus_present; ++i) { | |
3565 | if (domain->dev_iommu[i] == 0) | |
3566 | continue; | |
3567 | ||
3568 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3569 | if (ret != 0) | |
3570 | goto out; | |
3571 | } | |
3572 | ||
3573 | /* Wait until IOMMU TLB flushes are complete */ | |
3574 | domain_flush_complete(domain); | |
3575 | ||
3576 | /* Now flush device TLBs */ | |
3577 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3578 | struct amd_iommu *iommu; | |
3579 | int qdep; | |
3580 | ||
3581 | BUG_ON(!dev_data->ats.enabled); | |
3582 | ||
3583 | qdep = dev_data->ats.qdep; | |
3584 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3585 | ||
3586 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3587 | qdep, address, size); | |
3588 | ||
3589 | ret = iommu_queue_command(iommu, &cmd); | |
3590 | if (ret != 0) | |
3591 | goto out; | |
3592 | } | |
3593 | ||
3594 | /* Wait until all device TLBs are flushed */ | |
3595 | domain_flush_complete(domain); | |
3596 | ||
3597 | ret = 0; | |
3598 | ||
3599 | out: | |
3600 | ||
3601 | return ret; | |
3602 | } | |
3603 | ||
3604 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3605 | u64 address) | |
3606 | { | |
399be2f5 JR |
3607 | INC_STATS_COUNTER(invalidate_iotlb); |
3608 | ||
22e266c7 JR |
3609 | return __flush_pasid(domain, pasid, address, false); |
3610 | } | |
3611 | ||
3612 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3613 | u64 address) | |
3614 | { | |
3f4b87b9 | 3615 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3616 | unsigned long flags; |
3617 | int ret; | |
3618 | ||
3619 | spin_lock_irqsave(&domain->lock, flags); | |
3620 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3621 | spin_unlock_irqrestore(&domain->lock, flags); | |
3622 | ||
3623 | return ret; | |
3624 | } | |
3625 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3626 | ||
3627 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3628 | { | |
399be2f5 JR |
3629 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3630 | ||
22e266c7 JR |
3631 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3632 | true); | |
3633 | } | |
3634 | ||
3635 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3636 | { | |
3f4b87b9 | 3637 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3638 | unsigned long flags; |
3639 | int ret; | |
3640 | ||
3641 | spin_lock_irqsave(&domain->lock, flags); | |
3642 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3643 | spin_unlock_irqrestore(&domain->lock, flags); | |
3644 | ||
3645 | return ret; | |
3646 | } | |
3647 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3648 | ||
b16137b1 JR |
3649 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3650 | { | |
3651 | int index; | |
3652 | u64 *pte; | |
3653 | ||
3654 | while (true) { | |
3655 | ||
3656 | index = (pasid >> (9 * level)) & 0x1ff; | |
3657 | pte = &root[index]; | |
3658 | ||
3659 | if (level == 0) | |
3660 | break; | |
3661 | ||
3662 | if (!(*pte & GCR3_VALID)) { | |
3663 | if (!alloc) | |
3664 | return NULL; | |
3665 | ||
3666 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3667 | if (root == NULL) | |
3668 | return NULL; | |
3669 | ||
3670 | *pte = __pa(root) | GCR3_VALID; | |
3671 | } | |
3672 | ||
3673 | root = __va(*pte & PAGE_MASK); | |
3674 | ||
3675 | level -= 1; | |
3676 | } | |
3677 | ||
3678 | return pte; | |
3679 | } | |
3680 | ||
3681 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3682 | unsigned long cr3) | |
3683 | { | |
3684 | u64 *pte; | |
3685 | ||
3686 | if (domain->mode != PAGE_MODE_NONE) | |
3687 | return -EINVAL; | |
3688 | ||
3689 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3690 | if (pte == NULL) | |
3691 | return -ENOMEM; | |
3692 | ||
3693 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3694 | ||
3695 | return __amd_iommu_flush_tlb(domain, pasid); | |
3696 | } | |
3697 | ||
3698 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3699 | { | |
3700 | u64 *pte; | |
3701 | ||
3702 | if (domain->mode != PAGE_MODE_NONE) | |
3703 | return -EINVAL; | |
3704 | ||
3705 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3706 | if (pte == NULL) | |
3707 | return 0; | |
3708 | ||
3709 | *pte = 0; | |
3710 | ||
3711 | return __amd_iommu_flush_tlb(domain, pasid); | |
3712 | } | |
3713 | ||
3714 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3715 | unsigned long cr3) | |
3716 | { | |
3f4b87b9 | 3717 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3718 | unsigned long flags; |
3719 | int ret; | |
3720 | ||
3721 | spin_lock_irqsave(&domain->lock, flags); | |
3722 | ret = __set_gcr3(domain, pasid, cr3); | |
3723 | spin_unlock_irqrestore(&domain->lock, flags); | |
3724 | ||
3725 | return ret; | |
3726 | } | |
3727 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3728 | ||
3729 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3730 | { | |
3f4b87b9 | 3731 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3732 | unsigned long flags; |
3733 | int ret; | |
3734 | ||
3735 | spin_lock_irqsave(&domain->lock, flags); | |
3736 | ret = __clear_gcr3(domain, pasid); | |
3737 | spin_unlock_irqrestore(&domain->lock, flags); | |
3738 | ||
3739 | return ret; | |
3740 | } | |
3741 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3742 | |
3743 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3744 | int status, int tag) | |
3745 | { | |
3746 | struct iommu_dev_data *dev_data; | |
3747 | struct amd_iommu *iommu; | |
3748 | struct iommu_cmd cmd; | |
3749 | ||
399be2f5 JR |
3750 | INC_STATS_COUNTER(complete_ppr); |
3751 | ||
c99afa25 JR |
3752 | dev_data = get_dev_data(&pdev->dev); |
3753 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3754 | ||
3755 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3756 | tag, dev_data->pri_tlp); | |
3757 | ||
3758 | return iommu_queue_command(iommu, &cmd); | |
3759 | } | |
3760 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3761 | |
3762 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3763 | { | |
3f4b87b9 | 3764 | struct protection_domain *pdomain; |
f3572db8 | 3765 | |
3f4b87b9 JR |
3766 | pdomain = get_domain(&pdev->dev); |
3767 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3768 | return NULL; |
3769 | ||
3770 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3771 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3772 | return NULL; |
3773 | ||
3f4b87b9 | 3774 | return &pdomain->domain; |
f3572db8 JR |
3775 | } |
3776 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3777 | |
3778 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3779 | { | |
3780 | struct iommu_dev_data *dev_data; | |
3781 | ||
3782 | if (!amd_iommu_v2_supported()) | |
3783 | return; | |
3784 | ||
3785 | dev_data = get_dev_data(&pdev->dev); | |
3786 | dev_data->errata |= (1 << erratum); | |
3787 | } | |
3788 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3789 | |
3790 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3791 | struct amd_iommu_device_info *info) | |
3792 | { | |
3793 | int max_pasids; | |
3794 | int pos; | |
3795 | ||
3796 | if (pdev == NULL || info == NULL) | |
3797 | return -EINVAL; | |
3798 | ||
3799 | if (!amd_iommu_v2_supported()) | |
3800 | return -EINVAL; | |
3801 | ||
3802 | memset(info, 0, sizeof(*info)); | |
3803 | ||
3804 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3805 | if (pos) | |
3806 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3807 | ||
3808 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3809 | if (pos) | |
3810 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3811 | ||
3812 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3813 | if (pos) { | |
3814 | int features; | |
3815 | ||
3816 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3817 | max_pasids = min(max_pasids, (1 << 20)); | |
3818 | ||
3819 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3820 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3821 | ||
3822 | features = pci_pasid_features(pdev); | |
3823 | if (features & PCI_PASID_CAP_EXEC) | |
3824 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3825 | if (features & PCI_PASID_CAP_PRIV) | |
3826 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3827 | } | |
3828 | ||
3829 | return 0; | |
3830 | } | |
3831 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3832 | |
3833 | #ifdef CONFIG_IRQ_REMAP | |
3834 | ||
3835 | /***************************************************************************** | |
3836 | * | |
3837 | * Interrupt Remapping Implementation | |
3838 | * | |
3839 | *****************************************************************************/ | |
3840 | ||
3841 | union irte { | |
3842 | u32 val; | |
3843 | struct { | |
3844 | u32 valid : 1, | |
3845 | no_fault : 1, | |
3846 | int_type : 3, | |
3847 | rq_eoi : 1, | |
3848 | dm : 1, | |
3849 | rsvd_1 : 1, | |
3850 | destination : 8, | |
3851 | vector : 8, | |
3852 | rsvd_2 : 8; | |
3853 | } fields; | |
3854 | }; | |
3855 | ||
9c724966 JL |
3856 | struct irq_2_irte { |
3857 | u16 devid; /* Device ID for IRTE table */ | |
3858 | u16 index; /* Index into IRTE table*/ | |
3859 | }; | |
3860 | ||
7c71d306 JL |
3861 | struct amd_ir_data { |
3862 | struct irq_2_irte irq_2_irte; | |
3863 | union irte irte_entry; | |
3864 | union { | |
3865 | struct msi_msg msi_entry; | |
3866 | }; | |
3867 | }; | |
3868 | ||
3869 | static struct irq_chip amd_ir_chip; | |
3870 | ||
2b324506 JR |
3871 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3872 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3873 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3874 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3875 | ||
3876 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3877 | { | |
3878 | u64 dte; | |
3879 | ||
3880 | dte = amd_iommu_dev_table[devid].data[2]; | |
3881 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3882 | dte |= virt_to_phys(table->table); | |
3883 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3884 | dte |= DTE_IRQ_TABLE_LEN; | |
3885 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3886 | ||
3887 | amd_iommu_dev_table[devid].data[2] = dte; | |
3888 | } | |
3889 | ||
3890 | #define IRTE_ALLOCATED (~1U) | |
3891 | ||
3892 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3893 | { | |
3894 | struct irq_remap_table *table = NULL; | |
3895 | struct amd_iommu *iommu; | |
3896 | unsigned long flags; | |
3897 | u16 alias; | |
3898 | ||
3899 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3900 | ||
3901 | iommu = amd_iommu_rlookup_table[devid]; | |
3902 | if (!iommu) | |
3903 | goto out_unlock; | |
3904 | ||
3905 | table = irq_lookup_table[devid]; | |
3906 | if (table) | |
3907 | goto out; | |
3908 | ||
3909 | alias = amd_iommu_alias_table[devid]; | |
3910 | table = irq_lookup_table[alias]; | |
3911 | if (table) { | |
3912 | irq_lookup_table[devid] = table; | |
3913 | set_dte_irq_entry(devid, table); | |
3914 | iommu_flush_dte(iommu, devid); | |
3915 | goto out; | |
3916 | } | |
3917 | ||
3918 | /* Nothing there yet, allocate new irq remapping table */ | |
3919 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3920 | if (!table) | |
3921 | goto out; | |
3922 | ||
197887f0 JR |
3923 | /* Initialize table spin-lock */ |
3924 | spin_lock_init(&table->lock); | |
3925 | ||
2b324506 JR |
3926 | if (ioapic) |
3927 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3928 | table->min_index = 32; | |
3929 | ||
3930 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3931 | if (!table->table) { | |
3932 | kfree(table); | |
821f0f68 | 3933 | table = NULL; |
2b324506 JR |
3934 | goto out; |
3935 | } | |
3936 | ||
3937 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3938 | ||
3939 | if (ioapic) { | |
3940 | int i; | |
3941 | ||
3942 | for (i = 0; i < 32; ++i) | |
3943 | table->table[i] = IRTE_ALLOCATED; | |
3944 | } | |
3945 | ||
3946 | irq_lookup_table[devid] = table; | |
3947 | set_dte_irq_entry(devid, table); | |
3948 | iommu_flush_dte(iommu, devid); | |
3949 | if (devid != alias) { | |
3950 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3951 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3952 | iommu_flush_dte(iommu, alias); |
3953 | } | |
3954 | ||
3955 | out: | |
3956 | iommu_completion_wait(iommu); | |
3957 | ||
3958 | out_unlock: | |
3959 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3960 | ||
3961 | return table; | |
3962 | } | |
3963 | ||
3c3d4f90 | 3964 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3965 | { |
3966 | struct irq_remap_table *table; | |
3967 | unsigned long flags; | |
3968 | int index, c; | |
3969 | ||
3970 | table = get_irq_table(devid, false); | |
3971 | if (!table) | |
3972 | return -ENODEV; | |
3973 | ||
3974 | spin_lock_irqsave(&table->lock, flags); | |
3975 | ||
3976 | /* Scan table for free entries */ | |
3977 | for (c = 0, index = table->min_index; | |
3978 | index < MAX_IRQS_PER_TABLE; | |
3979 | ++index) { | |
3980 | if (table->table[index] == 0) | |
3981 | c += 1; | |
3982 | else | |
3983 | c = 0; | |
3984 | ||
3985 | if (c == count) { | |
2b324506 JR |
3986 | for (; c != 0; --c) |
3987 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3988 | ||
3989 | index -= count - 1; | |
2b324506 JR |
3990 | goto out; |
3991 | } | |
3992 | } | |
3993 | ||
3994 | index = -ENOSPC; | |
3995 | ||
3996 | out: | |
3997 | spin_unlock_irqrestore(&table->lock, flags); | |
3998 | ||
3999 | return index; | |
4000 | } | |
4001 | ||
2b324506 JR |
4002 | static int modify_irte(u16 devid, int index, union irte irte) |
4003 | { | |
4004 | struct irq_remap_table *table; | |
4005 | struct amd_iommu *iommu; | |
4006 | unsigned long flags; | |
4007 | ||
4008 | iommu = amd_iommu_rlookup_table[devid]; | |
4009 | if (iommu == NULL) | |
4010 | return -EINVAL; | |
4011 | ||
4012 | table = get_irq_table(devid, false); | |
4013 | if (!table) | |
4014 | return -ENOMEM; | |
4015 | ||
4016 | spin_lock_irqsave(&table->lock, flags); | |
4017 | table->table[index] = irte.val; | |
4018 | spin_unlock_irqrestore(&table->lock, flags); | |
4019 | ||
4020 | iommu_flush_irt(iommu, devid); | |
4021 | iommu_completion_wait(iommu); | |
4022 | ||
4023 | return 0; | |
4024 | } | |
4025 | ||
4026 | static void free_irte(u16 devid, int index) | |
4027 | { | |
4028 | struct irq_remap_table *table; | |
4029 | struct amd_iommu *iommu; | |
4030 | unsigned long flags; | |
4031 | ||
4032 | iommu = amd_iommu_rlookup_table[devid]; | |
4033 | if (iommu == NULL) | |
4034 | return; | |
4035 | ||
4036 | table = get_irq_table(devid, false); | |
4037 | if (!table) | |
4038 | return; | |
4039 | ||
4040 | spin_lock_irqsave(&table->lock, flags); | |
4041 | table->table[index] = 0; | |
4042 | spin_unlock_irqrestore(&table->lock, flags); | |
4043 | ||
4044 | iommu_flush_irt(iommu, devid); | |
4045 | iommu_completion_wait(iommu); | |
4046 | } | |
4047 | ||
7c71d306 | 4048 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 4049 | { |
7c71d306 | 4050 | int devid = -1; |
5527de74 | 4051 | |
7c71d306 JL |
4052 | switch (info->type) { |
4053 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4054 | devid = get_ioapic_devid(info->ioapic_id); | |
4055 | break; | |
4056 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4057 | devid = get_hpet_devid(info->hpet_id); | |
4058 | break; | |
4059 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4060 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4061 | devid = get_device_id(&info->msi_dev->dev); | |
4062 | break; | |
4063 | default: | |
4064 | BUG_ON(1); | |
4065 | break; | |
4066 | } | |
5527de74 | 4067 | |
7c71d306 JL |
4068 | return devid; |
4069 | } | |
5527de74 | 4070 | |
7c71d306 JL |
4071 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4072 | { | |
4073 | struct amd_iommu *iommu; | |
4074 | int devid; | |
5527de74 | 4075 | |
7c71d306 JL |
4076 | if (!info) |
4077 | return NULL; | |
5527de74 | 4078 | |
7c71d306 JL |
4079 | devid = get_devid(info); |
4080 | if (devid >= 0) { | |
4081 | iommu = amd_iommu_rlookup_table[devid]; | |
4082 | if (iommu) | |
4083 | return iommu->ir_domain; | |
4084 | } | |
5527de74 | 4085 | |
7c71d306 | 4086 | return NULL; |
5527de74 JR |
4087 | } |
4088 | ||
7c71d306 | 4089 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4090 | { |
7c71d306 JL |
4091 | struct amd_iommu *iommu; |
4092 | int devid; | |
5527de74 | 4093 | |
7c71d306 JL |
4094 | if (!info) |
4095 | return NULL; | |
5527de74 | 4096 | |
7c71d306 JL |
4097 | switch (info->type) { |
4098 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4099 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4100 | devid = get_device_id(&info->msi_dev->dev); | |
4101 | if (devid >= 0) { | |
4102 | iommu = amd_iommu_rlookup_table[devid]; | |
4103 | if (iommu) | |
4104 | return iommu->msi_domain; | |
4105 | } | |
4106 | break; | |
4107 | default: | |
4108 | break; | |
4109 | } | |
5527de74 | 4110 | |
7c71d306 JL |
4111 | return NULL; |
4112 | } | |
5527de74 | 4113 | |
6b474b82 | 4114 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4115 | .prepare = amd_iommu_prepare, |
4116 | .enable = amd_iommu_enable, | |
4117 | .disable = amd_iommu_disable, | |
4118 | .reenable = amd_iommu_reenable, | |
4119 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4120 | .get_ir_irq_domain = get_ir_irq_domain, |
4121 | .get_irq_domain = get_irq_domain, | |
4122 | }; | |
5527de74 | 4123 | |
7c71d306 JL |
4124 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4125 | struct irq_cfg *irq_cfg, | |
4126 | struct irq_alloc_info *info, | |
4127 | int devid, int index, int sub_handle) | |
4128 | { | |
4129 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4130 | struct msi_msg *msg = &data->msi_entry; | |
4131 | union irte *irte = &data->irte_entry; | |
4132 | struct IO_APIC_route_entry *entry; | |
5527de74 | 4133 | |
7c71d306 JL |
4134 | data->irq_2_irte.devid = devid; |
4135 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 4136 | |
7c71d306 JL |
4137 | /* Setup IRTE for IOMMU */ |
4138 | irte->val = 0; | |
4139 | irte->fields.vector = irq_cfg->vector; | |
4140 | irte->fields.int_type = apic->irq_delivery_mode; | |
4141 | irte->fields.destination = irq_cfg->dest_apicid; | |
4142 | irte->fields.dm = apic->irq_dest_mode; | |
4143 | irte->fields.valid = 1; | |
4144 | ||
4145 | switch (info->type) { | |
4146 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4147 | /* Setup IOAPIC entry */ | |
4148 | entry = info->ioapic_entry; | |
4149 | info->ioapic_entry = NULL; | |
4150 | memset(entry, 0, sizeof(*entry)); | |
4151 | entry->vector = index; | |
4152 | entry->mask = 0; | |
4153 | entry->trigger = info->ioapic_trigger; | |
4154 | entry->polarity = info->ioapic_polarity; | |
4155 | /* Mask level triggered irqs. */ | |
4156 | if (info->ioapic_trigger) | |
4157 | entry->mask = 1; | |
4158 | break; | |
5527de74 | 4159 | |
7c71d306 JL |
4160 | case X86_IRQ_ALLOC_TYPE_HPET: |
4161 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4162 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4163 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4164 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4165 | msg->data = irte_info->index; | |
4166 | break; | |
5527de74 | 4167 | |
7c71d306 JL |
4168 | default: |
4169 | BUG_ON(1); | |
4170 | break; | |
4171 | } | |
5527de74 JR |
4172 | } |
4173 | ||
7c71d306 JL |
4174 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4175 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4176 | { |
7c71d306 JL |
4177 | struct irq_alloc_info *info = arg; |
4178 | struct irq_data *irq_data; | |
4179 | struct amd_ir_data *data; | |
5527de74 | 4180 | struct irq_cfg *cfg; |
7c71d306 JL |
4181 | int i, ret, devid; |
4182 | int index = -1; | |
5527de74 | 4183 | |
7c71d306 JL |
4184 | if (!info) |
4185 | return -EINVAL; | |
4186 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4187 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4188 | return -EINVAL; |
4189 | ||
7c71d306 JL |
4190 | /* |
4191 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4192 | * to support multiple MSI interrupts. | |
4193 | */ | |
4194 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4195 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4196 | |
7c71d306 JL |
4197 | devid = get_devid(info); |
4198 | if (devid < 0) | |
4199 | return -EINVAL; | |
5527de74 | 4200 | |
7c71d306 JL |
4201 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4202 | if (ret < 0) | |
4203 | return ret; | |
0b4d48cb | 4204 | |
7c71d306 JL |
4205 | ret = -ENOMEM; |
4206 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4207 | if (!data) | |
4208 | goto out_free_parent; | |
0b4d48cb | 4209 | |
7c71d306 JL |
4210 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4211 | if (get_irq_table(devid, true)) | |
4212 | index = info->ioapic_pin; | |
4213 | else | |
4214 | ret = -ENOMEM; | |
4215 | } else { | |
3c3d4f90 | 4216 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4217 | } |
4218 | if (index < 0) { | |
4219 | pr_warn("Failed to allocate IRTE\n"); | |
4220 | kfree(data); | |
4221 | goto out_free_parent; | |
4222 | } | |
0b4d48cb | 4223 | |
7c71d306 JL |
4224 | for (i = 0; i < nr_irqs; i++) { |
4225 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4226 | cfg = irqd_cfg(irq_data); | |
4227 | if (!irq_data || !cfg) { | |
4228 | ret = -EINVAL; | |
4229 | goto out_free_data; | |
4230 | } | |
0b4d48cb | 4231 | |
7c71d306 JL |
4232 | if (i > 0) { |
4233 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4234 | if (!data) | |
4235 | goto out_free_data; | |
4236 | } | |
4237 | irq_data->hwirq = (devid << 16) + i; | |
4238 | irq_data->chip_data = data; | |
4239 | irq_data->chip = &amd_ir_chip; | |
4240 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4241 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4242 | } | |
4243 | return 0; | |
0b4d48cb | 4244 | |
7c71d306 JL |
4245 | out_free_data: |
4246 | for (i--; i >= 0; i--) { | |
4247 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4248 | if (irq_data) | |
4249 | kfree(irq_data->chip_data); | |
4250 | } | |
4251 | for (i = 0; i < nr_irqs; i++) | |
4252 | free_irte(devid, index + i); | |
4253 | out_free_parent: | |
4254 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4255 | return ret; | |
0b4d48cb JR |
4256 | } |
4257 | ||
7c71d306 JL |
4258 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4259 | unsigned int nr_irqs) | |
0b4d48cb | 4260 | { |
7c71d306 JL |
4261 | struct irq_2_irte *irte_info; |
4262 | struct irq_data *irq_data; | |
4263 | struct amd_ir_data *data; | |
4264 | int i; | |
0b4d48cb | 4265 | |
7c71d306 JL |
4266 | for (i = 0; i < nr_irqs; i++) { |
4267 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4268 | if (irq_data && irq_data->chip_data) { | |
4269 | data = irq_data->chip_data; | |
4270 | irte_info = &data->irq_2_irte; | |
4271 | free_irte(irte_info->devid, irte_info->index); | |
4272 | kfree(data); | |
4273 | } | |
4274 | } | |
4275 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4276 | } | |
0b4d48cb | 4277 | |
7c71d306 JL |
4278 | static void irq_remapping_activate(struct irq_domain *domain, |
4279 | struct irq_data *irq_data) | |
4280 | { | |
4281 | struct amd_ir_data *data = irq_data->chip_data; | |
4282 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4283 | |
7c71d306 | 4284 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4285 | } |
4286 | ||
7c71d306 JL |
4287 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4288 | struct irq_data *irq_data) | |
0b4d48cb | 4289 | { |
7c71d306 JL |
4290 | struct amd_ir_data *data = irq_data->chip_data; |
4291 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4292 | union irte entry; | |
0b4d48cb | 4293 | |
7c71d306 JL |
4294 | entry.val = 0; |
4295 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4296 | } | |
0b4d48cb | 4297 | |
7c71d306 JL |
4298 | static struct irq_domain_ops amd_ir_domain_ops = { |
4299 | .alloc = irq_remapping_alloc, | |
4300 | .free = irq_remapping_free, | |
4301 | .activate = irq_remapping_activate, | |
4302 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4303 | }; |
0b4d48cb | 4304 | |
7c71d306 JL |
4305 | static int amd_ir_set_affinity(struct irq_data *data, |
4306 | const struct cpumask *mask, bool force) | |
4307 | { | |
4308 | struct amd_ir_data *ir_data = data->chip_data; | |
4309 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4310 | struct irq_cfg *cfg = irqd_cfg(data); | |
4311 | struct irq_data *parent = data->parent_data; | |
4312 | int ret; | |
0b4d48cb | 4313 | |
7c71d306 JL |
4314 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4315 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4316 | return ret; | |
0b4d48cb | 4317 | |
7c71d306 JL |
4318 | /* |
4319 | * Atomically updates the IRTE with the new destination, vector | |
4320 | * and flushes the interrupt entry cache. | |
4321 | */ | |
4322 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4323 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4324 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4325 | |
7c71d306 JL |
4326 | /* |
4327 | * After this point, all the interrupts will start arriving | |
4328 | * at the new destination. So, time to cleanup the previous | |
4329 | * vector allocation. | |
4330 | */ | |
c6c2002b | 4331 | send_cleanup_vector(cfg); |
7c71d306 JL |
4332 | |
4333 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4334 | } |
4335 | ||
7c71d306 | 4336 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4337 | { |
7c71d306 | 4338 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4339 | |
7c71d306 JL |
4340 | *msg = ir_data->msi_entry; |
4341 | } | |
d976195c | 4342 | |
7c71d306 JL |
4343 | static struct irq_chip amd_ir_chip = { |
4344 | .irq_ack = ir_ack_apic_edge, | |
4345 | .irq_set_affinity = amd_ir_set_affinity, | |
4346 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4347 | }; | |
d976195c | 4348 | |
7c71d306 JL |
4349 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4350 | { | |
4351 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4352 | if (!iommu->ir_domain) | |
4353 | return -ENOMEM; | |
d976195c | 4354 | |
7c71d306 JL |
4355 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4356 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4357 | |
4358 | return 0; | |
4359 | } | |
2b324506 | 4360 | #endif |