Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
36 | #include <asm/irq_remapping.h> | |
37 | #include <asm/io_apic.h> | |
38 | #include <asm/apic.h> | |
39 | #include <asm/hw_irq.h> | |
17f5b569 | 40 | #include <asm/msidef.h> |
b6c02715 | 41 | #include <asm/proto.h> |
46a7fa27 | 42 | #include <asm/iommu.h> |
1d9b16d1 | 43 | #include <asm/gart.h> |
27c2127a | 44 | #include <asm/dma.h> |
403f81d8 JR |
45 | |
46 | #include "amd_iommu_proto.h" | |
47 | #include "amd_iommu_types.h" | |
6b474b82 | 48 | #include "irq_remapping.h" |
b6c02715 JR |
49 | |
50 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
51 | ||
815b33fd | 52 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 53 | |
aa3de9c0 OBC |
54 | /* |
55 | * This bitmap is used to advertise the page sizes our hardware support | |
56 | * to the IOMMU core, which will then use this information to split | |
57 | * physically contiguous memory regions it is mapping into page sizes | |
58 | * that we support. | |
59 | * | |
954e3dd8 | 60 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 61 | */ |
954e3dd8 | 62 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 63 | |
b6c02715 JR |
64 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
65 | ||
bd60b735 JR |
66 | /* A list of preallocated protection domains */ |
67 | static LIST_HEAD(iommu_pd_list); | |
68 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
69 | ||
8fa5f802 JR |
70 | /* List of all available dev_data structures */ |
71 | static LIST_HEAD(dev_data_list); | |
72 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
73 | ||
6efed63b JR |
74 | LIST_HEAD(ioapic_map); |
75 | LIST_HEAD(hpet_map); | |
76 | ||
0feae533 JR |
77 | /* |
78 | * Domain for untranslated devices - only allocated | |
79 | * if iommu=pt passed on kernel cmd line. | |
80 | */ | |
81 | static struct protection_domain *pt_domain; | |
82 | ||
b22f6434 | 83 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 84 | |
72e1dcc4 | 85 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 86 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 87 | |
ac1534a5 JR |
88 | static struct dma_map_ops amd_iommu_dma_ops; |
89 | ||
50917e26 JR |
90 | /* |
91 | * This struct contains device specific data for the IOMMU | |
92 | */ | |
93 | struct iommu_dev_data { | |
94 | struct list_head list; /* For domain->dev_list */ | |
95 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 96 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
97 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
98 | struct protection_domain *domain; /* Domain the device is bound to */ | |
99 | atomic_t bind; /* Domain attach reference count */ | |
100 | u16 devid; /* PCI Device ID */ | |
101 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
102 | bool passthrough; /* Default for device is pt_domain */ | |
103 | struct { | |
104 | bool enabled; | |
105 | int qdep; | |
106 | } ats; /* ATS state */ | |
107 | bool pri_tlp; /* PASID TLB required for | |
108 | PPR completions */ | |
109 | u32 errata; /* Bitmap for errata to apply */ | |
110 | }; | |
111 | ||
431b2a20 JR |
112 | /* |
113 | * general struct to manage commands send to an IOMMU | |
114 | */ | |
d6449536 | 115 | struct iommu_cmd { |
b6c02715 JR |
116 | u32 data[4]; |
117 | }; | |
118 | ||
05152a04 JR |
119 | struct kmem_cache *amd_iommu_irq_cache; |
120 | ||
04bfdd84 | 121 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 122 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 123 | |
15898bbc JR |
124 | /**************************************************************************** |
125 | * | |
126 | * Helper functions | |
127 | * | |
128 | ****************************************************************************/ | |
129 | ||
f62dda66 | 130 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
131 | { |
132 | struct iommu_dev_data *dev_data; | |
133 | unsigned long flags; | |
134 | ||
135 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
136 | if (!dev_data) | |
137 | return NULL; | |
138 | ||
f251e187 JR |
139 | INIT_LIST_HEAD(&dev_data->alias_list); |
140 | ||
f62dda66 | 141 | dev_data->devid = devid; |
8fa5f802 JR |
142 | atomic_set(&dev_data->bind, 0); |
143 | ||
144 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
145 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
146 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
147 | ||
148 | return dev_data; | |
149 | } | |
150 | ||
151 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
152 | { | |
153 | unsigned long flags; | |
154 | ||
155 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
156 | list_del(&dev_data->dev_data_list); | |
157 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
158 | ||
159 | kfree(dev_data); | |
160 | } | |
161 | ||
3b03bb74 JR |
162 | static struct iommu_dev_data *search_dev_data(u16 devid) |
163 | { | |
164 | struct iommu_dev_data *dev_data; | |
165 | unsigned long flags; | |
166 | ||
167 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
168 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
169 | if (dev_data->devid == devid) | |
170 | goto out_unlock; | |
171 | } | |
172 | ||
173 | dev_data = NULL; | |
174 | ||
175 | out_unlock: | |
176 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
177 | ||
178 | return dev_data; | |
179 | } | |
180 | ||
181 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
182 | { | |
183 | struct iommu_dev_data *dev_data; | |
184 | ||
185 | dev_data = search_dev_data(devid); | |
186 | ||
187 | if (dev_data == NULL) | |
188 | dev_data = alloc_dev_data(devid); | |
189 | ||
190 | return dev_data; | |
191 | } | |
192 | ||
15898bbc JR |
193 | static inline u16 get_device_id(struct device *dev) |
194 | { | |
195 | struct pci_dev *pdev = to_pci_dev(dev); | |
196 | ||
6f2729ba | 197 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
198 | } |
199 | ||
657cbb6b JR |
200 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
201 | { | |
202 | return dev->archdata.iommu; | |
203 | } | |
204 | ||
5abcdba4 JR |
205 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
206 | { | |
207 | static const int caps[] = { | |
208 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
209 | PCI_EXT_CAP_ID_PRI, |
210 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
211 | }; |
212 | int i, pos; | |
213 | ||
214 | for (i = 0; i < 3; ++i) { | |
215 | pos = pci_find_ext_capability(pdev, caps[i]); | |
216 | if (pos == 0) | |
217 | return false; | |
218 | } | |
219 | ||
220 | return true; | |
221 | } | |
222 | ||
6a113ddc JR |
223 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
224 | { | |
225 | struct iommu_dev_data *dev_data; | |
226 | ||
227 | dev_data = get_dev_data(&pdev->dev); | |
228 | ||
229 | return dev_data->errata & (1 << erratum) ? true : false; | |
230 | } | |
231 | ||
71c70984 JR |
232 | /* |
233 | * In this function the list of preallocated protection domains is traversed to | |
234 | * find the domain for a specific device | |
235 | */ | |
236 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
237 | { | |
238 | struct dma_ops_domain *entry, *ret = NULL; | |
239 | unsigned long flags; | |
240 | u16 alias = amd_iommu_alias_table[devid]; | |
241 | ||
242 | if (list_empty(&iommu_pd_list)) | |
243 | return NULL; | |
244 | ||
245 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
246 | ||
247 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
248 | if (entry->target_dev == devid || | |
249 | entry->target_dev == alias) { | |
250 | ret = entry; | |
251 | break; | |
252 | } | |
253 | } | |
254 | ||
255 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
256 | ||
257 | return ret; | |
258 | } | |
259 | ||
98fc5a69 JR |
260 | /* |
261 | * This function checks if the driver got a valid device from the caller to | |
262 | * avoid dereferencing invalid pointers. | |
263 | */ | |
264 | static bool check_device(struct device *dev) | |
265 | { | |
266 | u16 devid; | |
267 | ||
268 | if (!dev || !dev->dma_mask) | |
269 | return false; | |
270 | ||
b82a2272 YW |
271 | /* No PCI device */ |
272 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
273 | return false; |
274 | ||
275 | devid = get_device_id(dev); | |
276 | ||
277 | /* Out of our scope? */ | |
278 | if (devid > amd_iommu_last_bdf) | |
279 | return false; | |
280 | ||
281 | if (amd_iommu_rlookup_table[devid] == NULL) | |
282 | return false; | |
283 | ||
284 | return true; | |
285 | } | |
286 | ||
2851db21 AW |
287 | static int init_iommu_group(struct device *dev) |
288 | { | |
2851db21 | 289 | struct iommu_group *group; |
2851db21 | 290 | |
65d5352f | 291 | group = iommu_group_get_for_dev(dev); |
2851db21 | 292 | |
65d5352f AW |
293 | if (IS_ERR(group)) |
294 | return PTR_ERR(group); | |
2851db21 | 295 | |
65d5352f AW |
296 | iommu_group_put(group); |
297 | return 0; | |
eb9c9527 AW |
298 | } |
299 | ||
c1931090 AW |
300 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
301 | { | |
302 | *(u16 *)data = alias; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static u16 get_alias(struct device *dev) | |
307 | { | |
308 | struct pci_dev *pdev = to_pci_dev(dev); | |
309 | u16 devid, ivrs_alias, pci_alias; | |
310 | ||
311 | devid = get_device_id(dev); | |
312 | ivrs_alias = amd_iommu_alias_table[devid]; | |
313 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
314 | ||
315 | if (ivrs_alias == pci_alias) | |
316 | return ivrs_alias; | |
317 | ||
318 | /* | |
319 | * DMA alias showdown | |
320 | * | |
321 | * The IVRS is fairly reliable in telling us about aliases, but it | |
322 | * can't know about every screwy device. If we don't have an IVRS | |
323 | * reported alias, use the PCI reported alias. In that case we may | |
324 | * still need to initialize the rlookup and dev_table entries if the | |
325 | * alias is to a non-existent device. | |
326 | */ | |
327 | if (ivrs_alias == devid) { | |
328 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
329 | amd_iommu_rlookup_table[pci_alias] = | |
330 | amd_iommu_rlookup_table[devid]; | |
331 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
332 | amd_iommu_dev_table[devid].data, | |
333 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
334 | } | |
335 | ||
336 | return pci_alias; | |
337 | } | |
338 | ||
339 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
340 | "for device %s[%04x:%04x], kernel reported alias " | |
341 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
342 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
343 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
344 | PCI_FUNC(pci_alias)); | |
345 | ||
346 | /* | |
347 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
348 | * bus, then the IVRS table may know about a quirk that we don't. | |
349 | */ | |
350 | if (pci_alias == devid && | |
351 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
352 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
353 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
354 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
355 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
356 | dev_name(dev)); | |
357 | } | |
358 | ||
359 | return ivrs_alias; | |
360 | } | |
361 | ||
eb9c9527 AW |
362 | static int iommu_init_device(struct device *dev) |
363 | { | |
364 | struct pci_dev *pdev = to_pci_dev(dev); | |
365 | struct iommu_dev_data *dev_data; | |
366 | u16 alias; | |
367 | int ret; | |
368 | ||
369 | if (dev->archdata.iommu) | |
370 | return 0; | |
371 | ||
372 | dev_data = find_dev_data(get_device_id(dev)); | |
373 | if (!dev_data) | |
374 | return -ENOMEM; | |
375 | ||
c1931090 AW |
376 | alias = get_alias(dev); |
377 | ||
eb9c9527 AW |
378 | if (alias != dev_data->devid) { |
379 | struct iommu_dev_data *alias_data; | |
380 | ||
381 | alias_data = find_dev_data(alias); | |
382 | if (alias_data == NULL) { | |
383 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
384 | dev_name(dev)); | |
385 | free_dev_data(dev_data); | |
386 | return -ENOTSUPP; | |
387 | } | |
388 | dev_data->alias_data = alias_data; | |
f251e187 JR |
389 | |
390 | /* Add device to the alias_list */ | |
391 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
eb9c9527 AW |
392 | } |
393 | ||
394 | ret = init_iommu_group(dev); | |
e644a013 RK |
395 | if (ret) { |
396 | free_dev_data(dev_data); | |
9dcd6130 | 397 | return ret; |
e644a013 | 398 | } |
9dcd6130 | 399 | |
5abcdba4 JR |
400 | if (pci_iommuv2_capable(pdev)) { |
401 | struct amd_iommu *iommu; | |
402 | ||
403 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
404 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
405 | } | |
406 | ||
657cbb6b JR |
407 | dev->archdata.iommu = dev_data; |
408 | ||
066f2e98 AW |
409 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
410 | dev); | |
411 | ||
657cbb6b JR |
412 | return 0; |
413 | } | |
414 | ||
26018874 JR |
415 | static void iommu_ignore_device(struct device *dev) |
416 | { | |
417 | u16 devid, alias; | |
418 | ||
419 | devid = get_device_id(dev); | |
420 | alias = amd_iommu_alias_table[devid]; | |
421 | ||
422 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
423 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
424 | ||
425 | amd_iommu_rlookup_table[devid] = NULL; | |
426 | amd_iommu_rlookup_table[alias] = NULL; | |
427 | } | |
428 | ||
657cbb6b JR |
429 | static void iommu_uninit_device(struct device *dev) |
430 | { | |
c1931090 AW |
431 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
432 | ||
433 | if (!dev_data) | |
434 | return; | |
435 | ||
066f2e98 AW |
436 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
437 | dev); | |
438 | ||
9dcd6130 AW |
439 | iommu_group_remove_device(dev); |
440 | ||
c1931090 AW |
441 | /* Unlink from alias, it may change if another device is re-plugged */ |
442 | dev_data->alias_data = NULL; | |
443 | ||
8fa5f802 | 444 | /* |
c1931090 AW |
445 | * We keep dev_data around for unplugged devices and reuse it when the |
446 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 447 | */ |
657cbb6b | 448 | } |
b7cc9554 JR |
449 | |
450 | void __init amd_iommu_uninit_devices(void) | |
451 | { | |
8fa5f802 | 452 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
453 | struct pci_dev *pdev = NULL; |
454 | ||
455 | for_each_pci_dev(pdev) { | |
456 | ||
457 | if (!check_device(&pdev->dev)) | |
458 | continue; | |
459 | ||
460 | iommu_uninit_device(&pdev->dev); | |
461 | } | |
8fa5f802 JR |
462 | |
463 | /* Free all of our dev_data structures */ | |
464 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
465 | free_dev_data(dev_data); | |
b7cc9554 JR |
466 | } |
467 | ||
468 | int __init amd_iommu_init_devices(void) | |
469 | { | |
470 | struct pci_dev *pdev = NULL; | |
471 | int ret = 0; | |
472 | ||
473 | for_each_pci_dev(pdev) { | |
474 | ||
475 | if (!check_device(&pdev->dev)) | |
476 | continue; | |
477 | ||
478 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
479 | if (ret == -ENOTSUPP) |
480 | iommu_ignore_device(&pdev->dev); | |
481 | else if (ret) | |
b7cc9554 JR |
482 | goto out_free; |
483 | } | |
484 | ||
485 | return 0; | |
486 | ||
487 | out_free: | |
488 | ||
489 | amd_iommu_uninit_devices(); | |
490 | ||
491 | return ret; | |
492 | } | |
7f26508b JR |
493 | #ifdef CONFIG_AMD_IOMMU_STATS |
494 | ||
495 | /* | |
496 | * Initialization code for statistics collection | |
497 | */ | |
498 | ||
da49f6df | 499 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 500 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 501 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 502 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 503 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 504 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 505 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 506 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 507 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 508 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 509 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 510 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
511 | DECLARE_STATS_COUNTER(complete_ppr); |
512 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
513 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
514 | DECLARE_STATS_COUNTER(pri_requests); | |
515 | ||
7f26508b | 516 | static struct dentry *stats_dir; |
7f26508b JR |
517 | static struct dentry *de_fflush; |
518 | ||
519 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
520 | { | |
521 | if (stats_dir == NULL) | |
522 | return; | |
523 | ||
524 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
525 | &cnt->value); | |
526 | } | |
527 | ||
528 | static void amd_iommu_stats_init(void) | |
529 | { | |
530 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
531 | if (stats_dir == NULL) | |
532 | return; | |
533 | ||
7f26508b | 534 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 535 | &amd_iommu_unmap_flush); |
da49f6df JR |
536 | |
537 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 538 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 539 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 540 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 541 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 542 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 543 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 544 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 545 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 546 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 547 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 548 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
549 | amd_iommu_stats_add(&complete_ppr); |
550 | amd_iommu_stats_add(&invalidate_iotlb); | |
551 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
552 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
553 | } |
554 | ||
555 | #endif | |
556 | ||
a80dc3e0 JR |
557 | /**************************************************************************** |
558 | * | |
559 | * Interrupt handling functions | |
560 | * | |
561 | ****************************************************************************/ | |
562 | ||
e3e59876 JR |
563 | static void dump_dte_entry(u16 devid) |
564 | { | |
565 | int i; | |
566 | ||
ee6c2868 JR |
567 | for (i = 0; i < 4; ++i) |
568 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
569 | amd_iommu_dev_table[devid].data[i]); |
570 | } | |
571 | ||
945b4ac4 JR |
572 | static void dump_command(unsigned long phys_addr) |
573 | { | |
574 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
575 | int i; | |
576 | ||
577 | for (i = 0; i < 4; ++i) | |
578 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
579 | } | |
580 | ||
a345b23b | 581 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 582 | { |
3d06fca8 JR |
583 | int type, devid, domid, flags; |
584 | volatile u32 *event = __evt; | |
585 | int count = 0; | |
586 | u64 address; | |
587 | ||
588 | retry: | |
589 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
590 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
591 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
592 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
593 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
594 | ||
595 | if (type == 0) { | |
596 | /* Did we hit the erratum? */ | |
597 | if (++count == LOOP_TIMEOUT) { | |
598 | pr_err("AMD-Vi: No event written to event log\n"); | |
599 | return; | |
600 | } | |
601 | udelay(1); | |
602 | goto retry; | |
603 | } | |
90008ee4 | 604 | |
4c6f40d4 | 605 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
606 | |
607 | switch (type) { | |
608 | case EVENT_TYPE_ILL_DEV: | |
609 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
610 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 611 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 612 | address, flags); |
e3e59876 | 613 | dump_dte_entry(devid); |
90008ee4 JR |
614 | break; |
615 | case EVENT_TYPE_IO_FAULT: | |
616 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
617 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 618 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
619 | domid, address, flags); |
620 | break; | |
621 | case EVENT_TYPE_DEV_TAB_ERR: | |
622 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
623 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 624 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
625 | address, flags); |
626 | break; | |
627 | case EVENT_TYPE_PAGE_TAB_ERR: | |
628 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
629 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 630 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
631 | domid, address, flags); |
632 | break; | |
633 | case EVENT_TYPE_ILL_CMD: | |
634 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 635 | dump_command(address); |
90008ee4 JR |
636 | break; |
637 | case EVENT_TYPE_CMD_HARD_ERR: | |
638 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
639 | "flags=0x%04x]\n", address, flags); | |
640 | break; | |
641 | case EVENT_TYPE_IOTLB_INV_TO: | |
642 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
643 | "address=0x%016llx]\n", | |
c5081cd7 | 644 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
645 | address); |
646 | break; | |
647 | case EVENT_TYPE_INV_DEV_REQ: | |
648 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
649 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 650 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
651 | address, flags); |
652 | break; | |
653 | default: | |
654 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
655 | } | |
3d06fca8 JR |
656 | |
657 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
658 | } |
659 | ||
660 | static void iommu_poll_events(struct amd_iommu *iommu) | |
661 | { | |
662 | u32 head, tail; | |
90008ee4 JR |
663 | |
664 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
665 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
666 | ||
667 | while (head != tail) { | |
a345b23b | 668 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
669 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
670 | } | |
671 | ||
672 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
673 | } |
674 | ||
eee53537 | 675 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
676 | { |
677 | struct amd_iommu_fault fault; | |
72e1dcc4 | 678 | |
399be2f5 JR |
679 | INC_STATS_COUNTER(pri_requests); |
680 | ||
72e1dcc4 JR |
681 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
682 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
683 | return; | |
684 | } | |
685 | ||
686 | fault.address = raw[1]; | |
687 | fault.pasid = PPR_PASID(raw[0]); | |
688 | fault.device_id = PPR_DEVID(raw[0]); | |
689 | fault.tag = PPR_TAG(raw[0]); | |
690 | fault.flags = PPR_FLAGS(raw[0]); | |
691 | ||
72e1dcc4 JR |
692 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
693 | } | |
694 | ||
695 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
696 | { | |
72e1dcc4 JR |
697 | u32 head, tail; |
698 | ||
699 | if (iommu->ppr_log == NULL) | |
700 | return; | |
701 | ||
72e1dcc4 JR |
702 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
703 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
704 | ||
705 | while (head != tail) { | |
eee53537 JR |
706 | volatile u64 *raw; |
707 | u64 entry[2]; | |
708 | int i; | |
709 | ||
710 | raw = (u64 *)(iommu->ppr_log + head); | |
711 | ||
712 | /* | |
713 | * Hardware bug: Interrupt may arrive before the entry is | |
714 | * written to memory. If this happens we need to wait for the | |
715 | * entry to arrive. | |
716 | */ | |
717 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
718 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
719 | break; | |
720 | udelay(1); | |
721 | } | |
72e1dcc4 | 722 | |
eee53537 JR |
723 | /* Avoid memcpy function-call overhead */ |
724 | entry[0] = raw[0]; | |
725 | entry[1] = raw[1]; | |
72e1dcc4 | 726 | |
eee53537 JR |
727 | /* |
728 | * To detect the hardware bug we need to clear the entry | |
729 | * back to zero. | |
730 | */ | |
731 | raw[0] = raw[1] = 0UL; | |
732 | ||
733 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
734 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
735 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 736 | |
eee53537 JR |
737 | /* Handle PPR entry */ |
738 | iommu_handle_ppr_entry(iommu, entry); | |
739 | ||
eee53537 JR |
740 | /* Refresh ring-buffer information */ |
741 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
742 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
743 | } | |
72e1dcc4 JR |
744 | } |
745 | ||
72fe00f0 | 746 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 747 | { |
3f398bc7 SS |
748 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
749 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 750 | |
3f398bc7 SS |
751 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
752 | /* Enable EVT and PPR interrupts again */ | |
753 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
754 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 755 | |
3f398bc7 SS |
756 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
757 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
758 | iommu_poll_events(iommu); | |
759 | } | |
90008ee4 | 760 | |
3f398bc7 SS |
761 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
762 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
763 | iommu_poll_ppr_log(iommu); | |
764 | } | |
90008ee4 | 765 | |
3f398bc7 SS |
766 | /* |
767 | * Hardware bug: ERBT1312 | |
768 | * When re-enabling interrupt (by writing 1 | |
769 | * to clear the bit), the hardware might also try to set | |
770 | * the interrupt bit in the event status register. | |
771 | * In this scenario, the bit will be set, and disable | |
772 | * subsequent interrupts. | |
773 | * | |
774 | * Workaround: The IOMMU driver should read back the | |
775 | * status register and check if the interrupt bits are cleared. | |
776 | * If not, driver will need to go through the interrupt handler | |
777 | * again and re-clear the bits | |
778 | */ | |
779 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
780 | } | |
90008ee4 | 781 | return IRQ_HANDLED; |
a80dc3e0 JR |
782 | } |
783 | ||
72fe00f0 JR |
784 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
785 | { | |
786 | return IRQ_WAKE_THREAD; | |
787 | } | |
788 | ||
431b2a20 JR |
789 | /**************************************************************************** |
790 | * | |
791 | * IOMMU command queuing functions | |
792 | * | |
793 | ****************************************************************************/ | |
794 | ||
ac0ea6e9 JR |
795 | static int wait_on_sem(volatile u64 *sem) |
796 | { | |
797 | int i = 0; | |
798 | ||
799 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
800 | udelay(1); | |
801 | i += 1; | |
802 | } | |
803 | ||
804 | if (i == LOOP_TIMEOUT) { | |
805 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
806 | return -EIO; | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
813 | struct iommu_cmd *cmd, | |
814 | u32 tail) | |
a19ae1ec | 815 | { |
a19ae1ec JR |
816 | u8 *target; |
817 | ||
8a7c5ef3 | 818 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
819 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
820 | ||
821 | /* Copy command to buffer */ | |
822 | memcpy(target, cmd, sizeof(*cmd)); | |
823 | ||
824 | /* Tell the IOMMU about it */ | |
a19ae1ec | 825 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 826 | } |
a19ae1ec | 827 | |
815b33fd | 828 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 829 | { |
815b33fd JR |
830 | WARN_ON(address & 0x7ULL); |
831 | ||
ded46737 | 832 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
833 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
834 | cmd->data[1] = upper_32_bits(__pa(address)); | |
835 | cmd->data[2] = 1; | |
ded46737 JR |
836 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
837 | } | |
838 | ||
94fe79e2 JR |
839 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
840 | { | |
841 | memset(cmd, 0, sizeof(*cmd)); | |
842 | cmd->data[0] = devid; | |
843 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
844 | } | |
845 | ||
11b6402c JR |
846 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
847 | size_t size, u16 domid, int pde) | |
848 | { | |
849 | u64 pages; | |
850 | int s; | |
851 | ||
852 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
853 | s = 0; | |
854 | ||
855 | if (pages > 1) { | |
856 | /* | |
857 | * If we have to flush more than one page, flush all | |
858 | * TLB entries for this domain | |
859 | */ | |
860 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
861 | s = 1; | |
862 | } | |
863 | ||
864 | address &= PAGE_MASK; | |
865 | ||
866 | memset(cmd, 0, sizeof(*cmd)); | |
867 | cmd->data[1] |= domid; | |
868 | cmd->data[2] = lower_32_bits(address); | |
869 | cmd->data[3] = upper_32_bits(address); | |
870 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
871 | if (s) /* size bit - we flush more than one 4kb page */ | |
872 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 873 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
874 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
875 | } | |
876 | ||
cb41ed85 JR |
877 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
878 | u64 address, size_t size) | |
879 | { | |
880 | u64 pages; | |
881 | int s; | |
882 | ||
883 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
884 | s = 0; | |
885 | ||
886 | if (pages > 1) { | |
887 | /* | |
888 | * If we have to flush more than one page, flush all | |
889 | * TLB entries for this domain | |
890 | */ | |
891 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
892 | s = 1; | |
893 | } | |
894 | ||
895 | address &= PAGE_MASK; | |
896 | ||
897 | memset(cmd, 0, sizeof(*cmd)); | |
898 | cmd->data[0] = devid; | |
899 | cmd->data[0] |= (qdep & 0xff) << 24; | |
900 | cmd->data[1] = devid; | |
901 | cmd->data[2] = lower_32_bits(address); | |
902 | cmd->data[3] = upper_32_bits(address); | |
903 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
904 | if (s) | |
905 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
906 | } | |
907 | ||
22e266c7 JR |
908 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
909 | u64 address, bool size) | |
910 | { | |
911 | memset(cmd, 0, sizeof(*cmd)); | |
912 | ||
913 | address &= ~(0xfffULL); | |
914 | ||
a919a018 | 915 | cmd->data[0] = pasid; |
22e266c7 JR |
916 | cmd->data[1] = domid; |
917 | cmd->data[2] = lower_32_bits(address); | |
918 | cmd->data[3] = upper_32_bits(address); | |
919 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
920 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
921 | if (size) | |
922 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
923 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
924 | } | |
925 | ||
926 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
927 | int qdep, u64 address, bool size) | |
928 | { | |
929 | memset(cmd, 0, sizeof(*cmd)); | |
930 | ||
931 | address &= ~(0xfffULL); | |
932 | ||
933 | cmd->data[0] = devid; | |
e8d2d82d | 934 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
935 | cmd->data[0] |= (qdep & 0xff) << 24; |
936 | cmd->data[1] = devid; | |
e8d2d82d | 937 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
938 | cmd->data[2] = lower_32_bits(address); |
939 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
940 | cmd->data[3] = upper_32_bits(address); | |
941 | if (size) | |
942 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
943 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
944 | } | |
945 | ||
c99afa25 JR |
946 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
947 | int status, int tag, bool gn) | |
948 | { | |
949 | memset(cmd, 0, sizeof(*cmd)); | |
950 | ||
951 | cmd->data[0] = devid; | |
952 | if (gn) { | |
a919a018 | 953 | cmd->data[1] = pasid; |
c99afa25 JR |
954 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
955 | } | |
956 | cmd->data[3] = tag & 0x1ff; | |
957 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
958 | ||
959 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
960 | } | |
961 | ||
58fc7f14 JR |
962 | static void build_inv_all(struct iommu_cmd *cmd) |
963 | { | |
964 | memset(cmd, 0, sizeof(*cmd)); | |
965 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
966 | } |
967 | ||
7ef2798d JR |
968 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
969 | { | |
970 | memset(cmd, 0, sizeof(*cmd)); | |
971 | cmd->data[0] = devid; | |
972 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
973 | } | |
974 | ||
431b2a20 | 975 | /* |
431b2a20 | 976 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 977 | * hardware about the new command. |
431b2a20 | 978 | */ |
f1ca1512 JR |
979 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
980 | struct iommu_cmd *cmd, | |
981 | bool sync) | |
a19ae1ec | 982 | { |
ac0ea6e9 | 983 | u32 left, tail, head, next_tail; |
a19ae1ec | 984 | unsigned long flags; |
a19ae1ec | 985 | |
549c90dc | 986 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
987 | |
988 | again: | |
a19ae1ec | 989 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 990 | |
ac0ea6e9 JR |
991 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
992 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
993 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
994 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 995 | |
ac0ea6e9 JR |
996 | if (left <= 2) { |
997 | struct iommu_cmd sync_cmd; | |
998 | volatile u64 sem = 0; | |
999 | int ret; | |
8d201968 | 1000 | |
ac0ea6e9 JR |
1001 | build_completion_wait(&sync_cmd, (u64)&sem); |
1002 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1003 | |
ac0ea6e9 JR |
1004 | spin_unlock_irqrestore(&iommu->lock, flags); |
1005 | ||
1006 | if ((ret = wait_on_sem(&sem)) != 0) | |
1007 | return ret; | |
1008 | ||
1009 | goto again; | |
8d201968 JR |
1010 | } |
1011 | ||
ac0ea6e9 JR |
1012 | copy_cmd_to_buffer(iommu, cmd, tail); |
1013 | ||
1014 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1015 | iommu->need_sync = sync; |
ac0ea6e9 | 1016 | |
a19ae1ec | 1017 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1018 | |
815b33fd | 1019 | return 0; |
8d201968 JR |
1020 | } |
1021 | ||
f1ca1512 JR |
1022 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1023 | { | |
1024 | return iommu_queue_command_sync(iommu, cmd, true); | |
1025 | } | |
1026 | ||
8d201968 JR |
1027 | /* |
1028 | * This function queues a completion wait command into the command | |
1029 | * buffer of an IOMMU | |
1030 | */ | |
a19ae1ec | 1031 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1032 | { |
1033 | struct iommu_cmd cmd; | |
815b33fd | 1034 | volatile u64 sem = 0; |
ac0ea6e9 | 1035 | int ret; |
8d201968 | 1036 | |
09ee17eb | 1037 | if (!iommu->need_sync) |
815b33fd | 1038 | return 0; |
09ee17eb | 1039 | |
815b33fd | 1040 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1041 | |
f1ca1512 | 1042 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1043 | if (ret) |
815b33fd | 1044 | return ret; |
8d201968 | 1045 | |
ac0ea6e9 | 1046 | return wait_on_sem(&sem); |
8d201968 JR |
1047 | } |
1048 | ||
d8c13085 | 1049 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1050 | { |
d8c13085 | 1051 | struct iommu_cmd cmd; |
a19ae1ec | 1052 | |
d8c13085 | 1053 | build_inv_dte(&cmd, devid); |
7e4f88da | 1054 | |
d8c13085 JR |
1055 | return iommu_queue_command(iommu, &cmd); |
1056 | } | |
09ee17eb | 1057 | |
7d0c5cc5 JR |
1058 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1059 | { | |
1060 | u32 devid; | |
09ee17eb | 1061 | |
7d0c5cc5 JR |
1062 | for (devid = 0; devid <= 0xffff; ++devid) |
1063 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1064 | |
7d0c5cc5 JR |
1065 | iommu_completion_wait(iommu); |
1066 | } | |
84df8175 | 1067 | |
7d0c5cc5 JR |
1068 | /* |
1069 | * This function uses heavy locking and may disable irqs for some time. But | |
1070 | * this is no issue because it is only called during resume. | |
1071 | */ | |
1072 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1073 | { | |
1074 | u32 dom_id; | |
a19ae1ec | 1075 | |
7d0c5cc5 JR |
1076 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1077 | struct iommu_cmd cmd; | |
1078 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1079 | dom_id, 1); | |
1080 | iommu_queue_command(iommu, &cmd); | |
1081 | } | |
8eed9833 | 1082 | |
7d0c5cc5 | 1083 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1084 | } |
1085 | ||
58fc7f14 | 1086 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1087 | { |
58fc7f14 | 1088 | struct iommu_cmd cmd; |
0518a3a4 | 1089 | |
58fc7f14 | 1090 | build_inv_all(&cmd); |
0518a3a4 | 1091 | |
58fc7f14 JR |
1092 | iommu_queue_command(iommu, &cmd); |
1093 | iommu_completion_wait(iommu); | |
1094 | } | |
1095 | ||
7ef2798d JR |
1096 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1097 | { | |
1098 | struct iommu_cmd cmd; | |
1099 | ||
1100 | build_inv_irt(&cmd, devid); | |
1101 | ||
1102 | iommu_queue_command(iommu, &cmd); | |
1103 | } | |
1104 | ||
1105 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1106 | { | |
1107 | u32 devid; | |
1108 | ||
1109 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1110 | iommu_flush_irt(iommu, devid); | |
1111 | ||
1112 | iommu_completion_wait(iommu); | |
1113 | } | |
1114 | ||
7d0c5cc5 JR |
1115 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1116 | { | |
58fc7f14 JR |
1117 | if (iommu_feature(iommu, FEATURE_IA)) { |
1118 | iommu_flush_all(iommu); | |
1119 | } else { | |
1120 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1121 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1122 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1123 | } |
1124 | } | |
1125 | ||
431b2a20 | 1126 | /* |
cb41ed85 | 1127 | * Command send function for flushing on-device TLB |
431b2a20 | 1128 | */ |
6c542047 JR |
1129 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1130 | u64 address, size_t size) | |
3fa43655 JR |
1131 | { |
1132 | struct amd_iommu *iommu; | |
b00d3bcf | 1133 | struct iommu_cmd cmd; |
cb41ed85 | 1134 | int qdep; |
3fa43655 | 1135 | |
ea61cddb JR |
1136 | qdep = dev_data->ats.qdep; |
1137 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1138 | |
ea61cddb | 1139 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1140 | |
1141 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1142 | } |
1143 | ||
431b2a20 | 1144 | /* |
431b2a20 | 1145 | * Command send function for invalidating a device table entry |
431b2a20 | 1146 | */ |
6c542047 | 1147 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1148 | { |
3fa43655 | 1149 | struct amd_iommu *iommu; |
ee2fa743 | 1150 | int ret; |
a19ae1ec | 1151 | |
6c542047 | 1152 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1153 | |
f62dda66 | 1154 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1155 | if (ret) |
1156 | return ret; | |
1157 | ||
ea61cddb | 1158 | if (dev_data->ats.enabled) |
6c542047 | 1159 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1160 | |
ee2fa743 | 1161 | return ret; |
a19ae1ec JR |
1162 | } |
1163 | ||
431b2a20 JR |
1164 | /* |
1165 | * TLB invalidation function which is called from the mapping functions. | |
1166 | * It invalidates a single PTE if the range to flush is within a single | |
1167 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1168 | */ | |
17b124bf JR |
1169 | static void __domain_flush_pages(struct protection_domain *domain, |
1170 | u64 address, size_t size, int pde) | |
a19ae1ec | 1171 | { |
cb41ed85 | 1172 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1173 | struct iommu_cmd cmd; |
1174 | int ret = 0, i; | |
a19ae1ec | 1175 | |
11b6402c | 1176 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1177 | |
6de8ad9b JR |
1178 | for (i = 0; i < amd_iommus_present; ++i) { |
1179 | if (!domain->dev_iommu[i]) | |
1180 | continue; | |
1181 | ||
1182 | /* | |
1183 | * Devices of this domain are behind this IOMMU | |
1184 | * We need a TLB flush | |
1185 | */ | |
11b6402c | 1186 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1187 | } |
1188 | ||
cb41ed85 | 1189 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1190 | |
ea61cddb | 1191 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1192 | continue; |
1193 | ||
6c542047 | 1194 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1195 | } |
1196 | ||
11b6402c | 1197 | WARN_ON(ret); |
6de8ad9b JR |
1198 | } |
1199 | ||
17b124bf JR |
1200 | static void domain_flush_pages(struct protection_domain *domain, |
1201 | u64 address, size_t size) | |
6de8ad9b | 1202 | { |
17b124bf | 1203 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1204 | } |
b6c02715 | 1205 | |
1c655773 | 1206 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1207 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1208 | { |
17b124bf | 1209 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1210 | } |
1211 | ||
42a49f96 | 1212 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1213 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1214 | { |
17b124bf | 1215 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1216 | } |
1217 | ||
17b124bf | 1218 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1219 | { |
17b124bf | 1220 | int i; |
18811f55 | 1221 | |
17b124bf JR |
1222 | for (i = 0; i < amd_iommus_present; ++i) { |
1223 | if (!domain->dev_iommu[i]) | |
1224 | continue; | |
bfd1be18 | 1225 | |
17b124bf JR |
1226 | /* |
1227 | * Devices of this domain are behind this IOMMU | |
1228 | * We need to wait for completion of all commands. | |
1229 | */ | |
1230 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1231 | } |
e394d72a JR |
1232 | } |
1233 | ||
b00d3bcf | 1234 | |
09b42804 | 1235 | /* |
b00d3bcf | 1236 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1237 | */ |
17b124bf | 1238 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1239 | { |
b00d3bcf | 1240 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1241 | |
b00d3bcf | 1242 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1243 | device_flush_dte(dev_data); |
a345b23b JR |
1244 | } |
1245 | ||
431b2a20 JR |
1246 | /**************************************************************************** |
1247 | * | |
1248 | * The functions below are used the create the page table mappings for | |
1249 | * unity mapped regions. | |
1250 | * | |
1251 | ****************************************************************************/ | |
1252 | ||
308973d3 JR |
1253 | /* |
1254 | * This function is used to add another level to an IO page table. Adding | |
1255 | * another level increases the size of the address space by 9 bits to a size up | |
1256 | * to 64 bits. | |
1257 | */ | |
1258 | static bool increase_address_space(struct protection_domain *domain, | |
1259 | gfp_t gfp) | |
1260 | { | |
1261 | u64 *pte; | |
1262 | ||
1263 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1264 | /* address space already 64 bit large */ | |
1265 | return false; | |
1266 | ||
1267 | pte = (void *)get_zeroed_page(gfp); | |
1268 | if (!pte) | |
1269 | return false; | |
1270 | ||
1271 | *pte = PM_LEVEL_PDE(domain->mode, | |
1272 | virt_to_phys(domain->pt_root)); | |
1273 | domain->pt_root = pte; | |
1274 | domain->mode += 1; | |
1275 | domain->updated = true; | |
1276 | ||
1277 | return true; | |
1278 | } | |
1279 | ||
1280 | static u64 *alloc_pte(struct protection_domain *domain, | |
1281 | unsigned long address, | |
cbb9d729 | 1282 | unsigned long page_size, |
308973d3 JR |
1283 | u64 **pte_page, |
1284 | gfp_t gfp) | |
1285 | { | |
cbb9d729 | 1286 | int level, end_lvl; |
308973d3 | 1287 | u64 *pte, *page; |
cbb9d729 JR |
1288 | |
1289 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1290 | |
1291 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1292 | increase_address_space(domain, gfp); | |
1293 | ||
cbb9d729 JR |
1294 | level = domain->mode - 1; |
1295 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1296 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1297 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1298 | |
1299 | while (level > end_lvl) { | |
1300 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1301 | page = (u64 *)get_zeroed_page(gfp); | |
1302 | if (!page) | |
1303 | return NULL; | |
1304 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1305 | } | |
1306 | ||
cbb9d729 JR |
1307 | /* No level skipping support yet */ |
1308 | if (PM_PTE_LEVEL(*pte) != level) | |
1309 | return NULL; | |
1310 | ||
308973d3 JR |
1311 | level -= 1; |
1312 | ||
1313 | pte = IOMMU_PTE_PAGE(*pte); | |
1314 | ||
1315 | if (pte_page && level == end_lvl) | |
1316 | *pte_page = pte; | |
1317 | ||
1318 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1319 | } | |
1320 | ||
1321 | return pte; | |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * This function checks if there is a PTE for a given dma address. If | |
1326 | * there is one, it returns the pointer to it. | |
1327 | */ | |
24cd7723 | 1328 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1329 | { |
1330 | int level; | |
1331 | u64 *pte; | |
1332 | ||
24cd7723 JR |
1333 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1334 | return NULL; | |
1335 | ||
1336 | level = domain->mode - 1; | |
1337 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1338 | |
24cd7723 JR |
1339 | while (level > 0) { |
1340 | ||
1341 | /* Not Present */ | |
308973d3 JR |
1342 | if (!IOMMU_PTE_PRESENT(*pte)) |
1343 | return NULL; | |
1344 | ||
24cd7723 JR |
1345 | /* Large PTE */ |
1346 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1347 | unsigned long pte_mask, __pte; | |
1348 | ||
1349 | /* | |
1350 | * If we have a series of large PTEs, make | |
1351 | * sure to return a pointer to the first one. | |
1352 | */ | |
1353 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1354 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1355 | __pte = ((unsigned long)pte) & pte_mask; | |
1356 | ||
1357 | return (u64 *)__pte; | |
1358 | } | |
1359 | ||
1360 | /* No level skipping support yet */ | |
1361 | if (PM_PTE_LEVEL(*pte) != level) | |
1362 | return NULL; | |
1363 | ||
308973d3 JR |
1364 | level -= 1; |
1365 | ||
24cd7723 | 1366 | /* Walk to the next level */ |
308973d3 JR |
1367 | pte = IOMMU_PTE_PAGE(*pte); |
1368 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1369 | } |
1370 | ||
1371 | return pte; | |
1372 | } | |
1373 | ||
431b2a20 JR |
1374 | /* |
1375 | * Generic mapping functions. It maps a physical address into a DMA | |
1376 | * address space. It allocates the page table pages if necessary. | |
1377 | * In the future it can be extended to a generic mapping function | |
1378 | * supporting all features of AMD IOMMU page tables like level skipping | |
1379 | * and full 64 bit address spaces. | |
1380 | */ | |
38e817fe JR |
1381 | static int iommu_map_page(struct protection_domain *dom, |
1382 | unsigned long bus_addr, | |
1383 | unsigned long phys_addr, | |
abdc5eb3 | 1384 | int prot, |
cbb9d729 | 1385 | unsigned long page_size) |
bd0e5211 | 1386 | { |
8bda3092 | 1387 | u64 __pte, *pte; |
cbb9d729 | 1388 | int i, count; |
abdc5eb3 | 1389 | |
bad1cac2 | 1390 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1391 | return -EINVAL; |
1392 | ||
cbb9d729 JR |
1393 | bus_addr = PAGE_ALIGN(bus_addr); |
1394 | phys_addr = PAGE_ALIGN(phys_addr); | |
1395 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1396 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1397 | ||
1398 | for (i = 0; i < count; ++i) | |
1399 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1400 | return -EBUSY; | |
bd0e5211 | 1401 | |
cbb9d729 JR |
1402 | if (page_size > PAGE_SIZE) { |
1403 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1404 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1405 | } else | |
1406 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1407 | |
bd0e5211 JR |
1408 | if (prot & IOMMU_PROT_IR) |
1409 | __pte |= IOMMU_PTE_IR; | |
1410 | if (prot & IOMMU_PROT_IW) | |
1411 | __pte |= IOMMU_PTE_IW; | |
1412 | ||
cbb9d729 JR |
1413 | for (i = 0; i < count; ++i) |
1414 | pte[i] = __pte; | |
bd0e5211 | 1415 | |
04bfdd84 JR |
1416 | update_domain(dom); |
1417 | ||
bd0e5211 JR |
1418 | return 0; |
1419 | } | |
1420 | ||
24cd7723 JR |
1421 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1422 | unsigned long bus_addr, | |
1423 | unsigned long page_size) | |
eb74ff6c | 1424 | { |
24cd7723 JR |
1425 | unsigned long long unmap_size, unmapped; |
1426 | u64 *pte; | |
1427 | ||
1428 | BUG_ON(!is_power_of_2(page_size)); | |
1429 | ||
1430 | unmapped = 0; | |
eb74ff6c | 1431 | |
24cd7723 JR |
1432 | while (unmapped < page_size) { |
1433 | ||
1434 | pte = fetch_pte(dom, bus_addr); | |
1435 | ||
1436 | if (!pte) { | |
1437 | /* | |
1438 | * No PTE for this address | |
1439 | * move forward in 4kb steps | |
1440 | */ | |
1441 | unmap_size = PAGE_SIZE; | |
1442 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1443 | /* 4kb PTE found for this address */ | |
1444 | unmap_size = PAGE_SIZE; | |
1445 | *pte = 0ULL; | |
1446 | } else { | |
1447 | int count, i; | |
1448 | ||
1449 | /* Large PTE found which maps this address */ | |
1450 | unmap_size = PTE_PAGE_SIZE(*pte); | |
60d0ca3c AW |
1451 | |
1452 | /* Only unmap from the first pte in the page */ | |
1453 | if ((unmap_size - 1) & bus_addr) | |
1454 | break; | |
24cd7723 JR |
1455 | count = PAGE_SIZE_PTE_COUNT(unmap_size); |
1456 | for (i = 0; i < count; i++) | |
1457 | pte[i] = 0ULL; | |
1458 | } | |
1459 | ||
1460 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1461 | unmapped += unmap_size; | |
1462 | } | |
1463 | ||
60d0ca3c | 1464 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1465 | |
24cd7723 | 1466 | return unmapped; |
eb74ff6c | 1467 | } |
eb74ff6c | 1468 | |
431b2a20 JR |
1469 | /* |
1470 | * This function checks if a specific unity mapping entry is needed for | |
1471 | * this specific IOMMU. | |
1472 | */ | |
bd0e5211 JR |
1473 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1474 | struct unity_map_entry *entry) | |
1475 | { | |
1476 | u16 bdf, i; | |
1477 | ||
1478 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1479 | bdf = amd_iommu_alias_table[i]; | |
1480 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1481 | return 1; | |
1482 | } | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
431b2a20 JR |
1487 | /* |
1488 | * This function actually applies the mapping to the page table of the | |
1489 | * dma_ops domain. | |
1490 | */ | |
bd0e5211 JR |
1491 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1492 | struct unity_map_entry *e) | |
1493 | { | |
1494 | u64 addr; | |
1495 | int ret; | |
1496 | ||
1497 | for (addr = e->address_start; addr < e->address_end; | |
1498 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1499 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1500 | PAGE_SIZE); |
bd0e5211 JR |
1501 | if (ret) |
1502 | return ret; | |
1503 | /* | |
1504 | * if unity mapping is in aperture range mark the page | |
1505 | * as allocated in the aperture | |
1506 | */ | |
1507 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1508 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1509 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1510 | } |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
171e7b37 JR |
1515 | /* |
1516 | * Init the unity mappings for a specific IOMMU in the system | |
1517 | * | |
1518 | * Basically iterates over all unity mapping entries and applies them to | |
1519 | * the default domain DMA of that IOMMU if necessary. | |
1520 | */ | |
1521 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1522 | { | |
1523 | struct unity_map_entry *entry; | |
1524 | int ret; | |
1525 | ||
1526 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1527 | if (!iommu_for_unity_map(iommu, entry)) | |
1528 | continue; | |
1529 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1530 | if (ret) | |
1531 | return ret; | |
1532 | } | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
431b2a20 JR |
1537 | /* |
1538 | * Inits the unity mappings required for a specific device | |
1539 | */ | |
bd0e5211 JR |
1540 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1541 | u16 devid) | |
1542 | { | |
1543 | struct unity_map_entry *e; | |
1544 | int ret; | |
1545 | ||
1546 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1547 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1548 | continue; | |
1549 | ret = dma_ops_unity_map(dma_dom, e); | |
1550 | if (ret) | |
1551 | return ret; | |
1552 | } | |
1553 | ||
1554 | return 0; | |
1555 | } | |
1556 | ||
431b2a20 JR |
1557 | /**************************************************************************** |
1558 | * | |
1559 | * The next functions belong to the address allocator for the dma_ops | |
1560 | * interface functions. They work like the allocators in the other IOMMU | |
1561 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1562 | * the aperture. Maybe it could be enhanced in the future to a more | |
1563 | * efficient allocator. | |
1564 | * | |
1565 | ****************************************************************************/ | |
d3086444 | 1566 | |
431b2a20 | 1567 | /* |
384de729 | 1568 | * The address allocator core functions. |
431b2a20 JR |
1569 | * |
1570 | * called with domain->lock held | |
1571 | */ | |
384de729 | 1572 | |
171e7b37 JR |
1573 | /* |
1574 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1575 | * ranges. | |
1576 | */ | |
1577 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1578 | unsigned long start_page, | |
1579 | unsigned int pages) | |
1580 | { | |
1581 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1582 | ||
1583 | if (start_page + pages > last_page) | |
1584 | pages = last_page - start_page; | |
1585 | ||
1586 | for (i = start_page; i < start_page + pages; ++i) { | |
1587 | int index = i / APERTURE_RANGE_PAGES; | |
1588 | int page = i % APERTURE_RANGE_PAGES; | |
1589 | __set_bit(page, dom->aperture[index]->bitmap); | |
1590 | } | |
1591 | } | |
1592 | ||
9cabe89b JR |
1593 | /* |
1594 | * This function is used to add a new aperture range to an existing | |
1595 | * aperture in case of dma_ops domain allocation or address allocation | |
1596 | * failure. | |
1597 | */ | |
576175c2 | 1598 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1599 | bool populate, gfp_t gfp) |
1600 | { | |
1601 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1602 | struct amd_iommu *iommu; |
17f5b569 | 1603 | unsigned long i, old_size; |
9cabe89b | 1604 | |
f5e9705c JR |
1605 | #ifdef CONFIG_IOMMU_STRESS |
1606 | populate = false; | |
1607 | #endif | |
1608 | ||
9cabe89b JR |
1609 | if (index >= APERTURE_MAX_RANGES) |
1610 | return -ENOMEM; | |
1611 | ||
1612 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1613 | if (!dma_dom->aperture[index]) | |
1614 | return -ENOMEM; | |
1615 | ||
1616 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1617 | if (!dma_dom->aperture[index]->bitmap) | |
1618 | goto out_free; | |
1619 | ||
1620 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1621 | ||
1622 | if (populate) { | |
1623 | unsigned long address = dma_dom->aperture_size; | |
1624 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1625 | u64 *pte, *pte_page; | |
1626 | ||
1627 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1628 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1629 | &pte_page, gfp); |
1630 | if (!pte) | |
1631 | goto out_free; | |
1632 | ||
1633 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1634 | ||
1635 | address += APERTURE_RANGE_SIZE / 64; | |
1636 | } | |
1637 | } | |
1638 | ||
17f5b569 | 1639 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1640 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1641 | ||
17f5b569 JR |
1642 | /* Reserve address range used for MSI messages */ |
1643 | if (old_size < MSI_ADDR_BASE_LO && | |
1644 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1645 | unsigned long spage; | |
1646 | int pages; | |
1647 | ||
1648 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1649 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1650 | ||
1651 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1652 | } | |
1653 | ||
b595076a | 1654 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1655 | for_each_iommu(iommu) { |
1656 | if (iommu->exclusion_start && | |
1657 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1658 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1659 | unsigned long startpage; | |
1660 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1661 | iommu->exclusion_length, | |
1662 | PAGE_SIZE); | |
1663 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1664 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1665 | } | |
00cd122a JR |
1666 | } |
1667 | ||
1668 | /* | |
1669 | * Check for areas already mapped as present in the new aperture | |
1670 | * range and mark those pages as reserved in the allocator. Such | |
1671 | * mappings may already exist as a result of requested unity | |
1672 | * mappings for devices. | |
1673 | */ | |
1674 | for (i = dma_dom->aperture[index]->offset; | |
1675 | i < dma_dom->aperture_size; | |
1676 | i += PAGE_SIZE) { | |
24cd7723 | 1677 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1678 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1679 | continue; | |
1680 | ||
fcd0861d | 1681 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1682 | } |
1683 | ||
04bfdd84 JR |
1684 | update_domain(&dma_dom->domain); |
1685 | ||
9cabe89b JR |
1686 | return 0; |
1687 | ||
1688 | out_free: | |
04bfdd84 JR |
1689 | update_domain(&dma_dom->domain); |
1690 | ||
9cabe89b JR |
1691 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1692 | ||
1693 | kfree(dma_dom->aperture[index]); | |
1694 | dma_dom->aperture[index] = NULL; | |
1695 | ||
1696 | return -ENOMEM; | |
1697 | } | |
1698 | ||
384de729 JR |
1699 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1700 | struct dma_ops_domain *dom, | |
1701 | unsigned int pages, | |
1702 | unsigned long align_mask, | |
1703 | u64 dma_mask, | |
1704 | unsigned long start) | |
1705 | { | |
803b8cb4 | 1706 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1707 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1708 | int i = start >> APERTURE_RANGE_SHIFT; | |
1709 | unsigned long boundary_size; | |
1710 | unsigned long address = -1; | |
1711 | unsigned long limit; | |
1712 | ||
803b8cb4 JR |
1713 | next_bit >>= PAGE_SHIFT; |
1714 | ||
384de729 JR |
1715 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1716 | PAGE_SIZE) >> PAGE_SHIFT; | |
1717 | ||
1718 | for (;i < max_index; ++i) { | |
1719 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1720 | ||
1721 | if (dom->aperture[i]->offset >= dma_mask) | |
1722 | break; | |
1723 | ||
1724 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1725 | dma_mask >> PAGE_SHIFT); | |
1726 | ||
1727 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1728 | limit, next_bit, pages, 0, | |
1729 | boundary_size, align_mask); | |
1730 | if (address != -1) { | |
1731 | address = dom->aperture[i]->offset + | |
1732 | (address << PAGE_SHIFT); | |
803b8cb4 | 1733 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1734 | break; |
1735 | } | |
1736 | ||
1737 | next_bit = 0; | |
1738 | } | |
1739 | ||
1740 | return address; | |
1741 | } | |
1742 | ||
d3086444 JR |
1743 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1744 | struct dma_ops_domain *dom, | |
6d4f343f | 1745 | unsigned int pages, |
832a90c3 JR |
1746 | unsigned long align_mask, |
1747 | u64 dma_mask) | |
d3086444 | 1748 | { |
d3086444 | 1749 | unsigned long address; |
d3086444 | 1750 | |
fe16f088 JR |
1751 | #ifdef CONFIG_IOMMU_STRESS |
1752 | dom->next_address = 0; | |
1753 | dom->need_flush = true; | |
1754 | #endif | |
d3086444 | 1755 | |
384de729 | 1756 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1757 | dma_mask, dom->next_address); |
d3086444 | 1758 | |
1c655773 | 1759 | if (address == -1) { |
803b8cb4 | 1760 | dom->next_address = 0; |
384de729 JR |
1761 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1762 | dma_mask, 0); | |
1c655773 JR |
1763 | dom->need_flush = true; |
1764 | } | |
d3086444 | 1765 | |
384de729 | 1766 | if (unlikely(address == -1)) |
8fd524b3 | 1767 | address = DMA_ERROR_CODE; |
d3086444 JR |
1768 | |
1769 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1770 | ||
1771 | return address; | |
1772 | } | |
1773 | ||
431b2a20 JR |
1774 | /* |
1775 | * The address free function. | |
1776 | * | |
1777 | * called with domain->lock held | |
1778 | */ | |
d3086444 JR |
1779 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1780 | unsigned long address, | |
1781 | unsigned int pages) | |
1782 | { | |
384de729 JR |
1783 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1784 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1785 | |
384de729 JR |
1786 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1787 | ||
47bccd6b JR |
1788 | #ifdef CONFIG_IOMMU_STRESS |
1789 | if (i < 4) | |
1790 | return; | |
1791 | #endif | |
80be308d | 1792 | |
803b8cb4 | 1793 | if (address >= dom->next_address) |
80be308d | 1794 | dom->need_flush = true; |
384de729 JR |
1795 | |
1796 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1797 | |
a66022c4 | 1798 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1799 | |
d3086444 JR |
1800 | } |
1801 | ||
431b2a20 JR |
1802 | /**************************************************************************** |
1803 | * | |
1804 | * The next functions belong to the domain allocation. A domain is | |
1805 | * allocated for every IOMMU as the default domain. If device isolation | |
1806 | * is enabled, every device get its own domain. The most important thing | |
1807 | * about domains is the page table mapping the DMA address space they | |
1808 | * contain. | |
1809 | * | |
1810 | ****************************************************************************/ | |
1811 | ||
aeb26f55 JR |
1812 | /* |
1813 | * This function adds a protection domain to the global protection domain list | |
1814 | */ | |
1815 | static void add_domain_to_list(struct protection_domain *domain) | |
1816 | { | |
1817 | unsigned long flags; | |
1818 | ||
1819 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1820 | list_add(&domain->list, &amd_iommu_pd_list); | |
1821 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1822 | } | |
1823 | ||
1824 | /* | |
1825 | * This function removes a protection domain to the global | |
1826 | * protection domain list | |
1827 | */ | |
1828 | static void del_domain_from_list(struct protection_domain *domain) | |
1829 | { | |
1830 | unsigned long flags; | |
1831 | ||
1832 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1833 | list_del(&domain->list); | |
1834 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1835 | } | |
1836 | ||
ec487d1a JR |
1837 | static u16 domain_id_alloc(void) |
1838 | { | |
1839 | unsigned long flags; | |
1840 | int id; | |
1841 | ||
1842 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1843 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1844 | BUG_ON(id == 0); | |
1845 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1846 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1847 | else | |
1848 | id = 0; | |
1849 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1850 | ||
1851 | return id; | |
1852 | } | |
1853 | ||
a2acfb75 JR |
1854 | static void domain_id_free(int id) |
1855 | { | |
1856 | unsigned long flags; | |
1857 | ||
1858 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1859 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1860 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1861 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1862 | } | |
a2acfb75 | 1863 | |
5c34c403 JR |
1864 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1865 | static void free_pt_##LVL (unsigned long __pt) \ | |
1866 | { \ | |
1867 | unsigned long p; \ | |
1868 | u64 *pt; \ | |
1869 | int i; \ | |
1870 | \ | |
1871 | pt = (u64 *)__pt; \ | |
1872 | \ | |
1873 | for (i = 0; i < 512; ++i) { \ | |
1874 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1875 | continue; \ | |
1876 | \ | |
1877 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1878 | FN(p); \ | |
1879 | } \ | |
1880 | free_page((unsigned long)pt); \ | |
1881 | } | |
1882 | ||
1883 | DEFINE_FREE_PT_FN(l2, free_page) | |
1884 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1885 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1886 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1887 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1888 | ||
86db2e5d | 1889 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1890 | { |
5c34c403 | 1891 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1892 | |
5c34c403 JR |
1893 | switch (domain->mode) { |
1894 | case PAGE_MODE_NONE: | |
1895 | break; | |
1896 | case PAGE_MODE_1_LEVEL: | |
1897 | free_page(root); | |
1898 | break; | |
1899 | case PAGE_MODE_2_LEVEL: | |
1900 | free_pt_l2(root); | |
1901 | break; | |
1902 | case PAGE_MODE_3_LEVEL: | |
1903 | free_pt_l3(root); | |
1904 | break; | |
1905 | case PAGE_MODE_4_LEVEL: | |
1906 | free_pt_l4(root); | |
1907 | break; | |
1908 | case PAGE_MODE_5_LEVEL: | |
1909 | free_pt_l5(root); | |
1910 | break; | |
1911 | case PAGE_MODE_6_LEVEL: | |
1912 | free_pt_l6(root); | |
1913 | break; | |
1914 | default: | |
1915 | BUG(); | |
ec487d1a | 1916 | } |
ec487d1a JR |
1917 | } |
1918 | ||
b16137b1 JR |
1919 | static void free_gcr3_tbl_level1(u64 *tbl) |
1920 | { | |
1921 | u64 *ptr; | |
1922 | int i; | |
1923 | ||
1924 | for (i = 0; i < 512; ++i) { | |
1925 | if (!(tbl[i] & GCR3_VALID)) | |
1926 | continue; | |
1927 | ||
1928 | ptr = __va(tbl[i] & PAGE_MASK); | |
1929 | ||
1930 | free_page((unsigned long)ptr); | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1935 | { | |
1936 | u64 *ptr; | |
1937 | int i; | |
1938 | ||
1939 | for (i = 0; i < 512; ++i) { | |
1940 | if (!(tbl[i] & GCR3_VALID)) | |
1941 | continue; | |
1942 | ||
1943 | ptr = __va(tbl[i] & PAGE_MASK); | |
1944 | ||
1945 | free_gcr3_tbl_level1(ptr); | |
1946 | } | |
1947 | } | |
1948 | ||
52815b75 JR |
1949 | static void free_gcr3_table(struct protection_domain *domain) |
1950 | { | |
b16137b1 JR |
1951 | if (domain->glx == 2) |
1952 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1953 | else if (domain->glx == 1) | |
1954 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1955 | else if (domain->glx != 0) | |
1956 | BUG(); | |
1957 | ||
52815b75 JR |
1958 | free_page((unsigned long)domain->gcr3_tbl); |
1959 | } | |
1960 | ||
431b2a20 JR |
1961 | /* |
1962 | * Free a domain, only used if something went wrong in the | |
1963 | * allocation path and we need to free an already allocated page table | |
1964 | */ | |
ec487d1a JR |
1965 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1966 | { | |
384de729 JR |
1967 | int i; |
1968 | ||
ec487d1a JR |
1969 | if (!dom) |
1970 | return; | |
1971 | ||
aeb26f55 JR |
1972 | del_domain_from_list(&dom->domain); |
1973 | ||
86db2e5d | 1974 | free_pagetable(&dom->domain); |
ec487d1a | 1975 | |
384de729 JR |
1976 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1977 | if (!dom->aperture[i]) | |
1978 | continue; | |
1979 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1980 | kfree(dom->aperture[i]); | |
1981 | } | |
ec487d1a JR |
1982 | |
1983 | kfree(dom); | |
1984 | } | |
1985 | ||
431b2a20 JR |
1986 | /* |
1987 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1988 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1989 | * structures required for the dma_ops interface |
1990 | */ | |
87a64d52 | 1991 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1992 | { |
1993 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1994 | |
1995 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1996 | if (!dma_dom) | |
1997 | return NULL; | |
1998 | ||
1999 | spin_lock_init(&dma_dom->domain.lock); | |
2000 | ||
2001 | dma_dom->domain.id = domain_id_alloc(); | |
2002 | if (dma_dom->domain.id == 0) | |
2003 | goto free_dma_dom; | |
7c392cbe | 2004 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 2005 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2006 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2007 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2008 | dma_dom->domain.priv = dma_dom; |
2009 | if (!dma_dom->domain.pt_root) | |
2010 | goto free_dma_dom; | |
ec487d1a | 2011 | |
1c655773 | 2012 | dma_dom->need_flush = false; |
bd60b735 | 2013 | dma_dom->target_dev = 0xffff; |
1c655773 | 2014 | |
aeb26f55 JR |
2015 | add_domain_to_list(&dma_dom->domain); |
2016 | ||
576175c2 | 2017 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2018 | goto free_dma_dom; |
ec487d1a | 2019 | |
431b2a20 | 2020 | /* |
ec487d1a JR |
2021 | * mark the first page as allocated so we never return 0 as |
2022 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2023 | */ |
384de729 | 2024 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 2025 | dma_dom->next_address = 0; |
ec487d1a | 2026 | |
ec487d1a JR |
2027 | |
2028 | return dma_dom; | |
2029 | ||
2030 | free_dma_dom: | |
2031 | dma_ops_domain_free(dma_dom); | |
2032 | ||
2033 | return NULL; | |
2034 | } | |
2035 | ||
5b28df6f JR |
2036 | /* |
2037 | * little helper function to check whether a given protection domain is a | |
2038 | * dma_ops domain | |
2039 | */ | |
2040 | static bool dma_ops_domain(struct protection_domain *domain) | |
2041 | { | |
2042 | return domain->flags & PD_DMA_OPS_MASK; | |
2043 | } | |
2044 | ||
fd7b5535 | 2045 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2046 | { |
132bd68f | 2047 | u64 pte_root = 0; |
ee6c2868 | 2048 | u64 flags = 0; |
863c74eb | 2049 | |
132bd68f JR |
2050 | if (domain->mode != PAGE_MODE_NONE) |
2051 | pte_root = virt_to_phys(domain->pt_root); | |
2052 | ||
38ddf41b JR |
2053 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2054 | << DEV_ENTRY_MODE_SHIFT; | |
2055 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2056 | |
ee6c2868 JR |
2057 | flags = amd_iommu_dev_table[devid].data[1]; |
2058 | ||
fd7b5535 JR |
2059 | if (ats) |
2060 | flags |= DTE_FLAG_IOTLB; | |
2061 | ||
52815b75 JR |
2062 | if (domain->flags & PD_IOMMUV2_MASK) { |
2063 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2064 | u64 glx = domain->glx; | |
2065 | u64 tmp; | |
2066 | ||
2067 | pte_root |= DTE_FLAG_GV; | |
2068 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2069 | ||
2070 | /* First mask out possible old values for GCR3 table */ | |
2071 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2072 | flags &= ~tmp; | |
2073 | ||
2074 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2075 | flags &= ~tmp; | |
2076 | ||
2077 | /* Encode GCR3 table into DTE */ | |
2078 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2079 | pte_root |= tmp; | |
2080 | ||
2081 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2082 | flags |= tmp; | |
2083 | ||
2084 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2085 | flags |= tmp; | |
2086 | } | |
2087 | ||
ee6c2868 JR |
2088 | flags &= ~(0xffffUL); |
2089 | flags |= domain->id; | |
2090 | ||
2091 | amd_iommu_dev_table[devid].data[1] = flags; | |
2092 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2093 | } |
2094 | ||
2095 | static void clear_dte_entry(u16 devid) | |
2096 | { | |
15898bbc JR |
2097 | /* remove entry from the device table seen by the hardware */ |
2098 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2099 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2100 | |
2101 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2102 | } |
2103 | ||
ec9e79ef JR |
2104 | static void do_attach(struct iommu_dev_data *dev_data, |
2105 | struct protection_domain *domain) | |
7f760ddd | 2106 | { |
7f760ddd | 2107 | struct amd_iommu *iommu; |
ec9e79ef | 2108 | bool ats; |
fd7b5535 | 2109 | |
ec9e79ef JR |
2110 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2111 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2112 | |
2113 | /* Update data structures */ | |
2114 | dev_data->domain = domain; | |
2115 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2116 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2117 | |
2118 | /* Do reference counting */ | |
2119 | domain->dev_iommu[iommu->index] += 1; | |
2120 | domain->dev_cnt += 1; | |
2121 | ||
2122 | /* Flush the DTE entry */ | |
6c542047 | 2123 | device_flush_dte(dev_data); |
7f760ddd JR |
2124 | } |
2125 | ||
ec9e79ef | 2126 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2127 | { |
7f760ddd | 2128 | struct amd_iommu *iommu; |
7f760ddd | 2129 | |
ec9e79ef | 2130 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2131 | |
2132 | /* decrease reference counters */ | |
7f760ddd JR |
2133 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2134 | dev_data->domain->dev_cnt -= 1; | |
2135 | ||
2136 | /* Update data structures */ | |
2137 | dev_data->domain = NULL; | |
2138 | list_del(&dev_data->list); | |
f62dda66 | 2139 | clear_dte_entry(dev_data->devid); |
15898bbc | 2140 | |
7f760ddd | 2141 | /* Flush the DTE entry */ |
6c542047 | 2142 | device_flush_dte(dev_data); |
2b681faf JR |
2143 | } |
2144 | ||
2145 | /* | |
2146 | * If a device is not yet associated with a domain, this function does | |
2147 | * assigns it visible for the hardware | |
2148 | */ | |
ec9e79ef | 2149 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2150 | struct protection_domain *domain) |
2b681faf | 2151 | { |
84fe6c19 | 2152 | int ret; |
657cbb6b | 2153 | |
2b681faf JR |
2154 | /* lock domain */ |
2155 | spin_lock(&domain->lock); | |
2156 | ||
71f77580 JR |
2157 | if (dev_data->alias_data != NULL) { |
2158 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2159 | |
2b02b091 JR |
2160 | /* Some sanity checks */ |
2161 | ret = -EBUSY; | |
2162 | if (alias_data->domain != NULL && | |
2163 | alias_data->domain != domain) | |
2164 | goto out_unlock; | |
eba6ac60 | 2165 | |
2b02b091 JR |
2166 | if (dev_data->domain != NULL && |
2167 | dev_data->domain != domain) | |
2168 | goto out_unlock; | |
15898bbc | 2169 | |
2b02b091 | 2170 | /* Do real assignment */ |
7f760ddd | 2171 | if (alias_data->domain == NULL) |
ec9e79ef | 2172 | do_attach(alias_data, domain); |
24100055 JR |
2173 | |
2174 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2175 | } |
15898bbc | 2176 | |
7f760ddd | 2177 | if (dev_data->domain == NULL) |
ec9e79ef | 2178 | do_attach(dev_data, domain); |
eba6ac60 | 2179 | |
24100055 JR |
2180 | atomic_inc(&dev_data->bind); |
2181 | ||
84fe6c19 JL |
2182 | ret = 0; |
2183 | ||
2184 | out_unlock: | |
2185 | ||
eba6ac60 JR |
2186 | /* ready */ |
2187 | spin_unlock(&domain->lock); | |
15898bbc | 2188 | |
84fe6c19 | 2189 | return ret; |
0feae533 | 2190 | } |
b20ac0d4 | 2191 | |
52815b75 JR |
2192 | |
2193 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2194 | { | |
2195 | pci_disable_ats(pdev); | |
2196 | pci_disable_pri(pdev); | |
2197 | pci_disable_pasid(pdev); | |
2198 | } | |
2199 | ||
6a113ddc JR |
2200 | /* FIXME: Change generic reset-function to do the same */ |
2201 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2202 | { | |
2203 | u16 control; | |
2204 | int pos; | |
2205 | ||
46277b75 | 2206 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2207 | if (!pos) |
2208 | return -EINVAL; | |
2209 | ||
46277b75 JR |
2210 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2211 | control |= PCI_PRI_CTRL_RESET; | |
2212 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2213 | |
2214 | return 0; | |
2215 | } | |
2216 | ||
52815b75 JR |
2217 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2218 | { | |
6a113ddc JR |
2219 | bool reset_enable; |
2220 | int reqs, ret; | |
2221 | ||
2222 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2223 | reqs = 32; | |
2224 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2225 | reqs = 1; | |
2226 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2227 | |
2228 | /* Only allow access to user-accessible pages */ | |
2229 | ret = pci_enable_pasid(pdev, 0); | |
2230 | if (ret) | |
2231 | goto out_err; | |
2232 | ||
2233 | /* First reset the PRI state of the device */ | |
2234 | ret = pci_reset_pri(pdev); | |
2235 | if (ret) | |
2236 | goto out_err; | |
2237 | ||
6a113ddc JR |
2238 | /* Enable PRI */ |
2239 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2240 | if (ret) |
2241 | goto out_err; | |
2242 | ||
6a113ddc JR |
2243 | if (reset_enable) { |
2244 | ret = pri_reset_while_enabled(pdev); | |
2245 | if (ret) | |
2246 | goto out_err; | |
2247 | } | |
2248 | ||
52815b75 JR |
2249 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2250 | if (ret) | |
2251 | goto out_err; | |
2252 | ||
2253 | return 0; | |
2254 | ||
2255 | out_err: | |
2256 | pci_disable_pri(pdev); | |
2257 | pci_disable_pasid(pdev); | |
2258 | ||
2259 | return ret; | |
2260 | } | |
2261 | ||
c99afa25 | 2262 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2263 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2264 | |
98f1ad25 | 2265 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2266 | { |
a3b93121 | 2267 | u16 status; |
c99afa25 JR |
2268 | int pos; |
2269 | ||
46277b75 | 2270 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2271 | if (!pos) |
2272 | return false; | |
2273 | ||
a3b93121 | 2274 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2275 | |
a3b93121 | 2276 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2277 | } |
2278 | ||
407d733e | 2279 | /* |
df805abb | 2280 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2281 | * assigns it visible for the hardware |
2282 | */ | |
15898bbc JR |
2283 | static int attach_device(struct device *dev, |
2284 | struct protection_domain *domain) | |
0feae533 | 2285 | { |
fd7b5535 | 2286 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2287 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2288 | unsigned long flags; |
15898bbc | 2289 | int ret; |
eba6ac60 | 2290 | |
ea61cddb JR |
2291 | dev_data = get_dev_data(dev); |
2292 | ||
52815b75 JR |
2293 | if (domain->flags & PD_IOMMUV2_MASK) { |
2294 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2295 | return -EINVAL; | |
2296 | ||
2297 | if (pdev_iommuv2_enable(pdev) != 0) | |
2298 | return -EINVAL; | |
2299 | ||
2300 | dev_data->ats.enabled = true; | |
2301 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2302 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2303 | } else if (amd_iommu_iotlb_sup && |
2304 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2305 | dev_data->ats.enabled = true; |
2306 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2307 | } | |
fd7b5535 | 2308 | |
eba6ac60 | 2309 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2310 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2311 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2312 | ||
0feae533 JR |
2313 | /* |
2314 | * We might boot into a crash-kernel here. The crashed kernel | |
2315 | * left the caches in the IOMMU dirty. So we have to flush | |
2316 | * here to evict all dirty stuff. | |
2317 | */ | |
17b124bf | 2318 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2319 | |
2320 | return ret; | |
b20ac0d4 JR |
2321 | } |
2322 | ||
355bf553 JR |
2323 | /* |
2324 | * Removes a device from a protection domain (unlocked) | |
2325 | */ | |
ec9e79ef | 2326 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2327 | { |
2ca76279 | 2328 | struct protection_domain *domain; |
7c392cbe | 2329 | unsigned long flags; |
c4596114 | 2330 | |
7f760ddd | 2331 | BUG_ON(!dev_data->domain); |
355bf553 | 2332 | |
2ca76279 JR |
2333 | domain = dev_data->domain; |
2334 | ||
2335 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2336 | |
71f77580 JR |
2337 | if (dev_data->alias_data != NULL) { |
2338 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2339 | ||
7f760ddd | 2340 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2341 | do_detach(alias_data); |
24100055 JR |
2342 | } |
2343 | ||
7f760ddd | 2344 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2345 | do_detach(dev_data); |
7f760ddd | 2346 | |
2ca76279 | 2347 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2348 | |
2349 | /* | |
2350 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2351 | * passthrough domain if it is detached from any other domain. |
2352 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2353 | */ |
5abcdba4 | 2354 | if (dev_data->passthrough && |
d3ad9373 | 2355 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2356 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2357 | } |
2358 | ||
2359 | /* | |
2360 | * Removes a device from a protection domain (with devtable_lock held) | |
2361 | */ | |
15898bbc | 2362 | static void detach_device(struct device *dev) |
355bf553 | 2363 | { |
52815b75 | 2364 | struct protection_domain *domain; |
ea61cddb | 2365 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2366 | unsigned long flags; |
2367 | ||
ec9e79ef | 2368 | dev_data = get_dev_data(dev); |
52815b75 | 2369 | domain = dev_data->domain; |
ec9e79ef | 2370 | |
355bf553 JR |
2371 | /* lock device table */ |
2372 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2373 | __detach_device(dev_data); |
355bf553 | 2374 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2375 | |
52815b75 JR |
2376 | if (domain->flags & PD_IOMMUV2_MASK) |
2377 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2378 | else if (dev_data->ats.enabled) | |
ea61cddb | 2379 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2380 | |
2381 | dev_data->ats.enabled = false; | |
355bf553 | 2382 | } |
e275a2a0 | 2383 | |
15898bbc JR |
2384 | /* |
2385 | * Find out the protection domain structure for a given PCI device. This | |
2386 | * will give us the pointer to the page table root for example. | |
2387 | */ | |
2388 | static struct protection_domain *domain_for_device(struct device *dev) | |
2389 | { | |
71f77580 | 2390 | struct iommu_dev_data *dev_data; |
2b02b091 | 2391 | struct protection_domain *dom = NULL; |
15898bbc | 2392 | unsigned long flags; |
15898bbc | 2393 | |
657cbb6b | 2394 | dev_data = get_dev_data(dev); |
15898bbc | 2395 | |
2b02b091 JR |
2396 | if (dev_data->domain) |
2397 | return dev_data->domain; | |
15898bbc | 2398 | |
71f77580 JR |
2399 | if (dev_data->alias_data != NULL) { |
2400 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2401 | |
2402 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2403 | if (alias_data->domain != NULL) { | |
2404 | __attach_device(dev_data, alias_data->domain); | |
2405 | dom = alias_data->domain; | |
2406 | } | |
2407 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2408 | } | |
15898bbc JR |
2409 | |
2410 | return dom; | |
2411 | } | |
2412 | ||
e275a2a0 JR |
2413 | static int device_change_notifier(struct notifier_block *nb, |
2414 | unsigned long action, void *data) | |
2415 | { | |
e275a2a0 | 2416 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2417 | struct protection_domain *domain; |
2418 | struct iommu_dev_data *dev_data; | |
2419 | struct device *dev = data; | |
e275a2a0 | 2420 | struct amd_iommu *iommu; |
1ac4cbbc | 2421 | unsigned long flags; |
5abcdba4 | 2422 | u16 devid; |
e275a2a0 | 2423 | |
98fc5a69 JR |
2424 | if (!check_device(dev)) |
2425 | return 0; | |
e275a2a0 | 2426 | |
5abcdba4 JR |
2427 | devid = get_device_id(dev); |
2428 | iommu = amd_iommu_rlookup_table[devid]; | |
2429 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2430 | |
2431 | switch (action) { | |
c1eee67b | 2432 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2433 | |
2434 | domain = domain_for_device(dev); | |
2435 | ||
e275a2a0 JR |
2436 | if (!domain) |
2437 | goto out; | |
5abcdba4 | 2438 | if (dev_data->passthrough) |
a1ca331c | 2439 | break; |
15898bbc | 2440 | detach_device(dev); |
1ac4cbbc JR |
2441 | break; |
2442 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2443 | |
2444 | iommu_init_device(dev); | |
2445 | ||
2c9195e9 JR |
2446 | /* |
2447 | * dev_data is still NULL and | |
2448 | * got initialized in iommu_init_device | |
2449 | */ | |
2450 | dev_data = get_dev_data(dev); | |
2451 | ||
2452 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2453 | dev_data->passthrough = true; | |
2454 | attach_device(dev, pt_domain); | |
2455 | break; | |
2456 | } | |
2457 | ||
657cbb6b JR |
2458 | domain = domain_for_device(dev); |
2459 | ||
1ac4cbbc JR |
2460 | /* allocate a protection domain if a device is added */ |
2461 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2462 | if (!dma_domain) { |
2463 | dma_domain = dma_ops_domain_alloc(); | |
2464 | if (!dma_domain) | |
2465 | goto out; | |
2466 | dma_domain->target_dev = devid; | |
2467 | ||
2468 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2469 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2470 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2471 | } | |
ac1534a5 | 2472 | |
2c9195e9 | 2473 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2474 | |
e275a2a0 | 2475 | break; |
657cbb6b JR |
2476 | case BUS_NOTIFY_DEL_DEVICE: |
2477 | ||
2478 | iommu_uninit_device(dev); | |
2479 | ||
e275a2a0 JR |
2480 | default: |
2481 | goto out; | |
2482 | } | |
2483 | ||
e275a2a0 JR |
2484 | iommu_completion_wait(iommu); |
2485 | ||
2486 | out: | |
2487 | return 0; | |
2488 | } | |
2489 | ||
b25ae679 | 2490 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2491 | .notifier_call = device_change_notifier, |
2492 | }; | |
355bf553 | 2493 | |
8638c491 JR |
2494 | void amd_iommu_init_notifier(void) |
2495 | { | |
2496 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2497 | } | |
2498 | ||
431b2a20 JR |
2499 | /***************************************************************************** |
2500 | * | |
2501 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2502 | * | |
2503 | *****************************************************************************/ | |
2504 | ||
2505 | /* | |
2506 | * In the dma_ops path we only have the struct device. This function | |
2507 | * finds the corresponding IOMMU, the protection domain and the | |
2508 | * requestor id for a given device. | |
2509 | * If the device is not yet associated with a domain this is also done | |
2510 | * in this function. | |
2511 | */ | |
94f6d190 | 2512 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2513 | { |
94f6d190 | 2514 | struct protection_domain *domain; |
b20ac0d4 | 2515 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2516 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2517 | |
f99c0f1c | 2518 | if (!check_device(dev)) |
94f6d190 | 2519 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2520 | |
94f6d190 JR |
2521 | domain = domain_for_device(dev); |
2522 | if (domain != NULL && !dma_ops_domain(domain)) | |
2523 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2524 | |
94f6d190 JR |
2525 | if (domain != NULL) |
2526 | return domain; | |
b20ac0d4 | 2527 | |
df805abb | 2528 | /* Device not bound yet - bind it */ |
94f6d190 | 2529 | dma_dom = find_protection_domain(devid); |
15898bbc | 2530 | if (!dma_dom) |
94f6d190 JR |
2531 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2532 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2533 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2534 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2535 | |
94f6d190 | 2536 | return &dma_dom->domain; |
b20ac0d4 JR |
2537 | } |
2538 | ||
04bfdd84 JR |
2539 | static void update_device_table(struct protection_domain *domain) |
2540 | { | |
492667da | 2541 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2542 | |
ea61cddb JR |
2543 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2544 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2545 | } |
2546 | ||
2547 | static void update_domain(struct protection_domain *domain) | |
2548 | { | |
2549 | if (!domain->updated) | |
2550 | return; | |
2551 | ||
2552 | update_device_table(domain); | |
17b124bf JR |
2553 | |
2554 | domain_flush_devices(domain); | |
2555 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2556 | |
2557 | domain->updated = false; | |
2558 | } | |
2559 | ||
8bda3092 JR |
2560 | /* |
2561 | * This function fetches the PTE for a given address in the aperture | |
2562 | */ | |
2563 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2564 | unsigned long address) | |
2565 | { | |
384de729 | 2566 | struct aperture_range *aperture; |
8bda3092 JR |
2567 | u64 *pte, *pte_page; |
2568 | ||
384de729 JR |
2569 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2570 | if (!aperture) | |
2571 | return NULL; | |
2572 | ||
2573 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2574 | if (!pte) { |
cbb9d729 | 2575 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2576 | GFP_ATOMIC); |
384de729 JR |
2577 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2578 | } else | |
8c8c143c | 2579 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2580 | |
04bfdd84 | 2581 | update_domain(&dom->domain); |
8bda3092 JR |
2582 | |
2583 | return pte; | |
2584 | } | |
2585 | ||
431b2a20 JR |
2586 | /* |
2587 | * This is the generic map function. It maps one 4kb page at paddr to | |
2588 | * the given address in the DMA address space for the domain. | |
2589 | */ | |
680525e0 | 2590 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2591 | unsigned long address, |
2592 | phys_addr_t paddr, | |
2593 | int direction) | |
2594 | { | |
2595 | u64 *pte, __pte; | |
2596 | ||
2597 | WARN_ON(address > dom->aperture_size); | |
2598 | ||
2599 | paddr &= PAGE_MASK; | |
2600 | ||
8bda3092 | 2601 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2602 | if (!pte) |
8fd524b3 | 2603 | return DMA_ERROR_CODE; |
cb76c322 JR |
2604 | |
2605 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2606 | ||
2607 | if (direction == DMA_TO_DEVICE) | |
2608 | __pte |= IOMMU_PTE_IR; | |
2609 | else if (direction == DMA_FROM_DEVICE) | |
2610 | __pte |= IOMMU_PTE_IW; | |
2611 | else if (direction == DMA_BIDIRECTIONAL) | |
2612 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2613 | ||
2614 | WARN_ON(*pte); | |
2615 | ||
2616 | *pte = __pte; | |
2617 | ||
2618 | return (dma_addr_t)address; | |
2619 | } | |
2620 | ||
431b2a20 JR |
2621 | /* |
2622 | * The generic unmapping function for on page in the DMA address space. | |
2623 | */ | |
680525e0 | 2624 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2625 | unsigned long address) |
2626 | { | |
384de729 | 2627 | struct aperture_range *aperture; |
cb76c322 JR |
2628 | u64 *pte; |
2629 | ||
2630 | if (address >= dom->aperture_size) | |
2631 | return; | |
2632 | ||
384de729 JR |
2633 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2634 | if (!aperture) | |
2635 | return; | |
2636 | ||
2637 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2638 | if (!pte) | |
2639 | return; | |
cb76c322 | 2640 | |
8c8c143c | 2641 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2642 | |
2643 | WARN_ON(!*pte); | |
2644 | ||
2645 | *pte = 0ULL; | |
2646 | } | |
2647 | ||
431b2a20 JR |
2648 | /* |
2649 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2650 | * contiguous memory region into DMA address space. It is used by all |
2651 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2652 | * Must be called with the domain lock held. |
2653 | */ | |
cb76c322 | 2654 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2655 | struct dma_ops_domain *dma_dom, |
2656 | phys_addr_t paddr, | |
2657 | size_t size, | |
6d4f343f | 2658 | int dir, |
832a90c3 JR |
2659 | bool align, |
2660 | u64 dma_mask) | |
cb76c322 JR |
2661 | { |
2662 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2663 | dma_addr_t address, start, ret; |
cb76c322 | 2664 | unsigned int pages; |
6d4f343f | 2665 | unsigned long align_mask = 0; |
cb76c322 JR |
2666 | int i; |
2667 | ||
e3c449f5 | 2668 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2669 | paddr &= PAGE_MASK; |
2670 | ||
8ecaf8f1 JR |
2671 | INC_STATS_COUNTER(total_map_requests); |
2672 | ||
c1858976 JR |
2673 | if (pages > 1) |
2674 | INC_STATS_COUNTER(cross_page); | |
2675 | ||
6d4f343f JR |
2676 | if (align) |
2677 | align_mask = (1UL << get_order(size)) - 1; | |
2678 | ||
11b83888 | 2679 | retry: |
832a90c3 JR |
2680 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2681 | dma_mask); | |
8fd524b3 | 2682 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2683 | /* |
2684 | * setting next_address here will let the address | |
2685 | * allocator only scan the new allocated range in the | |
2686 | * first run. This is a small optimization. | |
2687 | */ | |
2688 | dma_dom->next_address = dma_dom->aperture_size; | |
2689 | ||
576175c2 | 2690 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2691 | goto out; |
2692 | ||
2693 | /* | |
af901ca1 | 2694 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2695 | * allocation again |
2696 | */ | |
2697 | goto retry; | |
2698 | } | |
cb76c322 JR |
2699 | |
2700 | start = address; | |
2701 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2702 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2703 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2704 | goto out_unmap; |
2705 | ||
cb76c322 JR |
2706 | paddr += PAGE_SIZE; |
2707 | start += PAGE_SIZE; | |
2708 | } | |
2709 | address += offset; | |
2710 | ||
5774f7c5 JR |
2711 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2712 | ||
afa9fdc2 | 2713 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2714 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2715 | dma_dom->need_flush = false; |
318afd41 | 2716 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2717 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2718 | |
cb76c322 JR |
2719 | out: |
2720 | return address; | |
53812c11 JR |
2721 | |
2722 | out_unmap: | |
2723 | ||
2724 | for (--i; i >= 0; --i) { | |
2725 | start -= PAGE_SIZE; | |
680525e0 | 2726 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2727 | } |
2728 | ||
2729 | dma_ops_free_addresses(dma_dom, address, pages); | |
2730 | ||
8fd524b3 | 2731 | return DMA_ERROR_CODE; |
cb76c322 JR |
2732 | } |
2733 | ||
431b2a20 JR |
2734 | /* |
2735 | * Does the reverse of the __map_single function. Must be called with | |
2736 | * the domain lock held too | |
2737 | */ | |
cd8c82e8 | 2738 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2739 | dma_addr_t dma_addr, |
2740 | size_t size, | |
2741 | int dir) | |
2742 | { | |
04e0463e | 2743 | dma_addr_t flush_addr; |
cb76c322 JR |
2744 | dma_addr_t i, start; |
2745 | unsigned int pages; | |
2746 | ||
8fd524b3 | 2747 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2748 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2749 | return; |
2750 | ||
04e0463e | 2751 | flush_addr = dma_addr; |
e3c449f5 | 2752 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2753 | dma_addr &= PAGE_MASK; |
2754 | start = dma_addr; | |
2755 | ||
2756 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2757 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2758 | start += PAGE_SIZE; |
2759 | } | |
2760 | ||
5774f7c5 JR |
2761 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2762 | ||
cb76c322 | 2763 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2764 | |
80be308d | 2765 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2766 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2767 | dma_dom->need_flush = false; |
2768 | } | |
cb76c322 JR |
2769 | } |
2770 | ||
431b2a20 JR |
2771 | /* |
2772 | * The exported map_single function for dma_ops. | |
2773 | */ | |
51491367 FT |
2774 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2775 | unsigned long offset, size_t size, | |
2776 | enum dma_data_direction dir, | |
2777 | struct dma_attrs *attrs) | |
4da70b9e JR |
2778 | { |
2779 | unsigned long flags; | |
4da70b9e | 2780 | struct protection_domain *domain; |
4da70b9e | 2781 | dma_addr_t addr; |
832a90c3 | 2782 | u64 dma_mask; |
51491367 | 2783 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2784 | |
0f2a86f2 JR |
2785 | INC_STATS_COUNTER(cnt_map_single); |
2786 | ||
94f6d190 JR |
2787 | domain = get_domain(dev); |
2788 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2789 | return (dma_addr_t)paddr; |
94f6d190 JR |
2790 | else if (IS_ERR(domain)) |
2791 | return DMA_ERROR_CODE; | |
4da70b9e | 2792 | |
f99c0f1c JR |
2793 | dma_mask = *dev->dma_mask; |
2794 | ||
4da70b9e | 2795 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2796 | |
cd8c82e8 | 2797 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2798 | dma_mask); |
8fd524b3 | 2799 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2800 | goto out; |
2801 | ||
17b124bf | 2802 | domain_flush_complete(domain); |
4da70b9e JR |
2803 | |
2804 | out: | |
2805 | spin_unlock_irqrestore(&domain->lock, flags); | |
2806 | ||
2807 | return addr; | |
2808 | } | |
2809 | ||
431b2a20 JR |
2810 | /* |
2811 | * The exported unmap_single function for dma_ops. | |
2812 | */ | |
51491367 FT |
2813 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2814 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2815 | { |
2816 | unsigned long flags; | |
4da70b9e | 2817 | struct protection_domain *domain; |
4da70b9e | 2818 | |
146a6917 JR |
2819 | INC_STATS_COUNTER(cnt_unmap_single); |
2820 | ||
94f6d190 JR |
2821 | domain = get_domain(dev); |
2822 | if (IS_ERR(domain)) | |
5b28df6f JR |
2823 | return; |
2824 | ||
4da70b9e JR |
2825 | spin_lock_irqsave(&domain->lock, flags); |
2826 | ||
cd8c82e8 | 2827 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2828 | |
17b124bf | 2829 | domain_flush_complete(domain); |
4da70b9e JR |
2830 | |
2831 | spin_unlock_irqrestore(&domain->lock, flags); | |
2832 | } | |
2833 | ||
431b2a20 JR |
2834 | /* |
2835 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2836 | * lists). | |
2837 | */ | |
65b050ad | 2838 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2839 | int nelems, enum dma_data_direction dir, |
2840 | struct dma_attrs *attrs) | |
65b050ad JR |
2841 | { |
2842 | unsigned long flags; | |
65b050ad | 2843 | struct protection_domain *domain; |
65b050ad JR |
2844 | int i; |
2845 | struct scatterlist *s; | |
2846 | phys_addr_t paddr; | |
2847 | int mapped_elems = 0; | |
832a90c3 | 2848 | u64 dma_mask; |
65b050ad | 2849 | |
d03f067a JR |
2850 | INC_STATS_COUNTER(cnt_map_sg); |
2851 | ||
94f6d190 | 2852 | domain = get_domain(dev); |
a0e191b2 | 2853 | if (IS_ERR(domain)) |
94f6d190 | 2854 | return 0; |
dbcc112e | 2855 | |
832a90c3 | 2856 | dma_mask = *dev->dma_mask; |
65b050ad | 2857 | |
65b050ad JR |
2858 | spin_lock_irqsave(&domain->lock, flags); |
2859 | ||
2860 | for_each_sg(sglist, s, nelems, i) { | |
2861 | paddr = sg_phys(s); | |
2862 | ||
cd8c82e8 | 2863 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2864 | paddr, s->length, dir, false, |
2865 | dma_mask); | |
65b050ad JR |
2866 | |
2867 | if (s->dma_address) { | |
2868 | s->dma_length = s->length; | |
2869 | mapped_elems++; | |
2870 | } else | |
2871 | goto unmap; | |
65b050ad JR |
2872 | } |
2873 | ||
17b124bf | 2874 | domain_flush_complete(domain); |
65b050ad JR |
2875 | |
2876 | out: | |
2877 | spin_unlock_irqrestore(&domain->lock, flags); | |
2878 | ||
2879 | return mapped_elems; | |
2880 | unmap: | |
2881 | for_each_sg(sglist, s, mapped_elems, i) { | |
2882 | if (s->dma_address) | |
cd8c82e8 | 2883 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2884 | s->dma_length, dir); |
2885 | s->dma_address = s->dma_length = 0; | |
2886 | } | |
2887 | ||
2888 | mapped_elems = 0; | |
2889 | ||
2890 | goto out; | |
2891 | } | |
2892 | ||
431b2a20 JR |
2893 | /* |
2894 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2895 | * lists). | |
2896 | */ | |
65b050ad | 2897 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2898 | int nelems, enum dma_data_direction dir, |
2899 | struct dma_attrs *attrs) | |
65b050ad JR |
2900 | { |
2901 | unsigned long flags; | |
65b050ad JR |
2902 | struct protection_domain *domain; |
2903 | struct scatterlist *s; | |
65b050ad JR |
2904 | int i; |
2905 | ||
55877a6b JR |
2906 | INC_STATS_COUNTER(cnt_unmap_sg); |
2907 | ||
94f6d190 JR |
2908 | domain = get_domain(dev); |
2909 | if (IS_ERR(domain)) | |
5b28df6f JR |
2910 | return; |
2911 | ||
65b050ad JR |
2912 | spin_lock_irqsave(&domain->lock, flags); |
2913 | ||
2914 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2915 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2916 | s->dma_length, dir); |
65b050ad JR |
2917 | s->dma_address = s->dma_length = 0; |
2918 | } | |
2919 | ||
17b124bf | 2920 | domain_flush_complete(domain); |
65b050ad JR |
2921 | |
2922 | spin_unlock_irqrestore(&domain->lock, flags); | |
2923 | } | |
2924 | ||
431b2a20 JR |
2925 | /* |
2926 | * The exported alloc_coherent function for dma_ops. | |
2927 | */ | |
5d8b53cf | 2928 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2929 | dma_addr_t *dma_addr, gfp_t flag, |
2930 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2931 | { |
2932 | unsigned long flags; | |
2933 | void *virt_addr; | |
5d8b53cf | 2934 | struct protection_domain *domain; |
5d8b53cf | 2935 | phys_addr_t paddr; |
832a90c3 | 2936 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2937 | |
c8f0fb36 JR |
2938 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2939 | ||
94f6d190 JR |
2940 | domain = get_domain(dev); |
2941 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2942 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2943 | *dma_addr = __pa(virt_addr); | |
2944 | return virt_addr; | |
94f6d190 JR |
2945 | } else if (IS_ERR(domain)) |
2946 | return NULL; | |
5d8b53cf | 2947 | |
f99c0f1c JR |
2948 | dma_mask = dev->coherent_dma_mask; |
2949 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2950 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2951 | |
2952 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2953 | if (!virt_addr) | |
b25ae679 | 2954 | return NULL; |
5d8b53cf | 2955 | |
5d8b53cf JR |
2956 | paddr = virt_to_phys(virt_addr); |
2957 | ||
832a90c3 JR |
2958 | if (!dma_mask) |
2959 | dma_mask = *dev->dma_mask; | |
2960 | ||
5d8b53cf JR |
2961 | spin_lock_irqsave(&domain->lock, flags); |
2962 | ||
cd8c82e8 | 2963 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2964 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2965 | |
8fd524b3 | 2966 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2967 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2968 | goto out_free; |
367d04c4 | 2969 | } |
5d8b53cf | 2970 | |
17b124bf | 2971 | domain_flush_complete(domain); |
5d8b53cf | 2972 | |
5d8b53cf JR |
2973 | spin_unlock_irqrestore(&domain->lock, flags); |
2974 | ||
2975 | return virt_addr; | |
5b28df6f JR |
2976 | |
2977 | out_free: | |
2978 | ||
2979 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2980 | ||
2981 | return NULL; | |
5d8b53cf JR |
2982 | } |
2983 | ||
431b2a20 JR |
2984 | /* |
2985 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2986 | */ |
5d8b53cf | 2987 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2988 | void *virt_addr, dma_addr_t dma_addr, |
2989 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2990 | { |
2991 | unsigned long flags; | |
5d8b53cf | 2992 | struct protection_domain *domain; |
5d8b53cf | 2993 | |
5d31ee7e JR |
2994 | INC_STATS_COUNTER(cnt_free_coherent); |
2995 | ||
94f6d190 JR |
2996 | domain = get_domain(dev); |
2997 | if (IS_ERR(domain)) | |
5b28df6f JR |
2998 | goto free_mem; |
2999 | ||
5d8b53cf JR |
3000 | spin_lock_irqsave(&domain->lock, flags); |
3001 | ||
cd8c82e8 | 3002 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 3003 | |
17b124bf | 3004 | domain_flush_complete(domain); |
5d8b53cf JR |
3005 | |
3006 | spin_unlock_irqrestore(&domain->lock, flags); | |
3007 | ||
3008 | free_mem: | |
3009 | free_pages((unsigned long)virt_addr, get_order(size)); | |
3010 | } | |
3011 | ||
b39ba6ad JR |
3012 | /* |
3013 | * This function is called by the DMA layer to find out if we can handle a | |
3014 | * particular device. It is part of the dma_ops. | |
3015 | */ | |
3016 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
3017 | { | |
420aef8a | 3018 | return check_device(dev); |
b39ba6ad JR |
3019 | } |
3020 | ||
c432f3df | 3021 | /* |
431b2a20 JR |
3022 | * The function for pre-allocating protection domains. |
3023 | * | |
c432f3df JR |
3024 | * If the driver core informs the DMA layer if a driver grabs a device |
3025 | * we don't need to preallocate the protection domains anymore. | |
3026 | * For now we have to. | |
3027 | */ | |
943bc7e1 | 3028 | static void __init prealloc_protection_domains(void) |
c432f3df | 3029 | { |
5abcdba4 | 3030 | struct iommu_dev_data *dev_data; |
c432f3df | 3031 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3032 | struct pci_dev *dev = NULL; |
98fc5a69 | 3033 | u16 devid; |
c432f3df | 3034 | |
d18c69d3 | 3035 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3036 | |
3037 | /* Do we handle this device? */ | |
3038 | if (!check_device(&dev->dev)) | |
c432f3df | 3039 | continue; |
98fc5a69 | 3040 | |
5abcdba4 JR |
3041 | dev_data = get_dev_data(&dev->dev); |
3042 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3043 | /* Make sure passthrough domain is allocated */ | |
3044 | alloc_passthrough_domain(); | |
3045 | dev_data->passthrough = true; | |
3046 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3047 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3048 | dev_name(&dev->dev)); |
3049 | } | |
3050 | ||
98fc5a69 | 3051 | /* Is there already any domain for it? */ |
15898bbc | 3052 | if (domain_for_device(&dev->dev)) |
c432f3df | 3053 | continue; |
98fc5a69 JR |
3054 | |
3055 | devid = get_device_id(&dev->dev); | |
3056 | ||
87a64d52 | 3057 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3058 | if (!dma_dom) |
3059 | continue; | |
3060 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3061 | dma_dom->target_dev = devid; |
3062 | ||
15898bbc | 3063 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3064 | |
bd60b735 | 3065 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3066 | } |
3067 | } | |
3068 | ||
160c1d8e | 3069 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3070 | .alloc = alloc_coherent, |
3071 | .free = free_coherent, | |
51491367 FT |
3072 | .map_page = map_page, |
3073 | .unmap_page = unmap_page, | |
6631ee9d JR |
3074 | .map_sg = map_sg, |
3075 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3076 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3077 | }; |
3078 | ||
27c2127a JR |
3079 | static unsigned device_dma_ops_init(void) |
3080 | { | |
5abcdba4 | 3081 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3082 | struct pci_dev *pdev = NULL; |
3083 | unsigned unhandled = 0; | |
3084 | ||
3085 | for_each_pci_dev(pdev) { | |
3086 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3087 | |
3088 | iommu_ignore_device(&pdev->dev); | |
3089 | ||
27c2127a JR |
3090 | unhandled += 1; |
3091 | continue; | |
3092 | } | |
3093 | ||
5abcdba4 JR |
3094 | dev_data = get_dev_data(&pdev->dev); |
3095 | ||
3096 | if (!dev_data->passthrough) | |
3097 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3098 | else | |
3099 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3100 | } |
3101 | ||
3102 | return unhandled; | |
3103 | } | |
3104 | ||
431b2a20 JR |
3105 | /* |
3106 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3107 | */ | |
f5325094 JR |
3108 | |
3109 | void __init amd_iommu_init_api(void) | |
3110 | { | |
2cc21c42 | 3111 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3112 | } |
3113 | ||
6631ee9d JR |
3114 | int __init amd_iommu_init_dma_ops(void) |
3115 | { | |
3116 | struct amd_iommu *iommu; | |
27c2127a | 3117 | int ret, unhandled; |
6631ee9d | 3118 | |
431b2a20 JR |
3119 | /* |
3120 | * first allocate a default protection domain for every IOMMU we | |
3121 | * found in the system. Devices not assigned to any other | |
3122 | * protection domain will be assigned to the default one. | |
3123 | */ | |
3bd22172 | 3124 | for_each_iommu(iommu) { |
87a64d52 | 3125 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3126 | if (iommu->default_dom == NULL) |
3127 | return -ENOMEM; | |
e2dc14a2 | 3128 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3129 | ret = iommu_init_unity_mappings(iommu); |
3130 | if (ret) | |
3131 | goto free_domains; | |
3132 | } | |
3133 | ||
431b2a20 | 3134 | /* |
8793abeb | 3135 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3136 | */ |
8793abeb | 3137 | prealloc_protection_domains(); |
6631ee9d JR |
3138 | |
3139 | iommu_detected = 1; | |
75f1cdf1 | 3140 | swiotlb = 0; |
6631ee9d | 3141 | |
431b2a20 | 3142 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3143 | unhandled = device_dma_ops_init(); |
3144 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3145 | /* There are unhandled devices - initialize swiotlb for them */ | |
3146 | swiotlb = 1; | |
3147 | } | |
6631ee9d | 3148 | |
7f26508b JR |
3149 | amd_iommu_stats_init(); |
3150 | ||
62410eeb JR |
3151 | if (amd_iommu_unmap_flush) |
3152 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3153 | else | |
3154 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3155 | ||
6631ee9d JR |
3156 | return 0; |
3157 | ||
3158 | free_domains: | |
3159 | ||
3bd22172 | 3160 | for_each_iommu(iommu) { |
91457df7 | 3161 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3162 | } |
3163 | ||
3164 | return ret; | |
3165 | } | |
6d98cd80 JR |
3166 | |
3167 | /***************************************************************************** | |
3168 | * | |
3169 | * The following functions belong to the exported interface of AMD IOMMU | |
3170 | * | |
3171 | * This interface allows access to lower level functions of the IOMMU | |
3172 | * like protection domain handling and assignement of devices to domains | |
3173 | * which is not possible with the dma_ops interface. | |
3174 | * | |
3175 | *****************************************************************************/ | |
3176 | ||
6d98cd80 JR |
3177 | static void cleanup_domain(struct protection_domain *domain) |
3178 | { | |
9b29d3c6 | 3179 | struct iommu_dev_data *entry; |
6d98cd80 | 3180 | unsigned long flags; |
6d98cd80 JR |
3181 | |
3182 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3183 | ||
9b29d3c6 JR |
3184 | while (!list_empty(&domain->dev_list)) { |
3185 | entry = list_first_entry(&domain->dev_list, | |
3186 | struct iommu_dev_data, list); | |
3187 | __detach_device(entry); | |
3188 | atomic_set(&entry->bind, 0); | |
492667da | 3189 | } |
6d98cd80 JR |
3190 | |
3191 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3192 | } | |
3193 | ||
2650815f JR |
3194 | static void protection_domain_free(struct protection_domain *domain) |
3195 | { | |
3196 | if (!domain) | |
3197 | return; | |
3198 | ||
aeb26f55 JR |
3199 | del_domain_from_list(domain); |
3200 | ||
2650815f JR |
3201 | if (domain->id) |
3202 | domain_id_free(domain->id); | |
3203 | ||
3204 | kfree(domain); | |
3205 | } | |
3206 | ||
3207 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3208 | { |
3209 | struct protection_domain *domain; | |
3210 | ||
3211 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3212 | if (!domain) | |
2650815f | 3213 | return NULL; |
c156e347 JR |
3214 | |
3215 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3216 | mutex_init(&domain->api_lock); |
c156e347 JR |
3217 | domain->id = domain_id_alloc(); |
3218 | if (!domain->id) | |
2650815f | 3219 | goto out_err; |
7c392cbe | 3220 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3221 | |
aeb26f55 JR |
3222 | add_domain_to_list(domain); |
3223 | ||
2650815f JR |
3224 | return domain; |
3225 | ||
3226 | out_err: | |
3227 | kfree(domain); | |
3228 | ||
3229 | return NULL; | |
3230 | } | |
3231 | ||
5abcdba4 JR |
3232 | static int __init alloc_passthrough_domain(void) |
3233 | { | |
3234 | if (pt_domain != NULL) | |
3235 | return 0; | |
3236 | ||
3237 | /* allocate passthrough domain */ | |
3238 | pt_domain = protection_domain_alloc(); | |
3239 | if (!pt_domain) | |
3240 | return -ENOMEM; | |
3241 | ||
3242 | pt_domain->mode = PAGE_MODE_NONE; | |
3243 | ||
3244 | return 0; | |
3245 | } | |
2650815f JR |
3246 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3247 | { | |
3248 | struct protection_domain *domain; | |
3249 | ||
3250 | domain = protection_domain_alloc(); | |
3251 | if (!domain) | |
c156e347 | 3252 | goto out_free; |
2650815f JR |
3253 | |
3254 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3255 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3256 | if (!domain->pt_root) | |
3257 | goto out_free; | |
3258 | ||
f3572db8 JR |
3259 | domain->iommu_domain = dom; |
3260 | ||
c156e347 JR |
3261 | dom->priv = domain; |
3262 | ||
0ff64f80 JR |
3263 | dom->geometry.aperture_start = 0; |
3264 | dom->geometry.aperture_end = ~0ULL; | |
3265 | dom->geometry.force_aperture = true; | |
3266 | ||
c156e347 JR |
3267 | return 0; |
3268 | ||
3269 | out_free: | |
2650815f | 3270 | protection_domain_free(domain); |
c156e347 JR |
3271 | |
3272 | return -ENOMEM; | |
3273 | } | |
3274 | ||
98383fc3 JR |
3275 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3276 | { | |
3277 | struct protection_domain *domain = dom->priv; | |
3278 | ||
3279 | if (!domain) | |
3280 | return; | |
3281 | ||
3282 | if (domain->dev_cnt > 0) | |
3283 | cleanup_domain(domain); | |
3284 | ||
3285 | BUG_ON(domain->dev_cnt != 0); | |
3286 | ||
132bd68f JR |
3287 | if (domain->mode != PAGE_MODE_NONE) |
3288 | free_pagetable(domain); | |
98383fc3 | 3289 | |
52815b75 JR |
3290 | if (domain->flags & PD_IOMMUV2_MASK) |
3291 | free_gcr3_table(domain); | |
3292 | ||
8b408fe4 | 3293 | protection_domain_free(domain); |
98383fc3 JR |
3294 | |
3295 | dom->priv = NULL; | |
3296 | } | |
3297 | ||
684f2888 JR |
3298 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3299 | struct device *dev) | |
3300 | { | |
657cbb6b | 3301 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3302 | struct amd_iommu *iommu; |
684f2888 JR |
3303 | u16 devid; |
3304 | ||
98fc5a69 | 3305 | if (!check_device(dev)) |
684f2888 JR |
3306 | return; |
3307 | ||
98fc5a69 | 3308 | devid = get_device_id(dev); |
684f2888 | 3309 | |
657cbb6b | 3310 | if (dev_data->domain != NULL) |
15898bbc | 3311 | detach_device(dev); |
684f2888 JR |
3312 | |
3313 | iommu = amd_iommu_rlookup_table[devid]; | |
3314 | if (!iommu) | |
3315 | return; | |
3316 | ||
684f2888 JR |
3317 | iommu_completion_wait(iommu); |
3318 | } | |
3319 | ||
01106066 JR |
3320 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3321 | struct device *dev) | |
3322 | { | |
3323 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3324 | struct iommu_dev_data *dev_data; |
01106066 | 3325 | struct amd_iommu *iommu; |
15898bbc | 3326 | int ret; |
01106066 | 3327 | |
98fc5a69 | 3328 | if (!check_device(dev)) |
01106066 JR |
3329 | return -EINVAL; |
3330 | ||
657cbb6b JR |
3331 | dev_data = dev->archdata.iommu; |
3332 | ||
f62dda66 | 3333 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3334 | if (!iommu) |
3335 | return -EINVAL; | |
3336 | ||
657cbb6b | 3337 | if (dev_data->domain) |
15898bbc | 3338 | detach_device(dev); |
01106066 | 3339 | |
15898bbc | 3340 | ret = attach_device(dev, domain); |
01106066 JR |
3341 | |
3342 | iommu_completion_wait(iommu); | |
3343 | ||
15898bbc | 3344 | return ret; |
01106066 JR |
3345 | } |
3346 | ||
468e2366 | 3347 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3348 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3349 | { |
3350 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3351 | int prot = 0; |
3352 | int ret; | |
3353 | ||
132bd68f JR |
3354 | if (domain->mode == PAGE_MODE_NONE) |
3355 | return -EINVAL; | |
3356 | ||
c6229ca6 JR |
3357 | if (iommu_prot & IOMMU_READ) |
3358 | prot |= IOMMU_PROT_IR; | |
3359 | if (iommu_prot & IOMMU_WRITE) | |
3360 | prot |= IOMMU_PROT_IW; | |
3361 | ||
5d214fe6 | 3362 | mutex_lock(&domain->api_lock); |
795e74f7 | 3363 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3364 | mutex_unlock(&domain->api_lock); |
3365 | ||
795e74f7 | 3366 | return ret; |
c6229ca6 JR |
3367 | } |
3368 | ||
5009065d OBC |
3369 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3370 | size_t page_size) | |
eb74ff6c | 3371 | { |
eb74ff6c | 3372 | struct protection_domain *domain = dom->priv; |
5009065d | 3373 | size_t unmap_size; |
eb74ff6c | 3374 | |
132bd68f JR |
3375 | if (domain->mode == PAGE_MODE_NONE) |
3376 | return -EINVAL; | |
3377 | ||
5d214fe6 | 3378 | mutex_lock(&domain->api_lock); |
468e2366 | 3379 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3380 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3381 | |
17b124bf | 3382 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3383 | |
5009065d | 3384 | return unmap_size; |
eb74ff6c JR |
3385 | } |
3386 | ||
645c4c8d | 3387 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3388 | dma_addr_t iova) |
645c4c8d JR |
3389 | { |
3390 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3391 | unsigned long offset_mask; |
645c4c8d | 3392 | phys_addr_t paddr; |
f03152bb | 3393 | u64 *pte, __pte; |
645c4c8d | 3394 | |
132bd68f JR |
3395 | if (domain->mode == PAGE_MODE_NONE) |
3396 | return iova; | |
3397 | ||
24cd7723 | 3398 | pte = fetch_pte(domain, iova); |
645c4c8d | 3399 | |
a6d41a40 | 3400 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3401 | return 0; |
3402 | ||
f03152bb JR |
3403 | if (PM_PTE_LEVEL(*pte) == 0) |
3404 | offset_mask = PAGE_SIZE - 1; | |
3405 | else | |
3406 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3407 | ||
3408 | __pte = *pte & PM_ADDR_MASK; | |
3409 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3410 | |
3411 | return paddr; | |
3412 | } | |
3413 | ||
dbb9fd86 SY |
3414 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3415 | unsigned long cap) | |
3416 | { | |
80a506b8 JR |
3417 | switch (cap) { |
3418 | case IOMMU_CAP_CACHE_COHERENCY: | |
3419 | return 1; | |
bdddadcb JR |
3420 | case IOMMU_CAP_INTR_REMAP: |
3421 | return irq_remapping_enabled; | |
80a506b8 JR |
3422 | } |
3423 | ||
dbb9fd86 SY |
3424 | return 0; |
3425 | } | |
3426 | ||
b22f6434 | 3427 | static const struct iommu_ops amd_iommu_ops = { |
26961efe JR |
3428 | .domain_init = amd_iommu_domain_init, |
3429 | .domain_destroy = amd_iommu_domain_destroy, | |
3430 | .attach_dev = amd_iommu_attach_device, | |
3431 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3432 | .map = amd_iommu_map, |
3433 | .unmap = amd_iommu_unmap, | |
26961efe | 3434 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3435 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3436 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3437 | }; |
3438 | ||
0feae533 JR |
3439 | /***************************************************************************** |
3440 | * | |
3441 | * The next functions do a basic initialization of IOMMU for pass through | |
3442 | * mode | |
3443 | * | |
3444 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3445 | * DMA-API translation. | |
3446 | * | |
3447 | *****************************************************************************/ | |
3448 | ||
3449 | int __init amd_iommu_init_passthrough(void) | |
3450 | { | |
5abcdba4 | 3451 | struct iommu_dev_data *dev_data; |
0feae533 | 3452 | struct pci_dev *dev = NULL; |
5abcdba4 | 3453 | int ret; |
0feae533 | 3454 | |
5abcdba4 JR |
3455 | ret = alloc_passthrough_domain(); |
3456 | if (ret) | |
3457 | return ret; | |
0feae533 | 3458 | |
6c54aabd | 3459 | for_each_pci_dev(dev) { |
98fc5a69 | 3460 | if (!check_device(&dev->dev)) |
0feae533 JR |
3461 | continue; |
3462 | ||
5abcdba4 JR |
3463 | dev_data = get_dev_data(&dev->dev); |
3464 | dev_data->passthrough = true; | |
3465 | ||
15898bbc | 3466 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3467 | } |
3468 | ||
2655d7a2 JR |
3469 | amd_iommu_stats_init(); |
3470 | ||
0feae533 JR |
3471 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3472 | ||
3473 | return 0; | |
3474 | } | |
72e1dcc4 JR |
3475 | |
3476 | /* IOMMUv2 specific functions */ | |
3477 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3478 | { | |
3479 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3480 | } | |
3481 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3482 | ||
3483 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3484 | { | |
3485 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3486 | } | |
3487 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3488 | |
3489 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3490 | { | |
3491 | struct protection_domain *domain = dom->priv; | |
3492 | unsigned long flags; | |
3493 | ||
3494 | spin_lock_irqsave(&domain->lock, flags); | |
3495 | ||
3496 | /* Update data structure */ | |
3497 | domain->mode = PAGE_MODE_NONE; | |
3498 | domain->updated = true; | |
3499 | ||
3500 | /* Make changes visible to IOMMUs */ | |
3501 | update_domain(domain); | |
3502 | ||
3503 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3504 | free_pagetable(domain); | |
3505 | ||
3506 | spin_unlock_irqrestore(&domain->lock, flags); | |
3507 | } | |
3508 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3509 | |
3510 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3511 | { | |
3512 | struct protection_domain *domain = dom->priv; | |
3513 | unsigned long flags; | |
3514 | int levels, ret; | |
3515 | ||
3516 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3517 | return -EINVAL; | |
3518 | ||
3519 | /* Number of GCR3 table levels required */ | |
3520 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3521 | levels += 1; | |
3522 | ||
3523 | if (levels > amd_iommu_max_glx_val) | |
3524 | return -EINVAL; | |
3525 | ||
3526 | spin_lock_irqsave(&domain->lock, flags); | |
3527 | ||
3528 | /* | |
3529 | * Save us all sanity checks whether devices already in the | |
3530 | * domain support IOMMUv2. Just force that the domain has no | |
3531 | * devices attached when it is switched into IOMMUv2 mode. | |
3532 | */ | |
3533 | ret = -EBUSY; | |
3534 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3535 | goto out; | |
3536 | ||
3537 | ret = -ENOMEM; | |
3538 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3539 | if (domain->gcr3_tbl == NULL) | |
3540 | goto out; | |
3541 | ||
3542 | domain->glx = levels; | |
3543 | domain->flags |= PD_IOMMUV2_MASK; | |
3544 | domain->updated = true; | |
3545 | ||
3546 | update_domain(domain); | |
3547 | ||
3548 | ret = 0; | |
3549 | ||
3550 | out: | |
3551 | spin_unlock_irqrestore(&domain->lock, flags); | |
3552 | ||
3553 | return ret; | |
3554 | } | |
3555 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3556 | |
3557 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3558 | u64 address, bool size) | |
3559 | { | |
3560 | struct iommu_dev_data *dev_data; | |
3561 | struct iommu_cmd cmd; | |
3562 | int i, ret; | |
3563 | ||
3564 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3565 | return -EINVAL; | |
3566 | ||
3567 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3568 | ||
3569 | /* | |
3570 | * IOMMU TLB needs to be flushed before Device TLB to | |
3571 | * prevent device TLB refill from IOMMU TLB | |
3572 | */ | |
3573 | for (i = 0; i < amd_iommus_present; ++i) { | |
3574 | if (domain->dev_iommu[i] == 0) | |
3575 | continue; | |
3576 | ||
3577 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3578 | if (ret != 0) | |
3579 | goto out; | |
3580 | } | |
3581 | ||
3582 | /* Wait until IOMMU TLB flushes are complete */ | |
3583 | domain_flush_complete(domain); | |
3584 | ||
3585 | /* Now flush device TLBs */ | |
3586 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3587 | struct amd_iommu *iommu; | |
3588 | int qdep; | |
3589 | ||
3590 | BUG_ON(!dev_data->ats.enabled); | |
3591 | ||
3592 | qdep = dev_data->ats.qdep; | |
3593 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3594 | ||
3595 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3596 | qdep, address, size); | |
3597 | ||
3598 | ret = iommu_queue_command(iommu, &cmd); | |
3599 | if (ret != 0) | |
3600 | goto out; | |
3601 | } | |
3602 | ||
3603 | /* Wait until all device TLBs are flushed */ | |
3604 | domain_flush_complete(domain); | |
3605 | ||
3606 | ret = 0; | |
3607 | ||
3608 | out: | |
3609 | ||
3610 | return ret; | |
3611 | } | |
3612 | ||
3613 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3614 | u64 address) | |
3615 | { | |
399be2f5 JR |
3616 | INC_STATS_COUNTER(invalidate_iotlb); |
3617 | ||
22e266c7 JR |
3618 | return __flush_pasid(domain, pasid, address, false); |
3619 | } | |
3620 | ||
3621 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3622 | u64 address) | |
3623 | { | |
3624 | struct protection_domain *domain = dom->priv; | |
3625 | unsigned long flags; | |
3626 | int ret; | |
3627 | ||
3628 | spin_lock_irqsave(&domain->lock, flags); | |
3629 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3630 | spin_unlock_irqrestore(&domain->lock, flags); | |
3631 | ||
3632 | return ret; | |
3633 | } | |
3634 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3635 | ||
3636 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3637 | { | |
399be2f5 JR |
3638 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3639 | ||
22e266c7 JR |
3640 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3641 | true); | |
3642 | } | |
3643 | ||
3644 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3645 | { | |
3646 | struct protection_domain *domain = dom->priv; | |
3647 | unsigned long flags; | |
3648 | int ret; | |
3649 | ||
3650 | spin_lock_irqsave(&domain->lock, flags); | |
3651 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3652 | spin_unlock_irqrestore(&domain->lock, flags); | |
3653 | ||
3654 | return ret; | |
3655 | } | |
3656 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3657 | ||
b16137b1 JR |
3658 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3659 | { | |
3660 | int index; | |
3661 | u64 *pte; | |
3662 | ||
3663 | while (true) { | |
3664 | ||
3665 | index = (pasid >> (9 * level)) & 0x1ff; | |
3666 | pte = &root[index]; | |
3667 | ||
3668 | if (level == 0) | |
3669 | break; | |
3670 | ||
3671 | if (!(*pte & GCR3_VALID)) { | |
3672 | if (!alloc) | |
3673 | return NULL; | |
3674 | ||
3675 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3676 | if (root == NULL) | |
3677 | return NULL; | |
3678 | ||
3679 | *pte = __pa(root) | GCR3_VALID; | |
3680 | } | |
3681 | ||
3682 | root = __va(*pte & PAGE_MASK); | |
3683 | ||
3684 | level -= 1; | |
3685 | } | |
3686 | ||
3687 | return pte; | |
3688 | } | |
3689 | ||
3690 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3691 | unsigned long cr3) | |
3692 | { | |
3693 | u64 *pte; | |
3694 | ||
3695 | if (domain->mode != PAGE_MODE_NONE) | |
3696 | return -EINVAL; | |
3697 | ||
3698 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3699 | if (pte == NULL) | |
3700 | return -ENOMEM; | |
3701 | ||
3702 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3703 | ||
3704 | return __amd_iommu_flush_tlb(domain, pasid); | |
3705 | } | |
3706 | ||
3707 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3708 | { | |
3709 | u64 *pte; | |
3710 | ||
3711 | if (domain->mode != PAGE_MODE_NONE) | |
3712 | return -EINVAL; | |
3713 | ||
3714 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3715 | if (pte == NULL) | |
3716 | return 0; | |
3717 | ||
3718 | *pte = 0; | |
3719 | ||
3720 | return __amd_iommu_flush_tlb(domain, pasid); | |
3721 | } | |
3722 | ||
3723 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3724 | unsigned long cr3) | |
3725 | { | |
3726 | struct protection_domain *domain = dom->priv; | |
3727 | unsigned long flags; | |
3728 | int ret; | |
3729 | ||
3730 | spin_lock_irqsave(&domain->lock, flags); | |
3731 | ret = __set_gcr3(domain, pasid, cr3); | |
3732 | spin_unlock_irqrestore(&domain->lock, flags); | |
3733 | ||
3734 | return ret; | |
3735 | } | |
3736 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3737 | ||
3738 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3739 | { | |
3740 | struct protection_domain *domain = dom->priv; | |
3741 | unsigned long flags; | |
3742 | int ret; | |
3743 | ||
3744 | spin_lock_irqsave(&domain->lock, flags); | |
3745 | ret = __clear_gcr3(domain, pasid); | |
3746 | spin_unlock_irqrestore(&domain->lock, flags); | |
3747 | ||
3748 | return ret; | |
3749 | } | |
3750 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3751 | |
3752 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3753 | int status, int tag) | |
3754 | { | |
3755 | struct iommu_dev_data *dev_data; | |
3756 | struct amd_iommu *iommu; | |
3757 | struct iommu_cmd cmd; | |
3758 | ||
399be2f5 JR |
3759 | INC_STATS_COUNTER(complete_ppr); |
3760 | ||
c99afa25 JR |
3761 | dev_data = get_dev_data(&pdev->dev); |
3762 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3763 | ||
3764 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3765 | tag, dev_data->pri_tlp); | |
3766 | ||
3767 | return iommu_queue_command(iommu, &cmd); | |
3768 | } | |
3769 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3770 | |
3771 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3772 | { | |
3773 | struct protection_domain *domain; | |
3774 | ||
3775 | domain = get_domain(&pdev->dev); | |
3776 | if (IS_ERR(domain)) | |
3777 | return NULL; | |
3778 | ||
3779 | /* Only return IOMMUv2 domains */ | |
3780 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3781 | return NULL; | |
3782 | ||
3783 | return domain->iommu_domain; | |
3784 | } | |
3785 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3786 | |
3787 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3788 | { | |
3789 | struct iommu_dev_data *dev_data; | |
3790 | ||
3791 | if (!amd_iommu_v2_supported()) | |
3792 | return; | |
3793 | ||
3794 | dev_data = get_dev_data(&pdev->dev); | |
3795 | dev_data->errata |= (1 << erratum); | |
3796 | } | |
3797 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3798 | |
3799 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3800 | struct amd_iommu_device_info *info) | |
3801 | { | |
3802 | int max_pasids; | |
3803 | int pos; | |
3804 | ||
3805 | if (pdev == NULL || info == NULL) | |
3806 | return -EINVAL; | |
3807 | ||
3808 | if (!amd_iommu_v2_supported()) | |
3809 | return -EINVAL; | |
3810 | ||
3811 | memset(info, 0, sizeof(*info)); | |
3812 | ||
3813 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3814 | if (pos) | |
3815 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3816 | ||
3817 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3818 | if (pos) | |
3819 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3820 | ||
3821 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3822 | if (pos) { | |
3823 | int features; | |
3824 | ||
3825 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3826 | max_pasids = min(max_pasids, (1 << 20)); | |
3827 | ||
3828 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3829 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3830 | ||
3831 | features = pci_pasid_features(pdev); | |
3832 | if (features & PCI_PASID_CAP_EXEC) | |
3833 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3834 | if (features & PCI_PASID_CAP_PRIV) | |
3835 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3836 | } | |
3837 | ||
3838 | return 0; | |
3839 | } | |
3840 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3841 | |
3842 | #ifdef CONFIG_IRQ_REMAP | |
3843 | ||
3844 | /***************************************************************************** | |
3845 | * | |
3846 | * Interrupt Remapping Implementation | |
3847 | * | |
3848 | *****************************************************************************/ | |
3849 | ||
3850 | union irte { | |
3851 | u32 val; | |
3852 | struct { | |
3853 | u32 valid : 1, | |
3854 | no_fault : 1, | |
3855 | int_type : 3, | |
3856 | rq_eoi : 1, | |
3857 | dm : 1, | |
3858 | rsvd_1 : 1, | |
3859 | destination : 8, | |
3860 | vector : 8, | |
3861 | rsvd_2 : 8; | |
3862 | } fields; | |
3863 | }; | |
3864 | ||
3865 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3866 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3867 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3868 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3869 | ||
3870 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3871 | { | |
3872 | u64 dte; | |
3873 | ||
3874 | dte = amd_iommu_dev_table[devid].data[2]; | |
3875 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3876 | dte |= virt_to_phys(table->table); | |
3877 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3878 | dte |= DTE_IRQ_TABLE_LEN; | |
3879 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3880 | ||
3881 | amd_iommu_dev_table[devid].data[2] = dte; | |
3882 | } | |
3883 | ||
3884 | #define IRTE_ALLOCATED (~1U) | |
3885 | ||
3886 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3887 | { | |
3888 | struct irq_remap_table *table = NULL; | |
3889 | struct amd_iommu *iommu; | |
3890 | unsigned long flags; | |
3891 | u16 alias; | |
3892 | ||
3893 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3894 | ||
3895 | iommu = amd_iommu_rlookup_table[devid]; | |
3896 | if (!iommu) | |
3897 | goto out_unlock; | |
3898 | ||
3899 | table = irq_lookup_table[devid]; | |
3900 | if (table) | |
3901 | goto out; | |
3902 | ||
3903 | alias = amd_iommu_alias_table[devid]; | |
3904 | table = irq_lookup_table[alias]; | |
3905 | if (table) { | |
3906 | irq_lookup_table[devid] = table; | |
3907 | set_dte_irq_entry(devid, table); | |
3908 | iommu_flush_dte(iommu, devid); | |
3909 | goto out; | |
3910 | } | |
3911 | ||
3912 | /* Nothing there yet, allocate new irq remapping table */ | |
3913 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3914 | if (!table) | |
3915 | goto out; | |
3916 | ||
197887f0 JR |
3917 | /* Initialize table spin-lock */ |
3918 | spin_lock_init(&table->lock); | |
3919 | ||
2b324506 JR |
3920 | if (ioapic) |
3921 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3922 | table->min_index = 32; | |
3923 | ||
3924 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3925 | if (!table->table) { | |
3926 | kfree(table); | |
821f0f68 | 3927 | table = NULL; |
2b324506 JR |
3928 | goto out; |
3929 | } | |
3930 | ||
3931 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3932 | ||
3933 | if (ioapic) { | |
3934 | int i; | |
3935 | ||
3936 | for (i = 0; i < 32; ++i) | |
3937 | table->table[i] = IRTE_ALLOCATED; | |
3938 | } | |
3939 | ||
3940 | irq_lookup_table[devid] = table; | |
3941 | set_dte_irq_entry(devid, table); | |
3942 | iommu_flush_dte(iommu, devid); | |
3943 | if (devid != alias) { | |
3944 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3945 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3946 | iommu_flush_dte(iommu, alias); |
3947 | } | |
3948 | ||
3949 | out: | |
3950 | iommu_completion_wait(iommu); | |
3951 | ||
3952 | out_unlock: | |
3953 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3954 | ||
3955 | return table; | |
3956 | } | |
3957 | ||
3958 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3959 | { | |
3960 | struct irq_remap_table *table; | |
3961 | unsigned long flags; | |
3962 | int index, c; | |
3963 | ||
3964 | table = get_irq_table(devid, false); | |
3965 | if (!table) | |
3966 | return -ENODEV; | |
3967 | ||
3968 | spin_lock_irqsave(&table->lock, flags); | |
3969 | ||
3970 | /* Scan table for free entries */ | |
3971 | for (c = 0, index = table->min_index; | |
3972 | index < MAX_IRQS_PER_TABLE; | |
3973 | ++index) { | |
3974 | if (table->table[index] == 0) | |
3975 | c += 1; | |
3976 | else | |
3977 | c = 0; | |
3978 | ||
3979 | if (c == count) { | |
0dfedd61 | 3980 | struct irq_2_irte *irte_info; |
2b324506 JR |
3981 | |
3982 | for (; c != 0; --c) | |
3983 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3984 | ||
3985 | index -= count - 1; | |
3986 | ||
9b1b0e42 | 3987 | cfg->remapped = 1; |
0dfedd61 JR |
3988 | irte_info = &cfg->irq_2_irte; |
3989 | irte_info->devid = devid; | |
3990 | irte_info->index = index; | |
2b324506 JR |
3991 | |
3992 | goto out; | |
3993 | } | |
3994 | } | |
3995 | ||
3996 | index = -ENOSPC; | |
3997 | ||
3998 | out: | |
3999 | spin_unlock_irqrestore(&table->lock, flags); | |
4000 | ||
4001 | return index; | |
4002 | } | |
4003 | ||
4004 | static int get_irte(u16 devid, int index, union irte *irte) | |
4005 | { | |
4006 | struct irq_remap_table *table; | |
4007 | unsigned long flags; | |
4008 | ||
4009 | table = get_irq_table(devid, false); | |
4010 | if (!table) | |
4011 | return -ENOMEM; | |
4012 | ||
4013 | spin_lock_irqsave(&table->lock, flags); | |
4014 | irte->val = table->table[index]; | |
4015 | spin_unlock_irqrestore(&table->lock, flags); | |
4016 | ||
4017 | return 0; | |
4018 | } | |
4019 | ||
4020 | static int modify_irte(u16 devid, int index, union irte irte) | |
4021 | { | |
4022 | struct irq_remap_table *table; | |
4023 | struct amd_iommu *iommu; | |
4024 | unsigned long flags; | |
4025 | ||
4026 | iommu = amd_iommu_rlookup_table[devid]; | |
4027 | if (iommu == NULL) | |
4028 | return -EINVAL; | |
4029 | ||
4030 | table = get_irq_table(devid, false); | |
4031 | if (!table) | |
4032 | return -ENOMEM; | |
4033 | ||
4034 | spin_lock_irqsave(&table->lock, flags); | |
4035 | table->table[index] = irte.val; | |
4036 | spin_unlock_irqrestore(&table->lock, flags); | |
4037 | ||
4038 | iommu_flush_irt(iommu, devid); | |
4039 | iommu_completion_wait(iommu); | |
4040 | ||
4041 | return 0; | |
4042 | } | |
4043 | ||
4044 | static void free_irte(u16 devid, int index) | |
4045 | { | |
4046 | struct irq_remap_table *table; | |
4047 | struct amd_iommu *iommu; | |
4048 | unsigned long flags; | |
4049 | ||
4050 | iommu = amd_iommu_rlookup_table[devid]; | |
4051 | if (iommu == NULL) | |
4052 | return; | |
4053 | ||
4054 | table = get_irq_table(devid, false); | |
4055 | if (!table) | |
4056 | return; | |
4057 | ||
4058 | spin_lock_irqsave(&table->lock, flags); | |
4059 | table->table[index] = 0; | |
4060 | spin_unlock_irqrestore(&table->lock, flags); | |
4061 | ||
4062 | iommu_flush_irt(iommu, devid); | |
4063 | iommu_completion_wait(iommu); | |
4064 | } | |
4065 | ||
5527de74 JR |
4066 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4067 | unsigned int destination, int vector, | |
4068 | struct io_apic_irq_attr *attr) | |
4069 | { | |
4070 | struct irq_remap_table *table; | |
0dfedd61 | 4071 | struct irq_2_irte *irte_info; |
5527de74 JR |
4072 | struct irq_cfg *cfg; |
4073 | union irte irte; | |
4074 | int ioapic_id; | |
4075 | int index; | |
4076 | int devid; | |
4077 | int ret; | |
4078 | ||
4079 | cfg = irq_get_chip_data(irq); | |
4080 | if (!cfg) | |
4081 | return -EINVAL; | |
4082 | ||
0dfedd61 | 4083 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4084 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4085 | devid = get_ioapic_devid(ioapic_id); | |
4086 | ||
4087 | if (devid < 0) | |
4088 | return devid; | |
4089 | ||
4090 | table = get_irq_table(devid, true); | |
4091 | if (table == NULL) | |
4092 | return -ENOMEM; | |
4093 | ||
4094 | index = attr->ioapic_pin; | |
4095 | ||
4096 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4097 | cfg->remapped = 1; |
0dfedd61 JR |
4098 | irte_info->devid = devid; |
4099 | irte_info->index = index; | |
5527de74 JR |
4100 | |
4101 | /* Setup IRTE for IOMMU */ | |
4102 | irte.val = 0; | |
4103 | irte.fields.vector = vector; | |
4104 | irte.fields.int_type = apic->irq_delivery_mode; | |
4105 | irte.fields.destination = destination; | |
4106 | irte.fields.dm = apic->irq_dest_mode; | |
4107 | irte.fields.valid = 1; | |
4108 | ||
4109 | ret = modify_irte(devid, index, irte); | |
4110 | if (ret) | |
4111 | return ret; | |
4112 | ||
4113 | /* Setup IOAPIC entry */ | |
4114 | memset(entry, 0, sizeof(*entry)); | |
4115 | ||
4116 | entry->vector = index; | |
4117 | entry->mask = 0; | |
4118 | entry->trigger = attr->trigger; | |
4119 | entry->polarity = attr->polarity; | |
4120 | ||
4121 | /* | |
4122 | * Mask level triggered irqs. | |
5527de74 JR |
4123 | */ |
4124 | if (attr->trigger) | |
4125 | entry->mask = 1; | |
4126 | ||
4127 | return 0; | |
4128 | } | |
4129 | ||
4130 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4131 | bool force) | |
4132 | { | |
0dfedd61 | 4133 | struct irq_2_irte *irte_info; |
5527de74 JR |
4134 | unsigned int dest, irq; |
4135 | struct irq_cfg *cfg; | |
4136 | union irte irte; | |
4137 | int err; | |
4138 | ||
4139 | if (!config_enabled(CONFIG_SMP)) | |
4140 | return -1; | |
4141 | ||
4142 | cfg = data->chip_data; | |
4143 | irq = data->irq; | |
0dfedd61 | 4144 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4145 | |
4146 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4147 | return -EINVAL; | |
4148 | ||
0dfedd61 | 4149 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4150 | return -EBUSY; |
4151 | ||
4152 | if (assign_irq_vector(irq, cfg, mask)) | |
4153 | return -EBUSY; | |
4154 | ||
4155 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4156 | if (err) { | |
4157 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4158 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4159 | return err; | |
4160 | } | |
4161 | ||
4162 | irte.fields.vector = cfg->vector; | |
4163 | irte.fields.destination = dest; | |
4164 | ||
0dfedd61 | 4165 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4166 | |
4167 | if (cfg->move_in_progress) | |
4168 | send_cleanup_vector(cfg); | |
4169 | ||
4170 | cpumask_copy(data->affinity, mask); | |
4171 | ||
4172 | return 0; | |
4173 | } | |
4174 | ||
4175 | static int free_irq(int irq) | |
4176 | { | |
0dfedd61 | 4177 | struct irq_2_irte *irte_info; |
5527de74 JR |
4178 | struct irq_cfg *cfg; |
4179 | ||
4180 | cfg = irq_get_chip_data(irq); | |
4181 | if (!cfg) | |
4182 | return -EINVAL; | |
4183 | ||
0dfedd61 | 4184 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4185 | |
0dfedd61 | 4186 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4187 | |
4188 | return 0; | |
4189 | } | |
4190 | ||
0b4d48cb JR |
4191 | static void compose_msi_msg(struct pci_dev *pdev, |
4192 | unsigned int irq, unsigned int dest, | |
4193 | struct msi_msg *msg, u8 hpet_id) | |
4194 | { | |
0dfedd61 | 4195 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4196 | struct irq_cfg *cfg; |
4197 | union irte irte; | |
4198 | ||
4199 | cfg = irq_get_chip_data(irq); | |
4200 | if (!cfg) | |
4201 | return; | |
4202 | ||
0dfedd61 | 4203 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4204 | |
4205 | irte.val = 0; | |
4206 | irte.fields.vector = cfg->vector; | |
4207 | irte.fields.int_type = apic->irq_delivery_mode; | |
4208 | irte.fields.destination = dest; | |
4209 | irte.fields.dm = apic->irq_dest_mode; | |
4210 | irte.fields.valid = 1; | |
4211 | ||
0dfedd61 | 4212 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4213 | |
4214 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4215 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4216 | msg->data = irte_info->index; |
0b4d48cb JR |
4217 | } |
4218 | ||
4219 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4220 | { | |
4221 | struct irq_cfg *cfg; | |
4222 | int index; | |
4223 | u16 devid; | |
4224 | ||
4225 | if (!pdev) | |
4226 | return -EINVAL; | |
4227 | ||
4228 | cfg = irq_get_chip_data(irq); | |
4229 | if (!cfg) | |
4230 | return -EINVAL; | |
4231 | ||
4232 | devid = get_device_id(&pdev->dev); | |
4233 | index = alloc_irq_index(cfg, devid, nvec); | |
4234 | ||
4235 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4236 | } | |
4237 | ||
4238 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4239 | int index, int offset) | |
4240 | { | |
0dfedd61 | 4241 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4242 | struct irq_cfg *cfg; |
4243 | u16 devid; | |
4244 | ||
4245 | if (!pdev) | |
4246 | return -EINVAL; | |
4247 | ||
4248 | cfg = irq_get_chip_data(irq); | |
4249 | if (!cfg) | |
4250 | return -EINVAL; | |
4251 | ||
4252 | if (index >= MAX_IRQS_PER_TABLE) | |
4253 | return 0; | |
4254 | ||
4255 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4256 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4257 | |
9b1b0e42 | 4258 | cfg->remapped = 1; |
0dfedd61 JR |
4259 | irte_info->devid = devid; |
4260 | irte_info->index = index + offset; | |
0b4d48cb JR |
4261 | |
4262 | return 0; | |
4263 | } | |
4264 | ||
d976195c JR |
4265 | static int setup_hpet_msi(unsigned int irq, unsigned int id) |
4266 | { | |
0dfedd61 | 4267 | struct irq_2_irte *irte_info; |
d976195c JR |
4268 | struct irq_cfg *cfg; |
4269 | int index, devid; | |
4270 | ||
4271 | cfg = irq_get_chip_data(irq); | |
4272 | if (!cfg) | |
4273 | return -EINVAL; | |
4274 | ||
0dfedd61 | 4275 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4276 | devid = get_hpet_devid(id); |
4277 | if (devid < 0) | |
4278 | return devid; | |
4279 | ||
4280 | index = alloc_irq_index(cfg, devid, 1); | |
4281 | if (index < 0) | |
4282 | return index; | |
4283 | ||
9b1b0e42 | 4284 | cfg->remapped = 1; |
0dfedd61 JR |
4285 | irte_info->devid = devid; |
4286 | irte_info->index = index; | |
d976195c JR |
4287 | |
4288 | return 0; | |
4289 | } | |
4290 | ||
6b474b82 JR |
4291 | struct irq_remap_ops amd_iommu_irq_ops = { |
4292 | .supported = amd_iommu_supported, | |
4293 | .prepare = amd_iommu_prepare, | |
4294 | .enable = amd_iommu_enable, | |
4295 | .disable = amd_iommu_disable, | |
4296 | .reenable = amd_iommu_reenable, | |
4297 | .enable_faulting = amd_iommu_enable_faulting, | |
4298 | .setup_ioapic_entry = setup_ioapic_entry, | |
4299 | .set_affinity = set_affinity, | |
4300 | .free_irq = free_irq, | |
4301 | .compose_msi_msg = compose_msi_msg, | |
4302 | .msi_alloc_irq = msi_alloc_irq, | |
4303 | .msi_setup_irq = msi_setup_irq, | |
4304 | .setup_hpet_msi = setup_hpet_msi, | |
4305 | }; | |
2b324506 | 4306 | #endif |