Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
36 | #include <asm/irq_remapping.h> | |
37 | #include <asm/io_apic.h> | |
38 | #include <asm/apic.h> | |
39 | #include <asm/hw_irq.h> | |
17f5b569 | 40 | #include <asm/msidef.h> |
b6c02715 | 41 | #include <asm/proto.h> |
46a7fa27 | 42 | #include <asm/iommu.h> |
1d9b16d1 | 43 | #include <asm/gart.h> |
27c2127a | 44 | #include <asm/dma.h> |
403f81d8 JR |
45 | |
46 | #include "amd_iommu_proto.h" | |
47 | #include "amd_iommu_types.h" | |
6b474b82 | 48 | #include "irq_remapping.h" |
b6c02715 JR |
49 | |
50 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
51 | ||
815b33fd | 52 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 53 | |
aa3de9c0 OBC |
54 | /* |
55 | * This bitmap is used to advertise the page sizes our hardware support | |
56 | * to the IOMMU core, which will then use this information to split | |
57 | * physically contiguous memory regions it is mapping into page sizes | |
58 | * that we support. | |
59 | * | |
954e3dd8 | 60 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 61 | */ |
954e3dd8 | 62 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 63 | |
b6c02715 JR |
64 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
65 | ||
bd60b735 JR |
66 | /* A list of preallocated protection domains */ |
67 | static LIST_HEAD(iommu_pd_list); | |
68 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
69 | ||
8fa5f802 JR |
70 | /* List of all available dev_data structures */ |
71 | static LIST_HEAD(dev_data_list); | |
72 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
73 | ||
6efed63b JR |
74 | LIST_HEAD(ioapic_map); |
75 | LIST_HEAD(hpet_map); | |
76 | ||
0feae533 JR |
77 | /* |
78 | * Domain for untranslated devices - only allocated | |
79 | * if iommu=pt passed on kernel cmd line. | |
80 | */ | |
81 | static struct protection_domain *pt_domain; | |
82 | ||
b22f6434 | 83 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 84 | |
72e1dcc4 | 85 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 86 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 87 | |
ac1534a5 JR |
88 | static struct dma_map_ops amd_iommu_dma_ops; |
89 | ||
431b2a20 JR |
90 | /* |
91 | * general struct to manage commands send to an IOMMU | |
92 | */ | |
d6449536 | 93 | struct iommu_cmd { |
b6c02715 JR |
94 | u32 data[4]; |
95 | }; | |
96 | ||
05152a04 JR |
97 | struct kmem_cache *amd_iommu_irq_cache; |
98 | ||
04bfdd84 | 99 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 100 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 101 | |
15898bbc JR |
102 | /**************************************************************************** |
103 | * | |
104 | * Helper functions | |
105 | * | |
106 | ****************************************************************************/ | |
107 | ||
f62dda66 | 108 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
109 | { |
110 | struct iommu_dev_data *dev_data; | |
111 | unsigned long flags; | |
112 | ||
113 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
114 | if (!dev_data) | |
115 | return NULL; | |
116 | ||
f62dda66 | 117 | dev_data->devid = devid; |
8fa5f802 JR |
118 | atomic_set(&dev_data->bind, 0); |
119 | ||
120 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
121 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
122 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
123 | ||
124 | return dev_data; | |
125 | } | |
126 | ||
127 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
128 | { | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
132 | list_del(&dev_data->dev_data_list); | |
133 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
134 | ||
135 | kfree(dev_data); | |
136 | } | |
137 | ||
3b03bb74 JR |
138 | static struct iommu_dev_data *search_dev_data(u16 devid) |
139 | { | |
140 | struct iommu_dev_data *dev_data; | |
141 | unsigned long flags; | |
142 | ||
143 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
144 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
145 | if (dev_data->devid == devid) | |
146 | goto out_unlock; | |
147 | } | |
148 | ||
149 | dev_data = NULL; | |
150 | ||
151 | out_unlock: | |
152 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
153 | ||
154 | return dev_data; | |
155 | } | |
156 | ||
157 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
158 | { | |
159 | struct iommu_dev_data *dev_data; | |
160 | ||
161 | dev_data = search_dev_data(devid); | |
162 | ||
163 | if (dev_data == NULL) | |
164 | dev_data = alloc_dev_data(devid); | |
165 | ||
166 | return dev_data; | |
167 | } | |
168 | ||
15898bbc JR |
169 | static inline u16 get_device_id(struct device *dev) |
170 | { | |
171 | struct pci_dev *pdev = to_pci_dev(dev); | |
172 | ||
6f2729ba | 173 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
174 | } |
175 | ||
657cbb6b JR |
176 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
177 | { | |
178 | return dev->archdata.iommu; | |
179 | } | |
180 | ||
5abcdba4 JR |
181 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
182 | { | |
183 | static const int caps[] = { | |
184 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
185 | PCI_EXT_CAP_ID_PRI, |
186 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
187 | }; |
188 | int i, pos; | |
189 | ||
190 | for (i = 0; i < 3; ++i) { | |
191 | pos = pci_find_ext_capability(pdev, caps[i]); | |
192 | if (pos == 0) | |
193 | return false; | |
194 | } | |
195 | ||
196 | return true; | |
197 | } | |
198 | ||
6a113ddc JR |
199 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
200 | { | |
201 | struct iommu_dev_data *dev_data; | |
202 | ||
203 | dev_data = get_dev_data(&pdev->dev); | |
204 | ||
205 | return dev_data->errata & (1 << erratum) ? true : false; | |
206 | } | |
207 | ||
71c70984 JR |
208 | /* |
209 | * In this function the list of preallocated protection domains is traversed to | |
210 | * find the domain for a specific device | |
211 | */ | |
212 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
213 | { | |
214 | struct dma_ops_domain *entry, *ret = NULL; | |
215 | unsigned long flags; | |
216 | u16 alias = amd_iommu_alias_table[devid]; | |
217 | ||
218 | if (list_empty(&iommu_pd_list)) | |
219 | return NULL; | |
220 | ||
221 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
222 | ||
223 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
224 | if (entry->target_dev == devid || | |
225 | entry->target_dev == alias) { | |
226 | ret = entry; | |
227 | break; | |
228 | } | |
229 | } | |
230 | ||
231 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
98fc5a69 JR |
236 | /* |
237 | * This function checks if the driver got a valid device from the caller to | |
238 | * avoid dereferencing invalid pointers. | |
239 | */ | |
240 | static bool check_device(struct device *dev) | |
241 | { | |
242 | u16 devid; | |
243 | ||
244 | if (!dev || !dev->dma_mask) | |
245 | return false; | |
246 | ||
b82a2272 YW |
247 | /* No PCI device */ |
248 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
249 | return false; |
250 | ||
251 | devid = get_device_id(dev); | |
252 | ||
253 | /* Out of our scope? */ | |
254 | if (devid > amd_iommu_last_bdf) | |
255 | return false; | |
256 | ||
257 | if (amd_iommu_rlookup_table[devid] == NULL) | |
258 | return false; | |
259 | ||
260 | return true; | |
261 | } | |
262 | ||
25b11ce2 | 263 | static void init_iommu_group(struct device *dev) |
2851db21 | 264 | { |
2851db21 | 265 | struct iommu_group *group; |
2851db21 | 266 | |
65d5352f | 267 | group = iommu_group_get_for_dev(dev); |
25b11ce2 AW |
268 | if (!IS_ERR(group)) |
269 | iommu_group_put(group); | |
eb9c9527 AW |
270 | } |
271 | ||
c1931090 AW |
272 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
273 | { | |
274 | *(u16 *)data = alias; | |
275 | return 0; | |
276 | } | |
277 | ||
278 | static u16 get_alias(struct device *dev) | |
279 | { | |
280 | struct pci_dev *pdev = to_pci_dev(dev); | |
281 | u16 devid, ivrs_alias, pci_alias; | |
282 | ||
283 | devid = get_device_id(dev); | |
284 | ivrs_alias = amd_iommu_alias_table[devid]; | |
285 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
286 | ||
287 | if (ivrs_alias == pci_alias) | |
288 | return ivrs_alias; | |
289 | ||
290 | /* | |
291 | * DMA alias showdown | |
292 | * | |
293 | * The IVRS is fairly reliable in telling us about aliases, but it | |
294 | * can't know about every screwy device. If we don't have an IVRS | |
295 | * reported alias, use the PCI reported alias. In that case we may | |
296 | * still need to initialize the rlookup and dev_table entries if the | |
297 | * alias is to a non-existent device. | |
298 | */ | |
299 | if (ivrs_alias == devid) { | |
300 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
301 | amd_iommu_rlookup_table[pci_alias] = | |
302 | amd_iommu_rlookup_table[devid]; | |
303 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
304 | amd_iommu_dev_table[devid].data, | |
305 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
306 | } | |
307 | ||
308 | return pci_alias; | |
309 | } | |
310 | ||
311 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
312 | "for device %s[%04x:%04x], kernel reported alias " | |
313 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
314 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
315 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
316 | PCI_FUNC(pci_alias)); | |
317 | ||
318 | /* | |
319 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
320 | * bus, then the IVRS table may know about a quirk that we don't. | |
321 | */ | |
322 | if (pci_alias == devid && | |
323 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
324 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
325 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
326 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
327 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
328 | dev_name(dev)); | |
329 | } | |
330 | ||
331 | return ivrs_alias; | |
332 | } | |
333 | ||
eb9c9527 AW |
334 | static int iommu_init_device(struct device *dev) |
335 | { | |
336 | struct pci_dev *pdev = to_pci_dev(dev); | |
337 | struct iommu_dev_data *dev_data; | |
338 | u16 alias; | |
eb9c9527 AW |
339 | |
340 | if (dev->archdata.iommu) | |
341 | return 0; | |
342 | ||
343 | dev_data = find_dev_data(get_device_id(dev)); | |
344 | if (!dev_data) | |
345 | return -ENOMEM; | |
346 | ||
c1931090 AW |
347 | alias = get_alias(dev); |
348 | ||
eb9c9527 AW |
349 | if (alias != dev_data->devid) { |
350 | struct iommu_dev_data *alias_data; | |
351 | ||
352 | alias_data = find_dev_data(alias); | |
353 | if (alias_data == NULL) { | |
354 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
355 | dev_name(dev)); | |
356 | free_dev_data(dev_data); | |
357 | return -ENOTSUPP; | |
358 | } | |
359 | dev_data->alias_data = alias_data; | |
360 | } | |
361 | ||
5abcdba4 JR |
362 | if (pci_iommuv2_capable(pdev)) { |
363 | struct amd_iommu *iommu; | |
364 | ||
365 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
366 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
367 | } | |
368 | ||
657cbb6b JR |
369 | dev->archdata.iommu = dev_data; |
370 | ||
066f2e98 AW |
371 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
372 | dev); | |
373 | ||
657cbb6b JR |
374 | return 0; |
375 | } | |
376 | ||
26018874 JR |
377 | static void iommu_ignore_device(struct device *dev) |
378 | { | |
379 | u16 devid, alias; | |
380 | ||
381 | devid = get_device_id(dev); | |
382 | alias = amd_iommu_alias_table[devid]; | |
383 | ||
384 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
385 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
386 | ||
387 | amd_iommu_rlookup_table[devid] = NULL; | |
388 | amd_iommu_rlookup_table[alias] = NULL; | |
389 | } | |
390 | ||
657cbb6b JR |
391 | static void iommu_uninit_device(struct device *dev) |
392 | { | |
c1931090 AW |
393 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
394 | ||
395 | if (!dev_data) | |
396 | return; | |
397 | ||
066f2e98 AW |
398 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
399 | dev); | |
400 | ||
9dcd6130 AW |
401 | iommu_group_remove_device(dev); |
402 | ||
c1931090 AW |
403 | /* Unlink from alias, it may change if another device is re-plugged */ |
404 | dev_data->alias_data = NULL; | |
405 | ||
8fa5f802 | 406 | /* |
c1931090 AW |
407 | * We keep dev_data around for unplugged devices and reuse it when the |
408 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 409 | */ |
657cbb6b | 410 | } |
b7cc9554 JR |
411 | |
412 | void __init amd_iommu_uninit_devices(void) | |
413 | { | |
8fa5f802 | 414 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
415 | struct pci_dev *pdev = NULL; |
416 | ||
417 | for_each_pci_dev(pdev) { | |
418 | ||
419 | if (!check_device(&pdev->dev)) | |
420 | continue; | |
421 | ||
422 | iommu_uninit_device(&pdev->dev); | |
423 | } | |
8fa5f802 JR |
424 | |
425 | /* Free all of our dev_data structures */ | |
426 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
427 | free_dev_data(dev_data); | |
b7cc9554 JR |
428 | } |
429 | ||
430 | int __init amd_iommu_init_devices(void) | |
431 | { | |
432 | struct pci_dev *pdev = NULL; | |
433 | int ret = 0; | |
434 | ||
435 | for_each_pci_dev(pdev) { | |
436 | ||
437 | if (!check_device(&pdev->dev)) | |
438 | continue; | |
439 | ||
440 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
441 | if (ret == -ENOTSUPP) |
442 | iommu_ignore_device(&pdev->dev); | |
443 | else if (ret) | |
b7cc9554 JR |
444 | goto out_free; |
445 | } | |
446 | ||
25b11ce2 AW |
447 | /* |
448 | * Initialize IOMMU groups only after iommu_init_device() has | |
449 | * had a chance to populate any IVRS defined aliases. | |
450 | */ | |
451 | for_each_pci_dev(pdev) { | |
452 | if (check_device(&pdev->dev)) | |
453 | init_iommu_group(&pdev->dev); | |
454 | } | |
455 | ||
b7cc9554 JR |
456 | return 0; |
457 | ||
458 | out_free: | |
459 | ||
460 | amd_iommu_uninit_devices(); | |
461 | ||
462 | return ret; | |
463 | } | |
7f26508b JR |
464 | #ifdef CONFIG_AMD_IOMMU_STATS |
465 | ||
466 | /* | |
467 | * Initialization code for statistics collection | |
468 | */ | |
469 | ||
da49f6df | 470 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 471 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 472 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 473 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 474 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 475 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 476 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 477 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 478 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 479 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 480 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 481 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
482 | DECLARE_STATS_COUNTER(complete_ppr); |
483 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
484 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
485 | DECLARE_STATS_COUNTER(pri_requests); | |
486 | ||
7f26508b | 487 | static struct dentry *stats_dir; |
7f26508b JR |
488 | static struct dentry *de_fflush; |
489 | ||
490 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
491 | { | |
492 | if (stats_dir == NULL) | |
493 | return; | |
494 | ||
495 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
496 | &cnt->value); | |
497 | } | |
498 | ||
499 | static void amd_iommu_stats_init(void) | |
500 | { | |
501 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
502 | if (stats_dir == NULL) | |
503 | return; | |
504 | ||
7f26508b | 505 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 506 | &amd_iommu_unmap_flush); |
da49f6df JR |
507 | |
508 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 509 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 510 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 511 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 512 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 513 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 514 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 515 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 516 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 517 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 518 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 519 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
520 | amd_iommu_stats_add(&complete_ppr); |
521 | amd_iommu_stats_add(&invalidate_iotlb); | |
522 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
523 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
524 | } |
525 | ||
526 | #endif | |
527 | ||
a80dc3e0 JR |
528 | /**************************************************************************** |
529 | * | |
530 | * Interrupt handling functions | |
531 | * | |
532 | ****************************************************************************/ | |
533 | ||
e3e59876 JR |
534 | static void dump_dte_entry(u16 devid) |
535 | { | |
536 | int i; | |
537 | ||
ee6c2868 JR |
538 | for (i = 0; i < 4; ++i) |
539 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
540 | amd_iommu_dev_table[devid].data[i]); |
541 | } | |
542 | ||
945b4ac4 JR |
543 | static void dump_command(unsigned long phys_addr) |
544 | { | |
545 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
546 | int i; | |
547 | ||
548 | for (i = 0; i < 4; ++i) | |
549 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
550 | } | |
551 | ||
a345b23b | 552 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 553 | { |
3d06fca8 JR |
554 | int type, devid, domid, flags; |
555 | volatile u32 *event = __evt; | |
556 | int count = 0; | |
557 | u64 address; | |
558 | ||
559 | retry: | |
560 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
561 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
562 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
563 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
564 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
565 | ||
566 | if (type == 0) { | |
567 | /* Did we hit the erratum? */ | |
568 | if (++count == LOOP_TIMEOUT) { | |
569 | pr_err("AMD-Vi: No event written to event log\n"); | |
570 | return; | |
571 | } | |
572 | udelay(1); | |
573 | goto retry; | |
574 | } | |
90008ee4 | 575 | |
4c6f40d4 | 576 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
577 | |
578 | switch (type) { | |
579 | case EVENT_TYPE_ILL_DEV: | |
580 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
581 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 582 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 583 | address, flags); |
e3e59876 | 584 | dump_dte_entry(devid); |
90008ee4 JR |
585 | break; |
586 | case EVENT_TYPE_IO_FAULT: | |
587 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
588 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 589 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
590 | domid, address, flags); |
591 | break; | |
592 | case EVENT_TYPE_DEV_TAB_ERR: | |
593 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
594 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 595 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
596 | address, flags); |
597 | break; | |
598 | case EVENT_TYPE_PAGE_TAB_ERR: | |
599 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
600 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 601 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
602 | domid, address, flags); |
603 | break; | |
604 | case EVENT_TYPE_ILL_CMD: | |
605 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 606 | dump_command(address); |
90008ee4 JR |
607 | break; |
608 | case EVENT_TYPE_CMD_HARD_ERR: | |
609 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
610 | "flags=0x%04x]\n", address, flags); | |
611 | break; | |
612 | case EVENT_TYPE_IOTLB_INV_TO: | |
613 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
614 | "address=0x%016llx]\n", | |
c5081cd7 | 615 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
616 | address); |
617 | break; | |
618 | case EVENT_TYPE_INV_DEV_REQ: | |
619 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
620 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 621 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
622 | address, flags); |
623 | break; | |
624 | default: | |
625 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
626 | } | |
3d06fca8 JR |
627 | |
628 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
629 | } |
630 | ||
631 | static void iommu_poll_events(struct amd_iommu *iommu) | |
632 | { | |
633 | u32 head, tail; | |
90008ee4 JR |
634 | |
635 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
636 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
637 | ||
638 | while (head != tail) { | |
a345b23b | 639 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
640 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
641 | } | |
642 | ||
643 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
644 | } |
645 | ||
eee53537 | 646 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
647 | { |
648 | struct amd_iommu_fault fault; | |
72e1dcc4 | 649 | |
399be2f5 JR |
650 | INC_STATS_COUNTER(pri_requests); |
651 | ||
72e1dcc4 JR |
652 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
653 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
654 | return; | |
655 | } | |
656 | ||
657 | fault.address = raw[1]; | |
658 | fault.pasid = PPR_PASID(raw[0]); | |
659 | fault.device_id = PPR_DEVID(raw[0]); | |
660 | fault.tag = PPR_TAG(raw[0]); | |
661 | fault.flags = PPR_FLAGS(raw[0]); | |
662 | ||
72e1dcc4 JR |
663 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
664 | } | |
665 | ||
666 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
667 | { | |
72e1dcc4 JR |
668 | u32 head, tail; |
669 | ||
670 | if (iommu->ppr_log == NULL) | |
671 | return; | |
672 | ||
72e1dcc4 JR |
673 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
674 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
675 | ||
676 | while (head != tail) { | |
eee53537 JR |
677 | volatile u64 *raw; |
678 | u64 entry[2]; | |
679 | int i; | |
680 | ||
681 | raw = (u64 *)(iommu->ppr_log + head); | |
682 | ||
683 | /* | |
684 | * Hardware bug: Interrupt may arrive before the entry is | |
685 | * written to memory. If this happens we need to wait for the | |
686 | * entry to arrive. | |
687 | */ | |
688 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
689 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
690 | break; | |
691 | udelay(1); | |
692 | } | |
72e1dcc4 | 693 | |
eee53537 JR |
694 | /* Avoid memcpy function-call overhead */ |
695 | entry[0] = raw[0]; | |
696 | entry[1] = raw[1]; | |
72e1dcc4 | 697 | |
eee53537 JR |
698 | /* |
699 | * To detect the hardware bug we need to clear the entry | |
700 | * back to zero. | |
701 | */ | |
702 | raw[0] = raw[1] = 0UL; | |
703 | ||
704 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
705 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
706 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 707 | |
eee53537 JR |
708 | /* Handle PPR entry */ |
709 | iommu_handle_ppr_entry(iommu, entry); | |
710 | ||
eee53537 JR |
711 | /* Refresh ring-buffer information */ |
712 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
713 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
714 | } | |
72e1dcc4 JR |
715 | } |
716 | ||
72fe00f0 | 717 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 718 | { |
3f398bc7 SS |
719 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
720 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 721 | |
3f398bc7 SS |
722 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
723 | /* Enable EVT and PPR interrupts again */ | |
724 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
725 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 726 | |
3f398bc7 SS |
727 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
728 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
729 | iommu_poll_events(iommu); | |
730 | } | |
90008ee4 | 731 | |
3f398bc7 SS |
732 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
733 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
734 | iommu_poll_ppr_log(iommu); | |
735 | } | |
90008ee4 | 736 | |
3f398bc7 SS |
737 | /* |
738 | * Hardware bug: ERBT1312 | |
739 | * When re-enabling interrupt (by writing 1 | |
740 | * to clear the bit), the hardware might also try to set | |
741 | * the interrupt bit in the event status register. | |
742 | * In this scenario, the bit will be set, and disable | |
743 | * subsequent interrupts. | |
744 | * | |
745 | * Workaround: The IOMMU driver should read back the | |
746 | * status register and check if the interrupt bits are cleared. | |
747 | * If not, driver will need to go through the interrupt handler | |
748 | * again and re-clear the bits | |
749 | */ | |
750 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
751 | } | |
90008ee4 | 752 | return IRQ_HANDLED; |
a80dc3e0 JR |
753 | } |
754 | ||
72fe00f0 JR |
755 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
756 | { | |
757 | return IRQ_WAKE_THREAD; | |
758 | } | |
759 | ||
431b2a20 JR |
760 | /**************************************************************************** |
761 | * | |
762 | * IOMMU command queuing functions | |
763 | * | |
764 | ****************************************************************************/ | |
765 | ||
ac0ea6e9 JR |
766 | static int wait_on_sem(volatile u64 *sem) |
767 | { | |
768 | int i = 0; | |
769 | ||
770 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
771 | udelay(1); | |
772 | i += 1; | |
773 | } | |
774 | ||
775 | if (i == LOOP_TIMEOUT) { | |
776 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
777 | return -EIO; | |
778 | } | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
784 | struct iommu_cmd *cmd, | |
785 | u32 tail) | |
a19ae1ec | 786 | { |
a19ae1ec JR |
787 | u8 *target; |
788 | ||
8a7c5ef3 | 789 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
790 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
791 | ||
792 | /* Copy command to buffer */ | |
793 | memcpy(target, cmd, sizeof(*cmd)); | |
794 | ||
795 | /* Tell the IOMMU about it */ | |
a19ae1ec | 796 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 797 | } |
a19ae1ec | 798 | |
815b33fd | 799 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 800 | { |
815b33fd JR |
801 | WARN_ON(address & 0x7ULL); |
802 | ||
ded46737 | 803 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
804 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
805 | cmd->data[1] = upper_32_bits(__pa(address)); | |
806 | cmd->data[2] = 1; | |
ded46737 JR |
807 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
808 | } | |
809 | ||
94fe79e2 JR |
810 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
811 | { | |
812 | memset(cmd, 0, sizeof(*cmd)); | |
813 | cmd->data[0] = devid; | |
814 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
815 | } | |
816 | ||
11b6402c JR |
817 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
818 | size_t size, u16 domid, int pde) | |
819 | { | |
820 | u64 pages; | |
821 | int s; | |
822 | ||
823 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
824 | s = 0; | |
825 | ||
826 | if (pages > 1) { | |
827 | /* | |
828 | * If we have to flush more than one page, flush all | |
829 | * TLB entries for this domain | |
830 | */ | |
831 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
832 | s = 1; | |
833 | } | |
834 | ||
835 | address &= PAGE_MASK; | |
836 | ||
837 | memset(cmd, 0, sizeof(*cmd)); | |
838 | cmd->data[1] |= domid; | |
839 | cmd->data[2] = lower_32_bits(address); | |
840 | cmd->data[3] = upper_32_bits(address); | |
841 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
842 | if (s) /* size bit - we flush more than one 4kb page */ | |
843 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 844 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
845 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
846 | } | |
847 | ||
cb41ed85 JR |
848 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
849 | u64 address, size_t size) | |
850 | { | |
851 | u64 pages; | |
852 | int s; | |
853 | ||
854 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
855 | s = 0; | |
856 | ||
857 | if (pages > 1) { | |
858 | /* | |
859 | * If we have to flush more than one page, flush all | |
860 | * TLB entries for this domain | |
861 | */ | |
862 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
863 | s = 1; | |
864 | } | |
865 | ||
866 | address &= PAGE_MASK; | |
867 | ||
868 | memset(cmd, 0, sizeof(*cmd)); | |
869 | cmd->data[0] = devid; | |
870 | cmd->data[0] |= (qdep & 0xff) << 24; | |
871 | cmd->data[1] = devid; | |
872 | cmd->data[2] = lower_32_bits(address); | |
873 | cmd->data[3] = upper_32_bits(address); | |
874 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
875 | if (s) | |
876 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
877 | } | |
878 | ||
22e266c7 JR |
879 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
880 | u64 address, bool size) | |
881 | { | |
882 | memset(cmd, 0, sizeof(*cmd)); | |
883 | ||
884 | address &= ~(0xfffULL); | |
885 | ||
a919a018 | 886 | cmd->data[0] = pasid; |
22e266c7 JR |
887 | cmd->data[1] = domid; |
888 | cmd->data[2] = lower_32_bits(address); | |
889 | cmd->data[3] = upper_32_bits(address); | |
890 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
891 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
892 | if (size) | |
893 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
894 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
895 | } | |
896 | ||
897 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
898 | int qdep, u64 address, bool size) | |
899 | { | |
900 | memset(cmd, 0, sizeof(*cmd)); | |
901 | ||
902 | address &= ~(0xfffULL); | |
903 | ||
904 | cmd->data[0] = devid; | |
e8d2d82d | 905 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
906 | cmd->data[0] |= (qdep & 0xff) << 24; |
907 | cmd->data[1] = devid; | |
e8d2d82d | 908 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
909 | cmd->data[2] = lower_32_bits(address); |
910 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
911 | cmd->data[3] = upper_32_bits(address); | |
912 | if (size) | |
913 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
914 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
915 | } | |
916 | ||
c99afa25 JR |
917 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
918 | int status, int tag, bool gn) | |
919 | { | |
920 | memset(cmd, 0, sizeof(*cmd)); | |
921 | ||
922 | cmd->data[0] = devid; | |
923 | if (gn) { | |
a919a018 | 924 | cmd->data[1] = pasid; |
c99afa25 JR |
925 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
926 | } | |
927 | cmd->data[3] = tag & 0x1ff; | |
928 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
929 | ||
930 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
931 | } | |
932 | ||
58fc7f14 JR |
933 | static void build_inv_all(struct iommu_cmd *cmd) |
934 | { | |
935 | memset(cmd, 0, sizeof(*cmd)); | |
936 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
937 | } |
938 | ||
7ef2798d JR |
939 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
940 | { | |
941 | memset(cmd, 0, sizeof(*cmd)); | |
942 | cmd->data[0] = devid; | |
943 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
944 | } | |
945 | ||
431b2a20 | 946 | /* |
431b2a20 | 947 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 948 | * hardware about the new command. |
431b2a20 | 949 | */ |
f1ca1512 JR |
950 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
951 | struct iommu_cmd *cmd, | |
952 | bool sync) | |
a19ae1ec | 953 | { |
ac0ea6e9 | 954 | u32 left, tail, head, next_tail; |
a19ae1ec | 955 | unsigned long flags; |
a19ae1ec | 956 | |
549c90dc | 957 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
958 | |
959 | again: | |
a19ae1ec | 960 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 961 | |
ac0ea6e9 JR |
962 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
963 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
964 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
965 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 966 | |
ac0ea6e9 JR |
967 | if (left <= 2) { |
968 | struct iommu_cmd sync_cmd; | |
969 | volatile u64 sem = 0; | |
970 | int ret; | |
8d201968 | 971 | |
ac0ea6e9 JR |
972 | build_completion_wait(&sync_cmd, (u64)&sem); |
973 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 974 | |
ac0ea6e9 JR |
975 | spin_unlock_irqrestore(&iommu->lock, flags); |
976 | ||
977 | if ((ret = wait_on_sem(&sem)) != 0) | |
978 | return ret; | |
979 | ||
980 | goto again; | |
8d201968 JR |
981 | } |
982 | ||
ac0ea6e9 JR |
983 | copy_cmd_to_buffer(iommu, cmd, tail); |
984 | ||
985 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 986 | iommu->need_sync = sync; |
ac0ea6e9 | 987 | |
a19ae1ec | 988 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 989 | |
815b33fd | 990 | return 0; |
8d201968 JR |
991 | } |
992 | ||
f1ca1512 JR |
993 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
994 | { | |
995 | return iommu_queue_command_sync(iommu, cmd, true); | |
996 | } | |
997 | ||
8d201968 JR |
998 | /* |
999 | * This function queues a completion wait command into the command | |
1000 | * buffer of an IOMMU | |
1001 | */ | |
a19ae1ec | 1002 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1003 | { |
1004 | struct iommu_cmd cmd; | |
815b33fd | 1005 | volatile u64 sem = 0; |
ac0ea6e9 | 1006 | int ret; |
8d201968 | 1007 | |
09ee17eb | 1008 | if (!iommu->need_sync) |
815b33fd | 1009 | return 0; |
09ee17eb | 1010 | |
815b33fd | 1011 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1012 | |
f1ca1512 | 1013 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1014 | if (ret) |
815b33fd | 1015 | return ret; |
8d201968 | 1016 | |
ac0ea6e9 | 1017 | return wait_on_sem(&sem); |
8d201968 JR |
1018 | } |
1019 | ||
d8c13085 | 1020 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1021 | { |
d8c13085 | 1022 | struct iommu_cmd cmd; |
a19ae1ec | 1023 | |
d8c13085 | 1024 | build_inv_dte(&cmd, devid); |
7e4f88da | 1025 | |
d8c13085 JR |
1026 | return iommu_queue_command(iommu, &cmd); |
1027 | } | |
09ee17eb | 1028 | |
7d0c5cc5 JR |
1029 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1030 | { | |
1031 | u32 devid; | |
09ee17eb | 1032 | |
7d0c5cc5 JR |
1033 | for (devid = 0; devid <= 0xffff; ++devid) |
1034 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1035 | |
7d0c5cc5 JR |
1036 | iommu_completion_wait(iommu); |
1037 | } | |
84df8175 | 1038 | |
7d0c5cc5 JR |
1039 | /* |
1040 | * This function uses heavy locking and may disable irqs for some time. But | |
1041 | * this is no issue because it is only called during resume. | |
1042 | */ | |
1043 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1044 | { | |
1045 | u32 dom_id; | |
a19ae1ec | 1046 | |
7d0c5cc5 JR |
1047 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1048 | struct iommu_cmd cmd; | |
1049 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1050 | dom_id, 1); | |
1051 | iommu_queue_command(iommu, &cmd); | |
1052 | } | |
8eed9833 | 1053 | |
7d0c5cc5 | 1054 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1055 | } |
1056 | ||
58fc7f14 | 1057 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1058 | { |
58fc7f14 | 1059 | struct iommu_cmd cmd; |
0518a3a4 | 1060 | |
58fc7f14 | 1061 | build_inv_all(&cmd); |
0518a3a4 | 1062 | |
58fc7f14 JR |
1063 | iommu_queue_command(iommu, &cmd); |
1064 | iommu_completion_wait(iommu); | |
1065 | } | |
1066 | ||
7ef2798d JR |
1067 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1068 | { | |
1069 | struct iommu_cmd cmd; | |
1070 | ||
1071 | build_inv_irt(&cmd, devid); | |
1072 | ||
1073 | iommu_queue_command(iommu, &cmd); | |
1074 | } | |
1075 | ||
1076 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1077 | { | |
1078 | u32 devid; | |
1079 | ||
1080 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1081 | iommu_flush_irt(iommu, devid); | |
1082 | ||
1083 | iommu_completion_wait(iommu); | |
1084 | } | |
1085 | ||
7d0c5cc5 JR |
1086 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1087 | { | |
58fc7f14 JR |
1088 | if (iommu_feature(iommu, FEATURE_IA)) { |
1089 | iommu_flush_all(iommu); | |
1090 | } else { | |
1091 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1092 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1093 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1094 | } |
1095 | } | |
1096 | ||
431b2a20 | 1097 | /* |
cb41ed85 | 1098 | * Command send function for flushing on-device TLB |
431b2a20 | 1099 | */ |
6c542047 JR |
1100 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1101 | u64 address, size_t size) | |
3fa43655 JR |
1102 | { |
1103 | struct amd_iommu *iommu; | |
b00d3bcf | 1104 | struct iommu_cmd cmd; |
cb41ed85 | 1105 | int qdep; |
3fa43655 | 1106 | |
ea61cddb JR |
1107 | qdep = dev_data->ats.qdep; |
1108 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1109 | |
ea61cddb | 1110 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1111 | |
1112 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1113 | } |
1114 | ||
431b2a20 | 1115 | /* |
431b2a20 | 1116 | * Command send function for invalidating a device table entry |
431b2a20 | 1117 | */ |
6c542047 | 1118 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1119 | { |
3fa43655 | 1120 | struct amd_iommu *iommu; |
ee2fa743 | 1121 | int ret; |
a19ae1ec | 1122 | |
6c542047 | 1123 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1124 | |
f62dda66 | 1125 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1126 | if (ret) |
1127 | return ret; | |
1128 | ||
ea61cddb | 1129 | if (dev_data->ats.enabled) |
6c542047 | 1130 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1131 | |
ee2fa743 | 1132 | return ret; |
a19ae1ec JR |
1133 | } |
1134 | ||
431b2a20 JR |
1135 | /* |
1136 | * TLB invalidation function which is called from the mapping functions. | |
1137 | * It invalidates a single PTE if the range to flush is within a single | |
1138 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1139 | */ | |
17b124bf JR |
1140 | static void __domain_flush_pages(struct protection_domain *domain, |
1141 | u64 address, size_t size, int pde) | |
a19ae1ec | 1142 | { |
cb41ed85 | 1143 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1144 | struct iommu_cmd cmd; |
1145 | int ret = 0, i; | |
a19ae1ec | 1146 | |
11b6402c | 1147 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1148 | |
6de8ad9b JR |
1149 | for (i = 0; i < amd_iommus_present; ++i) { |
1150 | if (!domain->dev_iommu[i]) | |
1151 | continue; | |
1152 | ||
1153 | /* | |
1154 | * Devices of this domain are behind this IOMMU | |
1155 | * We need a TLB flush | |
1156 | */ | |
11b6402c | 1157 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1158 | } |
1159 | ||
cb41ed85 | 1160 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1161 | |
ea61cddb | 1162 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1163 | continue; |
1164 | ||
6c542047 | 1165 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1166 | } |
1167 | ||
11b6402c | 1168 | WARN_ON(ret); |
6de8ad9b JR |
1169 | } |
1170 | ||
17b124bf JR |
1171 | static void domain_flush_pages(struct protection_domain *domain, |
1172 | u64 address, size_t size) | |
6de8ad9b | 1173 | { |
17b124bf | 1174 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1175 | } |
b6c02715 | 1176 | |
1c655773 | 1177 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1178 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1179 | { |
17b124bf | 1180 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1181 | } |
1182 | ||
42a49f96 | 1183 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1184 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1185 | { |
17b124bf | 1186 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1187 | } |
1188 | ||
17b124bf | 1189 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1190 | { |
17b124bf | 1191 | int i; |
18811f55 | 1192 | |
17b124bf JR |
1193 | for (i = 0; i < amd_iommus_present; ++i) { |
1194 | if (!domain->dev_iommu[i]) | |
1195 | continue; | |
bfd1be18 | 1196 | |
17b124bf JR |
1197 | /* |
1198 | * Devices of this domain are behind this IOMMU | |
1199 | * We need to wait for completion of all commands. | |
1200 | */ | |
1201 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1202 | } |
e394d72a JR |
1203 | } |
1204 | ||
b00d3bcf | 1205 | |
09b42804 | 1206 | /* |
b00d3bcf | 1207 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1208 | */ |
17b124bf | 1209 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1210 | { |
b00d3bcf | 1211 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1212 | |
b00d3bcf | 1213 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1214 | device_flush_dte(dev_data); |
a345b23b JR |
1215 | } |
1216 | ||
431b2a20 JR |
1217 | /**************************************************************************** |
1218 | * | |
1219 | * The functions below are used the create the page table mappings for | |
1220 | * unity mapped regions. | |
1221 | * | |
1222 | ****************************************************************************/ | |
1223 | ||
308973d3 JR |
1224 | /* |
1225 | * This function is used to add another level to an IO page table. Adding | |
1226 | * another level increases the size of the address space by 9 bits to a size up | |
1227 | * to 64 bits. | |
1228 | */ | |
1229 | static bool increase_address_space(struct protection_domain *domain, | |
1230 | gfp_t gfp) | |
1231 | { | |
1232 | u64 *pte; | |
1233 | ||
1234 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1235 | /* address space already 64 bit large */ | |
1236 | return false; | |
1237 | ||
1238 | pte = (void *)get_zeroed_page(gfp); | |
1239 | if (!pte) | |
1240 | return false; | |
1241 | ||
1242 | *pte = PM_LEVEL_PDE(domain->mode, | |
1243 | virt_to_phys(domain->pt_root)); | |
1244 | domain->pt_root = pte; | |
1245 | domain->mode += 1; | |
1246 | domain->updated = true; | |
1247 | ||
1248 | return true; | |
1249 | } | |
1250 | ||
1251 | static u64 *alloc_pte(struct protection_domain *domain, | |
1252 | unsigned long address, | |
cbb9d729 | 1253 | unsigned long page_size, |
308973d3 JR |
1254 | u64 **pte_page, |
1255 | gfp_t gfp) | |
1256 | { | |
cbb9d729 | 1257 | int level, end_lvl; |
308973d3 | 1258 | u64 *pte, *page; |
cbb9d729 JR |
1259 | |
1260 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1261 | |
1262 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1263 | increase_address_space(domain, gfp); | |
1264 | ||
cbb9d729 JR |
1265 | level = domain->mode - 1; |
1266 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1267 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1268 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1269 | |
1270 | while (level > end_lvl) { | |
1271 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1272 | page = (u64 *)get_zeroed_page(gfp); | |
1273 | if (!page) | |
1274 | return NULL; | |
1275 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1276 | } | |
1277 | ||
cbb9d729 JR |
1278 | /* No level skipping support yet */ |
1279 | if (PM_PTE_LEVEL(*pte) != level) | |
1280 | return NULL; | |
1281 | ||
308973d3 JR |
1282 | level -= 1; |
1283 | ||
1284 | pte = IOMMU_PTE_PAGE(*pte); | |
1285 | ||
1286 | if (pte_page && level == end_lvl) | |
1287 | *pte_page = pte; | |
1288 | ||
1289 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1290 | } | |
1291 | ||
1292 | return pte; | |
1293 | } | |
1294 | ||
1295 | /* | |
1296 | * This function checks if there is a PTE for a given dma address. If | |
1297 | * there is one, it returns the pointer to it. | |
1298 | */ | |
24cd7723 | 1299 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1300 | { |
1301 | int level; | |
1302 | u64 *pte; | |
1303 | ||
24cd7723 JR |
1304 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1305 | return NULL; | |
1306 | ||
1307 | level = domain->mode - 1; | |
1308 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1309 | |
24cd7723 JR |
1310 | while (level > 0) { |
1311 | ||
1312 | /* Not Present */ | |
308973d3 JR |
1313 | if (!IOMMU_PTE_PRESENT(*pte)) |
1314 | return NULL; | |
1315 | ||
24cd7723 JR |
1316 | /* Large PTE */ |
1317 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1318 | unsigned long pte_mask, __pte; | |
1319 | ||
1320 | /* | |
1321 | * If we have a series of large PTEs, make | |
1322 | * sure to return a pointer to the first one. | |
1323 | */ | |
1324 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1325 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1326 | __pte = ((unsigned long)pte) & pte_mask; | |
1327 | ||
1328 | return (u64 *)__pte; | |
1329 | } | |
1330 | ||
1331 | /* No level skipping support yet */ | |
1332 | if (PM_PTE_LEVEL(*pte) != level) | |
1333 | return NULL; | |
1334 | ||
308973d3 JR |
1335 | level -= 1; |
1336 | ||
24cd7723 | 1337 | /* Walk to the next level */ |
308973d3 JR |
1338 | pte = IOMMU_PTE_PAGE(*pte); |
1339 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1340 | } |
1341 | ||
1342 | return pte; | |
1343 | } | |
1344 | ||
431b2a20 JR |
1345 | /* |
1346 | * Generic mapping functions. It maps a physical address into a DMA | |
1347 | * address space. It allocates the page table pages if necessary. | |
1348 | * In the future it can be extended to a generic mapping function | |
1349 | * supporting all features of AMD IOMMU page tables like level skipping | |
1350 | * and full 64 bit address spaces. | |
1351 | */ | |
38e817fe JR |
1352 | static int iommu_map_page(struct protection_domain *dom, |
1353 | unsigned long bus_addr, | |
1354 | unsigned long phys_addr, | |
abdc5eb3 | 1355 | int prot, |
cbb9d729 | 1356 | unsigned long page_size) |
bd0e5211 | 1357 | { |
8bda3092 | 1358 | u64 __pte, *pte; |
cbb9d729 | 1359 | int i, count; |
abdc5eb3 | 1360 | |
bad1cac2 | 1361 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1362 | return -EINVAL; |
1363 | ||
cbb9d729 JR |
1364 | bus_addr = PAGE_ALIGN(bus_addr); |
1365 | phys_addr = PAGE_ALIGN(phys_addr); | |
1366 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1367 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1368 | ||
1369 | for (i = 0; i < count; ++i) | |
1370 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1371 | return -EBUSY; | |
bd0e5211 | 1372 | |
cbb9d729 JR |
1373 | if (page_size > PAGE_SIZE) { |
1374 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1375 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1376 | } else | |
1377 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1378 | |
bd0e5211 JR |
1379 | if (prot & IOMMU_PROT_IR) |
1380 | __pte |= IOMMU_PTE_IR; | |
1381 | if (prot & IOMMU_PROT_IW) | |
1382 | __pte |= IOMMU_PTE_IW; | |
1383 | ||
cbb9d729 JR |
1384 | for (i = 0; i < count; ++i) |
1385 | pte[i] = __pte; | |
bd0e5211 | 1386 | |
04bfdd84 JR |
1387 | update_domain(dom); |
1388 | ||
bd0e5211 JR |
1389 | return 0; |
1390 | } | |
1391 | ||
24cd7723 JR |
1392 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1393 | unsigned long bus_addr, | |
1394 | unsigned long page_size) | |
eb74ff6c | 1395 | { |
24cd7723 JR |
1396 | unsigned long long unmap_size, unmapped; |
1397 | u64 *pte; | |
1398 | ||
1399 | BUG_ON(!is_power_of_2(page_size)); | |
1400 | ||
1401 | unmapped = 0; | |
eb74ff6c | 1402 | |
24cd7723 JR |
1403 | while (unmapped < page_size) { |
1404 | ||
1405 | pte = fetch_pte(dom, bus_addr); | |
1406 | ||
1407 | if (!pte) { | |
1408 | /* | |
1409 | * No PTE for this address | |
1410 | * move forward in 4kb steps | |
1411 | */ | |
1412 | unmap_size = PAGE_SIZE; | |
1413 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1414 | /* 4kb PTE found for this address */ | |
1415 | unmap_size = PAGE_SIZE; | |
1416 | *pte = 0ULL; | |
1417 | } else { | |
1418 | int count, i; | |
1419 | ||
1420 | /* Large PTE found which maps this address */ | |
1421 | unmap_size = PTE_PAGE_SIZE(*pte); | |
60d0ca3c AW |
1422 | |
1423 | /* Only unmap from the first pte in the page */ | |
1424 | if ((unmap_size - 1) & bus_addr) | |
1425 | break; | |
24cd7723 JR |
1426 | count = PAGE_SIZE_PTE_COUNT(unmap_size); |
1427 | for (i = 0; i < count; i++) | |
1428 | pte[i] = 0ULL; | |
1429 | } | |
1430 | ||
1431 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1432 | unmapped += unmap_size; | |
1433 | } | |
1434 | ||
60d0ca3c | 1435 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1436 | |
24cd7723 | 1437 | return unmapped; |
eb74ff6c | 1438 | } |
eb74ff6c | 1439 | |
431b2a20 JR |
1440 | /* |
1441 | * This function checks if a specific unity mapping entry is needed for | |
1442 | * this specific IOMMU. | |
1443 | */ | |
bd0e5211 JR |
1444 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1445 | struct unity_map_entry *entry) | |
1446 | { | |
1447 | u16 bdf, i; | |
1448 | ||
1449 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1450 | bdf = amd_iommu_alias_table[i]; | |
1451 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1452 | return 1; | |
1453 | } | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
431b2a20 JR |
1458 | /* |
1459 | * This function actually applies the mapping to the page table of the | |
1460 | * dma_ops domain. | |
1461 | */ | |
bd0e5211 JR |
1462 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1463 | struct unity_map_entry *e) | |
1464 | { | |
1465 | u64 addr; | |
1466 | int ret; | |
1467 | ||
1468 | for (addr = e->address_start; addr < e->address_end; | |
1469 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1470 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1471 | PAGE_SIZE); |
bd0e5211 JR |
1472 | if (ret) |
1473 | return ret; | |
1474 | /* | |
1475 | * if unity mapping is in aperture range mark the page | |
1476 | * as allocated in the aperture | |
1477 | */ | |
1478 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1479 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1480 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1481 | } |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
171e7b37 JR |
1486 | /* |
1487 | * Init the unity mappings for a specific IOMMU in the system | |
1488 | * | |
1489 | * Basically iterates over all unity mapping entries and applies them to | |
1490 | * the default domain DMA of that IOMMU if necessary. | |
1491 | */ | |
1492 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1493 | { | |
1494 | struct unity_map_entry *entry; | |
1495 | int ret; | |
1496 | ||
1497 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1498 | if (!iommu_for_unity_map(iommu, entry)) | |
1499 | continue; | |
1500 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1501 | if (ret) | |
1502 | return ret; | |
1503 | } | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
431b2a20 JR |
1508 | /* |
1509 | * Inits the unity mappings required for a specific device | |
1510 | */ | |
bd0e5211 JR |
1511 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1512 | u16 devid) | |
1513 | { | |
1514 | struct unity_map_entry *e; | |
1515 | int ret; | |
1516 | ||
1517 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1518 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1519 | continue; | |
1520 | ret = dma_ops_unity_map(dma_dom, e); | |
1521 | if (ret) | |
1522 | return ret; | |
1523 | } | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
431b2a20 JR |
1528 | /**************************************************************************** |
1529 | * | |
1530 | * The next functions belong to the address allocator for the dma_ops | |
1531 | * interface functions. They work like the allocators in the other IOMMU | |
1532 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1533 | * the aperture. Maybe it could be enhanced in the future to a more | |
1534 | * efficient allocator. | |
1535 | * | |
1536 | ****************************************************************************/ | |
d3086444 | 1537 | |
431b2a20 | 1538 | /* |
384de729 | 1539 | * The address allocator core functions. |
431b2a20 JR |
1540 | * |
1541 | * called with domain->lock held | |
1542 | */ | |
384de729 | 1543 | |
171e7b37 JR |
1544 | /* |
1545 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1546 | * ranges. | |
1547 | */ | |
1548 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1549 | unsigned long start_page, | |
1550 | unsigned int pages) | |
1551 | { | |
1552 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1553 | ||
1554 | if (start_page + pages > last_page) | |
1555 | pages = last_page - start_page; | |
1556 | ||
1557 | for (i = start_page; i < start_page + pages; ++i) { | |
1558 | int index = i / APERTURE_RANGE_PAGES; | |
1559 | int page = i % APERTURE_RANGE_PAGES; | |
1560 | __set_bit(page, dom->aperture[index]->bitmap); | |
1561 | } | |
1562 | } | |
1563 | ||
9cabe89b JR |
1564 | /* |
1565 | * This function is used to add a new aperture range to an existing | |
1566 | * aperture in case of dma_ops domain allocation or address allocation | |
1567 | * failure. | |
1568 | */ | |
576175c2 | 1569 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1570 | bool populate, gfp_t gfp) |
1571 | { | |
1572 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1573 | struct amd_iommu *iommu; |
17f5b569 | 1574 | unsigned long i, old_size; |
9cabe89b | 1575 | |
f5e9705c JR |
1576 | #ifdef CONFIG_IOMMU_STRESS |
1577 | populate = false; | |
1578 | #endif | |
1579 | ||
9cabe89b JR |
1580 | if (index >= APERTURE_MAX_RANGES) |
1581 | return -ENOMEM; | |
1582 | ||
1583 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1584 | if (!dma_dom->aperture[index]) | |
1585 | return -ENOMEM; | |
1586 | ||
1587 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1588 | if (!dma_dom->aperture[index]->bitmap) | |
1589 | goto out_free; | |
1590 | ||
1591 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1592 | ||
1593 | if (populate) { | |
1594 | unsigned long address = dma_dom->aperture_size; | |
1595 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1596 | u64 *pte, *pte_page; | |
1597 | ||
1598 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1599 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1600 | &pte_page, gfp); |
1601 | if (!pte) | |
1602 | goto out_free; | |
1603 | ||
1604 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1605 | ||
1606 | address += APERTURE_RANGE_SIZE / 64; | |
1607 | } | |
1608 | } | |
1609 | ||
17f5b569 | 1610 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1611 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1612 | ||
17f5b569 JR |
1613 | /* Reserve address range used for MSI messages */ |
1614 | if (old_size < MSI_ADDR_BASE_LO && | |
1615 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1616 | unsigned long spage; | |
1617 | int pages; | |
1618 | ||
1619 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1620 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1621 | ||
1622 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1623 | } | |
1624 | ||
b595076a | 1625 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1626 | for_each_iommu(iommu) { |
1627 | if (iommu->exclusion_start && | |
1628 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1629 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1630 | unsigned long startpage; | |
1631 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1632 | iommu->exclusion_length, | |
1633 | PAGE_SIZE); | |
1634 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1635 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1636 | } | |
00cd122a JR |
1637 | } |
1638 | ||
1639 | /* | |
1640 | * Check for areas already mapped as present in the new aperture | |
1641 | * range and mark those pages as reserved in the allocator. Such | |
1642 | * mappings may already exist as a result of requested unity | |
1643 | * mappings for devices. | |
1644 | */ | |
1645 | for (i = dma_dom->aperture[index]->offset; | |
1646 | i < dma_dom->aperture_size; | |
1647 | i += PAGE_SIZE) { | |
24cd7723 | 1648 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1649 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1650 | continue; | |
1651 | ||
fcd0861d | 1652 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1653 | } |
1654 | ||
04bfdd84 JR |
1655 | update_domain(&dma_dom->domain); |
1656 | ||
9cabe89b JR |
1657 | return 0; |
1658 | ||
1659 | out_free: | |
04bfdd84 JR |
1660 | update_domain(&dma_dom->domain); |
1661 | ||
9cabe89b JR |
1662 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1663 | ||
1664 | kfree(dma_dom->aperture[index]); | |
1665 | dma_dom->aperture[index] = NULL; | |
1666 | ||
1667 | return -ENOMEM; | |
1668 | } | |
1669 | ||
384de729 JR |
1670 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1671 | struct dma_ops_domain *dom, | |
1672 | unsigned int pages, | |
1673 | unsigned long align_mask, | |
1674 | u64 dma_mask, | |
1675 | unsigned long start) | |
1676 | { | |
803b8cb4 | 1677 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1678 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1679 | int i = start >> APERTURE_RANGE_SHIFT; | |
1680 | unsigned long boundary_size; | |
1681 | unsigned long address = -1; | |
1682 | unsigned long limit; | |
1683 | ||
803b8cb4 JR |
1684 | next_bit >>= PAGE_SHIFT; |
1685 | ||
384de729 JR |
1686 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1687 | PAGE_SIZE) >> PAGE_SHIFT; | |
1688 | ||
1689 | for (;i < max_index; ++i) { | |
1690 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1691 | ||
1692 | if (dom->aperture[i]->offset >= dma_mask) | |
1693 | break; | |
1694 | ||
1695 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1696 | dma_mask >> PAGE_SHIFT); | |
1697 | ||
1698 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1699 | limit, next_bit, pages, 0, | |
1700 | boundary_size, align_mask); | |
1701 | if (address != -1) { | |
1702 | address = dom->aperture[i]->offset + | |
1703 | (address << PAGE_SHIFT); | |
803b8cb4 | 1704 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1705 | break; |
1706 | } | |
1707 | ||
1708 | next_bit = 0; | |
1709 | } | |
1710 | ||
1711 | return address; | |
1712 | } | |
1713 | ||
d3086444 JR |
1714 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1715 | struct dma_ops_domain *dom, | |
6d4f343f | 1716 | unsigned int pages, |
832a90c3 JR |
1717 | unsigned long align_mask, |
1718 | u64 dma_mask) | |
d3086444 | 1719 | { |
d3086444 | 1720 | unsigned long address; |
d3086444 | 1721 | |
fe16f088 JR |
1722 | #ifdef CONFIG_IOMMU_STRESS |
1723 | dom->next_address = 0; | |
1724 | dom->need_flush = true; | |
1725 | #endif | |
d3086444 | 1726 | |
384de729 | 1727 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1728 | dma_mask, dom->next_address); |
d3086444 | 1729 | |
1c655773 | 1730 | if (address == -1) { |
803b8cb4 | 1731 | dom->next_address = 0; |
384de729 JR |
1732 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1733 | dma_mask, 0); | |
1c655773 JR |
1734 | dom->need_flush = true; |
1735 | } | |
d3086444 | 1736 | |
384de729 | 1737 | if (unlikely(address == -1)) |
8fd524b3 | 1738 | address = DMA_ERROR_CODE; |
d3086444 JR |
1739 | |
1740 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1741 | ||
1742 | return address; | |
1743 | } | |
1744 | ||
431b2a20 JR |
1745 | /* |
1746 | * The address free function. | |
1747 | * | |
1748 | * called with domain->lock held | |
1749 | */ | |
d3086444 JR |
1750 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1751 | unsigned long address, | |
1752 | unsigned int pages) | |
1753 | { | |
384de729 JR |
1754 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1755 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1756 | |
384de729 JR |
1757 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1758 | ||
47bccd6b JR |
1759 | #ifdef CONFIG_IOMMU_STRESS |
1760 | if (i < 4) | |
1761 | return; | |
1762 | #endif | |
80be308d | 1763 | |
803b8cb4 | 1764 | if (address >= dom->next_address) |
80be308d | 1765 | dom->need_flush = true; |
384de729 JR |
1766 | |
1767 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1768 | |
a66022c4 | 1769 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1770 | |
d3086444 JR |
1771 | } |
1772 | ||
431b2a20 JR |
1773 | /**************************************************************************** |
1774 | * | |
1775 | * The next functions belong to the domain allocation. A domain is | |
1776 | * allocated for every IOMMU as the default domain. If device isolation | |
1777 | * is enabled, every device get its own domain. The most important thing | |
1778 | * about domains is the page table mapping the DMA address space they | |
1779 | * contain. | |
1780 | * | |
1781 | ****************************************************************************/ | |
1782 | ||
aeb26f55 JR |
1783 | /* |
1784 | * This function adds a protection domain to the global protection domain list | |
1785 | */ | |
1786 | static void add_domain_to_list(struct protection_domain *domain) | |
1787 | { | |
1788 | unsigned long flags; | |
1789 | ||
1790 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1791 | list_add(&domain->list, &amd_iommu_pd_list); | |
1792 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1793 | } | |
1794 | ||
1795 | /* | |
1796 | * This function removes a protection domain to the global | |
1797 | * protection domain list | |
1798 | */ | |
1799 | static void del_domain_from_list(struct protection_domain *domain) | |
1800 | { | |
1801 | unsigned long flags; | |
1802 | ||
1803 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1804 | list_del(&domain->list); | |
1805 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1806 | } | |
1807 | ||
ec487d1a JR |
1808 | static u16 domain_id_alloc(void) |
1809 | { | |
1810 | unsigned long flags; | |
1811 | int id; | |
1812 | ||
1813 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1814 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1815 | BUG_ON(id == 0); | |
1816 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1817 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1818 | else | |
1819 | id = 0; | |
1820 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1821 | ||
1822 | return id; | |
1823 | } | |
1824 | ||
a2acfb75 JR |
1825 | static void domain_id_free(int id) |
1826 | { | |
1827 | unsigned long flags; | |
1828 | ||
1829 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1830 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1831 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1832 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1833 | } | |
a2acfb75 | 1834 | |
5c34c403 JR |
1835 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1836 | static void free_pt_##LVL (unsigned long __pt) \ | |
1837 | { \ | |
1838 | unsigned long p; \ | |
1839 | u64 *pt; \ | |
1840 | int i; \ | |
1841 | \ | |
1842 | pt = (u64 *)__pt; \ | |
1843 | \ | |
1844 | for (i = 0; i < 512; ++i) { \ | |
1845 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1846 | continue; \ | |
1847 | \ | |
1848 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1849 | FN(p); \ | |
1850 | } \ | |
1851 | free_page((unsigned long)pt); \ | |
1852 | } | |
1853 | ||
1854 | DEFINE_FREE_PT_FN(l2, free_page) | |
1855 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1856 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1857 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1858 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1859 | ||
86db2e5d | 1860 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1861 | { |
5c34c403 | 1862 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1863 | |
5c34c403 JR |
1864 | switch (domain->mode) { |
1865 | case PAGE_MODE_NONE: | |
1866 | break; | |
1867 | case PAGE_MODE_1_LEVEL: | |
1868 | free_page(root); | |
1869 | break; | |
1870 | case PAGE_MODE_2_LEVEL: | |
1871 | free_pt_l2(root); | |
1872 | break; | |
1873 | case PAGE_MODE_3_LEVEL: | |
1874 | free_pt_l3(root); | |
1875 | break; | |
1876 | case PAGE_MODE_4_LEVEL: | |
1877 | free_pt_l4(root); | |
1878 | break; | |
1879 | case PAGE_MODE_5_LEVEL: | |
1880 | free_pt_l5(root); | |
1881 | break; | |
1882 | case PAGE_MODE_6_LEVEL: | |
1883 | free_pt_l6(root); | |
1884 | break; | |
1885 | default: | |
1886 | BUG(); | |
ec487d1a | 1887 | } |
ec487d1a JR |
1888 | } |
1889 | ||
b16137b1 JR |
1890 | static void free_gcr3_tbl_level1(u64 *tbl) |
1891 | { | |
1892 | u64 *ptr; | |
1893 | int i; | |
1894 | ||
1895 | for (i = 0; i < 512; ++i) { | |
1896 | if (!(tbl[i] & GCR3_VALID)) | |
1897 | continue; | |
1898 | ||
1899 | ptr = __va(tbl[i] & PAGE_MASK); | |
1900 | ||
1901 | free_page((unsigned long)ptr); | |
1902 | } | |
1903 | } | |
1904 | ||
1905 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1906 | { | |
1907 | u64 *ptr; | |
1908 | int i; | |
1909 | ||
1910 | for (i = 0; i < 512; ++i) { | |
1911 | if (!(tbl[i] & GCR3_VALID)) | |
1912 | continue; | |
1913 | ||
1914 | ptr = __va(tbl[i] & PAGE_MASK); | |
1915 | ||
1916 | free_gcr3_tbl_level1(ptr); | |
1917 | } | |
1918 | } | |
1919 | ||
52815b75 JR |
1920 | static void free_gcr3_table(struct protection_domain *domain) |
1921 | { | |
b16137b1 JR |
1922 | if (domain->glx == 2) |
1923 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1924 | else if (domain->glx == 1) | |
1925 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1926 | else if (domain->glx != 0) | |
1927 | BUG(); | |
1928 | ||
52815b75 JR |
1929 | free_page((unsigned long)domain->gcr3_tbl); |
1930 | } | |
1931 | ||
431b2a20 JR |
1932 | /* |
1933 | * Free a domain, only used if something went wrong in the | |
1934 | * allocation path and we need to free an already allocated page table | |
1935 | */ | |
ec487d1a JR |
1936 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1937 | { | |
384de729 JR |
1938 | int i; |
1939 | ||
ec487d1a JR |
1940 | if (!dom) |
1941 | return; | |
1942 | ||
aeb26f55 JR |
1943 | del_domain_from_list(&dom->domain); |
1944 | ||
86db2e5d | 1945 | free_pagetable(&dom->domain); |
ec487d1a | 1946 | |
384de729 JR |
1947 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1948 | if (!dom->aperture[i]) | |
1949 | continue; | |
1950 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1951 | kfree(dom->aperture[i]); | |
1952 | } | |
ec487d1a JR |
1953 | |
1954 | kfree(dom); | |
1955 | } | |
1956 | ||
431b2a20 JR |
1957 | /* |
1958 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1959 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1960 | * structures required for the dma_ops interface |
1961 | */ | |
87a64d52 | 1962 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1963 | { |
1964 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1965 | |
1966 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1967 | if (!dma_dom) | |
1968 | return NULL; | |
1969 | ||
1970 | spin_lock_init(&dma_dom->domain.lock); | |
1971 | ||
1972 | dma_dom->domain.id = domain_id_alloc(); | |
1973 | if (dma_dom->domain.id == 0) | |
1974 | goto free_dma_dom; | |
7c392cbe | 1975 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1976 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1977 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1978 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1979 | dma_dom->domain.priv = dma_dom; |
1980 | if (!dma_dom->domain.pt_root) | |
1981 | goto free_dma_dom; | |
ec487d1a | 1982 | |
1c655773 | 1983 | dma_dom->need_flush = false; |
bd60b735 | 1984 | dma_dom->target_dev = 0xffff; |
1c655773 | 1985 | |
aeb26f55 JR |
1986 | add_domain_to_list(&dma_dom->domain); |
1987 | ||
576175c2 | 1988 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1989 | goto free_dma_dom; |
ec487d1a | 1990 | |
431b2a20 | 1991 | /* |
ec487d1a JR |
1992 | * mark the first page as allocated so we never return 0 as |
1993 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1994 | */ |
384de729 | 1995 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1996 | dma_dom->next_address = 0; |
ec487d1a | 1997 | |
ec487d1a JR |
1998 | |
1999 | return dma_dom; | |
2000 | ||
2001 | free_dma_dom: | |
2002 | dma_ops_domain_free(dma_dom); | |
2003 | ||
2004 | return NULL; | |
2005 | } | |
2006 | ||
5b28df6f JR |
2007 | /* |
2008 | * little helper function to check whether a given protection domain is a | |
2009 | * dma_ops domain | |
2010 | */ | |
2011 | static bool dma_ops_domain(struct protection_domain *domain) | |
2012 | { | |
2013 | return domain->flags & PD_DMA_OPS_MASK; | |
2014 | } | |
2015 | ||
fd7b5535 | 2016 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2017 | { |
132bd68f | 2018 | u64 pte_root = 0; |
ee6c2868 | 2019 | u64 flags = 0; |
863c74eb | 2020 | |
132bd68f JR |
2021 | if (domain->mode != PAGE_MODE_NONE) |
2022 | pte_root = virt_to_phys(domain->pt_root); | |
2023 | ||
38ddf41b JR |
2024 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2025 | << DEV_ENTRY_MODE_SHIFT; | |
2026 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2027 | |
ee6c2868 JR |
2028 | flags = amd_iommu_dev_table[devid].data[1]; |
2029 | ||
fd7b5535 JR |
2030 | if (ats) |
2031 | flags |= DTE_FLAG_IOTLB; | |
2032 | ||
52815b75 JR |
2033 | if (domain->flags & PD_IOMMUV2_MASK) { |
2034 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2035 | u64 glx = domain->glx; | |
2036 | u64 tmp; | |
2037 | ||
2038 | pte_root |= DTE_FLAG_GV; | |
2039 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2040 | ||
2041 | /* First mask out possible old values for GCR3 table */ | |
2042 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2043 | flags &= ~tmp; | |
2044 | ||
2045 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2046 | flags &= ~tmp; | |
2047 | ||
2048 | /* Encode GCR3 table into DTE */ | |
2049 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2050 | pte_root |= tmp; | |
2051 | ||
2052 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2053 | flags |= tmp; | |
2054 | ||
2055 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2056 | flags |= tmp; | |
2057 | } | |
2058 | ||
ee6c2868 JR |
2059 | flags &= ~(0xffffUL); |
2060 | flags |= domain->id; | |
2061 | ||
2062 | amd_iommu_dev_table[devid].data[1] = flags; | |
2063 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2064 | } |
2065 | ||
2066 | static void clear_dte_entry(u16 devid) | |
2067 | { | |
15898bbc JR |
2068 | /* remove entry from the device table seen by the hardware */ |
2069 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2070 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2071 | |
2072 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2073 | } |
2074 | ||
ec9e79ef JR |
2075 | static void do_attach(struct iommu_dev_data *dev_data, |
2076 | struct protection_domain *domain) | |
7f760ddd | 2077 | { |
7f760ddd | 2078 | struct amd_iommu *iommu; |
ec9e79ef | 2079 | bool ats; |
fd7b5535 | 2080 | |
ec9e79ef JR |
2081 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2082 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2083 | |
2084 | /* Update data structures */ | |
2085 | dev_data->domain = domain; | |
2086 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2087 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2088 | |
2089 | /* Do reference counting */ | |
2090 | domain->dev_iommu[iommu->index] += 1; | |
2091 | domain->dev_cnt += 1; | |
2092 | ||
2093 | /* Flush the DTE entry */ | |
6c542047 | 2094 | device_flush_dte(dev_data); |
7f760ddd JR |
2095 | } |
2096 | ||
ec9e79ef | 2097 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2098 | { |
7f760ddd | 2099 | struct amd_iommu *iommu; |
7f760ddd | 2100 | |
ec9e79ef | 2101 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2102 | |
2103 | /* decrease reference counters */ | |
7f760ddd JR |
2104 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2105 | dev_data->domain->dev_cnt -= 1; | |
2106 | ||
2107 | /* Update data structures */ | |
2108 | dev_data->domain = NULL; | |
2109 | list_del(&dev_data->list); | |
f62dda66 | 2110 | clear_dte_entry(dev_data->devid); |
15898bbc | 2111 | |
7f760ddd | 2112 | /* Flush the DTE entry */ |
6c542047 | 2113 | device_flush_dte(dev_data); |
2b681faf JR |
2114 | } |
2115 | ||
2116 | /* | |
2117 | * If a device is not yet associated with a domain, this function does | |
2118 | * assigns it visible for the hardware | |
2119 | */ | |
ec9e79ef | 2120 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2121 | struct protection_domain *domain) |
2b681faf | 2122 | { |
84fe6c19 | 2123 | int ret; |
657cbb6b | 2124 | |
2b681faf JR |
2125 | /* lock domain */ |
2126 | spin_lock(&domain->lock); | |
2127 | ||
71f77580 JR |
2128 | if (dev_data->alias_data != NULL) { |
2129 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2130 | |
2b02b091 JR |
2131 | /* Some sanity checks */ |
2132 | ret = -EBUSY; | |
2133 | if (alias_data->domain != NULL && | |
2134 | alias_data->domain != domain) | |
2135 | goto out_unlock; | |
eba6ac60 | 2136 | |
2b02b091 JR |
2137 | if (dev_data->domain != NULL && |
2138 | dev_data->domain != domain) | |
2139 | goto out_unlock; | |
15898bbc | 2140 | |
2b02b091 | 2141 | /* Do real assignment */ |
7f760ddd | 2142 | if (alias_data->domain == NULL) |
ec9e79ef | 2143 | do_attach(alias_data, domain); |
24100055 JR |
2144 | |
2145 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2146 | } |
15898bbc | 2147 | |
7f760ddd | 2148 | if (dev_data->domain == NULL) |
ec9e79ef | 2149 | do_attach(dev_data, domain); |
eba6ac60 | 2150 | |
24100055 JR |
2151 | atomic_inc(&dev_data->bind); |
2152 | ||
84fe6c19 JL |
2153 | ret = 0; |
2154 | ||
2155 | out_unlock: | |
2156 | ||
eba6ac60 JR |
2157 | /* ready */ |
2158 | spin_unlock(&domain->lock); | |
15898bbc | 2159 | |
84fe6c19 | 2160 | return ret; |
0feae533 | 2161 | } |
b20ac0d4 | 2162 | |
52815b75 JR |
2163 | |
2164 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2165 | { | |
2166 | pci_disable_ats(pdev); | |
2167 | pci_disable_pri(pdev); | |
2168 | pci_disable_pasid(pdev); | |
2169 | } | |
2170 | ||
6a113ddc JR |
2171 | /* FIXME: Change generic reset-function to do the same */ |
2172 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2173 | { | |
2174 | u16 control; | |
2175 | int pos; | |
2176 | ||
46277b75 | 2177 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2178 | if (!pos) |
2179 | return -EINVAL; | |
2180 | ||
46277b75 JR |
2181 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2182 | control |= PCI_PRI_CTRL_RESET; | |
2183 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2184 | |
2185 | return 0; | |
2186 | } | |
2187 | ||
52815b75 JR |
2188 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2189 | { | |
6a113ddc JR |
2190 | bool reset_enable; |
2191 | int reqs, ret; | |
2192 | ||
2193 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2194 | reqs = 32; | |
2195 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2196 | reqs = 1; | |
2197 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2198 | |
2199 | /* Only allow access to user-accessible pages */ | |
2200 | ret = pci_enable_pasid(pdev, 0); | |
2201 | if (ret) | |
2202 | goto out_err; | |
2203 | ||
2204 | /* First reset the PRI state of the device */ | |
2205 | ret = pci_reset_pri(pdev); | |
2206 | if (ret) | |
2207 | goto out_err; | |
2208 | ||
6a113ddc JR |
2209 | /* Enable PRI */ |
2210 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2211 | if (ret) |
2212 | goto out_err; | |
2213 | ||
6a113ddc JR |
2214 | if (reset_enable) { |
2215 | ret = pri_reset_while_enabled(pdev); | |
2216 | if (ret) | |
2217 | goto out_err; | |
2218 | } | |
2219 | ||
52815b75 JR |
2220 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2221 | if (ret) | |
2222 | goto out_err; | |
2223 | ||
2224 | return 0; | |
2225 | ||
2226 | out_err: | |
2227 | pci_disable_pri(pdev); | |
2228 | pci_disable_pasid(pdev); | |
2229 | ||
2230 | return ret; | |
2231 | } | |
2232 | ||
c99afa25 | 2233 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2234 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2235 | |
98f1ad25 | 2236 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2237 | { |
a3b93121 | 2238 | u16 status; |
c99afa25 JR |
2239 | int pos; |
2240 | ||
46277b75 | 2241 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2242 | if (!pos) |
2243 | return false; | |
2244 | ||
a3b93121 | 2245 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2246 | |
a3b93121 | 2247 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2248 | } |
2249 | ||
407d733e | 2250 | /* |
df805abb | 2251 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2252 | * assigns it visible for the hardware |
2253 | */ | |
15898bbc JR |
2254 | static int attach_device(struct device *dev, |
2255 | struct protection_domain *domain) | |
0feae533 | 2256 | { |
fd7b5535 | 2257 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2258 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2259 | unsigned long flags; |
15898bbc | 2260 | int ret; |
eba6ac60 | 2261 | |
ea61cddb JR |
2262 | dev_data = get_dev_data(dev); |
2263 | ||
52815b75 JR |
2264 | if (domain->flags & PD_IOMMUV2_MASK) { |
2265 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2266 | return -EINVAL; | |
2267 | ||
2268 | if (pdev_iommuv2_enable(pdev) != 0) | |
2269 | return -EINVAL; | |
2270 | ||
2271 | dev_data->ats.enabled = true; | |
2272 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2273 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2274 | } else if (amd_iommu_iotlb_sup && |
2275 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2276 | dev_data->ats.enabled = true; |
2277 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2278 | } | |
fd7b5535 | 2279 | |
eba6ac60 | 2280 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2281 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2282 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2283 | ||
0feae533 JR |
2284 | /* |
2285 | * We might boot into a crash-kernel here. The crashed kernel | |
2286 | * left the caches in the IOMMU dirty. So we have to flush | |
2287 | * here to evict all dirty stuff. | |
2288 | */ | |
17b124bf | 2289 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2290 | |
2291 | return ret; | |
b20ac0d4 JR |
2292 | } |
2293 | ||
355bf553 JR |
2294 | /* |
2295 | * Removes a device from a protection domain (unlocked) | |
2296 | */ | |
ec9e79ef | 2297 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2298 | { |
2ca76279 | 2299 | struct protection_domain *domain; |
7c392cbe | 2300 | unsigned long flags; |
c4596114 | 2301 | |
7f760ddd | 2302 | BUG_ON(!dev_data->domain); |
355bf553 | 2303 | |
2ca76279 JR |
2304 | domain = dev_data->domain; |
2305 | ||
2306 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2307 | |
71f77580 JR |
2308 | if (dev_data->alias_data != NULL) { |
2309 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2310 | ||
7f760ddd | 2311 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2312 | do_detach(alias_data); |
24100055 JR |
2313 | } |
2314 | ||
7f760ddd | 2315 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2316 | do_detach(dev_data); |
7f760ddd | 2317 | |
2ca76279 | 2318 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2319 | |
2320 | /* | |
2321 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2322 | * passthrough domain if it is detached from any other domain. |
2323 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2324 | */ |
5abcdba4 | 2325 | if (dev_data->passthrough && |
d3ad9373 | 2326 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2327 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2328 | } |
2329 | ||
2330 | /* | |
2331 | * Removes a device from a protection domain (with devtable_lock held) | |
2332 | */ | |
15898bbc | 2333 | static void detach_device(struct device *dev) |
355bf553 | 2334 | { |
52815b75 | 2335 | struct protection_domain *domain; |
ea61cddb | 2336 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2337 | unsigned long flags; |
2338 | ||
ec9e79ef | 2339 | dev_data = get_dev_data(dev); |
52815b75 | 2340 | domain = dev_data->domain; |
ec9e79ef | 2341 | |
355bf553 JR |
2342 | /* lock device table */ |
2343 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2344 | __detach_device(dev_data); |
355bf553 | 2345 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2346 | |
52815b75 JR |
2347 | if (domain->flags & PD_IOMMUV2_MASK) |
2348 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2349 | else if (dev_data->ats.enabled) | |
ea61cddb | 2350 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2351 | |
2352 | dev_data->ats.enabled = false; | |
355bf553 | 2353 | } |
e275a2a0 | 2354 | |
15898bbc JR |
2355 | /* |
2356 | * Find out the protection domain structure for a given PCI device. This | |
2357 | * will give us the pointer to the page table root for example. | |
2358 | */ | |
2359 | static struct protection_domain *domain_for_device(struct device *dev) | |
2360 | { | |
71f77580 | 2361 | struct iommu_dev_data *dev_data; |
2b02b091 | 2362 | struct protection_domain *dom = NULL; |
15898bbc | 2363 | unsigned long flags; |
15898bbc | 2364 | |
657cbb6b | 2365 | dev_data = get_dev_data(dev); |
15898bbc | 2366 | |
2b02b091 JR |
2367 | if (dev_data->domain) |
2368 | return dev_data->domain; | |
15898bbc | 2369 | |
71f77580 JR |
2370 | if (dev_data->alias_data != NULL) { |
2371 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2372 | |
2373 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2374 | if (alias_data->domain != NULL) { | |
2375 | __attach_device(dev_data, alias_data->domain); | |
2376 | dom = alias_data->domain; | |
2377 | } | |
2378 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2379 | } | |
15898bbc JR |
2380 | |
2381 | return dom; | |
2382 | } | |
2383 | ||
e275a2a0 JR |
2384 | static int device_change_notifier(struct notifier_block *nb, |
2385 | unsigned long action, void *data) | |
2386 | { | |
e275a2a0 | 2387 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2388 | struct protection_domain *domain; |
2389 | struct iommu_dev_data *dev_data; | |
2390 | struct device *dev = data; | |
e275a2a0 | 2391 | struct amd_iommu *iommu; |
1ac4cbbc | 2392 | unsigned long flags; |
5abcdba4 | 2393 | u16 devid; |
e275a2a0 | 2394 | |
98fc5a69 JR |
2395 | if (!check_device(dev)) |
2396 | return 0; | |
e275a2a0 | 2397 | |
5abcdba4 JR |
2398 | devid = get_device_id(dev); |
2399 | iommu = amd_iommu_rlookup_table[devid]; | |
2400 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2401 | |
2402 | switch (action) { | |
c1eee67b | 2403 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2404 | |
2405 | domain = domain_for_device(dev); | |
2406 | ||
e275a2a0 JR |
2407 | if (!domain) |
2408 | goto out; | |
5abcdba4 | 2409 | if (dev_data->passthrough) |
a1ca331c | 2410 | break; |
15898bbc | 2411 | detach_device(dev); |
1ac4cbbc JR |
2412 | break; |
2413 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2414 | |
2415 | iommu_init_device(dev); | |
25b11ce2 | 2416 | init_iommu_group(dev); |
657cbb6b | 2417 | |
2c9195e9 JR |
2418 | /* |
2419 | * dev_data is still NULL and | |
2420 | * got initialized in iommu_init_device | |
2421 | */ | |
2422 | dev_data = get_dev_data(dev); | |
2423 | ||
2424 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2425 | dev_data->passthrough = true; | |
2426 | attach_device(dev, pt_domain); | |
2427 | break; | |
2428 | } | |
2429 | ||
657cbb6b JR |
2430 | domain = domain_for_device(dev); |
2431 | ||
1ac4cbbc JR |
2432 | /* allocate a protection domain if a device is added */ |
2433 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2434 | if (!dma_domain) { |
2435 | dma_domain = dma_ops_domain_alloc(); | |
2436 | if (!dma_domain) | |
2437 | goto out; | |
2438 | dma_domain->target_dev = devid; | |
2439 | ||
2440 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2441 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2442 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2443 | } | |
ac1534a5 | 2444 | |
2c9195e9 | 2445 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2446 | |
e275a2a0 | 2447 | break; |
657cbb6b JR |
2448 | case BUS_NOTIFY_DEL_DEVICE: |
2449 | ||
2450 | iommu_uninit_device(dev); | |
2451 | ||
e275a2a0 JR |
2452 | default: |
2453 | goto out; | |
2454 | } | |
2455 | ||
e275a2a0 JR |
2456 | iommu_completion_wait(iommu); |
2457 | ||
2458 | out: | |
2459 | return 0; | |
2460 | } | |
2461 | ||
b25ae679 | 2462 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2463 | .notifier_call = device_change_notifier, |
2464 | }; | |
355bf553 | 2465 | |
8638c491 JR |
2466 | void amd_iommu_init_notifier(void) |
2467 | { | |
2468 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2469 | } | |
2470 | ||
431b2a20 JR |
2471 | /***************************************************************************** |
2472 | * | |
2473 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2474 | * | |
2475 | *****************************************************************************/ | |
2476 | ||
2477 | /* | |
2478 | * In the dma_ops path we only have the struct device. This function | |
2479 | * finds the corresponding IOMMU, the protection domain and the | |
2480 | * requestor id for a given device. | |
2481 | * If the device is not yet associated with a domain this is also done | |
2482 | * in this function. | |
2483 | */ | |
94f6d190 | 2484 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2485 | { |
94f6d190 | 2486 | struct protection_domain *domain; |
b20ac0d4 | 2487 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2488 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2489 | |
f99c0f1c | 2490 | if (!check_device(dev)) |
94f6d190 | 2491 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2492 | |
94f6d190 JR |
2493 | domain = domain_for_device(dev); |
2494 | if (domain != NULL && !dma_ops_domain(domain)) | |
2495 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2496 | |
94f6d190 JR |
2497 | if (domain != NULL) |
2498 | return domain; | |
b20ac0d4 | 2499 | |
df805abb | 2500 | /* Device not bound yet - bind it */ |
94f6d190 | 2501 | dma_dom = find_protection_domain(devid); |
15898bbc | 2502 | if (!dma_dom) |
94f6d190 JR |
2503 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2504 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2505 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2506 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2507 | |
94f6d190 | 2508 | return &dma_dom->domain; |
b20ac0d4 JR |
2509 | } |
2510 | ||
04bfdd84 JR |
2511 | static void update_device_table(struct protection_domain *domain) |
2512 | { | |
492667da | 2513 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2514 | |
ea61cddb JR |
2515 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2516 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2517 | } |
2518 | ||
2519 | static void update_domain(struct protection_domain *domain) | |
2520 | { | |
2521 | if (!domain->updated) | |
2522 | return; | |
2523 | ||
2524 | update_device_table(domain); | |
17b124bf JR |
2525 | |
2526 | domain_flush_devices(domain); | |
2527 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2528 | |
2529 | domain->updated = false; | |
2530 | } | |
2531 | ||
8bda3092 JR |
2532 | /* |
2533 | * This function fetches the PTE for a given address in the aperture | |
2534 | */ | |
2535 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2536 | unsigned long address) | |
2537 | { | |
384de729 | 2538 | struct aperture_range *aperture; |
8bda3092 JR |
2539 | u64 *pte, *pte_page; |
2540 | ||
384de729 JR |
2541 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2542 | if (!aperture) | |
2543 | return NULL; | |
2544 | ||
2545 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2546 | if (!pte) { |
cbb9d729 | 2547 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2548 | GFP_ATOMIC); |
384de729 JR |
2549 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2550 | } else | |
8c8c143c | 2551 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2552 | |
04bfdd84 | 2553 | update_domain(&dom->domain); |
8bda3092 JR |
2554 | |
2555 | return pte; | |
2556 | } | |
2557 | ||
431b2a20 JR |
2558 | /* |
2559 | * This is the generic map function. It maps one 4kb page at paddr to | |
2560 | * the given address in the DMA address space for the domain. | |
2561 | */ | |
680525e0 | 2562 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2563 | unsigned long address, |
2564 | phys_addr_t paddr, | |
2565 | int direction) | |
2566 | { | |
2567 | u64 *pte, __pte; | |
2568 | ||
2569 | WARN_ON(address > dom->aperture_size); | |
2570 | ||
2571 | paddr &= PAGE_MASK; | |
2572 | ||
8bda3092 | 2573 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2574 | if (!pte) |
8fd524b3 | 2575 | return DMA_ERROR_CODE; |
cb76c322 JR |
2576 | |
2577 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2578 | ||
2579 | if (direction == DMA_TO_DEVICE) | |
2580 | __pte |= IOMMU_PTE_IR; | |
2581 | else if (direction == DMA_FROM_DEVICE) | |
2582 | __pte |= IOMMU_PTE_IW; | |
2583 | else if (direction == DMA_BIDIRECTIONAL) | |
2584 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2585 | ||
2586 | WARN_ON(*pte); | |
2587 | ||
2588 | *pte = __pte; | |
2589 | ||
2590 | return (dma_addr_t)address; | |
2591 | } | |
2592 | ||
431b2a20 JR |
2593 | /* |
2594 | * The generic unmapping function for on page in the DMA address space. | |
2595 | */ | |
680525e0 | 2596 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2597 | unsigned long address) |
2598 | { | |
384de729 | 2599 | struct aperture_range *aperture; |
cb76c322 JR |
2600 | u64 *pte; |
2601 | ||
2602 | if (address >= dom->aperture_size) | |
2603 | return; | |
2604 | ||
384de729 JR |
2605 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2606 | if (!aperture) | |
2607 | return; | |
2608 | ||
2609 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2610 | if (!pte) | |
2611 | return; | |
cb76c322 | 2612 | |
8c8c143c | 2613 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2614 | |
2615 | WARN_ON(!*pte); | |
2616 | ||
2617 | *pte = 0ULL; | |
2618 | } | |
2619 | ||
431b2a20 JR |
2620 | /* |
2621 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2622 | * contiguous memory region into DMA address space. It is used by all |
2623 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2624 | * Must be called with the domain lock held. |
2625 | */ | |
cb76c322 | 2626 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2627 | struct dma_ops_domain *dma_dom, |
2628 | phys_addr_t paddr, | |
2629 | size_t size, | |
6d4f343f | 2630 | int dir, |
832a90c3 JR |
2631 | bool align, |
2632 | u64 dma_mask) | |
cb76c322 JR |
2633 | { |
2634 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2635 | dma_addr_t address, start, ret; |
cb76c322 | 2636 | unsigned int pages; |
6d4f343f | 2637 | unsigned long align_mask = 0; |
cb76c322 JR |
2638 | int i; |
2639 | ||
e3c449f5 | 2640 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2641 | paddr &= PAGE_MASK; |
2642 | ||
8ecaf8f1 JR |
2643 | INC_STATS_COUNTER(total_map_requests); |
2644 | ||
c1858976 JR |
2645 | if (pages > 1) |
2646 | INC_STATS_COUNTER(cross_page); | |
2647 | ||
6d4f343f JR |
2648 | if (align) |
2649 | align_mask = (1UL << get_order(size)) - 1; | |
2650 | ||
11b83888 | 2651 | retry: |
832a90c3 JR |
2652 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2653 | dma_mask); | |
8fd524b3 | 2654 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2655 | /* |
2656 | * setting next_address here will let the address | |
2657 | * allocator only scan the new allocated range in the | |
2658 | * first run. This is a small optimization. | |
2659 | */ | |
2660 | dma_dom->next_address = dma_dom->aperture_size; | |
2661 | ||
576175c2 | 2662 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2663 | goto out; |
2664 | ||
2665 | /* | |
af901ca1 | 2666 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2667 | * allocation again |
2668 | */ | |
2669 | goto retry; | |
2670 | } | |
cb76c322 JR |
2671 | |
2672 | start = address; | |
2673 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2674 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2675 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2676 | goto out_unmap; |
2677 | ||
cb76c322 JR |
2678 | paddr += PAGE_SIZE; |
2679 | start += PAGE_SIZE; | |
2680 | } | |
2681 | address += offset; | |
2682 | ||
5774f7c5 JR |
2683 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2684 | ||
afa9fdc2 | 2685 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2686 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2687 | dma_dom->need_flush = false; |
318afd41 | 2688 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2689 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2690 | |
cb76c322 JR |
2691 | out: |
2692 | return address; | |
53812c11 JR |
2693 | |
2694 | out_unmap: | |
2695 | ||
2696 | for (--i; i >= 0; --i) { | |
2697 | start -= PAGE_SIZE; | |
680525e0 | 2698 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2699 | } |
2700 | ||
2701 | dma_ops_free_addresses(dma_dom, address, pages); | |
2702 | ||
8fd524b3 | 2703 | return DMA_ERROR_CODE; |
cb76c322 JR |
2704 | } |
2705 | ||
431b2a20 JR |
2706 | /* |
2707 | * Does the reverse of the __map_single function. Must be called with | |
2708 | * the domain lock held too | |
2709 | */ | |
cd8c82e8 | 2710 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2711 | dma_addr_t dma_addr, |
2712 | size_t size, | |
2713 | int dir) | |
2714 | { | |
04e0463e | 2715 | dma_addr_t flush_addr; |
cb76c322 JR |
2716 | dma_addr_t i, start; |
2717 | unsigned int pages; | |
2718 | ||
8fd524b3 | 2719 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2720 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2721 | return; |
2722 | ||
04e0463e | 2723 | flush_addr = dma_addr; |
e3c449f5 | 2724 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2725 | dma_addr &= PAGE_MASK; |
2726 | start = dma_addr; | |
2727 | ||
2728 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2729 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2730 | start += PAGE_SIZE; |
2731 | } | |
2732 | ||
5774f7c5 JR |
2733 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2734 | ||
cb76c322 | 2735 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2736 | |
80be308d | 2737 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2738 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2739 | dma_dom->need_flush = false; |
2740 | } | |
cb76c322 JR |
2741 | } |
2742 | ||
431b2a20 JR |
2743 | /* |
2744 | * The exported map_single function for dma_ops. | |
2745 | */ | |
51491367 FT |
2746 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2747 | unsigned long offset, size_t size, | |
2748 | enum dma_data_direction dir, | |
2749 | struct dma_attrs *attrs) | |
4da70b9e JR |
2750 | { |
2751 | unsigned long flags; | |
4da70b9e | 2752 | struct protection_domain *domain; |
4da70b9e | 2753 | dma_addr_t addr; |
832a90c3 | 2754 | u64 dma_mask; |
51491367 | 2755 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2756 | |
0f2a86f2 JR |
2757 | INC_STATS_COUNTER(cnt_map_single); |
2758 | ||
94f6d190 JR |
2759 | domain = get_domain(dev); |
2760 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2761 | return (dma_addr_t)paddr; |
94f6d190 JR |
2762 | else if (IS_ERR(domain)) |
2763 | return DMA_ERROR_CODE; | |
4da70b9e | 2764 | |
f99c0f1c JR |
2765 | dma_mask = *dev->dma_mask; |
2766 | ||
4da70b9e | 2767 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2768 | |
cd8c82e8 | 2769 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2770 | dma_mask); |
8fd524b3 | 2771 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2772 | goto out; |
2773 | ||
17b124bf | 2774 | domain_flush_complete(domain); |
4da70b9e JR |
2775 | |
2776 | out: | |
2777 | spin_unlock_irqrestore(&domain->lock, flags); | |
2778 | ||
2779 | return addr; | |
2780 | } | |
2781 | ||
431b2a20 JR |
2782 | /* |
2783 | * The exported unmap_single function for dma_ops. | |
2784 | */ | |
51491367 FT |
2785 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2786 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2787 | { |
2788 | unsigned long flags; | |
4da70b9e | 2789 | struct protection_domain *domain; |
4da70b9e | 2790 | |
146a6917 JR |
2791 | INC_STATS_COUNTER(cnt_unmap_single); |
2792 | ||
94f6d190 JR |
2793 | domain = get_domain(dev); |
2794 | if (IS_ERR(domain)) | |
5b28df6f JR |
2795 | return; |
2796 | ||
4da70b9e JR |
2797 | spin_lock_irqsave(&domain->lock, flags); |
2798 | ||
cd8c82e8 | 2799 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2800 | |
17b124bf | 2801 | domain_flush_complete(domain); |
4da70b9e JR |
2802 | |
2803 | spin_unlock_irqrestore(&domain->lock, flags); | |
2804 | } | |
2805 | ||
431b2a20 JR |
2806 | /* |
2807 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2808 | * lists). | |
2809 | */ | |
65b050ad | 2810 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2811 | int nelems, enum dma_data_direction dir, |
2812 | struct dma_attrs *attrs) | |
65b050ad JR |
2813 | { |
2814 | unsigned long flags; | |
65b050ad | 2815 | struct protection_domain *domain; |
65b050ad JR |
2816 | int i; |
2817 | struct scatterlist *s; | |
2818 | phys_addr_t paddr; | |
2819 | int mapped_elems = 0; | |
832a90c3 | 2820 | u64 dma_mask; |
65b050ad | 2821 | |
d03f067a JR |
2822 | INC_STATS_COUNTER(cnt_map_sg); |
2823 | ||
94f6d190 | 2824 | domain = get_domain(dev); |
a0e191b2 | 2825 | if (IS_ERR(domain)) |
94f6d190 | 2826 | return 0; |
dbcc112e | 2827 | |
832a90c3 | 2828 | dma_mask = *dev->dma_mask; |
65b050ad | 2829 | |
65b050ad JR |
2830 | spin_lock_irqsave(&domain->lock, flags); |
2831 | ||
2832 | for_each_sg(sglist, s, nelems, i) { | |
2833 | paddr = sg_phys(s); | |
2834 | ||
cd8c82e8 | 2835 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2836 | paddr, s->length, dir, false, |
2837 | dma_mask); | |
65b050ad JR |
2838 | |
2839 | if (s->dma_address) { | |
2840 | s->dma_length = s->length; | |
2841 | mapped_elems++; | |
2842 | } else | |
2843 | goto unmap; | |
65b050ad JR |
2844 | } |
2845 | ||
17b124bf | 2846 | domain_flush_complete(domain); |
65b050ad JR |
2847 | |
2848 | out: | |
2849 | spin_unlock_irqrestore(&domain->lock, flags); | |
2850 | ||
2851 | return mapped_elems; | |
2852 | unmap: | |
2853 | for_each_sg(sglist, s, mapped_elems, i) { | |
2854 | if (s->dma_address) | |
cd8c82e8 | 2855 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2856 | s->dma_length, dir); |
2857 | s->dma_address = s->dma_length = 0; | |
2858 | } | |
2859 | ||
2860 | mapped_elems = 0; | |
2861 | ||
2862 | goto out; | |
2863 | } | |
2864 | ||
431b2a20 JR |
2865 | /* |
2866 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2867 | * lists). | |
2868 | */ | |
65b050ad | 2869 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2870 | int nelems, enum dma_data_direction dir, |
2871 | struct dma_attrs *attrs) | |
65b050ad JR |
2872 | { |
2873 | unsigned long flags; | |
65b050ad JR |
2874 | struct protection_domain *domain; |
2875 | struct scatterlist *s; | |
65b050ad JR |
2876 | int i; |
2877 | ||
55877a6b JR |
2878 | INC_STATS_COUNTER(cnt_unmap_sg); |
2879 | ||
94f6d190 JR |
2880 | domain = get_domain(dev); |
2881 | if (IS_ERR(domain)) | |
5b28df6f JR |
2882 | return; |
2883 | ||
65b050ad JR |
2884 | spin_lock_irqsave(&domain->lock, flags); |
2885 | ||
2886 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2887 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2888 | s->dma_length, dir); |
65b050ad JR |
2889 | s->dma_address = s->dma_length = 0; |
2890 | } | |
2891 | ||
17b124bf | 2892 | domain_flush_complete(domain); |
65b050ad JR |
2893 | |
2894 | spin_unlock_irqrestore(&domain->lock, flags); | |
2895 | } | |
2896 | ||
431b2a20 JR |
2897 | /* |
2898 | * The exported alloc_coherent function for dma_ops. | |
2899 | */ | |
5d8b53cf | 2900 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2901 | dma_addr_t *dma_addr, gfp_t flag, |
2902 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2903 | { |
2904 | unsigned long flags; | |
2905 | void *virt_addr; | |
5d8b53cf | 2906 | struct protection_domain *domain; |
5d8b53cf | 2907 | phys_addr_t paddr; |
832a90c3 | 2908 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2909 | |
c8f0fb36 JR |
2910 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2911 | ||
94f6d190 JR |
2912 | domain = get_domain(dev); |
2913 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2914 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2915 | *dma_addr = __pa(virt_addr); | |
2916 | return virt_addr; | |
94f6d190 JR |
2917 | } else if (IS_ERR(domain)) |
2918 | return NULL; | |
5d8b53cf | 2919 | |
f99c0f1c JR |
2920 | dma_mask = dev->coherent_dma_mask; |
2921 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2922 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2923 | |
2924 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2925 | if (!virt_addr) | |
b25ae679 | 2926 | return NULL; |
5d8b53cf | 2927 | |
5d8b53cf JR |
2928 | paddr = virt_to_phys(virt_addr); |
2929 | ||
832a90c3 JR |
2930 | if (!dma_mask) |
2931 | dma_mask = *dev->dma_mask; | |
2932 | ||
5d8b53cf JR |
2933 | spin_lock_irqsave(&domain->lock, flags); |
2934 | ||
cd8c82e8 | 2935 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2936 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2937 | |
8fd524b3 | 2938 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2939 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2940 | goto out_free; |
367d04c4 | 2941 | } |
5d8b53cf | 2942 | |
17b124bf | 2943 | domain_flush_complete(domain); |
5d8b53cf | 2944 | |
5d8b53cf JR |
2945 | spin_unlock_irqrestore(&domain->lock, flags); |
2946 | ||
2947 | return virt_addr; | |
5b28df6f JR |
2948 | |
2949 | out_free: | |
2950 | ||
2951 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2952 | ||
2953 | return NULL; | |
5d8b53cf JR |
2954 | } |
2955 | ||
431b2a20 JR |
2956 | /* |
2957 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2958 | */ |
5d8b53cf | 2959 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2960 | void *virt_addr, dma_addr_t dma_addr, |
2961 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2962 | { |
2963 | unsigned long flags; | |
5d8b53cf | 2964 | struct protection_domain *domain; |
5d8b53cf | 2965 | |
5d31ee7e JR |
2966 | INC_STATS_COUNTER(cnt_free_coherent); |
2967 | ||
94f6d190 JR |
2968 | domain = get_domain(dev); |
2969 | if (IS_ERR(domain)) | |
5b28df6f JR |
2970 | goto free_mem; |
2971 | ||
5d8b53cf JR |
2972 | spin_lock_irqsave(&domain->lock, flags); |
2973 | ||
cd8c82e8 | 2974 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2975 | |
17b124bf | 2976 | domain_flush_complete(domain); |
5d8b53cf JR |
2977 | |
2978 | spin_unlock_irqrestore(&domain->lock, flags); | |
2979 | ||
2980 | free_mem: | |
2981 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2982 | } | |
2983 | ||
b39ba6ad JR |
2984 | /* |
2985 | * This function is called by the DMA layer to find out if we can handle a | |
2986 | * particular device. It is part of the dma_ops. | |
2987 | */ | |
2988 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2989 | { | |
420aef8a | 2990 | return check_device(dev); |
b39ba6ad JR |
2991 | } |
2992 | ||
c432f3df | 2993 | /* |
431b2a20 JR |
2994 | * The function for pre-allocating protection domains. |
2995 | * | |
c432f3df JR |
2996 | * If the driver core informs the DMA layer if a driver grabs a device |
2997 | * we don't need to preallocate the protection domains anymore. | |
2998 | * For now we have to. | |
2999 | */ | |
943bc7e1 | 3000 | static void __init prealloc_protection_domains(void) |
c432f3df | 3001 | { |
5abcdba4 | 3002 | struct iommu_dev_data *dev_data; |
c432f3df | 3003 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3004 | struct pci_dev *dev = NULL; |
98fc5a69 | 3005 | u16 devid; |
c432f3df | 3006 | |
d18c69d3 | 3007 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3008 | |
3009 | /* Do we handle this device? */ | |
3010 | if (!check_device(&dev->dev)) | |
c432f3df | 3011 | continue; |
98fc5a69 | 3012 | |
5abcdba4 JR |
3013 | dev_data = get_dev_data(&dev->dev); |
3014 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3015 | /* Make sure passthrough domain is allocated */ | |
3016 | alloc_passthrough_domain(); | |
3017 | dev_data->passthrough = true; | |
3018 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3019 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3020 | dev_name(&dev->dev)); |
3021 | } | |
3022 | ||
98fc5a69 | 3023 | /* Is there already any domain for it? */ |
15898bbc | 3024 | if (domain_for_device(&dev->dev)) |
c432f3df | 3025 | continue; |
98fc5a69 JR |
3026 | |
3027 | devid = get_device_id(&dev->dev); | |
3028 | ||
87a64d52 | 3029 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3030 | if (!dma_dom) |
3031 | continue; | |
3032 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3033 | dma_dom->target_dev = devid; |
3034 | ||
15898bbc | 3035 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3036 | |
bd60b735 | 3037 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3038 | } |
3039 | } | |
3040 | ||
160c1d8e | 3041 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3042 | .alloc = alloc_coherent, |
3043 | .free = free_coherent, | |
51491367 FT |
3044 | .map_page = map_page, |
3045 | .unmap_page = unmap_page, | |
6631ee9d JR |
3046 | .map_sg = map_sg, |
3047 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3048 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3049 | }; |
3050 | ||
27c2127a JR |
3051 | static unsigned device_dma_ops_init(void) |
3052 | { | |
5abcdba4 | 3053 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3054 | struct pci_dev *pdev = NULL; |
3055 | unsigned unhandled = 0; | |
3056 | ||
3057 | for_each_pci_dev(pdev) { | |
3058 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3059 | |
3060 | iommu_ignore_device(&pdev->dev); | |
3061 | ||
27c2127a JR |
3062 | unhandled += 1; |
3063 | continue; | |
3064 | } | |
3065 | ||
5abcdba4 JR |
3066 | dev_data = get_dev_data(&pdev->dev); |
3067 | ||
3068 | if (!dev_data->passthrough) | |
3069 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3070 | else | |
3071 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3072 | } |
3073 | ||
3074 | return unhandled; | |
3075 | } | |
3076 | ||
431b2a20 JR |
3077 | /* |
3078 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3079 | */ | |
f5325094 JR |
3080 | |
3081 | void __init amd_iommu_init_api(void) | |
3082 | { | |
2cc21c42 | 3083 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3084 | } |
3085 | ||
6631ee9d JR |
3086 | int __init amd_iommu_init_dma_ops(void) |
3087 | { | |
3088 | struct amd_iommu *iommu; | |
27c2127a | 3089 | int ret, unhandled; |
6631ee9d | 3090 | |
431b2a20 JR |
3091 | /* |
3092 | * first allocate a default protection domain for every IOMMU we | |
3093 | * found in the system. Devices not assigned to any other | |
3094 | * protection domain will be assigned to the default one. | |
3095 | */ | |
3bd22172 | 3096 | for_each_iommu(iommu) { |
87a64d52 | 3097 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3098 | if (iommu->default_dom == NULL) |
3099 | return -ENOMEM; | |
e2dc14a2 | 3100 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3101 | ret = iommu_init_unity_mappings(iommu); |
3102 | if (ret) | |
3103 | goto free_domains; | |
3104 | } | |
3105 | ||
431b2a20 | 3106 | /* |
8793abeb | 3107 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3108 | */ |
8793abeb | 3109 | prealloc_protection_domains(); |
6631ee9d JR |
3110 | |
3111 | iommu_detected = 1; | |
75f1cdf1 | 3112 | swiotlb = 0; |
6631ee9d | 3113 | |
431b2a20 | 3114 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3115 | unhandled = device_dma_ops_init(); |
3116 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3117 | /* There are unhandled devices - initialize swiotlb for them */ | |
3118 | swiotlb = 1; | |
3119 | } | |
6631ee9d | 3120 | |
7f26508b JR |
3121 | amd_iommu_stats_init(); |
3122 | ||
62410eeb JR |
3123 | if (amd_iommu_unmap_flush) |
3124 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3125 | else | |
3126 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3127 | ||
6631ee9d JR |
3128 | return 0; |
3129 | ||
3130 | free_domains: | |
3131 | ||
3bd22172 | 3132 | for_each_iommu(iommu) { |
91457df7 | 3133 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3134 | } |
3135 | ||
3136 | return ret; | |
3137 | } | |
6d98cd80 JR |
3138 | |
3139 | /***************************************************************************** | |
3140 | * | |
3141 | * The following functions belong to the exported interface of AMD IOMMU | |
3142 | * | |
3143 | * This interface allows access to lower level functions of the IOMMU | |
3144 | * like protection domain handling and assignement of devices to domains | |
3145 | * which is not possible with the dma_ops interface. | |
3146 | * | |
3147 | *****************************************************************************/ | |
3148 | ||
6d98cd80 JR |
3149 | static void cleanup_domain(struct protection_domain *domain) |
3150 | { | |
9b29d3c6 | 3151 | struct iommu_dev_data *entry; |
6d98cd80 | 3152 | unsigned long flags; |
6d98cd80 JR |
3153 | |
3154 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3155 | ||
9b29d3c6 JR |
3156 | while (!list_empty(&domain->dev_list)) { |
3157 | entry = list_first_entry(&domain->dev_list, | |
3158 | struct iommu_dev_data, list); | |
3159 | __detach_device(entry); | |
3160 | atomic_set(&entry->bind, 0); | |
492667da | 3161 | } |
6d98cd80 JR |
3162 | |
3163 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3164 | } | |
3165 | ||
2650815f JR |
3166 | static void protection_domain_free(struct protection_domain *domain) |
3167 | { | |
3168 | if (!domain) | |
3169 | return; | |
3170 | ||
aeb26f55 JR |
3171 | del_domain_from_list(domain); |
3172 | ||
2650815f JR |
3173 | if (domain->id) |
3174 | domain_id_free(domain->id); | |
3175 | ||
3176 | kfree(domain); | |
3177 | } | |
3178 | ||
3179 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3180 | { |
3181 | struct protection_domain *domain; | |
3182 | ||
3183 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3184 | if (!domain) | |
2650815f | 3185 | return NULL; |
c156e347 JR |
3186 | |
3187 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3188 | mutex_init(&domain->api_lock); |
c156e347 JR |
3189 | domain->id = domain_id_alloc(); |
3190 | if (!domain->id) | |
2650815f | 3191 | goto out_err; |
7c392cbe | 3192 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3193 | |
aeb26f55 JR |
3194 | add_domain_to_list(domain); |
3195 | ||
2650815f JR |
3196 | return domain; |
3197 | ||
3198 | out_err: | |
3199 | kfree(domain); | |
3200 | ||
3201 | return NULL; | |
3202 | } | |
3203 | ||
5abcdba4 JR |
3204 | static int __init alloc_passthrough_domain(void) |
3205 | { | |
3206 | if (pt_domain != NULL) | |
3207 | return 0; | |
3208 | ||
3209 | /* allocate passthrough domain */ | |
3210 | pt_domain = protection_domain_alloc(); | |
3211 | if (!pt_domain) | |
3212 | return -ENOMEM; | |
3213 | ||
3214 | pt_domain->mode = PAGE_MODE_NONE; | |
3215 | ||
3216 | return 0; | |
3217 | } | |
2650815f JR |
3218 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3219 | { | |
3220 | struct protection_domain *domain; | |
3221 | ||
3222 | domain = protection_domain_alloc(); | |
3223 | if (!domain) | |
c156e347 | 3224 | goto out_free; |
2650815f JR |
3225 | |
3226 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3227 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3228 | if (!domain->pt_root) | |
3229 | goto out_free; | |
3230 | ||
f3572db8 JR |
3231 | domain->iommu_domain = dom; |
3232 | ||
c156e347 JR |
3233 | dom->priv = domain; |
3234 | ||
0ff64f80 JR |
3235 | dom->geometry.aperture_start = 0; |
3236 | dom->geometry.aperture_end = ~0ULL; | |
3237 | dom->geometry.force_aperture = true; | |
3238 | ||
c156e347 JR |
3239 | return 0; |
3240 | ||
3241 | out_free: | |
2650815f | 3242 | protection_domain_free(domain); |
c156e347 JR |
3243 | |
3244 | return -ENOMEM; | |
3245 | } | |
3246 | ||
98383fc3 JR |
3247 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3248 | { | |
3249 | struct protection_domain *domain = dom->priv; | |
3250 | ||
3251 | if (!domain) | |
3252 | return; | |
3253 | ||
3254 | if (domain->dev_cnt > 0) | |
3255 | cleanup_domain(domain); | |
3256 | ||
3257 | BUG_ON(domain->dev_cnt != 0); | |
3258 | ||
132bd68f JR |
3259 | if (domain->mode != PAGE_MODE_NONE) |
3260 | free_pagetable(domain); | |
98383fc3 | 3261 | |
52815b75 JR |
3262 | if (domain->flags & PD_IOMMUV2_MASK) |
3263 | free_gcr3_table(domain); | |
3264 | ||
8b408fe4 | 3265 | protection_domain_free(domain); |
98383fc3 JR |
3266 | |
3267 | dom->priv = NULL; | |
3268 | } | |
3269 | ||
684f2888 JR |
3270 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3271 | struct device *dev) | |
3272 | { | |
657cbb6b | 3273 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3274 | struct amd_iommu *iommu; |
684f2888 JR |
3275 | u16 devid; |
3276 | ||
98fc5a69 | 3277 | if (!check_device(dev)) |
684f2888 JR |
3278 | return; |
3279 | ||
98fc5a69 | 3280 | devid = get_device_id(dev); |
684f2888 | 3281 | |
657cbb6b | 3282 | if (dev_data->domain != NULL) |
15898bbc | 3283 | detach_device(dev); |
684f2888 JR |
3284 | |
3285 | iommu = amd_iommu_rlookup_table[devid]; | |
3286 | if (!iommu) | |
3287 | return; | |
3288 | ||
684f2888 JR |
3289 | iommu_completion_wait(iommu); |
3290 | } | |
3291 | ||
01106066 JR |
3292 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3293 | struct device *dev) | |
3294 | { | |
3295 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3296 | struct iommu_dev_data *dev_data; |
01106066 | 3297 | struct amd_iommu *iommu; |
15898bbc | 3298 | int ret; |
01106066 | 3299 | |
98fc5a69 | 3300 | if (!check_device(dev)) |
01106066 JR |
3301 | return -EINVAL; |
3302 | ||
657cbb6b JR |
3303 | dev_data = dev->archdata.iommu; |
3304 | ||
f62dda66 | 3305 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3306 | if (!iommu) |
3307 | return -EINVAL; | |
3308 | ||
657cbb6b | 3309 | if (dev_data->domain) |
15898bbc | 3310 | detach_device(dev); |
01106066 | 3311 | |
15898bbc | 3312 | ret = attach_device(dev, domain); |
01106066 JR |
3313 | |
3314 | iommu_completion_wait(iommu); | |
3315 | ||
15898bbc | 3316 | return ret; |
01106066 JR |
3317 | } |
3318 | ||
468e2366 | 3319 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3320 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3321 | { |
3322 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3323 | int prot = 0; |
3324 | int ret; | |
3325 | ||
132bd68f JR |
3326 | if (domain->mode == PAGE_MODE_NONE) |
3327 | return -EINVAL; | |
3328 | ||
c6229ca6 JR |
3329 | if (iommu_prot & IOMMU_READ) |
3330 | prot |= IOMMU_PROT_IR; | |
3331 | if (iommu_prot & IOMMU_WRITE) | |
3332 | prot |= IOMMU_PROT_IW; | |
3333 | ||
5d214fe6 | 3334 | mutex_lock(&domain->api_lock); |
795e74f7 | 3335 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3336 | mutex_unlock(&domain->api_lock); |
3337 | ||
795e74f7 | 3338 | return ret; |
c6229ca6 JR |
3339 | } |
3340 | ||
5009065d OBC |
3341 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3342 | size_t page_size) | |
eb74ff6c | 3343 | { |
eb74ff6c | 3344 | struct protection_domain *domain = dom->priv; |
5009065d | 3345 | size_t unmap_size; |
eb74ff6c | 3346 | |
132bd68f JR |
3347 | if (domain->mode == PAGE_MODE_NONE) |
3348 | return -EINVAL; | |
3349 | ||
5d214fe6 | 3350 | mutex_lock(&domain->api_lock); |
468e2366 | 3351 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3352 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3353 | |
17b124bf | 3354 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3355 | |
5009065d | 3356 | return unmap_size; |
eb74ff6c JR |
3357 | } |
3358 | ||
645c4c8d | 3359 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3360 | dma_addr_t iova) |
645c4c8d JR |
3361 | { |
3362 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3363 | unsigned long offset_mask; |
645c4c8d | 3364 | phys_addr_t paddr; |
f03152bb | 3365 | u64 *pte, __pte; |
645c4c8d | 3366 | |
132bd68f JR |
3367 | if (domain->mode == PAGE_MODE_NONE) |
3368 | return iova; | |
3369 | ||
24cd7723 | 3370 | pte = fetch_pte(domain, iova); |
645c4c8d | 3371 | |
a6d41a40 | 3372 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3373 | return 0; |
3374 | ||
f03152bb JR |
3375 | if (PM_PTE_LEVEL(*pte) == 0) |
3376 | offset_mask = PAGE_SIZE - 1; | |
3377 | else | |
3378 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3379 | ||
3380 | __pte = *pte & PM_ADDR_MASK; | |
3381 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3382 | |
3383 | return paddr; | |
3384 | } | |
3385 | ||
ab636481 | 3386 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3387 | { |
80a506b8 JR |
3388 | switch (cap) { |
3389 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3390 | return true; |
bdddadcb | 3391 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3392 | return (irq_remapping_enabled == 1); |
80a506b8 JR |
3393 | } |
3394 | ||
ab636481 | 3395 | return false; |
dbb9fd86 SY |
3396 | } |
3397 | ||
b22f6434 | 3398 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3399 | .capable = amd_iommu_capable, |
26961efe JR |
3400 | .domain_init = amd_iommu_domain_init, |
3401 | .domain_destroy = amd_iommu_domain_destroy, | |
3402 | .attach_dev = amd_iommu_attach_device, | |
3403 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3404 | .map = amd_iommu_map, |
3405 | .unmap = amd_iommu_unmap, | |
26961efe | 3406 | .iova_to_phys = amd_iommu_iova_to_phys, |
aa3de9c0 | 3407 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3408 | }; |
3409 | ||
0feae533 JR |
3410 | /***************************************************************************** |
3411 | * | |
3412 | * The next functions do a basic initialization of IOMMU for pass through | |
3413 | * mode | |
3414 | * | |
3415 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3416 | * DMA-API translation. | |
3417 | * | |
3418 | *****************************************************************************/ | |
3419 | ||
3420 | int __init amd_iommu_init_passthrough(void) | |
3421 | { | |
5abcdba4 | 3422 | struct iommu_dev_data *dev_data; |
0feae533 | 3423 | struct pci_dev *dev = NULL; |
5abcdba4 | 3424 | int ret; |
0feae533 | 3425 | |
5abcdba4 JR |
3426 | ret = alloc_passthrough_domain(); |
3427 | if (ret) | |
3428 | return ret; | |
0feae533 | 3429 | |
6c54aabd | 3430 | for_each_pci_dev(dev) { |
98fc5a69 | 3431 | if (!check_device(&dev->dev)) |
0feae533 JR |
3432 | continue; |
3433 | ||
5abcdba4 JR |
3434 | dev_data = get_dev_data(&dev->dev); |
3435 | dev_data->passthrough = true; | |
3436 | ||
15898bbc | 3437 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3438 | } |
3439 | ||
2655d7a2 JR |
3440 | amd_iommu_stats_init(); |
3441 | ||
0feae533 JR |
3442 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3443 | ||
3444 | return 0; | |
3445 | } | |
72e1dcc4 JR |
3446 | |
3447 | /* IOMMUv2 specific functions */ | |
3448 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3449 | { | |
3450 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3451 | } | |
3452 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3453 | ||
3454 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3455 | { | |
3456 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3457 | } | |
3458 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3459 | |
3460 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3461 | { | |
3462 | struct protection_domain *domain = dom->priv; | |
3463 | unsigned long flags; | |
3464 | ||
3465 | spin_lock_irqsave(&domain->lock, flags); | |
3466 | ||
3467 | /* Update data structure */ | |
3468 | domain->mode = PAGE_MODE_NONE; | |
3469 | domain->updated = true; | |
3470 | ||
3471 | /* Make changes visible to IOMMUs */ | |
3472 | update_domain(domain); | |
3473 | ||
3474 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3475 | free_pagetable(domain); | |
3476 | ||
3477 | spin_unlock_irqrestore(&domain->lock, flags); | |
3478 | } | |
3479 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3480 | |
3481 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3482 | { | |
3483 | struct protection_domain *domain = dom->priv; | |
3484 | unsigned long flags; | |
3485 | int levels, ret; | |
3486 | ||
3487 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3488 | return -EINVAL; | |
3489 | ||
3490 | /* Number of GCR3 table levels required */ | |
3491 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3492 | levels += 1; | |
3493 | ||
3494 | if (levels > amd_iommu_max_glx_val) | |
3495 | return -EINVAL; | |
3496 | ||
3497 | spin_lock_irqsave(&domain->lock, flags); | |
3498 | ||
3499 | /* | |
3500 | * Save us all sanity checks whether devices already in the | |
3501 | * domain support IOMMUv2. Just force that the domain has no | |
3502 | * devices attached when it is switched into IOMMUv2 mode. | |
3503 | */ | |
3504 | ret = -EBUSY; | |
3505 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3506 | goto out; | |
3507 | ||
3508 | ret = -ENOMEM; | |
3509 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3510 | if (domain->gcr3_tbl == NULL) | |
3511 | goto out; | |
3512 | ||
3513 | domain->glx = levels; | |
3514 | domain->flags |= PD_IOMMUV2_MASK; | |
3515 | domain->updated = true; | |
3516 | ||
3517 | update_domain(domain); | |
3518 | ||
3519 | ret = 0; | |
3520 | ||
3521 | out: | |
3522 | spin_unlock_irqrestore(&domain->lock, flags); | |
3523 | ||
3524 | return ret; | |
3525 | } | |
3526 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3527 | |
3528 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3529 | u64 address, bool size) | |
3530 | { | |
3531 | struct iommu_dev_data *dev_data; | |
3532 | struct iommu_cmd cmd; | |
3533 | int i, ret; | |
3534 | ||
3535 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3536 | return -EINVAL; | |
3537 | ||
3538 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3539 | ||
3540 | /* | |
3541 | * IOMMU TLB needs to be flushed before Device TLB to | |
3542 | * prevent device TLB refill from IOMMU TLB | |
3543 | */ | |
3544 | for (i = 0; i < amd_iommus_present; ++i) { | |
3545 | if (domain->dev_iommu[i] == 0) | |
3546 | continue; | |
3547 | ||
3548 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3549 | if (ret != 0) | |
3550 | goto out; | |
3551 | } | |
3552 | ||
3553 | /* Wait until IOMMU TLB flushes are complete */ | |
3554 | domain_flush_complete(domain); | |
3555 | ||
3556 | /* Now flush device TLBs */ | |
3557 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3558 | struct amd_iommu *iommu; | |
3559 | int qdep; | |
3560 | ||
3561 | BUG_ON(!dev_data->ats.enabled); | |
3562 | ||
3563 | qdep = dev_data->ats.qdep; | |
3564 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3565 | ||
3566 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3567 | qdep, address, size); | |
3568 | ||
3569 | ret = iommu_queue_command(iommu, &cmd); | |
3570 | if (ret != 0) | |
3571 | goto out; | |
3572 | } | |
3573 | ||
3574 | /* Wait until all device TLBs are flushed */ | |
3575 | domain_flush_complete(domain); | |
3576 | ||
3577 | ret = 0; | |
3578 | ||
3579 | out: | |
3580 | ||
3581 | return ret; | |
3582 | } | |
3583 | ||
3584 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3585 | u64 address) | |
3586 | { | |
399be2f5 JR |
3587 | INC_STATS_COUNTER(invalidate_iotlb); |
3588 | ||
22e266c7 JR |
3589 | return __flush_pasid(domain, pasid, address, false); |
3590 | } | |
3591 | ||
3592 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3593 | u64 address) | |
3594 | { | |
3595 | struct protection_domain *domain = dom->priv; | |
3596 | unsigned long flags; | |
3597 | int ret; | |
3598 | ||
3599 | spin_lock_irqsave(&domain->lock, flags); | |
3600 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3601 | spin_unlock_irqrestore(&domain->lock, flags); | |
3602 | ||
3603 | return ret; | |
3604 | } | |
3605 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3606 | ||
3607 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3608 | { | |
399be2f5 JR |
3609 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3610 | ||
22e266c7 JR |
3611 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3612 | true); | |
3613 | } | |
3614 | ||
3615 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3616 | { | |
3617 | struct protection_domain *domain = dom->priv; | |
3618 | unsigned long flags; | |
3619 | int ret; | |
3620 | ||
3621 | spin_lock_irqsave(&domain->lock, flags); | |
3622 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3623 | spin_unlock_irqrestore(&domain->lock, flags); | |
3624 | ||
3625 | return ret; | |
3626 | } | |
3627 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3628 | ||
b16137b1 JR |
3629 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3630 | { | |
3631 | int index; | |
3632 | u64 *pte; | |
3633 | ||
3634 | while (true) { | |
3635 | ||
3636 | index = (pasid >> (9 * level)) & 0x1ff; | |
3637 | pte = &root[index]; | |
3638 | ||
3639 | if (level == 0) | |
3640 | break; | |
3641 | ||
3642 | if (!(*pte & GCR3_VALID)) { | |
3643 | if (!alloc) | |
3644 | return NULL; | |
3645 | ||
3646 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3647 | if (root == NULL) | |
3648 | return NULL; | |
3649 | ||
3650 | *pte = __pa(root) | GCR3_VALID; | |
3651 | } | |
3652 | ||
3653 | root = __va(*pte & PAGE_MASK); | |
3654 | ||
3655 | level -= 1; | |
3656 | } | |
3657 | ||
3658 | return pte; | |
3659 | } | |
3660 | ||
3661 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3662 | unsigned long cr3) | |
3663 | { | |
3664 | u64 *pte; | |
3665 | ||
3666 | if (domain->mode != PAGE_MODE_NONE) | |
3667 | return -EINVAL; | |
3668 | ||
3669 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3670 | if (pte == NULL) | |
3671 | return -ENOMEM; | |
3672 | ||
3673 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3674 | ||
3675 | return __amd_iommu_flush_tlb(domain, pasid); | |
3676 | } | |
3677 | ||
3678 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3679 | { | |
3680 | u64 *pte; | |
3681 | ||
3682 | if (domain->mode != PAGE_MODE_NONE) | |
3683 | return -EINVAL; | |
3684 | ||
3685 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3686 | if (pte == NULL) | |
3687 | return 0; | |
3688 | ||
3689 | *pte = 0; | |
3690 | ||
3691 | return __amd_iommu_flush_tlb(domain, pasid); | |
3692 | } | |
3693 | ||
3694 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3695 | unsigned long cr3) | |
3696 | { | |
3697 | struct protection_domain *domain = dom->priv; | |
3698 | unsigned long flags; | |
3699 | int ret; | |
3700 | ||
3701 | spin_lock_irqsave(&domain->lock, flags); | |
3702 | ret = __set_gcr3(domain, pasid, cr3); | |
3703 | spin_unlock_irqrestore(&domain->lock, flags); | |
3704 | ||
3705 | return ret; | |
3706 | } | |
3707 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3708 | ||
3709 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3710 | { | |
3711 | struct protection_domain *domain = dom->priv; | |
3712 | unsigned long flags; | |
3713 | int ret; | |
3714 | ||
3715 | spin_lock_irqsave(&domain->lock, flags); | |
3716 | ret = __clear_gcr3(domain, pasid); | |
3717 | spin_unlock_irqrestore(&domain->lock, flags); | |
3718 | ||
3719 | return ret; | |
3720 | } | |
3721 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3722 | |
3723 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3724 | int status, int tag) | |
3725 | { | |
3726 | struct iommu_dev_data *dev_data; | |
3727 | struct amd_iommu *iommu; | |
3728 | struct iommu_cmd cmd; | |
3729 | ||
399be2f5 JR |
3730 | INC_STATS_COUNTER(complete_ppr); |
3731 | ||
c99afa25 JR |
3732 | dev_data = get_dev_data(&pdev->dev); |
3733 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3734 | ||
3735 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3736 | tag, dev_data->pri_tlp); | |
3737 | ||
3738 | return iommu_queue_command(iommu, &cmd); | |
3739 | } | |
3740 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3741 | |
3742 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3743 | { | |
3744 | struct protection_domain *domain; | |
3745 | ||
3746 | domain = get_domain(&pdev->dev); | |
3747 | if (IS_ERR(domain)) | |
3748 | return NULL; | |
3749 | ||
3750 | /* Only return IOMMUv2 domains */ | |
3751 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3752 | return NULL; | |
3753 | ||
3754 | return domain->iommu_domain; | |
3755 | } | |
3756 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3757 | |
3758 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3759 | { | |
3760 | struct iommu_dev_data *dev_data; | |
3761 | ||
3762 | if (!amd_iommu_v2_supported()) | |
3763 | return; | |
3764 | ||
3765 | dev_data = get_dev_data(&pdev->dev); | |
3766 | dev_data->errata |= (1 << erratum); | |
3767 | } | |
3768 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3769 | |
3770 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3771 | struct amd_iommu_device_info *info) | |
3772 | { | |
3773 | int max_pasids; | |
3774 | int pos; | |
3775 | ||
3776 | if (pdev == NULL || info == NULL) | |
3777 | return -EINVAL; | |
3778 | ||
3779 | if (!amd_iommu_v2_supported()) | |
3780 | return -EINVAL; | |
3781 | ||
3782 | memset(info, 0, sizeof(*info)); | |
3783 | ||
3784 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3785 | if (pos) | |
3786 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3787 | ||
3788 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3789 | if (pos) | |
3790 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3791 | ||
3792 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3793 | if (pos) { | |
3794 | int features; | |
3795 | ||
3796 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3797 | max_pasids = min(max_pasids, (1 << 20)); | |
3798 | ||
3799 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3800 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3801 | ||
3802 | features = pci_pasid_features(pdev); | |
3803 | if (features & PCI_PASID_CAP_EXEC) | |
3804 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3805 | if (features & PCI_PASID_CAP_PRIV) | |
3806 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3807 | } | |
3808 | ||
3809 | return 0; | |
3810 | } | |
3811 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3812 | |
3813 | #ifdef CONFIG_IRQ_REMAP | |
3814 | ||
3815 | /***************************************************************************** | |
3816 | * | |
3817 | * Interrupt Remapping Implementation | |
3818 | * | |
3819 | *****************************************************************************/ | |
3820 | ||
3821 | union irte { | |
3822 | u32 val; | |
3823 | struct { | |
3824 | u32 valid : 1, | |
3825 | no_fault : 1, | |
3826 | int_type : 3, | |
3827 | rq_eoi : 1, | |
3828 | dm : 1, | |
3829 | rsvd_1 : 1, | |
3830 | destination : 8, | |
3831 | vector : 8, | |
3832 | rsvd_2 : 8; | |
3833 | } fields; | |
3834 | }; | |
3835 | ||
3836 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3837 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3838 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3839 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3840 | ||
3841 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3842 | { | |
3843 | u64 dte; | |
3844 | ||
3845 | dte = amd_iommu_dev_table[devid].data[2]; | |
3846 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3847 | dte |= virt_to_phys(table->table); | |
3848 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3849 | dte |= DTE_IRQ_TABLE_LEN; | |
3850 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3851 | ||
3852 | amd_iommu_dev_table[devid].data[2] = dte; | |
3853 | } | |
3854 | ||
3855 | #define IRTE_ALLOCATED (~1U) | |
3856 | ||
3857 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3858 | { | |
3859 | struct irq_remap_table *table = NULL; | |
3860 | struct amd_iommu *iommu; | |
3861 | unsigned long flags; | |
3862 | u16 alias; | |
3863 | ||
3864 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3865 | ||
3866 | iommu = amd_iommu_rlookup_table[devid]; | |
3867 | if (!iommu) | |
3868 | goto out_unlock; | |
3869 | ||
3870 | table = irq_lookup_table[devid]; | |
3871 | if (table) | |
3872 | goto out; | |
3873 | ||
3874 | alias = amd_iommu_alias_table[devid]; | |
3875 | table = irq_lookup_table[alias]; | |
3876 | if (table) { | |
3877 | irq_lookup_table[devid] = table; | |
3878 | set_dte_irq_entry(devid, table); | |
3879 | iommu_flush_dte(iommu, devid); | |
3880 | goto out; | |
3881 | } | |
3882 | ||
3883 | /* Nothing there yet, allocate new irq remapping table */ | |
3884 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3885 | if (!table) | |
3886 | goto out; | |
3887 | ||
197887f0 JR |
3888 | /* Initialize table spin-lock */ |
3889 | spin_lock_init(&table->lock); | |
3890 | ||
2b324506 JR |
3891 | if (ioapic) |
3892 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3893 | table->min_index = 32; | |
3894 | ||
3895 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3896 | if (!table->table) { | |
3897 | kfree(table); | |
821f0f68 | 3898 | table = NULL; |
2b324506 JR |
3899 | goto out; |
3900 | } | |
3901 | ||
3902 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3903 | ||
3904 | if (ioapic) { | |
3905 | int i; | |
3906 | ||
3907 | for (i = 0; i < 32; ++i) | |
3908 | table->table[i] = IRTE_ALLOCATED; | |
3909 | } | |
3910 | ||
3911 | irq_lookup_table[devid] = table; | |
3912 | set_dte_irq_entry(devid, table); | |
3913 | iommu_flush_dte(iommu, devid); | |
3914 | if (devid != alias) { | |
3915 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3916 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3917 | iommu_flush_dte(iommu, alias); |
3918 | } | |
3919 | ||
3920 | out: | |
3921 | iommu_completion_wait(iommu); | |
3922 | ||
3923 | out_unlock: | |
3924 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3925 | ||
3926 | return table; | |
3927 | } | |
3928 | ||
3929 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3930 | { | |
3931 | struct irq_remap_table *table; | |
3932 | unsigned long flags; | |
3933 | int index, c; | |
3934 | ||
3935 | table = get_irq_table(devid, false); | |
3936 | if (!table) | |
3937 | return -ENODEV; | |
3938 | ||
3939 | spin_lock_irqsave(&table->lock, flags); | |
3940 | ||
3941 | /* Scan table for free entries */ | |
3942 | for (c = 0, index = table->min_index; | |
3943 | index < MAX_IRQS_PER_TABLE; | |
3944 | ++index) { | |
3945 | if (table->table[index] == 0) | |
3946 | c += 1; | |
3947 | else | |
3948 | c = 0; | |
3949 | ||
3950 | if (c == count) { | |
0dfedd61 | 3951 | struct irq_2_irte *irte_info; |
2b324506 JR |
3952 | |
3953 | for (; c != 0; --c) | |
3954 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3955 | ||
3956 | index -= count - 1; | |
3957 | ||
9b1b0e42 | 3958 | cfg->remapped = 1; |
0dfedd61 JR |
3959 | irte_info = &cfg->irq_2_irte; |
3960 | irte_info->devid = devid; | |
3961 | irte_info->index = index; | |
2b324506 JR |
3962 | |
3963 | goto out; | |
3964 | } | |
3965 | } | |
3966 | ||
3967 | index = -ENOSPC; | |
3968 | ||
3969 | out: | |
3970 | spin_unlock_irqrestore(&table->lock, flags); | |
3971 | ||
3972 | return index; | |
3973 | } | |
3974 | ||
3975 | static int get_irte(u16 devid, int index, union irte *irte) | |
3976 | { | |
3977 | struct irq_remap_table *table; | |
3978 | unsigned long flags; | |
3979 | ||
3980 | table = get_irq_table(devid, false); | |
3981 | if (!table) | |
3982 | return -ENOMEM; | |
3983 | ||
3984 | spin_lock_irqsave(&table->lock, flags); | |
3985 | irte->val = table->table[index]; | |
3986 | spin_unlock_irqrestore(&table->lock, flags); | |
3987 | ||
3988 | return 0; | |
3989 | } | |
3990 | ||
3991 | static int modify_irte(u16 devid, int index, union irte irte) | |
3992 | { | |
3993 | struct irq_remap_table *table; | |
3994 | struct amd_iommu *iommu; | |
3995 | unsigned long flags; | |
3996 | ||
3997 | iommu = amd_iommu_rlookup_table[devid]; | |
3998 | if (iommu == NULL) | |
3999 | return -EINVAL; | |
4000 | ||
4001 | table = get_irq_table(devid, false); | |
4002 | if (!table) | |
4003 | return -ENOMEM; | |
4004 | ||
4005 | spin_lock_irqsave(&table->lock, flags); | |
4006 | table->table[index] = irte.val; | |
4007 | spin_unlock_irqrestore(&table->lock, flags); | |
4008 | ||
4009 | iommu_flush_irt(iommu, devid); | |
4010 | iommu_completion_wait(iommu); | |
4011 | ||
4012 | return 0; | |
4013 | } | |
4014 | ||
4015 | static void free_irte(u16 devid, int index) | |
4016 | { | |
4017 | struct irq_remap_table *table; | |
4018 | struct amd_iommu *iommu; | |
4019 | unsigned long flags; | |
4020 | ||
4021 | iommu = amd_iommu_rlookup_table[devid]; | |
4022 | if (iommu == NULL) | |
4023 | return; | |
4024 | ||
4025 | table = get_irq_table(devid, false); | |
4026 | if (!table) | |
4027 | return; | |
4028 | ||
4029 | spin_lock_irqsave(&table->lock, flags); | |
4030 | table->table[index] = 0; | |
4031 | spin_unlock_irqrestore(&table->lock, flags); | |
4032 | ||
4033 | iommu_flush_irt(iommu, devid); | |
4034 | iommu_completion_wait(iommu); | |
4035 | } | |
4036 | ||
5527de74 JR |
4037 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4038 | unsigned int destination, int vector, | |
4039 | struct io_apic_irq_attr *attr) | |
4040 | { | |
4041 | struct irq_remap_table *table; | |
0dfedd61 | 4042 | struct irq_2_irte *irte_info; |
5527de74 JR |
4043 | struct irq_cfg *cfg; |
4044 | union irte irte; | |
4045 | int ioapic_id; | |
4046 | int index; | |
4047 | int devid; | |
4048 | int ret; | |
4049 | ||
4050 | cfg = irq_get_chip_data(irq); | |
4051 | if (!cfg) | |
4052 | return -EINVAL; | |
4053 | ||
0dfedd61 | 4054 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4055 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4056 | devid = get_ioapic_devid(ioapic_id); | |
4057 | ||
4058 | if (devid < 0) | |
4059 | return devid; | |
4060 | ||
4061 | table = get_irq_table(devid, true); | |
4062 | if (table == NULL) | |
4063 | return -ENOMEM; | |
4064 | ||
4065 | index = attr->ioapic_pin; | |
4066 | ||
4067 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4068 | cfg->remapped = 1; |
0dfedd61 JR |
4069 | irte_info->devid = devid; |
4070 | irte_info->index = index; | |
5527de74 JR |
4071 | |
4072 | /* Setup IRTE for IOMMU */ | |
4073 | irte.val = 0; | |
4074 | irte.fields.vector = vector; | |
4075 | irte.fields.int_type = apic->irq_delivery_mode; | |
4076 | irte.fields.destination = destination; | |
4077 | irte.fields.dm = apic->irq_dest_mode; | |
4078 | irte.fields.valid = 1; | |
4079 | ||
4080 | ret = modify_irte(devid, index, irte); | |
4081 | if (ret) | |
4082 | return ret; | |
4083 | ||
4084 | /* Setup IOAPIC entry */ | |
4085 | memset(entry, 0, sizeof(*entry)); | |
4086 | ||
4087 | entry->vector = index; | |
4088 | entry->mask = 0; | |
4089 | entry->trigger = attr->trigger; | |
4090 | entry->polarity = attr->polarity; | |
4091 | ||
4092 | /* | |
4093 | * Mask level triggered irqs. | |
5527de74 JR |
4094 | */ |
4095 | if (attr->trigger) | |
4096 | entry->mask = 1; | |
4097 | ||
4098 | return 0; | |
4099 | } | |
4100 | ||
4101 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4102 | bool force) | |
4103 | { | |
0dfedd61 | 4104 | struct irq_2_irte *irte_info; |
5527de74 JR |
4105 | unsigned int dest, irq; |
4106 | struct irq_cfg *cfg; | |
4107 | union irte irte; | |
4108 | int err; | |
4109 | ||
4110 | if (!config_enabled(CONFIG_SMP)) | |
4111 | return -1; | |
4112 | ||
4113 | cfg = data->chip_data; | |
4114 | irq = data->irq; | |
0dfedd61 | 4115 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4116 | |
4117 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4118 | return -EINVAL; | |
4119 | ||
0dfedd61 | 4120 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4121 | return -EBUSY; |
4122 | ||
4123 | if (assign_irq_vector(irq, cfg, mask)) | |
4124 | return -EBUSY; | |
4125 | ||
4126 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4127 | if (err) { | |
4128 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4129 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4130 | return err; | |
4131 | } | |
4132 | ||
4133 | irte.fields.vector = cfg->vector; | |
4134 | irte.fields.destination = dest; | |
4135 | ||
0dfedd61 | 4136 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4137 | |
4138 | if (cfg->move_in_progress) | |
4139 | send_cleanup_vector(cfg); | |
4140 | ||
4141 | cpumask_copy(data->affinity, mask); | |
4142 | ||
4143 | return 0; | |
4144 | } | |
4145 | ||
4146 | static int free_irq(int irq) | |
4147 | { | |
0dfedd61 | 4148 | struct irq_2_irte *irte_info; |
5527de74 JR |
4149 | struct irq_cfg *cfg; |
4150 | ||
4151 | cfg = irq_get_chip_data(irq); | |
4152 | if (!cfg) | |
4153 | return -EINVAL; | |
4154 | ||
0dfedd61 | 4155 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4156 | |
0dfedd61 | 4157 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4158 | |
4159 | return 0; | |
4160 | } | |
4161 | ||
0b4d48cb JR |
4162 | static void compose_msi_msg(struct pci_dev *pdev, |
4163 | unsigned int irq, unsigned int dest, | |
4164 | struct msi_msg *msg, u8 hpet_id) | |
4165 | { | |
0dfedd61 | 4166 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4167 | struct irq_cfg *cfg; |
4168 | union irte irte; | |
4169 | ||
4170 | cfg = irq_get_chip_data(irq); | |
4171 | if (!cfg) | |
4172 | return; | |
4173 | ||
0dfedd61 | 4174 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4175 | |
4176 | irte.val = 0; | |
4177 | irte.fields.vector = cfg->vector; | |
4178 | irte.fields.int_type = apic->irq_delivery_mode; | |
4179 | irte.fields.destination = dest; | |
4180 | irte.fields.dm = apic->irq_dest_mode; | |
4181 | irte.fields.valid = 1; | |
4182 | ||
0dfedd61 | 4183 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4184 | |
4185 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4186 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4187 | msg->data = irte_info->index; |
0b4d48cb JR |
4188 | } |
4189 | ||
4190 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4191 | { | |
4192 | struct irq_cfg *cfg; | |
4193 | int index; | |
4194 | u16 devid; | |
4195 | ||
4196 | if (!pdev) | |
4197 | return -EINVAL; | |
4198 | ||
4199 | cfg = irq_get_chip_data(irq); | |
4200 | if (!cfg) | |
4201 | return -EINVAL; | |
4202 | ||
4203 | devid = get_device_id(&pdev->dev); | |
4204 | index = alloc_irq_index(cfg, devid, nvec); | |
4205 | ||
4206 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4207 | } | |
4208 | ||
4209 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4210 | int index, int offset) | |
4211 | { | |
0dfedd61 | 4212 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4213 | struct irq_cfg *cfg; |
4214 | u16 devid; | |
4215 | ||
4216 | if (!pdev) | |
4217 | return -EINVAL; | |
4218 | ||
4219 | cfg = irq_get_chip_data(irq); | |
4220 | if (!cfg) | |
4221 | return -EINVAL; | |
4222 | ||
4223 | if (index >= MAX_IRQS_PER_TABLE) | |
4224 | return 0; | |
4225 | ||
4226 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4227 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4228 | |
9b1b0e42 | 4229 | cfg->remapped = 1; |
0dfedd61 JR |
4230 | irte_info->devid = devid; |
4231 | irte_info->index = index + offset; | |
0b4d48cb JR |
4232 | |
4233 | return 0; | |
4234 | } | |
4235 | ||
d976195c JR |
4236 | static int setup_hpet_msi(unsigned int irq, unsigned int id) |
4237 | { | |
0dfedd61 | 4238 | struct irq_2_irte *irte_info; |
d976195c JR |
4239 | struct irq_cfg *cfg; |
4240 | int index, devid; | |
4241 | ||
4242 | cfg = irq_get_chip_data(irq); | |
4243 | if (!cfg) | |
4244 | return -EINVAL; | |
4245 | ||
0dfedd61 | 4246 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4247 | devid = get_hpet_devid(id); |
4248 | if (devid < 0) | |
4249 | return devid; | |
4250 | ||
4251 | index = alloc_irq_index(cfg, devid, 1); | |
4252 | if (index < 0) | |
4253 | return index; | |
4254 | ||
9b1b0e42 | 4255 | cfg->remapped = 1; |
0dfedd61 JR |
4256 | irte_info->devid = devid; |
4257 | irte_info->index = index; | |
d976195c JR |
4258 | |
4259 | return 0; | |
4260 | } | |
4261 | ||
6b474b82 JR |
4262 | struct irq_remap_ops amd_iommu_irq_ops = { |
4263 | .supported = amd_iommu_supported, | |
4264 | .prepare = amd_iommu_prepare, | |
4265 | .enable = amd_iommu_enable, | |
4266 | .disable = amd_iommu_disable, | |
4267 | .reenable = amd_iommu_reenable, | |
4268 | .enable_faulting = amd_iommu_enable_faulting, | |
4269 | .setup_ioapic_entry = setup_ioapic_entry, | |
4270 | .set_affinity = set_affinity, | |
4271 | .free_irq = free_irq, | |
4272 | .compose_msi_msg = compose_msi_msg, | |
4273 | .msi_alloc_irq = msi_alloc_irq, | |
4274 | .msi_setup_irq = msi_setup_irq, | |
4275 | .setup_hpet_msi = setup_hpet_msi, | |
4276 | }; | |
2b324506 | 4277 | #endif |