Commit | Line | Data |
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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
400a28a0 | 28 | #include <linux/export.h> |
f6e2e6b6 | 29 | #include <asm/pci-direct.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
ea1b0d39 | 32 | #include <asm/x86_init.h> |
22e6daf4 | 33 | #include <asm/iommu_table.h> |
403f81d8 JR |
34 | |
35 | #include "amd_iommu_proto.h" | |
36 | #include "amd_iommu_types.h" | |
37 | ||
f6e2e6b6 JR |
38 | /* |
39 | * definitions for the ACPI scanning code | |
40 | */ | |
f6e2e6b6 | 41 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
42 | |
43 | #define ACPI_IVHD_TYPE 0x10 | |
44 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
45 | #define ACPI_IVMD_TYPE 0x21 | |
46 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
47 | ||
48 | #define IVHD_DEV_ALL 0x01 | |
49 | #define IVHD_DEV_SELECT 0x02 | |
50 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
51 | #define IVHD_DEV_RANGE_END 0x04 | |
52 | #define IVHD_DEV_ALIAS 0x42 | |
53 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
54 | #define IVHD_DEV_EXT_SELECT 0x46 | |
55 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
56 | ||
6da7342f JR |
57 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
58 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
59 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
60 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
61 | |
62 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
63 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
64 | ||
65 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
66 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
67 | #define ACPI_DEVFLAG_NMI 0x04 | |
68 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
69 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
70 | #define ACPI_DEVFLAG_LINT0 0x40 | |
71 | #define ACPI_DEVFLAG_LINT1 0x80 | |
72 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
73 | ||
b65233a9 JR |
74 | /* |
75 | * ACPI table definitions | |
76 | * | |
77 | * These data structures are laid over the table to parse the important values | |
78 | * out of it. | |
79 | */ | |
80 | ||
81 | /* | |
82 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
83 | * or more ivhd_entrys. | |
84 | */ | |
f6e2e6b6 JR |
85 | struct ivhd_header { |
86 | u8 type; | |
87 | u8 flags; | |
88 | u16 length; | |
89 | u16 devid; | |
90 | u16 cap_ptr; | |
91 | u64 mmio_phys; | |
92 | u16 pci_seg; | |
93 | u16 info; | |
94 | u32 reserved; | |
95 | } __attribute__((packed)); | |
96 | ||
b65233a9 JR |
97 | /* |
98 | * A device entry describing which devices a specific IOMMU translates and | |
99 | * which requestor ids they use. | |
100 | */ | |
f6e2e6b6 JR |
101 | struct ivhd_entry { |
102 | u8 type; | |
103 | u16 devid; | |
104 | u8 flags; | |
105 | u32 ext; | |
106 | } __attribute__((packed)); | |
107 | ||
b65233a9 JR |
108 | /* |
109 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
110 | * ranges for devices and regions that should be unity mapped. | |
111 | */ | |
f6e2e6b6 JR |
112 | struct ivmd_header { |
113 | u8 type; | |
114 | u8 flags; | |
115 | u16 length; | |
116 | u16 devid; | |
117 | u16 aux; | |
118 | u64 resv; | |
119 | u64 range_start; | |
120 | u64 range_length; | |
121 | } __attribute__((packed)); | |
122 | ||
fefda117 JR |
123 | bool amd_iommu_dump; |
124 | ||
c1cbebee | 125 | static int __initdata amd_iommu_detected; |
a5235725 | 126 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 127 | |
b65233a9 JR |
128 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
129 | to handle */ | |
2e22847f | 130 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 131 | we find in ACPI */ |
afa9fdc2 | 132 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 133 | |
2e22847f | 134 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 135 | system */ |
928abd25 | 136 | |
bb52777e JR |
137 | /* Array to assign indices to IOMMUs*/ |
138 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
139 | int amd_iommus_present; | |
140 | ||
318afd41 JR |
141 | /* IOMMUs have a non-present cache? */ |
142 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 143 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 144 | |
62f71abb JR |
145 | u32 amd_iommu_max_pasids __read_mostly = ~0; |
146 | ||
400a28a0 JR |
147 | bool amd_iommu_v2_present __read_mostly; |
148 | ||
5abcdba4 JR |
149 | bool amd_iommu_force_isolation __read_mostly; |
150 | ||
0f764806 | 151 | /* |
3551a708 | 152 | * The ACPI table parsing functions set this variable on an error |
0f764806 | 153 | */ |
3551a708 | 154 | static int __initdata amd_iommu_init_err; |
0f764806 | 155 | |
aeb26f55 JR |
156 | /* |
157 | * List of protection domains - used during resume | |
158 | */ | |
159 | LIST_HEAD(amd_iommu_pd_list); | |
160 | spinlock_t amd_iommu_pd_lock; | |
161 | ||
b65233a9 JR |
162 | /* |
163 | * Pointer to the device table which is shared by all AMD IOMMUs | |
164 | * it is indexed by the PCI device id or the HT unit id and contains | |
165 | * information about the domain the device belongs to as well as the | |
166 | * page table root pointer. | |
167 | */ | |
928abd25 | 168 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
169 | |
170 | /* | |
171 | * The alias table is a driver specific data structure which contains the | |
172 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
173 | * More than one device can share the same requestor id. | |
174 | */ | |
928abd25 | 175 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
176 | |
177 | /* | |
178 | * The rlookup table is used to find the IOMMU which is responsible | |
179 | * for a specific device. It is also indexed by the PCI device id. | |
180 | */ | |
928abd25 | 181 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 182 | |
b65233a9 JR |
183 | /* |
184 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
185 | * to know which ones are already in use. | |
186 | */ | |
928abd25 JR |
187 | unsigned long *amd_iommu_pd_alloc_bitmap; |
188 | ||
b65233a9 JR |
189 | static u32 dev_table_size; /* size of the device table */ |
190 | static u32 alias_table_size; /* size of the alias table */ | |
191 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 192 | |
7d0c5cc5 JR |
193 | /* |
194 | * This function flushes all internal caches of | |
195 | * the IOMMU used by this driver. | |
196 | */ | |
197 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
198 | ||
ae295142 | 199 | static int amd_iommu_enable_interrupts(void); |
3d9761e7 | 200 | |
208ec8c9 JR |
201 | static inline void update_last_devid(u16 devid) |
202 | { | |
203 | if (devid > amd_iommu_last_bdf) | |
204 | amd_iommu_last_bdf = devid; | |
205 | } | |
206 | ||
c571484e JR |
207 | static inline unsigned long tbl_size(int entry_size) |
208 | { | |
209 | unsigned shift = PAGE_SHIFT + | |
421f909c | 210 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
211 | |
212 | return 1UL << shift; | |
213 | } | |
214 | ||
5bcd757f MG |
215 | /* Access to l1 and l2 indexed register spaces */ |
216 | ||
217 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
218 | { | |
219 | u32 val; | |
220 | ||
221 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
222 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
223 | return val; | |
224 | } | |
225 | ||
226 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
227 | { | |
228 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
229 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
230 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
231 | } | |
232 | ||
233 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
234 | { | |
235 | u32 val; | |
236 | ||
237 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
238 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
239 | return val; | |
240 | } | |
241 | ||
242 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
243 | { | |
244 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
245 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
246 | } | |
247 | ||
b65233a9 JR |
248 | /**************************************************************************** |
249 | * | |
250 | * AMD IOMMU MMIO register space handling functions | |
251 | * | |
252 | * These functions are used to program the IOMMU device registers in | |
253 | * MMIO space required for that driver. | |
254 | * | |
255 | ****************************************************************************/ | |
3e8064ba | 256 | |
b65233a9 JR |
257 | /* |
258 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
259 | * exclusion range are passed through untranslated | |
260 | */ | |
05f92db9 | 261 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
262 | { |
263 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
264 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
265 | u64 entry; | |
266 | ||
267 | if (!iommu->exclusion_start) | |
268 | return; | |
269 | ||
270 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
271 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
272 | &entry, sizeof(entry)); | |
273 | ||
274 | entry = limit; | |
275 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
276 | &entry, sizeof(entry)); | |
277 | } | |
278 | ||
b65233a9 | 279 | /* Programs the physical address of the device table into the IOMMU hardware */ |
6b7f000e | 280 | static void iommu_set_device_table(struct amd_iommu *iommu) |
b2026aa2 | 281 | { |
f609891f | 282 | u64 entry; |
b2026aa2 JR |
283 | |
284 | BUG_ON(iommu->mmio_base == NULL); | |
285 | ||
286 | entry = virt_to_phys(amd_iommu_dev_table); | |
287 | entry |= (dev_table_size >> 12) - 1; | |
288 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
289 | &entry, sizeof(entry)); | |
290 | } | |
291 | ||
b65233a9 | 292 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 293 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
294 | { |
295 | u32 ctrl; | |
296 | ||
297 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
298 | ctrl |= (1 << bit); | |
299 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
300 | } | |
301 | ||
ca020711 | 302 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
303 | { |
304 | u32 ctrl; | |
305 | ||
199d0d50 | 306 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
307 | ctrl &= ~(1 << bit); |
308 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
309 | } | |
310 | ||
1456e9d2 JR |
311 | static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) |
312 | { | |
313 | u32 ctrl; | |
314 | ||
315 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
316 | ctrl &= ~CTRL_INV_TO_MASK; | |
317 | ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; | |
318 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
319 | } | |
320 | ||
b65233a9 | 321 | /* Function to enable the hardware */ |
05f92db9 | 322 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 323 | { |
d99ddec3 JR |
324 | static const char * const feat_str[] = { |
325 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
326 | "IA", "GA", "HE", "PC", NULL | |
327 | }; | |
328 | int i; | |
329 | ||
330 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx", | |
a4e267c8 | 331 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 | 332 | |
d99ddec3 JR |
333 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { |
334 | printk(KERN_CONT " extended features: "); | |
335 | for (i = 0; feat_str[i]; ++i) | |
336 | if (iommu_feature(iommu, (1ULL << i))) | |
337 | printk(KERN_CONT " %s", feat_str[i]); | |
338 | } | |
339 | printk(KERN_CONT "\n"); | |
340 | ||
b2026aa2 | 341 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
342 | } |
343 | ||
92ac4320 | 344 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 345 | { |
a8c485bb CW |
346 | /* Disable command buffer */ |
347 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
348 | ||
349 | /* Disable event logging and event interrupts */ | |
350 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
351 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
352 | ||
353 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 354 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
355 | } |
356 | ||
b65233a9 JR |
357 | /* |
358 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
359 | * the system has one. | |
360 | */ | |
6c56747b JR |
361 | static u8 * __init iommu_map_mmio_space(u64 address) |
362 | { | |
e82752d8 JR |
363 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
364 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
365 | address); | |
366 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 367 | return NULL; |
e82752d8 | 368 | } |
6c56747b | 369 | |
6e930045 | 370 | return ioremap_nocache(address, MMIO_REGION_LENGTH); |
6c56747b JR |
371 | } |
372 | ||
373 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
374 | { | |
375 | if (iommu->mmio_base) | |
376 | iounmap(iommu->mmio_base); | |
377 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
378 | } | |
379 | ||
b65233a9 JR |
380 | /**************************************************************************** |
381 | * | |
382 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
383 | * parsing. In this pass we try to find out the highest device id this | |
384 | * code has to handle. Upon this information the size of the shared data | |
385 | * structures is determined later. | |
386 | * | |
387 | ****************************************************************************/ | |
388 | ||
b514e555 JR |
389 | /* |
390 | * This function calculates the length of a given IVHD entry | |
391 | */ | |
392 | static inline int ivhd_entry_length(u8 *ivhd) | |
393 | { | |
394 | return 0x04 << (*ivhd >> 6); | |
395 | } | |
396 | ||
b65233a9 JR |
397 | /* |
398 | * This function reads the last device id the IOMMU has to handle from the PCI | |
399 | * capability header for this IOMMU | |
400 | */ | |
3e8064ba JR |
401 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
402 | { | |
403 | u32 cap; | |
404 | ||
405 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 406 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
b65233a9 JR |
411 | /* |
412 | * After reading the highest device id from the IOMMU PCI capability header | |
413 | * this function looks if there is a higher device id defined in the ACPI table | |
414 | */ | |
3e8064ba JR |
415 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
416 | { | |
417 | u8 *p = (void *)h, *end = (void *)h; | |
418 | struct ivhd_entry *dev; | |
419 | ||
420 | p += sizeof(*h); | |
421 | end += h->length; | |
422 | ||
423 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
424 | PCI_SLOT(h->devid), | |
425 | PCI_FUNC(h->devid), | |
426 | h->cap_ptr); | |
427 | ||
428 | while (p < end) { | |
429 | dev = (struct ivhd_entry *)p; | |
430 | switch (dev->type) { | |
431 | case IVHD_DEV_SELECT: | |
432 | case IVHD_DEV_RANGE_END: | |
433 | case IVHD_DEV_ALIAS: | |
434 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 435 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 436 | update_last_devid(dev->devid); |
3e8064ba JR |
437 | break; |
438 | default: | |
439 | break; | |
440 | } | |
b514e555 | 441 | p += ivhd_entry_length(p); |
3e8064ba JR |
442 | } |
443 | ||
444 | WARN_ON(p != end); | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
b65233a9 JR |
449 | /* |
450 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
451 | * id which we need to handle. This is the first of three functions which parse | |
452 | * the ACPI table. So we check the checksum here. | |
453 | */ | |
3e8064ba JR |
454 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
455 | { | |
456 | int i; | |
457 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
458 | struct ivhd_header *h; | |
459 | ||
460 | /* | |
461 | * Validate checksum here so we don't need to do it when | |
462 | * we actually parse the table | |
463 | */ | |
464 | for (i = 0; i < table->length; ++i) | |
465 | checksum += p[i]; | |
3551a708 | 466 | if (checksum != 0) { |
3e8064ba | 467 | /* ACPI table corrupt */ |
3551a708 JR |
468 | amd_iommu_init_err = -ENODEV; |
469 | return 0; | |
470 | } | |
3e8064ba JR |
471 | |
472 | p += IVRS_HEADER_LENGTH; | |
473 | ||
474 | end += table->length; | |
475 | while (p < end) { | |
476 | h = (struct ivhd_header *)p; | |
477 | switch (h->type) { | |
478 | case ACPI_IVHD_TYPE: | |
479 | find_last_devid_from_ivhd(h); | |
480 | break; | |
481 | default: | |
482 | break; | |
483 | } | |
484 | p += h->length; | |
485 | } | |
486 | WARN_ON(p != end); | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
b65233a9 JR |
491 | /**************************************************************************** |
492 | * | |
493 | * The following functions belong the the code path which parses the ACPI table | |
494 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
495 | * data structures, initialize the device/alias/rlookup table and also | |
496 | * basically initialize the hardware. | |
497 | * | |
498 | ****************************************************************************/ | |
499 | ||
500 | /* | |
501 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
502 | * write commands to that buffer later and the IOMMU will execute them | |
503 | * asynchronously | |
504 | */ | |
b36ca91e JR |
505 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
506 | { | |
d0312b21 | 507 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 508 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
509 | |
510 | if (cmd_buf == NULL) | |
511 | return NULL; | |
512 | ||
549c90dc | 513 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 514 | |
58492e12 JR |
515 | return cmd_buf; |
516 | } | |
517 | ||
93f1cc67 JR |
518 | /* |
519 | * This function resets the command buffer if the IOMMU stopped fetching | |
520 | * commands from it. | |
521 | */ | |
522 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
523 | { | |
524 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
525 | ||
526 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
527 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
528 | ||
529 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
530 | } | |
531 | ||
58492e12 JR |
532 | /* |
533 | * This function writes the command buffer address to the hardware and | |
534 | * enables it. | |
535 | */ | |
536 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
537 | { | |
538 | u64 entry; | |
539 | ||
540 | BUG_ON(iommu->cmd_buf == NULL); | |
541 | ||
542 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 543 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 544 | |
b36ca91e | 545 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 546 | &entry, sizeof(entry)); |
b36ca91e | 547 | |
93f1cc67 | 548 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 549 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
550 | } |
551 | ||
552 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
553 | { | |
23c1713f | 554 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 555 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
556 | } |
557 | ||
335503e5 JR |
558 | /* allocates the memory where the IOMMU will log its events to */ |
559 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
560 | { | |
335503e5 JR |
561 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
562 | get_order(EVT_BUFFER_SIZE)); | |
563 | ||
564 | if (iommu->evt_buf == NULL) | |
565 | return NULL; | |
566 | ||
1bc6f838 JR |
567 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
568 | ||
58492e12 JR |
569 | return iommu->evt_buf; |
570 | } | |
571 | ||
572 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
573 | { | |
574 | u64 entry; | |
575 | ||
576 | BUG_ON(iommu->evt_buf == NULL); | |
577 | ||
335503e5 | 578 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 579 | |
335503e5 JR |
580 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
581 | &entry, sizeof(entry)); | |
582 | ||
09067207 JR |
583 | /* set head and tail to zero manually */ |
584 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
585 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
586 | ||
58492e12 | 587 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
588 | } |
589 | ||
590 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
591 | { | |
592 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
593 | } | |
594 | ||
1a29ac01 JR |
595 | /* allocates the memory where the IOMMU will log its events to */ |
596 | static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) | |
597 | { | |
598 | iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
599 | get_order(PPR_LOG_SIZE)); | |
600 | ||
601 | if (iommu->ppr_log == NULL) | |
602 | return NULL; | |
603 | ||
604 | return iommu->ppr_log; | |
605 | } | |
606 | ||
607 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
608 | { | |
609 | u64 entry; | |
610 | ||
611 | if (iommu->ppr_log == NULL) | |
612 | return; | |
613 | ||
614 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
615 | ||
616 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
617 | &entry, sizeof(entry)); | |
618 | ||
619 | /* set head and tail to zero manually */ | |
620 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
621 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
622 | ||
623 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
624 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
625 | } | |
626 | ||
627 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
628 | { | |
629 | if (iommu->ppr_log == NULL) | |
630 | return; | |
631 | ||
632 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
633 | } | |
634 | ||
cbc33a90 JR |
635 | static void iommu_enable_gt(struct amd_iommu *iommu) |
636 | { | |
637 | if (!iommu_feature(iommu, FEATURE_GT)) | |
638 | return; | |
639 | ||
640 | iommu_feature_enable(iommu, CONTROL_GT_EN); | |
641 | } | |
642 | ||
b65233a9 | 643 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
644 | static void set_dev_entry_bit(u16 devid, u8 bit) |
645 | { | |
ee6c2868 JR |
646 | int i = (bit >> 6) & 0x03; |
647 | int _bit = bit & 0x3f; | |
3566b778 | 648 | |
ee6c2868 | 649 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
650 | } |
651 | ||
c5cca146 JR |
652 | static int get_dev_entry_bit(u16 devid, u8 bit) |
653 | { | |
ee6c2868 JR |
654 | int i = (bit >> 6) & 0x03; |
655 | int _bit = bit & 0x3f; | |
c5cca146 | 656 | |
ee6c2868 | 657 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
658 | } |
659 | ||
660 | ||
661 | void amd_iommu_apply_erratum_63(u16 devid) | |
662 | { | |
663 | int sysmgt; | |
664 | ||
665 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
666 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
667 | ||
668 | if (sysmgt == 0x01) | |
669 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
670 | } | |
671 | ||
5ff4789d JR |
672 | /* Writes the specific IOMMU for a device into the rlookup table */ |
673 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
674 | { | |
675 | amd_iommu_rlookup_table[devid] = iommu; | |
676 | } | |
677 | ||
b65233a9 JR |
678 | /* |
679 | * This function takes the device specific flags read from the ACPI | |
680 | * table and sets up the device table entry with that information | |
681 | */ | |
5ff4789d JR |
682 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
683 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
684 | { |
685 | if (flags & ACPI_DEVFLAG_INITPASS) | |
686 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
687 | if (flags & ACPI_DEVFLAG_EXTINT) | |
688 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
689 | if (flags & ACPI_DEVFLAG_NMI) | |
690 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
691 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
692 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
693 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
694 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
695 | if (flags & ACPI_DEVFLAG_LINT0) | |
696 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
697 | if (flags & ACPI_DEVFLAG_LINT1) | |
698 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 699 | |
c5cca146 JR |
700 | amd_iommu_apply_erratum_63(devid); |
701 | ||
5ff4789d | 702 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
703 | } |
704 | ||
b65233a9 JR |
705 | /* |
706 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
707 | * it | |
708 | */ | |
3566b778 JR |
709 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
710 | { | |
711 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
712 | ||
713 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
714 | return; | |
715 | ||
716 | if (iommu) { | |
b65233a9 JR |
717 | /* |
718 | * We only can configure exclusion ranges per IOMMU, not | |
719 | * per device. But we can enable the exclusion range per | |
720 | * device. This is done here | |
721 | */ | |
3566b778 JR |
722 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
723 | iommu->exclusion_start = m->range_start; | |
724 | iommu->exclusion_length = m->range_length; | |
725 | } | |
726 | } | |
727 | ||
b65233a9 JR |
728 | /* |
729 | * This function reads some important data from the IOMMU PCI space and | |
730 | * initializes the driver data structure with it. It reads the hardware | |
731 | * capabilities and the first/last device entries | |
732 | */ | |
5d0c8e49 JR |
733 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
734 | { | |
5d0c8e49 | 735 | int cap_ptr = iommu->cap_ptr; |
d99ddec3 | 736 | u32 range, misc, low, high; |
5bcd757f | 737 | int i, j; |
5d0c8e49 | 738 | |
3eaf28a1 JR |
739 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
740 | &iommu->cap); | |
741 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
742 | &range); | |
a80dc3e0 JR |
743 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
744 | &misc); | |
5d0c8e49 | 745 | |
d591b0a3 JR |
746 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
747 | MMIO_GET_FD(range)); | |
748 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
749 | MMIO_GET_LD(range)); | |
a80dc3e0 | 750 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
4c894f47 | 751 | |
60f723b4 JR |
752 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) |
753 | amd_iommu_iotlb_sup = false; | |
754 | ||
d99ddec3 JR |
755 | /* read extended feature bits */ |
756 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
757 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
758 | ||
759 | iommu->features = ((u64)high << 32) | low; | |
760 | ||
62f71abb | 761 | if (iommu_feature(iommu, FEATURE_GT)) { |
52815b75 | 762 | int glxval; |
62f71abb JR |
763 | u32 pasids; |
764 | u64 shift; | |
765 | ||
766 | shift = iommu->features & FEATURE_PASID_MASK; | |
767 | shift >>= FEATURE_PASID_SHIFT; | |
768 | pasids = (1 << shift); | |
769 | ||
770 | amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids); | |
52815b75 JR |
771 | |
772 | glxval = iommu->features & FEATURE_GLXVAL_MASK; | |
773 | glxval >>= FEATURE_GLXVAL_SHIFT; | |
774 | ||
775 | if (amd_iommu_max_glx_val == -1) | |
776 | amd_iommu_max_glx_val = glxval; | |
777 | else | |
778 | amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); | |
62f71abb JR |
779 | } |
780 | ||
400a28a0 JR |
781 | if (iommu_feature(iommu, FEATURE_GT) && |
782 | iommu_feature(iommu, FEATURE_PPR)) { | |
783 | iommu->is_iommu_v2 = true; | |
784 | amd_iommu_v2_present = true; | |
785 | } | |
786 | ||
5bcd757f MG |
787 | if (!is_rd890_iommu(iommu->dev)) |
788 | return; | |
789 | ||
790 | /* | |
791 | * Some rd890 systems may not be fully reconfigured by the BIOS, so | |
792 | * it's necessary for us to store this information so it can be | |
793 | * reprogrammed on resume | |
794 | */ | |
795 | ||
796 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
797 | &iommu->stored_addr_lo); | |
798 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
799 | &iommu->stored_addr_hi); | |
800 | ||
801 | /* Low bit locks writes to configuration space */ | |
802 | iommu->stored_addr_lo &= ~1; | |
803 | ||
804 | for (i = 0; i < 6; i++) | |
805 | for (j = 0; j < 0x12; j++) | |
806 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
807 | ||
808 | for (i = 0; i < 0x83; i++) | |
809 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
5d0c8e49 JR |
810 | } |
811 | ||
b65233a9 JR |
812 | /* |
813 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
814 | * initializes the hardware and our data structures with it. | |
815 | */ | |
5d0c8e49 JR |
816 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
817 | struct ivhd_header *h) | |
818 | { | |
819 | u8 *p = (u8 *)h; | |
820 | u8 *end = p, flags = 0; | |
0de66d5b JR |
821 | u16 devid = 0, devid_start = 0, devid_to = 0; |
822 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 823 | bool alias = false; |
5d0c8e49 JR |
824 | struct ivhd_entry *e; |
825 | ||
826 | /* | |
e9bf5197 | 827 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 828 | */ |
e9bf5197 | 829 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
830 | |
831 | /* | |
832 | * Done. Now parse the device entries | |
833 | */ | |
834 | p += sizeof(struct ivhd_header); | |
835 | end += h->length; | |
836 | ||
42a698f4 | 837 | |
5d0c8e49 JR |
838 | while (p < end) { |
839 | e = (struct ivhd_entry *)p; | |
840 | switch (e->type) { | |
841 | case IVHD_DEV_ALL: | |
42a698f4 JR |
842 | |
843 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
844 | " last device %02x:%02x.%x flags: %02x\n", | |
845 | PCI_BUS(iommu->first_device), | |
846 | PCI_SLOT(iommu->first_device), | |
847 | PCI_FUNC(iommu->first_device), | |
848 | PCI_BUS(iommu->last_device), | |
849 | PCI_SLOT(iommu->last_device), | |
850 | PCI_FUNC(iommu->last_device), | |
851 | e->flags); | |
852 | ||
5d0c8e49 JR |
853 | for (dev_i = iommu->first_device; |
854 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
855 | set_dev_entry_from_acpi(iommu, dev_i, |
856 | e->flags, 0); | |
5d0c8e49 JR |
857 | break; |
858 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
859 | |
860 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
861 | "flags: %02x\n", | |
862 | PCI_BUS(e->devid), | |
863 | PCI_SLOT(e->devid), | |
864 | PCI_FUNC(e->devid), | |
865 | e->flags); | |
866 | ||
5d0c8e49 | 867 | devid = e->devid; |
5ff4789d | 868 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
869 | break; |
870 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
871 | |
872 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
873 | "devid: %02x:%02x.%x flags: %02x\n", | |
874 | PCI_BUS(e->devid), | |
875 | PCI_SLOT(e->devid), | |
876 | PCI_FUNC(e->devid), | |
877 | e->flags); | |
878 | ||
5d0c8e49 JR |
879 | devid_start = e->devid; |
880 | flags = e->flags; | |
881 | ext_flags = 0; | |
58a3bee5 | 882 | alias = false; |
5d0c8e49 JR |
883 | break; |
884 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
885 | |
886 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
887 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
888 | PCI_BUS(e->devid), | |
889 | PCI_SLOT(e->devid), | |
890 | PCI_FUNC(e->devid), | |
891 | e->flags, | |
892 | PCI_BUS(e->ext >> 8), | |
893 | PCI_SLOT(e->ext >> 8), | |
894 | PCI_FUNC(e->ext >> 8)); | |
895 | ||
5d0c8e49 JR |
896 | devid = e->devid; |
897 | devid_to = e->ext >> 8; | |
7a6a3a08 | 898 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 899 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
900 | amd_iommu_alias_table[devid] = devid_to; |
901 | break; | |
902 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
903 | |
904 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
905 | "devid: %02x:%02x.%x flags: %02x " | |
906 | "devid_to: %02x:%02x.%x\n", | |
907 | PCI_BUS(e->devid), | |
908 | PCI_SLOT(e->devid), | |
909 | PCI_FUNC(e->devid), | |
910 | e->flags, | |
911 | PCI_BUS(e->ext >> 8), | |
912 | PCI_SLOT(e->ext >> 8), | |
913 | PCI_FUNC(e->ext >> 8)); | |
914 | ||
5d0c8e49 JR |
915 | devid_start = e->devid; |
916 | flags = e->flags; | |
917 | devid_to = e->ext >> 8; | |
918 | ext_flags = 0; | |
58a3bee5 | 919 | alias = true; |
5d0c8e49 JR |
920 | break; |
921 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
922 | |
923 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
924 | "flags: %02x ext: %08x\n", | |
925 | PCI_BUS(e->devid), | |
926 | PCI_SLOT(e->devid), | |
927 | PCI_FUNC(e->devid), | |
928 | e->flags, e->ext); | |
929 | ||
5d0c8e49 | 930 | devid = e->devid; |
5ff4789d JR |
931 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
932 | e->ext); | |
5d0c8e49 JR |
933 | break; |
934 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
935 | |
936 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
937 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
938 | PCI_BUS(e->devid), | |
939 | PCI_SLOT(e->devid), | |
940 | PCI_FUNC(e->devid), | |
941 | e->flags, e->ext); | |
942 | ||
5d0c8e49 JR |
943 | devid_start = e->devid; |
944 | flags = e->flags; | |
945 | ext_flags = e->ext; | |
58a3bee5 | 946 | alias = false; |
5d0c8e49 JR |
947 | break; |
948 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
949 | |
950 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
951 | PCI_BUS(e->devid), | |
952 | PCI_SLOT(e->devid), | |
953 | PCI_FUNC(e->devid)); | |
954 | ||
5d0c8e49 JR |
955 | devid = e->devid; |
956 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 957 | if (alias) { |
5d0c8e49 | 958 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
959 | set_dev_entry_from_acpi(iommu, |
960 | devid_to, flags, ext_flags); | |
961 | } | |
962 | set_dev_entry_from_acpi(iommu, dev_i, | |
963 | flags, ext_flags); | |
5d0c8e49 JR |
964 | } |
965 | break; | |
966 | default: | |
967 | break; | |
968 | } | |
969 | ||
b514e555 | 970 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
971 | } |
972 | } | |
973 | ||
b65233a9 | 974 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
975 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
976 | { | |
0de66d5b | 977 | u32 i; |
5d0c8e49 JR |
978 | |
979 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
980 | set_iommu_for_device(iommu, i); | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
e47d402d JR |
985 | static void __init free_iommu_one(struct amd_iommu *iommu) |
986 | { | |
987 | free_command_buffer(iommu); | |
335503e5 | 988 | free_event_buffer(iommu); |
1a29ac01 | 989 | free_ppr_log(iommu); |
e47d402d JR |
990 | iommu_unmap_mmio_space(iommu); |
991 | } | |
992 | ||
993 | static void __init free_iommu_all(void) | |
994 | { | |
995 | struct amd_iommu *iommu, *next; | |
996 | ||
3bd22172 | 997 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
998 | list_del(&iommu->list); |
999 | free_iommu_one(iommu); | |
1000 | kfree(iommu); | |
1001 | } | |
1002 | } | |
1003 | ||
b65233a9 JR |
1004 | /* |
1005 | * This function clues the initialization function for one IOMMU | |
1006 | * together and also allocates the command buffer and programs the | |
1007 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
1008 | */ | |
e47d402d JR |
1009 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
1010 | { | |
1011 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
1012 | |
1013 | /* Add IOMMU to internal data structures */ | |
e47d402d | 1014 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
1015 | iommu->index = amd_iommus_present++; |
1016 | ||
1017 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
1018 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
1019 | return -ENOSYS; | |
1020 | } | |
1021 | ||
1022 | /* Index is fine - add IOMMU to the array */ | |
1023 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
1024 | |
1025 | /* | |
1026 | * Copy data from ACPI table entry to the iommu struct | |
1027 | */ | |
3eaf28a1 JR |
1028 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
1029 | if (!iommu->dev) | |
1030 | return 1; | |
1031 | ||
e47d402d | 1032 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1033 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
1034 | iommu->mmio_phys = h->mmio_phys; |
1035 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
1036 | if (!iommu->mmio_base) | |
1037 | return -ENOMEM; | |
1038 | ||
e47d402d JR |
1039 | iommu->cmd_buf = alloc_command_buffer(iommu); |
1040 | if (!iommu->cmd_buf) | |
1041 | return -ENOMEM; | |
1042 | ||
335503e5 JR |
1043 | iommu->evt_buf = alloc_event_buffer(iommu); |
1044 | if (!iommu->evt_buf) | |
1045 | return -ENOMEM; | |
1046 | ||
a80dc3e0 JR |
1047 | iommu->int_enabled = false; |
1048 | ||
e47d402d JR |
1049 | init_iommu_from_pci(iommu); |
1050 | init_iommu_from_acpi(iommu, h); | |
1051 | init_iommu_devices(iommu); | |
1052 | ||
1a29ac01 JR |
1053 | if (iommu_feature(iommu, FEATURE_PPR)) { |
1054 | iommu->ppr_log = alloc_ppr_log(iommu); | |
1055 | if (!iommu->ppr_log) | |
1056 | return -ENOMEM; | |
1057 | } | |
1058 | ||
318afd41 JR |
1059 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
1060 | amd_iommu_np_cache = true; | |
1061 | ||
8a66712b | 1062 | return pci_enable_device(iommu->dev); |
e47d402d JR |
1063 | } |
1064 | ||
b65233a9 JR |
1065 | /* |
1066 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1067 | * IOMMU structure and initializes it with init_iommu_one() | |
1068 | */ | |
e47d402d JR |
1069 | static int __init init_iommu_all(struct acpi_table_header *table) |
1070 | { | |
1071 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1072 | struct ivhd_header *h; | |
1073 | struct amd_iommu *iommu; | |
1074 | int ret; | |
1075 | ||
e47d402d JR |
1076 | end += table->length; |
1077 | p += IVRS_HEADER_LENGTH; | |
1078 | ||
1079 | while (p < end) { | |
1080 | h = (struct ivhd_header *)p; | |
1081 | switch (*p) { | |
1082 | case ACPI_IVHD_TYPE: | |
9c72041f | 1083 | |
ae908c22 | 1084 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
1085 | "seg: %d flags: %01x info %04x\n", |
1086 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
1087 | PCI_FUNC(h->devid), h->cap_ptr, | |
1088 | h->pci_seg, h->flags, h->info); | |
1089 | DUMP_printk(" mmio-addr: %016llx\n", | |
1090 | h->mmio_phys); | |
1091 | ||
e47d402d | 1092 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
3551a708 JR |
1093 | if (iommu == NULL) { |
1094 | amd_iommu_init_err = -ENOMEM; | |
1095 | return 0; | |
1096 | } | |
1097 | ||
e47d402d | 1098 | ret = init_iommu_one(iommu, h); |
3551a708 JR |
1099 | if (ret) { |
1100 | amd_iommu_init_err = ret; | |
1101 | return 0; | |
1102 | } | |
e47d402d JR |
1103 | break; |
1104 | default: | |
1105 | break; | |
1106 | } | |
1107 | p += h->length; | |
1108 | ||
1109 | } | |
1110 | WARN_ON(p != end); | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
a80dc3e0 JR |
1115 | /**************************************************************************** |
1116 | * | |
1117 | * The following functions initialize the MSI interrupts for all IOMMUs | |
1118 | * in the system. Its a bit challenging because there could be multiple | |
1119 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
1120 | * pci_dev. | |
1121 | * | |
1122 | ****************************************************************************/ | |
1123 | ||
9f800de3 | 1124 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1125 | { |
1126 | int r; | |
a80dc3e0 | 1127 | |
9ddd592a JR |
1128 | r = pci_enable_msi(iommu->dev); |
1129 | if (r) | |
1130 | return r; | |
a80dc3e0 | 1131 | |
72fe00f0 JR |
1132 | r = request_threaded_irq(iommu->dev->irq, |
1133 | amd_iommu_int_handler, | |
1134 | amd_iommu_int_thread, | |
1135 | 0, "AMD-Vi", | |
1136 | iommu->dev); | |
a80dc3e0 JR |
1137 | |
1138 | if (r) { | |
1139 | pci_disable_msi(iommu->dev); | |
9ddd592a | 1140 | return r; |
a80dc3e0 JR |
1141 | } |
1142 | ||
fab6afa3 | 1143 | iommu->int_enabled = true; |
1a29ac01 | 1144 | |
a80dc3e0 JR |
1145 | return 0; |
1146 | } | |
1147 | ||
05f92db9 | 1148 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 | 1149 | { |
9ddd592a JR |
1150 | int ret; |
1151 | ||
a80dc3e0 | 1152 | if (iommu->int_enabled) |
9ddd592a | 1153 | goto enable_faults; |
a80dc3e0 | 1154 | |
d91cecdd | 1155 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
9ddd592a JR |
1156 | ret = iommu_setup_msi(iommu); |
1157 | else | |
1158 | ret = -ENODEV; | |
1159 | ||
1160 | if (ret) | |
1161 | return ret; | |
a80dc3e0 | 1162 | |
9ddd592a JR |
1163 | enable_faults: |
1164 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
a80dc3e0 | 1165 | |
9ddd592a JR |
1166 | if (iommu->ppr_log != NULL) |
1167 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1168 | ||
1169 | return 0; | |
a80dc3e0 JR |
1170 | } |
1171 | ||
b65233a9 JR |
1172 | /**************************************************************************** |
1173 | * | |
1174 | * The next functions belong to the third pass of parsing the ACPI | |
1175 | * table. In this last pass the memory mapping requirements are | |
1176 | * gathered (like exclusion and unity mapping reanges). | |
1177 | * | |
1178 | ****************************************************************************/ | |
1179 | ||
be2a022c JR |
1180 | static void __init free_unity_maps(void) |
1181 | { | |
1182 | struct unity_map_entry *entry, *next; | |
1183 | ||
1184 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1185 | list_del(&entry->list); | |
1186 | kfree(entry); | |
1187 | } | |
1188 | } | |
1189 | ||
b65233a9 | 1190 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1191 | static int __init init_exclusion_range(struct ivmd_header *m) |
1192 | { | |
1193 | int i; | |
1194 | ||
1195 | switch (m->type) { | |
1196 | case ACPI_IVMD_TYPE: | |
1197 | set_device_exclusion_range(m->devid, m); | |
1198 | break; | |
1199 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1200 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1201 | set_device_exclusion_range(i, m); |
1202 | break; | |
1203 | case ACPI_IVMD_TYPE_RANGE: | |
1204 | for (i = m->devid; i <= m->aux; ++i) | |
1205 | set_device_exclusion_range(i, m); | |
1206 | break; | |
1207 | default: | |
1208 | break; | |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
b65233a9 | 1214 | /* called for unity map ACPI definition */ |
be2a022c JR |
1215 | static int __init init_unity_map_range(struct ivmd_header *m) |
1216 | { | |
1217 | struct unity_map_entry *e = 0; | |
02acc43a | 1218 | char *s; |
be2a022c JR |
1219 | |
1220 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1221 | if (e == NULL) | |
1222 | return -ENOMEM; | |
1223 | ||
1224 | switch (m->type) { | |
1225 | default: | |
0bc252f4 JR |
1226 | kfree(e); |
1227 | return 0; | |
be2a022c | 1228 | case ACPI_IVMD_TYPE: |
02acc43a | 1229 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1230 | e->devid_start = e->devid_end = m->devid; |
1231 | break; | |
1232 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1233 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1234 | e->devid_start = 0; |
1235 | e->devid_end = amd_iommu_last_bdf; | |
1236 | break; | |
1237 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1238 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1239 | e->devid_start = m->devid; |
1240 | e->devid_end = m->aux; | |
1241 | break; | |
1242 | } | |
1243 | e->address_start = PAGE_ALIGN(m->range_start); | |
1244 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1245 | e->prot = m->flags >> 1; | |
1246 | ||
02acc43a JR |
1247 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1248 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1249 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1250 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1251 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1252 | e->address_start, e->address_end, m->flags); | |
1253 | ||
be2a022c JR |
1254 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
b65233a9 | 1259 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1260 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1261 | { | |
1262 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1263 | struct ivmd_header *m; | |
1264 | ||
be2a022c JR |
1265 | end += table->length; |
1266 | p += IVRS_HEADER_LENGTH; | |
1267 | ||
1268 | while (p < end) { | |
1269 | m = (struct ivmd_header *)p; | |
1270 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1271 | init_exclusion_range(m); | |
1272 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1273 | init_unity_map_range(m); | |
1274 | ||
1275 | p += m->length; | |
1276 | } | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
9f5f5fb3 JR |
1281 | /* |
1282 | * Init the device table to not allow DMA access for devices and | |
1283 | * suppress all page faults | |
1284 | */ | |
1285 | static void init_device_table(void) | |
1286 | { | |
0de66d5b | 1287 | u32 devid; |
9f5f5fb3 JR |
1288 | |
1289 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1290 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1291 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1292 | } |
1293 | } | |
1294 | ||
e9bf5197 JR |
1295 | static void iommu_init_flags(struct amd_iommu *iommu) |
1296 | { | |
1297 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1298 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1299 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1300 | ||
1301 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1302 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1303 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1304 | ||
1305 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1306 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1307 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1308 | ||
1309 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1310 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1311 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1312 | ||
1313 | /* | |
1314 | * make IOMMU memory accesses cache coherent | |
1315 | */ | |
1316 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1456e9d2 JR |
1317 | |
1318 | /* Set IOTLB invalidation timeout to 1s */ | |
1319 | iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); | |
e9bf5197 JR |
1320 | } |
1321 | ||
5bcd757f | 1322 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1323 | { |
5bcd757f MG |
1324 | int i, j; |
1325 | u32 ioc_feature_control; | |
1326 | struct pci_dev *pdev = NULL; | |
1327 | ||
1328 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
1329 | if (!is_rd890_iommu(iommu->dev)) | |
1330 | return; | |
1331 | ||
1332 | /* | |
1333 | * First, we need to ensure that the iommu is enabled. This is | |
1334 | * controlled by a register in the northbridge | |
1335 | */ | |
1336 | pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0)); | |
1337 | ||
1338 | if (!pdev) | |
1339 | return; | |
1340 | ||
1341 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1342 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1343 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1344 | ||
1345 | /* Enable the iommu */ | |
1346 | if (!(ioc_feature_control & 0x1)) | |
1347 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1348 | ||
1349 | pci_dev_put(pdev); | |
1350 | ||
1351 | /* Restore the iommu BAR */ | |
1352 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1353 | iommu->stored_addr_lo); | |
1354 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1355 | iommu->stored_addr_hi); | |
1356 | ||
1357 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1358 | for (i = 0; i < 6; i++) | |
1359 | for (j = 0; j < 0x12; j++) | |
1360 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1361 | ||
1362 | /* Restore the l2 indirect regs */ | |
1363 | for (i = 0; i < 0x83; i++) | |
1364 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1365 | ||
1366 | /* Lock PCI setup registers */ | |
1367 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1368 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1369 | } |
1370 | ||
b65233a9 JR |
1371 | /* |
1372 | * This function finally enables all IOMMUs found in the system after | |
1373 | * they have been initialized | |
1374 | */ | |
05f92db9 | 1375 | static void enable_iommus(void) |
8736197b JR |
1376 | { |
1377 | struct amd_iommu *iommu; | |
1378 | ||
3bd22172 | 1379 | for_each_iommu(iommu) { |
a8c485bb | 1380 | iommu_disable(iommu); |
e9bf5197 | 1381 | iommu_init_flags(iommu); |
58492e12 JR |
1382 | iommu_set_device_table(iommu); |
1383 | iommu_enable_command_buffer(iommu); | |
1384 | iommu_enable_event_buffer(iommu); | |
1a29ac01 | 1385 | iommu_enable_ppr_log(iommu); |
cbc33a90 | 1386 | iommu_enable_gt(iommu); |
8736197b JR |
1387 | iommu_set_exclusion_range(iommu); |
1388 | iommu_enable(iommu); | |
7d0c5cc5 | 1389 | iommu_flush_all_caches(iommu); |
8736197b JR |
1390 | } |
1391 | } | |
1392 | ||
92ac4320 JR |
1393 | static void disable_iommus(void) |
1394 | { | |
1395 | struct amd_iommu *iommu; | |
1396 | ||
1397 | for_each_iommu(iommu) | |
1398 | iommu_disable(iommu); | |
1399 | } | |
1400 | ||
7441e9cb JR |
1401 | /* |
1402 | * Suspend/Resume support | |
1403 | * disable suspend until real resume implemented | |
1404 | */ | |
1405 | ||
f3c6ea1b | 1406 | static void amd_iommu_resume(void) |
7441e9cb | 1407 | { |
5bcd757f MG |
1408 | struct amd_iommu *iommu; |
1409 | ||
1410 | for_each_iommu(iommu) | |
1411 | iommu_apply_resume_quirks(iommu); | |
1412 | ||
736501ee JR |
1413 | /* re-load the hardware */ |
1414 | enable_iommus(); | |
3d9761e7 JR |
1415 | |
1416 | amd_iommu_enable_interrupts(); | |
7441e9cb JR |
1417 | } |
1418 | ||
f3c6ea1b | 1419 | static int amd_iommu_suspend(void) |
7441e9cb | 1420 | { |
736501ee JR |
1421 | /* disable IOMMUs to go out of the way for BIOS */ |
1422 | disable_iommus(); | |
1423 | ||
1424 | return 0; | |
7441e9cb JR |
1425 | } |
1426 | ||
f3c6ea1b | 1427 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1428 | .suspend = amd_iommu_suspend, |
1429 | .resume = amd_iommu_resume, | |
1430 | }; | |
1431 | ||
8704a1ba JR |
1432 | static void __init free_on_init_error(void) |
1433 | { | |
1434 | amd_iommu_uninit_devices(); | |
1435 | ||
1436 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, | |
1437 | get_order(MAX_DOMAIN_ID/8)); | |
1438 | ||
1439 | free_pages((unsigned long)amd_iommu_rlookup_table, | |
1440 | get_order(rlookup_table_size)); | |
1441 | ||
1442 | free_pages((unsigned long)amd_iommu_alias_table, | |
1443 | get_order(alias_table_size)); | |
1444 | ||
1445 | free_pages((unsigned long)amd_iommu_dev_table, | |
1446 | get_order(dev_table_size)); | |
1447 | ||
1448 | free_iommu_all(); | |
1449 | ||
1450 | free_unity_maps(); | |
1451 | ||
1452 | #ifdef CONFIG_GART_IOMMU | |
1453 | /* | |
1454 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1455 | * if possible. | |
1456 | */ | |
1457 | gart_iommu_init(); | |
1458 | ||
1459 | #endif | |
1460 | } | |
1461 | ||
b65233a9 | 1462 | /* |
8704a1ba JR |
1463 | * This is the hardware init function for AMD IOMMU in the system. |
1464 | * This function is called either from amd_iommu_init or from the interrupt | |
1465 | * remapping setup code. | |
b65233a9 JR |
1466 | * |
1467 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1468 | * three times: | |
1469 | * | |
1470 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1471 | * Upon this information the size of the data structures is | |
1472 | * determined that needs to be allocated. | |
1473 | * | |
1474 | * 2 pass) Initialize the data structures just allocated with the | |
1475 | * information in the ACPI table about available AMD IOMMUs | |
1476 | * in the system. It also maps the PCI devices in the | |
1477 | * system to specific IOMMUs | |
1478 | * | |
1479 | * 3 pass) After the basic data structures are allocated and | |
1480 | * initialized we update them with information about memory | |
1481 | * remapping requirements parsed out of the ACPI table in | |
1482 | * this last pass. | |
1483 | * | |
8704a1ba JR |
1484 | * After everything is set up the IOMMUs are enabled and the necessary |
1485 | * hotplug and suspend notifiers are registered. | |
b65233a9 | 1486 | */ |
8704a1ba | 1487 | int __init amd_iommu_init_hardware(void) |
fe74c9cf JR |
1488 | { |
1489 | int i, ret = 0; | |
1490 | ||
8704a1ba JR |
1491 | if (!amd_iommu_detected) |
1492 | return -ENODEV; | |
1493 | ||
1494 | if (amd_iommu_dev_table != NULL) { | |
1495 | /* Hardware already initialized */ | |
1496 | return 0; | |
1497 | } | |
1498 | ||
fe74c9cf JR |
1499 | /* |
1500 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1501 | * we need to handle. Upon this information the shared data | |
1502 | * structures for the IOMMUs in the system will be allocated | |
1503 | */ | |
1504 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1505 | return -ENODEV; | |
1506 | ||
3551a708 JR |
1507 | ret = amd_iommu_init_err; |
1508 | if (ret) | |
1509 | goto out; | |
1510 | ||
c571484e JR |
1511 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1512 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1513 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf | 1514 | |
fe74c9cf | 1515 | /* Device table - directly used by all IOMMUs */ |
8704a1ba | 1516 | ret = -ENOMEM; |
5dc8bff0 | 1517 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1518 | get_order(dev_table_size)); |
1519 | if (amd_iommu_dev_table == NULL) | |
1520 | goto out; | |
1521 | ||
1522 | /* | |
1523 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1524 | * IOMMU see for that device | |
1525 | */ | |
1526 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1527 | get_order(alias_table_size)); | |
1528 | if (amd_iommu_alias_table == NULL) | |
1529 | goto free; | |
1530 | ||
1531 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1532 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1533 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1534 | get_order(rlookup_table_size)); |
1535 | if (amd_iommu_rlookup_table == NULL) | |
1536 | goto free; | |
1537 | ||
5dc8bff0 JR |
1538 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1539 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1540 | get_order(MAX_DOMAIN_ID/8)); |
1541 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1542 | goto free; | |
1543 | ||
9f5f5fb3 JR |
1544 | /* init the device table */ |
1545 | init_device_table(); | |
1546 | ||
fe74c9cf | 1547 | /* |
5dc8bff0 | 1548 | * let all alias entries point to itself |
fe74c9cf | 1549 | */ |
3a61ec38 | 1550 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1551 | amd_iommu_alias_table[i] = i; |
1552 | ||
fe74c9cf JR |
1553 | /* |
1554 | * never allocate domain 0 because its used as the non-allocated and | |
1555 | * error value placeholder | |
1556 | */ | |
1557 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1558 | ||
aeb26f55 JR |
1559 | spin_lock_init(&amd_iommu_pd_lock); |
1560 | ||
fe74c9cf JR |
1561 | /* |
1562 | * now the data structures are allocated and basically initialized | |
1563 | * start the real acpi table scan | |
1564 | */ | |
1565 | ret = -ENODEV; | |
1566 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1567 | goto free; | |
1568 | ||
3551a708 JR |
1569 | if (amd_iommu_init_err) { |
1570 | ret = amd_iommu_init_err; | |
0f764806 | 1571 | goto free; |
3551a708 | 1572 | } |
0f764806 | 1573 | |
fe74c9cf JR |
1574 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) |
1575 | goto free; | |
1576 | ||
3551a708 JR |
1577 | if (amd_iommu_init_err) { |
1578 | ret = amd_iommu_init_err; | |
1579 | goto free; | |
1580 | } | |
1581 | ||
b7cc9554 JR |
1582 | ret = amd_iommu_init_devices(); |
1583 | if (ret) | |
1584 | goto free; | |
1585 | ||
75f66533 CW |
1586 | enable_iommus(); |
1587 | ||
8704a1ba JR |
1588 | amd_iommu_init_notifier(); |
1589 | ||
1590 | register_syscore_ops(&amd_iommu_syscore_ops); | |
1591 | ||
1592 | out: | |
1593 | return ret; | |
1594 | ||
1595 | free: | |
1596 | free_on_init_error(); | |
1597 | ||
1598 | return ret; | |
1599 | } | |
1600 | ||
ae295142 | 1601 | static int amd_iommu_enable_interrupts(void) |
3d9761e7 JR |
1602 | { |
1603 | struct amd_iommu *iommu; | |
1604 | int ret = 0; | |
1605 | ||
1606 | for_each_iommu(iommu) { | |
1607 | ret = iommu_init_msi(iommu); | |
1608 | if (ret) | |
1609 | goto out; | |
1610 | } | |
1611 | ||
1612 | out: | |
1613 | return ret; | |
1614 | } | |
1615 | ||
8704a1ba JR |
1616 | /* |
1617 | * This is the core init function for AMD IOMMU hardware in the system. | |
1618 | * This function is called from the generic x86 DMA layer initialization | |
1619 | * code. | |
1620 | * | |
1621 | * The function calls amd_iommu_init_hardware() to setup and enable the | |
1622 | * IOMMU hardware if this has not happened yet. After that the driver | |
1623 | * registers for the DMA-API and for the IOMMU-API as necessary. | |
1624 | */ | |
1625 | static int __init amd_iommu_init(void) | |
1626 | { | |
1627 | int ret = 0; | |
1628 | ||
1629 | ret = amd_iommu_init_hardware(); | |
1630 | if (ret) | |
1631 | goto out; | |
1632 | ||
3d9761e7 JR |
1633 | ret = amd_iommu_enable_interrupts(); |
1634 | if (ret) | |
1635 | goto free; | |
1636 | ||
4751a951 JR |
1637 | if (iommu_pass_through) |
1638 | ret = amd_iommu_init_passthrough(); | |
1639 | else | |
1640 | ret = amd_iommu_init_dma_ops(); | |
f5325094 | 1641 | |
7441e9cb | 1642 | if (ret) |
8704a1ba | 1643 | goto free; |
7441e9cb | 1644 | |
f5325094 JR |
1645 | amd_iommu_init_api(); |
1646 | ||
4751a951 JR |
1647 | if (iommu_pass_through) |
1648 | goto out; | |
1649 | ||
afa9fdc2 | 1650 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1651 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1652 | else |
4c6f40d4 | 1653 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1654 | |
338bac52 | 1655 | x86_platform.iommu_shutdown = disable_iommus; |
8704a1ba | 1656 | |
fe74c9cf JR |
1657 | out: |
1658 | return ret; | |
1659 | ||
e82752d8 | 1660 | free: |
8704a1ba | 1661 | disable_iommus(); |
d7f07769 | 1662 | |
8704a1ba | 1663 | free_on_init_error(); |
d7f07769 | 1664 | |
fe74c9cf JR |
1665 | goto out; |
1666 | } | |
1667 | ||
b65233a9 JR |
1668 | /**************************************************************************** |
1669 | * | |
1670 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1671 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1672 | * IOMMUs | |
1673 | * | |
1674 | ****************************************************************************/ | |
ae7877de JR |
1675 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1676 | { | |
1677 | return 0; | |
1678 | } | |
1679 | ||
480125ba | 1680 | int __init amd_iommu_detect(void) |
ae7877de | 1681 | { |
75f1cdf1 | 1682 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 1683 | return -ENODEV; |
ae7877de | 1684 | |
a5235725 | 1685 | if (amd_iommu_disabled) |
480125ba | 1686 | return -ENODEV; |
a5235725 | 1687 | |
ae7877de JR |
1688 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1689 | iommu_detected = 1; | |
c1cbebee | 1690 | amd_iommu_detected = 1; |
ea1b0d39 | 1691 | x86_init.iommu.iommu_init = amd_iommu_init; |
11bd04f6 | 1692 | |
5d990b62 CW |
1693 | /* Make sure ACS will be enabled */ |
1694 | pci_request_acs(); | |
480125ba | 1695 | return 1; |
ae7877de | 1696 | } |
480125ba | 1697 | return -ENODEV; |
ae7877de JR |
1698 | } |
1699 | ||
b65233a9 JR |
1700 | /**************************************************************************** |
1701 | * | |
1702 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1703 | * options. | |
1704 | * | |
1705 | ****************************************************************************/ | |
1706 | ||
fefda117 JR |
1707 | static int __init parse_amd_iommu_dump(char *str) |
1708 | { | |
1709 | amd_iommu_dump = true; | |
1710 | ||
1711 | return 1; | |
1712 | } | |
1713 | ||
918ad6c5 JR |
1714 | static int __init parse_amd_iommu_options(char *str) |
1715 | { | |
1716 | for (; *str; ++str) { | |
695b5676 | 1717 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1718 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1719 | if (strncmp(str, "off", 3) == 0) |
1720 | amd_iommu_disabled = true; | |
5abcdba4 JR |
1721 | if (strncmp(str, "force_isolation", 15) == 0) |
1722 | amd_iommu_force_isolation = true; | |
918ad6c5 JR |
1723 | } |
1724 | ||
1725 | return 1; | |
1726 | } | |
1727 | ||
fefda117 | 1728 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1729 | __setup("amd_iommu=", parse_amd_iommu_options); |
22e6daf4 KRW |
1730 | |
1731 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
1732 | gart_iommu_hole_init, | |
1733 | 0, | |
1734 | 0); | |
400a28a0 JR |
1735 | |
1736 | bool amd_iommu_v2_supported(void) | |
1737 | { | |
1738 | return amd_iommu_v2_present; | |
1739 | } | |
1740 | EXPORT_SYMBOL(amd_iommu_v2_supported); |