Commit | Line | Data |
---|---|---|
e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
d73a6d72 | 48 | unsigned mmu_notifier_count; /* Counting nested mmu_notifier |
e79df31c | 49 | calls */ |
ed96f228 | 50 | struct mm_struct *mm; /* mm_struct for the faults */ |
ff6d0cce | 51 | struct mmu_notifier mn; /* mmu_notifier handle */ |
ed96f228 JR |
52 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
53 | struct device_state *device_state; /* Link to our device_state */ | |
54 | int pasid; /* PASID index */ | |
d9e1611e JR |
55 | bool invalid; /* Used during setup and |
56 | teardown of the pasid */ | |
d73a6d72 JR |
57 | spinlock_t lock; /* Protect pri_queues and |
58 | mmu_notifer_count */ | |
028eeacc | 59 | wait_queue_head_t wq; /* To wait for count == 0 */ |
ed96f228 JR |
60 | }; |
61 | ||
62 | struct device_state { | |
741669c7 JR |
63 | struct list_head list; |
64 | u16 devid; | |
ed96f228 JR |
65 | atomic_t count; |
66 | struct pci_dev *pdev; | |
67 | struct pasid_state **states; | |
68 | struct iommu_domain *domain; | |
69 | int pasid_levels; | |
70 | int max_pasids; | |
175d6146 | 71 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
bc21662f | 72 | amd_iommu_invalidate_ctx inv_ctx_cb; |
ed96f228 | 73 | spinlock_t lock; |
028eeacc JR |
74 | wait_queue_head_t wq; |
75 | }; | |
76 | ||
77 | struct fault { | |
78 | struct work_struct work; | |
79 | struct device_state *dev_state; | |
80 | struct pasid_state *state; | |
81 | struct mm_struct *mm; | |
82 | u64 address; | |
83 | u16 devid; | |
84 | u16 pasid; | |
85 | u16 tag; | |
86 | u16 finish; | |
87 | u16 flags; | |
ed96f228 JR |
88 | }; |
89 | ||
741669c7 | 90 | static LIST_HEAD(state_list); |
ed96f228 JR |
91 | static spinlock_t state_lock; |
92 | ||
028eeacc JR |
93 | static struct workqueue_struct *iommu_wq; |
94 | ||
8736b2c3 JR |
95 | /* |
96 | * Empty page table - Used between | |
97 | * mmu_notifier_invalidate_range_start and | |
98 | * mmu_notifier_invalidate_range_end | |
99 | */ | |
100 | static u64 *empty_page_table; | |
101 | ||
2d5503b6 | 102 | static void free_pasid_states(struct device_state *dev_state); |
ed96f228 JR |
103 | |
104 | static u16 device_id(struct pci_dev *pdev) | |
105 | { | |
106 | u16 devid; | |
107 | ||
108 | devid = pdev->bus->number; | |
109 | devid = (devid << 8) | pdev->devfn; | |
110 | ||
111 | return devid; | |
112 | } | |
113 | ||
b87d2d7c JR |
114 | static struct device_state *__get_device_state(u16 devid) |
115 | { | |
741669c7 JR |
116 | struct device_state *dev_state; |
117 | ||
118 | list_for_each_entry(dev_state, &state_list, list) { | |
119 | if (dev_state->devid == devid) | |
120 | return dev_state; | |
121 | } | |
122 | ||
123 | return NULL; | |
b87d2d7c JR |
124 | } |
125 | ||
ed96f228 JR |
126 | static struct device_state *get_device_state(u16 devid) |
127 | { | |
128 | struct device_state *dev_state; | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&state_lock, flags); | |
b87d2d7c | 132 | dev_state = __get_device_state(devid); |
ed96f228 JR |
133 | if (dev_state != NULL) |
134 | atomic_inc(&dev_state->count); | |
135 | spin_unlock_irqrestore(&state_lock, flags); | |
136 | ||
137 | return dev_state; | |
138 | } | |
139 | ||
140 | static void free_device_state(struct device_state *dev_state) | |
141 | { | |
2d5503b6 JR |
142 | /* |
143 | * First detach device from domain - No more PRI requests will arrive | |
144 | * from that device after it is unbound from the IOMMUv2 domain. | |
145 | */ | |
ed96f228 | 146 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
147 | |
148 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 149 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
150 | |
151 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
152 | kfree(dev_state); |
153 | } | |
154 | ||
155 | static void put_device_state(struct device_state *dev_state) | |
156 | { | |
157 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 158 | wake_up(&dev_state->wq); |
ed96f228 JR |
159 | } |
160 | ||
028eeacc JR |
161 | static void put_device_state_wait(struct device_state *dev_state) |
162 | { | |
163 | DEFINE_WAIT(wait); | |
164 | ||
165 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
166 | if (!atomic_dec_and_test(&dev_state->count)) | |
167 | schedule(); | |
168 | finish_wait(&dev_state->wq, &wait); | |
169 | ||
170 | free_device_state(dev_state); | |
171 | } | |
8736b2c3 | 172 | |
2d5503b6 JR |
173 | /* Must be called under dev_state->lock */ |
174 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
175 | int pasid, bool alloc) | |
176 | { | |
177 | struct pasid_state **root, **ptr; | |
178 | int level, index; | |
179 | ||
180 | level = dev_state->pasid_levels; | |
181 | root = dev_state->states; | |
182 | ||
183 | while (true) { | |
184 | ||
185 | index = (pasid >> (9 * level)) & 0x1ff; | |
186 | ptr = &root[index]; | |
187 | ||
188 | if (level == 0) | |
189 | break; | |
190 | ||
191 | if (*ptr == NULL) { | |
192 | if (!alloc) | |
193 | return NULL; | |
194 | ||
195 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
196 | if (*ptr == NULL) | |
197 | return NULL; | |
198 | } | |
199 | ||
200 | root = (struct pasid_state **)*ptr; | |
201 | level -= 1; | |
202 | } | |
203 | ||
204 | return ptr; | |
205 | } | |
206 | ||
207 | static int set_pasid_state(struct device_state *dev_state, | |
208 | struct pasid_state *pasid_state, | |
209 | int pasid) | |
210 | { | |
211 | struct pasid_state **ptr; | |
212 | unsigned long flags; | |
213 | int ret; | |
214 | ||
215 | spin_lock_irqsave(&dev_state->lock, flags); | |
216 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
217 | ||
218 | ret = -ENOMEM; | |
219 | if (ptr == NULL) | |
220 | goto out_unlock; | |
221 | ||
222 | ret = -ENOMEM; | |
223 | if (*ptr != NULL) | |
224 | goto out_unlock; | |
225 | ||
226 | *ptr = pasid_state; | |
227 | ||
228 | ret = 0; | |
229 | ||
230 | out_unlock: | |
231 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
236 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
237 | { | |
238 | struct pasid_state **ptr; | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&dev_state->lock, flags); | |
242 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
243 | ||
244 | if (ptr == NULL) | |
245 | goto out_unlock; | |
246 | ||
247 | *ptr = NULL; | |
248 | ||
249 | out_unlock: | |
250 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
251 | } | |
252 | ||
253 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
254 | int pasid) | |
255 | { | |
256 | struct pasid_state **ptr, *ret = NULL; | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&dev_state->lock, flags); | |
260 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
261 | ||
262 | if (ptr == NULL) | |
263 | goto out_unlock; | |
264 | ||
265 | ret = *ptr; | |
266 | if (ret) | |
267 | atomic_inc(&ret->count); | |
268 | ||
269 | out_unlock: | |
270 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
275 | static void free_pasid_state(struct pasid_state *pasid_state) | |
276 | { | |
277 | kfree(pasid_state); | |
278 | } | |
279 | ||
280 | static void put_pasid_state(struct pasid_state *pasid_state) | |
281 | { | |
1c51099a | 282 | if (atomic_dec_and_test(&pasid_state->count)) |
028eeacc | 283 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
284 | } |
285 | ||
028eeacc JR |
286 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
287 | { | |
288 | DEFINE_WAIT(wait); | |
289 | ||
290 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
291 | ||
1c51099a | 292 | if (!atomic_dec_and_test(&pasid_state->count)) |
028eeacc JR |
293 | schedule(); |
294 | ||
295 | finish_wait(&pasid_state->wq, &wait); | |
028eeacc JR |
296 | free_pasid_state(pasid_state); |
297 | } | |
298 | ||
61feb438 | 299 | static void unbind_pasid(struct pasid_state *pasid_state) |
8736b2c3 JR |
300 | { |
301 | struct iommu_domain *domain; | |
302 | ||
303 | domain = pasid_state->device_state->domain; | |
304 | ||
53d340ef JR |
305 | /* |
306 | * Mark pasid_state as invalid, no more faults will we added to the | |
307 | * work queue after this is visible everywhere. | |
308 | */ | |
309 | pasid_state->invalid = true; | |
310 | ||
311 | /* Make sure this is visible */ | |
312 | smp_wmb(); | |
313 | ||
314 | /* After this the device/pasid can't access the mm anymore */ | |
8736b2c3 | 315 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); |
8736b2c3 JR |
316 | |
317 | /* Make sure no more pending faults are in the queue */ | |
318 | flush_workqueue(iommu_wq); | |
8736b2c3 JR |
319 | } |
320 | ||
2d5503b6 JR |
321 | static void free_pasid_states_level1(struct pasid_state **tbl) |
322 | { | |
323 | int i; | |
324 | ||
325 | for (i = 0; i < 512; ++i) { | |
326 | if (tbl[i] == NULL) | |
327 | continue; | |
328 | ||
329 | free_page((unsigned long)tbl[i]); | |
330 | } | |
331 | } | |
332 | ||
333 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
334 | { | |
335 | struct pasid_state **ptr; | |
336 | int i; | |
337 | ||
338 | for (i = 0; i < 512; ++i) { | |
339 | if (tbl[i] == NULL) | |
340 | continue; | |
341 | ||
342 | ptr = (struct pasid_state **)tbl[i]; | |
343 | free_pasid_states_level1(ptr); | |
344 | } | |
345 | } | |
346 | ||
347 | static void free_pasid_states(struct device_state *dev_state) | |
348 | { | |
349 | struct pasid_state *pasid_state; | |
350 | int i; | |
351 | ||
352 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
353 | pasid_state = get_pasid_state(dev_state, i); | |
354 | if (pasid_state == NULL) | |
355 | continue; | |
356 | ||
2d5503b6 | 357 | put_pasid_state(pasid_state); |
a40d4c67 JR |
358 | |
359 | /* | |
360 | * This will call the mn_release function and | |
361 | * unbind the PASID | |
362 | */ | |
363 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
c5db16ad JR |
364 | |
365 | put_pasid_state_wait(pasid_state); /* Reference taken in | |
daff2f9c | 366 | amd_iommu_bind_pasid */ |
75058a30 JR |
367 | |
368 | /* Drop reference taken in amd_iommu_bind_pasid */ | |
369 | put_device_state(dev_state); | |
2d5503b6 JR |
370 | } |
371 | ||
372 | if (dev_state->pasid_levels == 2) | |
373 | free_pasid_states_level2(dev_state->states); | |
374 | else if (dev_state->pasid_levels == 1) | |
375 | free_pasid_states_level1(dev_state->states); | |
376 | else if (dev_state->pasid_levels != 0) | |
377 | BUG(); | |
378 | ||
379 | free_page((unsigned long)dev_state->states); | |
380 | } | |
381 | ||
8736b2c3 JR |
382 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
383 | { | |
384 | return container_of(mn, struct pasid_state, mn); | |
385 | } | |
386 | ||
387 | static void __mn_flush_page(struct mmu_notifier *mn, | |
388 | unsigned long address) | |
389 | { | |
390 | struct pasid_state *pasid_state; | |
391 | struct device_state *dev_state; | |
392 | ||
393 | pasid_state = mn_to_state(mn); | |
394 | dev_state = pasid_state->device_state; | |
395 | ||
396 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
397 | } | |
398 | ||
399 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
400 | struct mm_struct *mm, | |
57128468 ALC |
401 | unsigned long start, |
402 | unsigned long end) | |
8736b2c3 | 403 | { |
57128468 ALC |
404 | for (; start < end; start += PAGE_SIZE) |
405 | __mn_flush_page(mn, start); | |
8736b2c3 JR |
406 | |
407 | return 0; | |
408 | } | |
409 | ||
8736b2c3 JR |
410 | static void mn_invalidate_page(struct mmu_notifier *mn, |
411 | struct mm_struct *mm, | |
412 | unsigned long address) | |
413 | { | |
414 | __mn_flush_page(mn, address); | |
415 | } | |
416 | ||
417 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
418 | struct mm_struct *mm, | |
419 | unsigned long start, unsigned long end) | |
420 | { | |
421 | struct pasid_state *pasid_state; | |
422 | struct device_state *dev_state; | |
d73a6d72 | 423 | unsigned long flags; |
8736b2c3 JR |
424 | |
425 | pasid_state = mn_to_state(mn); | |
426 | dev_state = pasid_state->device_state; | |
427 | ||
d73a6d72 JR |
428 | spin_lock_irqsave(&pasid_state->lock, flags); |
429 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
430 | amd_iommu_domain_set_gcr3(dev_state->domain, |
431 | pasid_state->pasid, | |
432 | __pa(empty_page_table)); | |
433 | } | |
d73a6d72 JR |
434 | pasid_state->mmu_notifier_count += 1; |
435 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
8736b2c3 JR |
436 | } |
437 | ||
438 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
439 | struct mm_struct *mm, | |
440 | unsigned long start, unsigned long end) | |
441 | { | |
442 | struct pasid_state *pasid_state; | |
443 | struct device_state *dev_state; | |
d73a6d72 | 444 | unsigned long flags; |
8736b2c3 JR |
445 | |
446 | pasid_state = mn_to_state(mn); | |
447 | dev_state = pasid_state->device_state; | |
448 | ||
d73a6d72 JR |
449 | spin_lock_irqsave(&pasid_state->lock, flags); |
450 | pasid_state->mmu_notifier_count -= 1; | |
451 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
452 | amd_iommu_domain_set_gcr3(dev_state->domain, |
453 | pasid_state->pasid, | |
454 | __pa(pasid_state->mm->pgd)); | |
455 | } | |
d73a6d72 | 456 | spin_unlock_irqrestore(&pasid_state->lock, flags); |
8736b2c3 JR |
457 | } |
458 | ||
a40d4c67 JR |
459 | static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm) |
460 | { | |
461 | struct pasid_state *pasid_state; | |
462 | struct device_state *dev_state; | |
d9e1611e | 463 | bool run_inv_ctx_cb; |
a40d4c67 JR |
464 | |
465 | might_sleep(); | |
466 | ||
d9e1611e JR |
467 | pasid_state = mn_to_state(mn); |
468 | dev_state = pasid_state->device_state; | |
469 | run_inv_ctx_cb = !pasid_state->invalid; | |
a40d4c67 | 470 | |
d9e1611e | 471 | if (run_inv_ctx_cb && pasid_state->device_state->inv_ctx_cb) |
a40d4c67 JR |
472 | dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid); |
473 | ||
61feb438 | 474 | unbind_pasid(pasid_state); |
a40d4c67 JR |
475 | } |
476 | ||
8736b2c3 | 477 | static struct mmu_notifier_ops iommu_mn = { |
a40d4c67 | 478 | .release = mn_release, |
8736b2c3 | 479 | .clear_flush_young = mn_clear_flush_young, |
8736b2c3 JR |
480 | .invalidate_page = mn_invalidate_page, |
481 | .invalidate_range_start = mn_invalidate_range_start, | |
482 | .invalidate_range_end = mn_invalidate_range_end, | |
483 | }; | |
484 | ||
028eeacc JR |
485 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
486 | u16 tag, int status) | |
487 | { | |
488 | unsigned long flags; | |
489 | ||
490 | spin_lock_irqsave(&pasid_state->lock, flags); | |
491 | pasid_state->pri[tag].status = status; | |
492 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
493 | } | |
494 | ||
495 | static void finish_pri_tag(struct device_state *dev_state, | |
496 | struct pasid_state *pasid_state, | |
497 | u16 tag) | |
498 | { | |
499 | unsigned long flags; | |
500 | ||
501 | spin_lock_irqsave(&pasid_state->lock, flags); | |
502 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
503 | pasid_state->pri[tag].finish) { | |
504 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
505 | pasid_state->pri[tag].status, tag); | |
506 | pasid_state->pri[tag].finish = false; | |
507 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
508 | } | |
509 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
510 | } | |
511 | ||
9dc00f4c JB |
512 | static void handle_fault_error(struct fault *fault) |
513 | { | |
514 | int status; | |
515 | ||
516 | if (!fault->dev_state->inv_ppr_cb) { | |
517 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
518 | return; | |
519 | } | |
520 | ||
521 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
522 | fault->pasid, | |
523 | fault->address, | |
524 | fault->flags); | |
525 | switch (status) { | |
526 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
527 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
528 | break; | |
529 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
530 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
531 | break; | |
532 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
533 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
534 | break; | |
535 | default: | |
536 | BUG(); | |
537 | } | |
538 | } | |
539 | ||
028eeacc JR |
540 | static void do_fault(struct work_struct *work) |
541 | { | |
542 | struct fault *fault = container_of(work, struct fault, work); | |
9dc00f4c JB |
543 | struct mm_struct *mm; |
544 | struct vm_area_struct *vma; | |
545 | u64 address; | |
546 | int ret, write; | |
028eeacc JR |
547 | |
548 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
549 | ||
9dc00f4c JB |
550 | mm = fault->state->mm; |
551 | address = fault->address; | |
552 | ||
553 | down_read(&mm->mmap_sem); | |
554 | vma = find_extend_vma(mm, address); | |
555 | if (!vma || address < vma->vm_start) { | |
556 | /* failed to get a vma in the right range */ | |
557 | up_read(&mm->mmap_sem); | |
558 | handle_fault_error(fault); | |
559 | goto out; | |
175d6146 | 560 | } |
028eeacc | 561 | |
9dc00f4c JB |
562 | ret = handle_mm_fault(mm, vma, address, write); |
563 | if (ret & VM_FAULT_ERROR) { | |
564 | /* failed to service fault */ | |
565 | up_read(&mm->mmap_sem); | |
566 | handle_fault_error(fault); | |
567 | goto out; | |
568 | } | |
569 | ||
570 | up_read(&mm->mmap_sem); | |
571 | ||
572 | out: | |
028eeacc JR |
573 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); |
574 | ||
575 | put_pasid_state(fault->state); | |
576 | ||
577 | kfree(fault); | |
578 | } | |
579 | ||
580 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
581 | { | |
582 | struct amd_iommu_fault *iommu_fault; | |
583 | struct pasid_state *pasid_state; | |
584 | struct device_state *dev_state; | |
585 | unsigned long flags; | |
586 | struct fault *fault; | |
587 | bool finish; | |
588 | u16 tag; | |
589 | int ret; | |
590 | ||
591 | iommu_fault = data; | |
592 | tag = iommu_fault->tag & 0x1ff; | |
593 | finish = (iommu_fault->tag >> 9) & 1; | |
594 | ||
595 | ret = NOTIFY_DONE; | |
596 | dev_state = get_device_state(iommu_fault->device_id); | |
597 | if (dev_state == NULL) | |
598 | goto out; | |
599 | ||
600 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
53d340ef | 601 | if (pasid_state == NULL || pasid_state->invalid) { |
028eeacc JR |
602 | /* We know the device but not the PASID -> send INVALID */ |
603 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
604 | PPR_INVALID, tag); | |
605 | goto out_drop_state; | |
606 | } | |
607 | ||
608 | spin_lock_irqsave(&pasid_state->lock, flags); | |
609 | atomic_inc(&pasid_state->pri[tag].inflight); | |
610 | if (finish) | |
611 | pasid_state->pri[tag].finish = true; | |
612 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
613 | ||
614 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
615 | if (fault == NULL) { | |
616 | /* We are OOM - send success and let the device re-fault */ | |
617 | finish_pri_tag(dev_state, pasid_state, tag); | |
618 | goto out_drop_state; | |
619 | } | |
620 | ||
621 | fault->dev_state = dev_state; | |
622 | fault->address = iommu_fault->address; | |
623 | fault->state = pasid_state; | |
624 | fault->tag = tag; | |
625 | fault->finish = finish; | |
b00675b8 | 626 | fault->pasid = iommu_fault->pasid; |
028eeacc JR |
627 | fault->flags = iommu_fault->flags; |
628 | INIT_WORK(&fault->work, do_fault); | |
629 | ||
630 | queue_work(iommu_wq, &fault->work); | |
631 | ||
632 | ret = NOTIFY_OK; | |
633 | ||
634 | out_drop_state: | |
dc88db7e JR |
635 | |
636 | if (ret != NOTIFY_OK && pasid_state) | |
637 | put_pasid_state(pasid_state); | |
638 | ||
028eeacc JR |
639 | put_device_state(dev_state); |
640 | ||
641 | out: | |
642 | return ret; | |
643 | } | |
644 | ||
645 | static struct notifier_block ppr_nb = { | |
646 | .notifier_call = ppr_notifier, | |
647 | }; | |
648 | ||
2d5503b6 JR |
649 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
650 | struct task_struct *task) | |
651 | { | |
652 | struct pasid_state *pasid_state; | |
653 | struct device_state *dev_state; | |
f0aac63b | 654 | struct mm_struct *mm; |
2d5503b6 JR |
655 | u16 devid; |
656 | int ret; | |
657 | ||
658 | might_sleep(); | |
659 | ||
660 | if (!amd_iommu_v2_supported()) | |
661 | return -ENODEV; | |
662 | ||
663 | devid = device_id(pdev); | |
664 | dev_state = get_device_state(devid); | |
665 | ||
666 | if (dev_state == NULL) | |
667 | return -EINVAL; | |
668 | ||
669 | ret = -EINVAL; | |
670 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
671 | goto out; | |
672 | ||
673 | ret = -ENOMEM; | |
674 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
675 | if (pasid_state == NULL) | |
676 | goto out; | |
677 | ||
f0aac63b | 678 | |
2d5503b6 | 679 | atomic_set(&pasid_state->count, 1); |
028eeacc | 680 | init_waitqueue_head(&pasid_state->wq); |
2c13d47a JR |
681 | spin_lock_init(&pasid_state->lock); |
682 | ||
f0aac63b | 683 | mm = get_task_mm(task); |
f0aac63b | 684 | pasid_state->mm = mm; |
2d5503b6 JR |
685 | pasid_state->device_state = dev_state; |
686 | pasid_state->pasid = pasid; | |
d9e1611e JR |
687 | pasid_state->invalid = true; /* Mark as valid only if we are |
688 | done with setting up the pasid */ | |
8736b2c3 | 689 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
690 | |
691 | if (pasid_state->mm == NULL) | |
692 | goto out_free; | |
693 | ||
f0aac63b | 694 | mmu_notifier_register(&pasid_state->mn, mm); |
8736b2c3 | 695 | |
2d5503b6 JR |
696 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
697 | if (ret) | |
8736b2c3 | 698 | goto out_unregister; |
2d5503b6 JR |
699 | |
700 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
701 | __pa(pasid_state->mm->pgd)); | |
702 | if (ret) | |
703 | goto out_clear_state; | |
704 | ||
d9e1611e JR |
705 | /* Now we are ready to handle faults */ |
706 | pasid_state->invalid = false; | |
707 | ||
f0aac63b JR |
708 | /* |
709 | * Drop the reference to the mm_struct here. We rely on the | |
710 | * mmu_notifier release call-back to inform us when the mm | |
711 | * is going away. | |
712 | */ | |
713 | mmput(mm); | |
714 | ||
2d5503b6 JR |
715 | return 0; |
716 | ||
717 | out_clear_state: | |
718 | clear_pasid_state(dev_state, pasid); | |
719 | ||
8736b2c3 | 720 | out_unregister: |
f0aac63b | 721 | mmu_notifier_unregister(&pasid_state->mn, mm); |
8736b2c3 | 722 | |
2d5503b6 | 723 | out_free: |
f0aac63b | 724 | mmput(mm); |
028eeacc | 725 | free_pasid_state(pasid_state); |
2d5503b6 JR |
726 | |
727 | out: | |
728 | put_device_state(dev_state); | |
729 | ||
730 | return ret; | |
731 | } | |
732 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
733 | ||
734 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
735 | { | |
a40d4c67 | 736 | struct pasid_state *pasid_state; |
2d5503b6 JR |
737 | struct device_state *dev_state; |
738 | u16 devid; | |
739 | ||
740 | might_sleep(); | |
741 | ||
742 | if (!amd_iommu_v2_supported()) | |
743 | return; | |
744 | ||
745 | devid = device_id(pdev); | |
746 | dev_state = get_device_state(devid); | |
747 | if (dev_state == NULL) | |
748 | return; | |
749 | ||
750 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
751 | goto out; | |
752 | ||
a40d4c67 JR |
753 | pasid_state = get_pasid_state(dev_state, pasid); |
754 | if (pasid_state == NULL) | |
755 | goto out; | |
756 | /* | |
757 | * Drop reference taken here. We are safe because we still hold | |
758 | * the reference taken in the amd_iommu_bind_pasid function. | |
759 | */ | |
760 | put_pasid_state(pasid_state); | |
761 | ||
53d340ef JR |
762 | /* Clear the pasid state so that the pasid can be re-used */ |
763 | clear_pasid_state(dev_state, pasid_state->pasid); | |
764 | ||
f0aac63b | 765 | /* |
fcaa9606 JR |
766 | * Call mmu_notifier_unregister to drop our reference |
767 | * to pasid_state->mm | |
f0aac63b | 768 | */ |
fcaa9606 | 769 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); |
2d5503b6 | 770 | |
c5db16ad | 771 | put_pasid_state_wait(pasid_state); /* Reference taken in |
daff2f9c | 772 | amd_iommu_bind_pasid */ |
2d5503b6 | 773 | out: |
75058a30 JR |
774 | /* Drop reference taken in this function */ |
775 | put_device_state(dev_state); | |
776 | ||
777 | /* Drop reference taken in amd_iommu_bind_pasid */ | |
2d5503b6 JR |
778 | put_device_state(dev_state); |
779 | } | |
780 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
781 | ||
ed96f228 JR |
782 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
783 | { | |
784 | struct device_state *dev_state; | |
785 | unsigned long flags; | |
786 | int ret, tmp; | |
787 | u16 devid; | |
788 | ||
789 | might_sleep(); | |
790 | ||
791 | if (!amd_iommu_v2_supported()) | |
792 | return -ENODEV; | |
793 | ||
794 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
795 | return -EINVAL; | |
796 | ||
797 | devid = device_id(pdev); | |
798 | ||
799 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
800 | if (dev_state == NULL) | |
801 | return -ENOMEM; | |
802 | ||
803 | spin_lock_init(&dev_state->lock); | |
028eeacc | 804 | init_waitqueue_head(&dev_state->wq); |
741669c7 JR |
805 | dev_state->pdev = pdev; |
806 | dev_state->devid = devid; | |
ed96f228 JR |
807 | |
808 | tmp = pasids; | |
809 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
810 | dev_state->pasid_levels += 1; | |
811 | ||
812 | atomic_set(&dev_state->count, 1); | |
813 | dev_state->max_pasids = pasids; | |
814 | ||
815 | ret = -ENOMEM; | |
816 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
817 | if (dev_state->states == NULL) | |
818 | goto out_free_dev_state; | |
819 | ||
820 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
821 | if (dev_state->domain == NULL) | |
822 | goto out_free_states; | |
823 | ||
824 | amd_iommu_domain_direct_map(dev_state->domain); | |
825 | ||
826 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
827 | if (ret) | |
828 | goto out_free_domain; | |
829 | ||
830 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
831 | if (ret != 0) | |
832 | goto out_free_domain; | |
833 | ||
834 | spin_lock_irqsave(&state_lock, flags); | |
835 | ||
741669c7 | 836 | if (__get_device_state(devid) != NULL) { |
ed96f228 JR |
837 | spin_unlock_irqrestore(&state_lock, flags); |
838 | ret = -EBUSY; | |
839 | goto out_free_domain; | |
840 | } | |
841 | ||
741669c7 | 842 | list_add_tail(&dev_state->list, &state_list); |
ed96f228 JR |
843 | |
844 | spin_unlock_irqrestore(&state_lock, flags); | |
845 | ||
846 | return 0; | |
847 | ||
848 | out_free_domain: | |
849 | iommu_domain_free(dev_state->domain); | |
850 | ||
851 | out_free_states: | |
852 | free_page((unsigned long)dev_state->states); | |
853 | ||
854 | out_free_dev_state: | |
855 | kfree(dev_state); | |
856 | ||
857 | return ret; | |
858 | } | |
859 | EXPORT_SYMBOL(amd_iommu_init_device); | |
860 | ||
861 | void amd_iommu_free_device(struct pci_dev *pdev) | |
862 | { | |
863 | struct device_state *dev_state; | |
864 | unsigned long flags; | |
865 | u16 devid; | |
866 | ||
867 | if (!amd_iommu_v2_supported()) | |
868 | return; | |
869 | ||
870 | devid = device_id(pdev); | |
871 | ||
872 | spin_lock_irqsave(&state_lock, flags); | |
873 | ||
b87d2d7c | 874 | dev_state = __get_device_state(devid); |
ed96f228 JR |
875 | if (dev_state == NULL) { |
876 | spin_unlock_irqrestore(&state_lock, flags); | |
877 | return; | |
878 | } | |
879 | ||
741669c7 | 880 | list_del(&dev_state->list); |
ed96f228 JR |
881 | |
882 | spin_unlock_irqrestore(&state_lock, flags); | |
883 | ||
2d5503b6 JR |
884 | /* Get rid of any remaining pasid states */ |
885 | free_pasid_states(dev_state); | |
886 | ||
028eeacc | 887 | put_device_state_wait(dev_state); |
ed96f228 JR |
888 | } |
889 | EXPORT_SYMBOL(amd_iommu_free_device); | |
890 | ||
175d6146 JR |
891 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
892 | amd_iommu_invalid_ppr_cb cb) | |
893 | { | |
894 | struct device_state *dev_state; | |
895 | unsigned long flags; | |
896 | u16 devid; | |
897 | int ret; | |
898 | ||
899 | if (!amd_iommu_v2_supported()) | |
900 | return -ENODEV; | |
901 | ||
902 | devid = device_id(pdev); | |
903 | ||
904 | spin_lock_irqsave(&state_lock, flags); | |
905 | ||
906 | ret = -EINVAL; | |
b87d2d7c | 907 | dev_state = __get_device_state(devid); |
175d6146 JR |
908 | if (dev_state == NULL) |
909 | goto out_unlock; | |
910 | ||
911 | dev_state->inv_ppr_cb = cb; | |
912 | ||
913 | ret = 0; | |
914 | ||
915 | out_unlock: | |
916 | spin_unlock_irqrestore(&state_lock, flags); | |
917 | ||
918 | return ret; | |
919 | } | |
920 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
921 | ||
bc21662f JR |
922 | int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
923 | amd_iommu_invalidate_ctx cb) | |
924 | { | |
925 | struct device_state *dev_state; | |
926 | unsigned long flags; | |
927 | u16 devid; | |
928 | int ret; | |
929 | ||
930 | if (!amd_iommu_v2_supported()) | |
931 | return -ENODEV; | |
932 | ||
933 | devid = device_id(pdev); | |
934 | ||
935 | spin_lock_irqsave(&state_lock, flags); | |
936 | ||
937 | ret = -EINVAL; | |
b87d2d7c | 938 | dev_state = __get_device_state(devid); |
bc21662f JR |
939 | if (dev_state == NULL) |
940 | goto out_unlock; | |
941 | ||
942 | dev_state->inv_ctx_cb = cb; | |
943 | ||
944 | ret = 0; | |
945 | ||
946 | out_unlock: | |
947 | spin_unlock_irqrestore(&state_lock, flags); | |
948 | ||
949 | return ret; | |
950 | } | |
951 | EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb); | |
952 | ||
e3c495c7 JR |
953 | static int __init amd_iommu_v2_init(void) |
954 | { | |
028eeacc | 955 | int ret; |
ed96f228 | 956 | |
474d567d JR |
957 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n"); |
958 | ||
959 | if (!amd_iommu_v2_supported()) { | |
07db0409 | 960 | pr_info("AMD IOMMUv2 functionality not available on this system\n"); |
474d567d JR |
961 | /* |
962 | * Load anyway to provide the symbols to other modules | |
963 | * which may use AMD IOMMUv2 optionally. | |
964 | */ | |
965 | return 0; | |
966 | } | |
e3c495c7 | 967 | |
ed96f228 JR |
968 | spin_lock_init(&state_lock); |
969 | ||
028eeacc JR |
970 | ret = -ENOMEM; |
971 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 972 | if (iommu_wq == NULL) |
741669c7 | 973 | goto out; |
8736b2c3 JR |
974 | |
975 | ret = -ENOMEM; | |
976 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
977 | if (empty_page_table == NULL) | |
978 | goto out_destroy_wq; | |
028eeacc JR |
979 | |
980 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
981 | ||
e3c495c7 | 982 | return 0; |
028eeacc | 983 | |
8736b2c3 JR |
984 | out_destroy_wq: |
985 | destroy_workqueue(iommu_wq); | |
986 | ||
741669c7 | 987 | out: |
028eeacc | 988 | return ret; |
e3c495c7 JR |
989 | } |
990 | ||
991 | static void __exit amd_iommu_v2_exit(void) | |
992 | { | |
ed96f228 | 993 | struct device_state *dev_state; |
ed96f228 JR |
994 | int i; |
995 | ||
474d567d JR |
996 | if (!amd_iommu_v2_supported()) |
997 | return; | |
998 | ||
028eeacc JR |
999 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
1000 | ||
1001 | flush_workqueue(iommu_wq); | |
1002 | ||
1003 | /* | |
1004 | * The loop below might call flush_workqueue(), so call | |
1005 | * destroy_workqueue() after it | |
1006 | */ | |
ed96f228 JR |
1007 | for (i = 0; i < MAX_DEVICES; ++i) { |
1008 | dev_state = get_device_state(i); | |
1009 | ||
1010 | if (dev_state == NULL) | |
1011 | continue; | |
1012 | ||
1013 | WARN_ON_ONCE(1); | |
1014 | ||
ed96f228 | 1015 | put_device_state(dev_state); |
028eeacc | 1016 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
1017 | } |
1018 | ||
028eeacc JR |
1019 | destroy_workqueue(iommu_wq); |
1020 | ||
8736b2c3 | 1021 | free_page((unsigned long)empty_page_table); |
e3c495c7 JR |
1022 | } |
1023 | ||
1024 | module_init(amd_iommu_v2_init); | |
1025 | module_exit(amd_iommu_v2_exit); |