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e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
48 | struct task_struct *task; /* Task bound to this PASID */ | |
49 | struct mm_struct *mm; /* mm_struct for the faults */ | |
8736b2c3 | 50 | struct mmu_notifier mn; /* mmu_otifier handle */ |
ed96f228 JR |
51 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
52 | struct device_state *device_state; /* Link to our device_state */ | |
53 | int pasid; /* PASID index */ | |
028eeacc JR |
54 | spinlock_t lock; /* Protect pri_queues */ |
55 | wait_queue_head_t wq; /* To wait for count == 0 */ | |
ed96f228 JR |
56 | }; |
57 | ||
58 | struct device_state { | |
59 | atomic_t count; | |
60 | struct pci_dev *pdev; | |
61 | struct pasid_state **states; | |
62 | struct iommu_domain *domain; | |
63 | int pasid_levels; | |
64 | int max_pasids; | |
175d6146 | 65 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
ed96f228 | 66 | spinlock_t lock; |
028eeacc JR |
67 | wait_queue_head_t wq; |
68 | }; | |
69 | ||
70 | struct fault { | |
71 | struct work_struct work; | |
72 | struct device_state *dev_state; | |
73 | struct pasid_state *state; | |
74 | struct mm_struct *mm; | |
75 | u64 address; | |
76 | u16 devid; | |
77 | u16 pasid; | |
78 | u16 tag; | |
79 | u16 finish; | |
80 | u16 flags; | |
ed96f228 JR |
81 | }; |
82 | ||
83 | struct device_state **state_table; | |
84 | static spinlock_t state_lock; | |
85 | ||
86 | /* List and lock for all pasid_states */ | |
87 | static LIST_HEAD(pasid_state_list); | |
2d5503b6 JR |
88 | static DEFINE_SPINLOCK(ps_lock); |
89 | ||
028eeacc JR |
90 | static struct workqueue_struct *iommu_wq; |
91 | ||
8736b2c3 JR |
92 | /* |
93 | * Empty page table - Used between | |
94 | * mmu_notifier_invalidate_range_start and | |
95 | * mmu_notifier_invalidate_range_end | |
96 | */ | |
97 | static u64 *empty_page_table; | |
98 | ||
2d5503b6 JR |
99 | static void free_pasid_states(struct device_state *dev_state); |
100 | static void unbind_pasid(struct device_state *dev_state, int pasid); | |
8736b2c3 | 101 | static int task_exit(struct notifier_block *nb, unsigned long e, void *data); |
ed96f228 JR |
102 | |
103 | static u16 device_id(struct pci_dev *pdev) | |
104 | { | |
105 | u16 devid; | |
106 | ||
107 | devid = pdev->bus->number; | |
108 | devid = (devid << 8) | pdev->devfn; | |
109 | ||
110 | return devid; | |
111 | } | |
112 | ||
113 | static struct device_state *get_device_state(u16 devid) | |
114 | { | |
115 | struct device_state *dev_state; | |
116 | unsigned long flags; | |
117 | ||
118 | spin_lock_irqsave(&state_lock, flags); | |
119 | dev_state = state_table[devid]; | |
120 | if (dev_state != NULL) | |
121 | atomic_inc(&dev_state->count); | |
122 | spin_unlock_irqrestore(&state_lock, flags); | |
123 | ||
124 | return dev_state; | |
125 | } | |
126 | ||
127 | static void free_device_state(struct device_state *dev_state) | |
128 | { | |
2d5503b6 JR |
129 | /* |
130 | * First detach device from domain - No more PRI requests will arrive | |
131 | * from that device after it is unbound from the IOMMUv2 domain. | |
132 | */ | |
ed96f228 | 133 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
134 | |
135 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 136 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
137 | |
138 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
139 | kfree(dev_state); |
140 | } | |
141 | ||
142 | static void put_device_state(struct device_state *dev_state) | |
143 | { | |
144 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 145 | wake_up(&dev_state->wq); |
ed96f228 JR |
146 | } |
147 | ||
028eeacc JR |
148 | static void put_device_state_wait(struct device_state *dev_state) |
149 | { | |
150 | DEFINE_WAIT(wait); | |
151 | ||
152 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
153 | if (!atomic_dec_and_test(&dev_state->count)) | |
154 | schedule(); | |
155 | finish_wait(&dev_state->wq, &wait); | |
156 | ||
157 | free_device_state(dev_state); | |
158 | } | |
8736b2c3 JR |
159 | |
160 | static struct notifier_block profile_nb = { | |
161 | .notifier_call = task_exit, | |
162 | }; | |
163 | ||
2d5503b6 JR |
164 | static void link_pasid_state(struct pasid_state *pasid_state) |
165 | { | |
166 | spin_lock(&ps_lock); | |
167 | list_add_tail(&pasid_state->list, &pasid_state_list); | |
168 | spin_unlock(&ps_lock); | |
169 | } | |
170 | ||
171 | static void __unlink_pasid_state(struct pasid_state *pasid_state) | |
172 | { | |
173 | list_del(&pasid_state->list); | |
174 | } | |
175 | ||
176 | static void unlink_pasid_state(struct pasid_state *pasid_state) | |
177 | { | |
178 | spin_lock(&ps_lock); | |
179 | __unlink_pasid_state(pasid_state); | |
180 | spin_unlock(&ps_lock); | |
181 | } | |
182 | ||
183 | /* Must be called under dev_state->lock */ | |
184 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
185 | int pasid, bool alloc) | |
186 | { | |
187 | struct pasid_state **root, **ptr; | |
188 | int level, index; | |
189 | ||
190 | level = dev_state->pasid_levels; | |
191 | root = dev_state->states; | |
192 | ||
193 | while (true) { | |
194 | ||
195 | index = (pasid >> (9 * level)) & 0x1ff; | |
196 | ptr = &root[index]; | |
197 | ||
198 | if (level == 0) | |
199 | break; | |
200 | ||
201 | if (*ptr == NULL) { | |
202 | if (!alloc) | |
203 | return NULL; | |
204 | ||
205 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
206 | if (*ptr == NULL) | |
207 | return NULL; | |
208 | } | |
209 | ||
210 | root = (struct pasid_state **)*ptr; | |
211 | level -= 1; | |
212 | } | |
213 | ||
214 | return ptr; | |
215 | } | |
216 | ||
217 | static int set_pasid_state(struct device_state *dev_state, | |
218 | struct pasid_state *pasid_state, | |
219 | int pasid) | |
220 | { | |
221 | struct pasid_state **ptr; | |
222 | unsigned long flags; | |
223 | int ret; | |
224 | ||
225 | spin_lock_irqsave(&dev_state->lock, flags); | |
226 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
227 | ||
228 | ret = -ENOMEM; | |
229 | if (ptr == NULL) | |
230 | goto out_unlock; | |
231 | ||
232 | ret = -ENOMEM; | |
233 | if (*ptr != NULL) | |
234 | goto out_unlock; | |
235 | ||
236 | *ptr = pasid_state; | |
237 | ||
238 | ret = 0; | |
239 | ||
240 | out_unlock: | |
241 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
246 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
247 | { | |
248 | struct pasid_state **ptr; | |
249 | unsigned long flags; | |
250 | ||
251 | spin_lock_irqsave(&dev_state->lock, flags); | |
252 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
253 | ||
254 | if (ptr == NULL) | |
255 | goto out_unlock; | |
256 | ||
257 | *ptr = NULL; | |
258 | ||
259 | out_unlock: | |
260 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
261 | } | |
262 | ||
263 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
264 | int pasid) | |
265 | { | |
266 | struct pasid_state **ptr, *ret = NULL; | |
267 | unsigned long flags; | |
268 | ||
269 | spin_lock_irqsave(&dev_state->lock, flags); | |
270 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
271 | ||
272 | if (ptr == NULL) | |
273 | goto out_unlock; | |
274 | ||
275 | ret = *ptr; | |
276 | if (ret) | |
277 | atomic_inc(&ret->count); | |
278 | ||
279 | out_unlock: | |
280 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
281 | ||
282 | return ret; | |
283 | } | |
284 | ||
285 | static void free_pasid_state(struct pasid_state *pasid_state) | |
286 | { | |
287 | kfree(pasid_state); | |
288 | } | |
289 | ||
290 | static void put_pasid_state(struct pasid_state *pasid_state) | |
291 | { | |
292 | if (atomic_dec_and_test(&pasid_state->count)) { | |
293 | put_device_state(pasid_state->device_state); | |
028eeacc | 294 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
295 | } |
296 | } | |
297 | ||
028eeacc JR |
298 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
299 | { | |
300 | DEFINE_WAIT(wait); | |
301 | ||
302 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
303 | ||
304 | if (atomic_dec_and_test(&pasid_state->count)) | |
305 | put_device_state(pasid_state->device_state); | |
306 | else | |
307 | schedule(); | |
308 | ||
309 | finish_wait(&pasid_state->wq, &wait); | |
310 | mmput(pasid_state->mm); | |
311 | free_pasid_state(pasid_state); | |
312 | } | |
313 | ||
8736b2c3 JR |
314 | static void __unbind_pasid(struct pasid_state *pasid_state) |
315 | { | |
316 | struct iommu_domain *domain; | |
317 | ||
318 | domain = pasid_state->device_state->domain; | |
319 | ||
320 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); | |
321 | clear_pasid_state(pasid_state->device_state, pasid_state->pasid); | |
322 | ||
323 | /* Make sure no more pending faults are in the queue */ | |
324 | flush_workqueue(iommu_wq); | |
325 | ||
326 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
327 | ||
328 | put_pasid_state(pasid_state); /* Reference taken in bind() function */ | |
329 | } | |
330 | ||
2d5503b6 JR |
331 | static void unbind_pasid(struct device_state *dev_state, int pasid) |
332 | { | |
333 | struct pasid_state *pasid_state; | |
334 | ||
335 | pasid_state = get_pasid_state(dev_state, pasid); | |
336 | if (pasid_state == NULL) | |
337 | return; | |
338 | ||
339 | unlink_pasid_state(pasid_state); | |
8736b2c3 JR |
340 | __unbind_pasid(pasid_state); |
341 | put_pasid_state_wait(pasid_state); /* Reference taken in this function */ | |
2d5503b6 JR |
342 | } |
343 | ||
344 | static void free_pasid_states_level1(struct pasid_state **tbl) | |
345 | { | |
346 | int i; | |
347 | ||
348 | for (i = 0; i < 512; ++i) { | |
349 | if (tbl[i] == NULL) | |
350 | continue; | |
351 | ||
352 | free_page((unsigned long)tbl[i]); | |
353 | } | |
354 | } | |
355 | ||
356 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
357 | { | |
358 | struct pasid_state **ptr; | |
359 | int i; | |
360 | ||
361 | for (i = 0; i < 512; ++i) { | |
362 | if (tbl[i] == NULL) | |
363 | continue; | |
364 | ||
365 | ptr = (struct pasid_state **)tbl[i]; | |
366 | free_pasid_states_level1(ptr); | |
367 | } | |
368 | } | |
369 | ||
370 | static void free_pasid_states(struct device_state *dev_state) | |
371 | { | |
372 | struct pasid_state *pasid_state; | |
373 | int i; | |
374 | ||
375 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
376 | pasid_state = get_pasid_state(dev_state, i); | |
377 | if (pasid_state == NULL) | |
378 | continue; | |
379 | ||
2d5503b6 | 380 | put_pasid_state(pasid_state); |
028eeacc | 381 | unbind_pasid(dev_state, i); |
2d5503b6 JR |
382 | } |
383 | ||
384 | if (dev_state->pasid_levels == 2) | |
385 | free_pasid_states_level2(dev_state->states); | |
386 | else if (dev_state->pasid_levels == 1) | |
387 | free_pasid_states_level1(dev_state->states); | |
388 | else if (dev_state->pasid_levels != 0) | |
389 | BUG(); | |
390 | ||
391 | free_page((unsigned long)dev_state->states); | |
392 | } | |
393 | ||
8736b2c3 JR |
394 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
395 | { | |
396 | return container_of(mn, struct pasid_state, mn); | |
397 | } | |
398 | ||
399 | static void __mn_flush_page(struct mmu_notifier *mn, | |
400 | unsigned long address) | |
401 | { | |
402 | struct pasid_state *pasid_state; | |
403 | struct device_state *dev_state; | |
404 | ||
405 | pasid_state = mn_to_state(mn); | |
406 | dev_state = pasid_state->device_state; | |
407 | ||
408 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
409 | } | |
410 | ||
411 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
412 | struct mm_struct *mm, | |
413 | unsigned long address) | |
414 | { | |
415 | __mn_flush_page(mn, address); | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static void mn_change_pte(struct mmu_notifier *mn, | |
421 | struct mm_struct *mm, | |
422 | unsigned long address, | |
423 | pte_t pte) | |
424 | { | |
425 | __mn_flush_page(mn, address); | |
426 | } | |
427 | ||
428 | static void mn_invalidate_page(struct mmu_notifier *mn, | |
429 | struct mm_struct *mm, | |
430 | unsigned long address) | |
431 | { | |
432 | __mn_flush_page(mn, address); | |
433 | } | |
434 | ||
435 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
436 | struct mm_struct *mm, | |
437 | unsigned long start, unsigned long end) | |
438 | { | |
439 | struct pasid_state *pasid_state; | |
440 | struct device_state *dev_state; | |
441 | ||
442 | pasid_state = mn_to_state(mn); | |
443 | dev_state = pasid_state->device_state; | |
444 | ||
445 | amd_iommu_domain_set_gcr3(dev_state->domain, pasid_state->pasid, | |
446 | __pa(empty_page_table)); | |
447 | } | |
448 | ||
449 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
450 | struct mm_struct *mm, | |
451 | unsigned long start, unsigned long end) | |
452 | { | |
453 | struct pasid_state *pasid_state; | |
454 | struct device_state *dev_state; | |
455 | ||
456 | pasid_state = mn_to_state(mn); | |
457 | dev_state = pasid_state->device_state; | |
458 | ||
459 | amd_iommu_domain_set_gcr3(dev_state->domain, pasid_state->pasid, | |
460 | __pa(pasid_state->mm->pgd)); | |
461 | } | |
462 | ||
463 | static struct mmu_notifier_ops iommu_mn = { | |
464 | .clear_flush_young = mn_clear_flush_young, | |
465 | .change_pte = mn_change_pte, | |
466 | .invalidate_page = mn_invalidate_page, | |
467 | .invalidate_range_start = mn_invalidate_range_start, | |
468 | .invalidate_range_end = mn_invalidate_range_end, | |
469 | }; | |
470 | ||
028eeacc JR |
471 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
472 | u16 tag, int status) | |
473 | { | |
474 | unsigned long flags; | |
475 | ||
476 | spin_lock_irqsave(&pasid_state->lock, flags); | |
477 | pasid_state->pri[tag].status = status; | |
478 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
479 | } | |
480 | ||
481 | static void finish_pri_tag(struct device_state *dev_state, | |
482 | struct pasid_state *pasid_state, | |
483 | u16 tag) | |
484 | { | |
485 | unsigned long flags; | |
486 | ||
487 | spin_lock_irqsave(&pasid_state->lock, flags); | |
488 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
489 | pasid_state->pri[tag].finish) { | |
490 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
491 | pasid_state->pri[tag].status, tag); | |
492 | pasid_state->pri[tag].finish = false; | |
493 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
494 | } | |
495 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
496 | } | |
497 | ||
498 | static void do_fault(struct work_struct *work) | |
499 | { | |
500 | struct fault *fault = container_of(work, struct fault, work); | |
501 | int npages, write; | |
502 | struct page *page; | |
503 | ||
504 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
505 | ||
506 | npages = get_user_pages(fault->state->task, fault->state->mm, | |
507 | fault->address, 1, write, 0, &page, NULL); | |
508 | ||
175d6146 | 509 | if (npages == 1) { |
028eeacc | 510 | put_page(page); |
175d6146 JR |
511 | } else if (fault->dev_state->inv_ppr_cb) { |
512 | int status; | |
513 | ||
514 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
515 | fault->pasid, | |
516 | fault->address, | |
517 | fault->flags); | |
518 | switch (status) { | |
519 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
520 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
521 | break; | |
522 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
523 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
524 | break; | |
525 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
526 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
527 | break; | |
528 | default: | |
529 | BUG(); | |
530 | } | |
531 | } else { | |
028eeacc | 532 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); |
175d6146 | 533 | } |
028eeacc JR |
534 | |
535 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
536 | ||
537 | put_pasid_state(fault->state); | |
538 | ||
539 | kfree(fault); | |
540 | } | |
541 | ||
542 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
543 | { | |
544 | struct amd_iommu_fault *iommu_fault; | |
545 | struct pasid_state *pasid_state; | |
546 | struct device_state *dev_state; | |
547 | unsigned long flags; | |
548 | struct fault *fault; | |
549 | bool finish; | |
550 | u16 tag; | |
551 | int ret; | |
552 | ||
553 | iommu_fault = data; | |
554 | tag = iommu_fault->tag & 0x1ff; | |
555 | finish = (iommu_fault->tag >> 9) & 1; | |
556 | ||
557 | ret = NOTIFY_DONE; | |
558 | dev_state = get_device_state(iommu_fault->device_id); | |
559 | if (dev_state == NULL) | |
560 | goto out; | |
561 | ||
562 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
563 | if (pasid_state == NULL) { | |
564 | /* We know the device but not the PASID -> send INVALID */ | |
565 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
566 | PPR_INVALID, tag); | |
567 | goto out_drop_state; | |
568 | } | |
569 | ||
570 | spin_lock_irqsave(&pasid_state->lock, flags); | |
571 | atomic_inc(&pasid_state->pri[tag].inflight); | |
572 | if (finish) | |
573 | pasid_state->pri[tag].finish = true; | |
574 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
575 | ||
576 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
577 | if (fault == NULL) { | |
578 | /* We are OOM - send success and let the device re-fault */ | |
579 | finish_pri_tag(dev_state, pasid_state, tag); | |
580 | goto out_drop_state; | |
581 | } | |
582 | ||
583 | fault->dev_state = dev_state; | |
584 | fault->address = iommu_fault->address; | |
585 | fault->state = pasid_state; | |
586 | fault->tag = tag; | |
587 | fault->finish = finish; | |
588 | fault->flags = iommu_fault->flags; | |
589 | INIT_WORK(&fault->work, do_fault); | |
590 | ||
591 | queue_work(iommu_wq, &fault->work); | |
592 | ||
593 | ret = NOTIFY_OK; | |
594 | ||
595 | out_drop_state: | |
596 | put_device_state(dev_state); | |
597 | ||
598 | out: | |
599 | return ret; | |
600 | } | |
601 | ||
602 | static struct notifier_block ppr_nb = { | |
603 | .notifier_call = ppr_notifier, | |
604 | }; | |
605 | ||
8736b2c3 JR |
606 | static int task_exit(struct notifier_block *nb, unsigned long e, void *data) |
607 | { | |
608 | struct pasid_state *pasid_state; | |
609 | struct task_struct *task; | |
610 | ||
611 | task = data; | |
612 | ||
613 | /* | |
614 | * Using this notifier is a hack - but there is no other choice | |
615 | * at the moment. What I really want is a sleeping notifier that | |
616 | * is called when an MM goes down. But such a notifier doesn't | |
617 | * exist yet. The notifier needs to sleep because it has to make | |
618 | * sure that the device does not use the PASID and the address | |
619 | * space anymore before it is destroyed. This includes waiting | |
620 | * for pending PRI requests to pass the workqueue. The | |
621 | * MMU-Notifiers would be a good fit, but they use RCU and so | |
622 | * they are not allowed to sleep. Lets see how we can solve this | |
623 | * in a more intelligent way in the future. | |
624 | */ | |
625 | again: | |
626 | spin_lock(&ps_lock); | |
627 | list_for_each_entry(pasid_state, &pasid_state_list, list) { | |
628 | struct device_state *dev_state; | |
629 | int pasid; | |
630 | ||
631 | if (pasid_state->task != task) | |
632 | continue; | |
633 | ||
634 | /* Drop Lock and unbind */ | |
635 | spin_unlock(&ps_lock); | |
636 | ||
637 | dev_state = pasid_state->device_state; | |
638 | pasid = pasid_state->pasid; | |
639 | ||
640 | unbind_pasid(dev_state, pasid); | |
641 | ||
642 | /* Task may be in the list multiple times */ | |
643 | goto again; | |
644 | } | |
645 | spin_unlock(&ps_lock); | |
646 | ||
647 | return NOTIFY_OK; | |
648 | } | |
649 | ||
2d5503b6 JR |
650 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
651 | struct task_struct *task) | |
652 | { | |
653 | struct pasid_state *pasid_state; | |
654 | struct device_state *dev_state; | |
655 | u16 devid; | |
656 | int ret; | |
657 | ||
658 | might_sleep(); | |
659 | ||
660 | if (!amd_iommu_v2_supported()) | |
661 | return -ENODEV; | |
662 | ||
663 | devid = device_id(pdev); | |
664 | dev_state = get_device_state(devid); | |
665 | ||
666 | if (dev_state == NULL) | |
667 | return -EINVAL; | |
668 | ||
669 | ret = -EINVAL; | |
670 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
671 | goto out; | |
672 | ||
673 | ret = -ENOMEM; | |
674 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
675 | if (pasid_state == NULL) | |
676 | goto out; | |
677 | ||
678 | atomic_set(&pasid_state->count, 1); | |
028eeacc | 679 | init_waitqueue_head(&pasid_state->wq); |
2d5503b6 JR |
680 | pasid_state->task = task; |
681 | pasid_state->mm = get_task_mm(task); | |
682 | pasid_state->device_state = dev_state; | |
683 | pasid_state->pasid = pasid; | |
8736b2c3 | 684 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
685 | |
686 | if (pasid_state->mm == NULL) | |
687 | goto out_free; | |
688 | ||
8736b2c3 JR |
689 | mmu_notifier_register(&pasid_state->mn, pasid_state->mm); |
690 | ||
2d5503b6 JR |
691 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
692 | if (ret) | |
8736b2c3 | 693 | goto out_unregister; |
2d5503b6 JR |
694 | |
695 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
696 | __pa(pasid_state->mm->pgd)); | |
697 | if (ret) | |
698 | goto out_clear_state; | |
699 | ||
700 | link_pasid_state(pasid_state); | |
701 | ||
702 | return 0; | |
703 | ||
704 | out_clear_state: | |
705 | clear_pasid_state(dev_state, pasid); | |
706 | ||
8736b2c3 JR |
707 | out_unregister: |
708 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
709 | ||
2d5503b6 | 710 | out_free: |
028eeacc | 711 | free_pasid_state(pasid_state); |
2d5503b6 JR |
712 | |
713 | out: | |
714 | put_device_state(dev_state); | |
715 | ||
716 | return ret; | |
717 | } | |
718 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
719 | ||
720 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
721 | { | |
722 | struct device_state *dev_state; | |
723 | u16 devid; | |
724 | ||
725 | might_sleep(); | |
726 | ||
727 | if (!amd_iommu_v2_supported()) | |
728 | return; | |
729 | ||
730 | devid = device_id(pdev); | |
731 | dev_state = get_device_state(devid); | |
732 | if (dev_state == NULL) | |
733 | return; | |
734 | ||
735 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
736 | goto out; | |
737 | ||
738 | unbind_pasid(dev_state, pasid); | |
739 | ||
740 | out: | |
741 | put_device_state(dev_state); | |
742 | } | |
743 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
744 | ||
ed96f228 JR |
745 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
746 | { | |
747 | struct device_state *dev_state; | |
748 | unsigned long flags; | |
749 | int ret, tmp; | |
750 | u16 devid; | |
751 | ||
752 | might_sleep(); | |
753 | ||
754 | if (!amd_iommu_v2_supported()) | |
755 | return -ENODEV; | |
756 | ||
757 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
758 | return -EINVAL; | |
759 | ||
760 | devid = device_id(pdev); | |
761 | ||
762 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
763 | if (dev_state == NULL) | |
764 | return -ENOMEM; | |
765 | ||
766 | spin_lock_init(&dev_state->lock); | |
028eeacc | 767 | init_waitqueue_head(&dev_state->wq); |
ed96f228 JR |
768 | dev_state->pdev = pdev; |
769 | ||
770 | tmp = pasids; | |
771 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
772 | dev_state->pasid_levels += 1; | |
773 | ||
774 | atomic_set(&dev_state->count, 1); | |
775 | dev_state->max_pasids = pasids; | |
776 | ||
777 | ret = -ENOMEM; | |
778 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
779 | if (dev_state->states == NULL) | |
780 | goto out_free_dev_state; | |
781 | ||
782 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
783 | if (dev_state->domain == NULL) | |
784 | goto out_free_states; | |
785 | ||
786 | amd_iommu_domain_direct_map(dev_state->domain); | |
787 | ||
788 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
789 | if (ret) | |
790 | goto out_free_domain; | |
791 | ||
792 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
793 | if (ret != 0) | |
794 | goto out_free_domain; | |
795 | ||
796 | spin_lock_irqsave(&state_lock, flags); | |
797 | ||
798 | if (state_table[devid] != NULL) { | |
799 | spin_unlock_irqrestore(&state_lock, flags); | |
800 | ret = -EBUSY; | |
801 | goto out_free_domain; | |
802 | } | |
803 | ||
804 | state_table[devid] = dev_state; | |
805 | ||
806 | spin_unlock_irqrestore(&state_lock, flags); | |
807 | ||
808 | return 0; | |
809 | ||
810 | out_free_domain: | |
811 | iommu_domain_free(dev_state->domain); | |
812 | ||
813 | out_free_states: | |
814 | free_page((unsigned long)dev_state->states); | |
815 | ||
816 | out_free_dev_state: | |
817 | kfree(dev_state); | |
818 | ||
819 | return ret; | |
820 | } | |
821 | EXPORT_SYMBOL(amd_iommu_init_device); | |
822 | ||
823 | void amd_iommu_free_device(struct pci_dev *pdev) | |
824 | { | |
825 | struct device_state *dev_state; | |
826 | unsigned long flags; | |
827 | u16 devid; | |
828 | ||
829 | if (!amd_iommu_v2_supported()) | |
830 | return; | |
831 | ||
832 | devid = device_id(pdev); | |
833 | ||
834 | spin_lock_irqsave(&state_lock, flags); | |
835 | ||
836 | dev_state = state_table[devid]; | |
837 | if (dev_state == NULL) { | |
838 | spin_unlock_irqrestore(&state_lock, flags); | |
839 | return; | |
840 | } | |
841 | ||
842 | state_table[devid] = NULL; | |
843 | ||
844 | spin_unlock_irqrestore(&state_lock, flags); | |
845 | ||
2d5503b6 JR |
846 | /* Get rid of any remaining pasid states */ |
847 | free_pasid_states(dev_state); | |
848 | ||
028eeacc | 849 | put_device_state_wait(dev_state); |
ed96f228 JR |
850 | } |
851 | EXPORT_SYMBOL(amd_iommu_free_device); | |
852 | ||
175d6146 JR |
853 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
854 | amd_iommu_invalid_ppr_cb cb) | |
855 | { | |
856 | struct device_state *dev_state; | |
857 | unsigned long flags; | |
858 | u16 devid; | |
859 | int ret; | |
860 | ||
861 | if (!amd_iommu_v2_supported()) | |
862 | return -ENODEV; | |
863 | ||
864 | devid = device_id(pdev); | |
865 | ||
866 | spin_lock_irqsave(&state_lock, flags); | |
867 | ||
868 | ret = -EINVAL; | |
869 | dev_state = state_table[devid]; | |
870 | if (dev_state == NULL) | |
871 | goto out_unlock; | |
872 | ||
873 | dev_state->inv_ppr_cb = cb; | |
874 | ||
875 | ret = 0; | |
876 | ||
877 | out_unlock: | |
878 | spin_unlock_irqrestore(&state_lock, flags); | |
879 | ||
880 | return ret; | |
881 | } | |
882 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
883 | ||
e3c495c7 JR |
884 | static int __init amd_iommu_v2_init(void) |
885 | { | |
ed96f228 | 886 | size_t state_table_size; |
028eeacc | 887 | int ret; |
ed96f228 | 888 | |
e3c495c7 JR |
889 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>"); |
890 | ||
ed96f228 JR |
891 | spin_lock_init(&state_lock); |
892 | ||
893 | state_table_size = MAX_DEVICES * sizeof(struct device_state *); | |
894 | state_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
895 | get_order(state_table_size)); | |
896 | if (state_table == NULL) | |
897 | return -ENOMEM; | |
898 | ||
028eeacc JR |
899 | ret = -ENOMEM; |
900 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 901 | if (iommu_wq == NULL) |
028eeacc | 902 | goto out_free; |
8736b2c3 JR |
903 | |
904 | ret = -ENOMEM; | |
905 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
906 | if (empty_page_table == NULL) | |
907 | goto out_destroy_wq; | |
028eeacc JR |
908 | |
909 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
8736b2c3 | 910 | profile_event_register(PROFILE_TASK_EXIT, &profile_nb); |
028eeacc | 911 | |
e3c495c7 | 912 | return 0; |
028eeacc | 913 | |
8736b2c3 JR |
914 | out_destroy_wq: |
915 | destroy_workqueue(iommu_wq); | |
916 | ||
028eeacc JR |
917 | out_free: |
918 | free_pages((unsigned long)state_table, get_order(state_table_size)); | |
919 | ||
920 | return ret; | |
e3c495c7 JR |
921 | } |
922 | ||
923 | static void __exit amd_iommu_v2_exit(void) | |
924 | { | |
ed96f228 JR |
925 | struct device_state *dev_state; |
926 | size_t state_table_size; | |
927 | int i; | |
928 | ||
8736b2c3 | 929 | profile_event_unregister(PROFILE_TASK_EXIT, &profile_nb); |
028eeacc JR |
930 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
931 | ||
932 | flush_workqueue(iommu_wq); | |
933 | ||
934 | /* | |
935 | * The loop below might call flush_workqueue(), so call | |
936 | * destroy_workqueue() after it | |
937 | */ | |
ed96f228 JR |
938 | for (i = 0; i < MAX_DEVICES; ++i) { |
939 | dev_state = get_device_state(i); | |
940 | ||
941 | if (dev_state == NULL) | |
942 | continue; | |
943 | ||
944 | WARN_ON_ONCE(1); | |
945 | ||
ed96f228 | 946 | put_device_state(dev_state); |
028eeacc | 947 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
948 | } |
949 | ||
028eeacc JR |
950 | destroy_workqueue(iommu_wq); |
951 | ||
ed96f228 JR |
952 | state_table_size = MAX_DEVICES * sizeof(struct device_state *); |
953 | free_pages((unsigned long)state_table, get_order(state_table_size)); | |
8736b2c3 JR |
954 | |
955 | free_page((unsigned long)empty_page_table); | |
e3c495c7 JR |
956 | } |
957 | ||
958 | module_init(amd_iommu_v2_init); | |
959 | module_exit(amd_iommu_v2_exit); |