Commit | Line | Data |
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e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
d73a6d72 | 48 | unsigned mmu_notifier_count; /* Counting nested mmu_notifier |
e79df31c | 49 | calls */ |
ed96f228 | 50 | struct mm_struct *mm; /* mm_struct for the faults */ |
ff6d0cce | 51 | struct mmu_notifier mn; /* mmu_notifier handle */ |
ed96f228 JR |
52 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
53 | struct device_state *device_state; /* Link to our device_state */ | |
54 | int pasid; /* PASID index */ | |
d9e1611e JR |
55 | bool invalid; /* Used during setup and |
56 | teardown of the pasid */ | |
d73a6d72 JR |
57 | spinlock_t lock; /* Protect pri_queues and |
58 | mmu_notifer_count */ | |
028eeacc | 59 | wait_queue_head_t wq; /* To wait for count == 0 */ |
ed96f228 JR |
60 | }; |
61 | ||
62 | struct device_state { | |
741669c7 JR |
63 | struct list_head list; |
64 | u16 devid; | |
ed96f228 JR |
65 | atomic_t count; |
66 | struct pci_dev *pdev; | |
67 | struct pasid_state **states; | |
68 | struct iommu_domain *domain; | |
69 | int pasid_levels; | |
70 | int max_pasids; | |
175d6146 | 71 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
bc21662f | 72 | amd_iommu_invalidate_ctx inv_ctx_cb; |
ed96f228 | 73 | spinlock_t lock; |
028eeacc JR |
74 | wait_queue_head_t wq; |
75 | }; | |
76 | ||
77 | struct fault { | |
78 | struct work_struct work; | |
79 | struct device_state *dev_state; | |
80 | struct pasid_state *state; | |
81 | struct mm_struct *mm; | |
82 | u64 address; | |
83 | u16 devid; | |
84 | u16 pasid; | |
85 | u16 tag; | |
86 | u16 finish; | |
87 | u16 flags; | |
ed96f228 JR |
88 | }; |
89 | ||
741669c7 | 90 | static LIST_HEAD(state_list); |
ed96f228 JR |
91 | static spinlock_t state_lock; |
92 | ||
028eeacc JR |
93 | static struct workqueue_struct *iommu_wq; |
94 | ||
8736b2c3 JR |
95 | /* |
96 | * Empty page table - Used between | |
97 | * mmu_notifier_invalidate_range_start and | |
98 | * mmu_notifier_invalidate_range_end | |
99 | */ | |
100 | static u64 *empty_page_table; | |
101 | ||
2d5503b6 | 102 | static void free_pasid_states(struct device_state *dev_state); |
ed96f228 JR |
103 | |
104 | static u16 device_id(struct pci_dev *pdev) | |
105 | { | |
106 | u16 devid; | |
107 | ||
108 | devid = pdev->bus->number; | |
109 | devid = (devid << 8) | pdev->devfn; | |
110 | ||
111 | return devid; | |
112 | } | |
113 | ||
b87d2d7c JR |
114 | static struct device_state *__get_device_state(u16 devid) |
115 | { | |
741669c7 JR |
116 | struct device_state *dev_state; |
117 | ||
118 | list_for_each_entry(dev_state, &state_list, list) { | |
119 | if (dev_state->devid == devid) | |
120 | return dev_state; | |
121 | } | |
122 | ||
123 | return NULL; | |
b87d2d7c JR |
124 | } |
125 | ||
ed96f228 JR |
126 | static struct device_state *get_device_state(u16 devid) |
127 | { | |
128 | struct device_state *dev_state; | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&state_lock, flags); | |
b87d2d7c | 132 | dev_state = __get_device_state(devid); |
ed96f228 JR |
133 | if (dev_state != NULL) |
134 | atomic_inc(&dev_state->count); | |
135 | spin_unlock_irqrestore(&state_lock, flags); | |
136 | ||
137 | return dev_state; | |
138 | } | |
139 | ||
140 | static void free_device_state(struct device_state *dev_state) | |
141 | { | |
2d5503b6 JR |
142 | /* |
143 | * First detach device from domain - No more PRI requests will arrive | |
144 | * from that device after it is unbound from the IOMMUv2 domain. | |
145 | */ | |
ed96f228 | 146 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
147 | |
148 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 149 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
150 | |
151 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
152 | kfree(dev_state); |
153 | } | |
154 | ||
155 | static void put_device_state(struct device_state *dev_state) | |
156 | { | |
157 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 158 | wake_up(&dev_state->wq); |
ed96f228 JR |
159 | } |
160 | ||
028eeacc JR |
161 | static void put_device_state_wait(struct device_state *dev_state) |
162 | { | |
163 | DEFINE_WAIT(wait); | |
164 | ||
165 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
166 | if (!atomic_dec_and_test(&dev_state->count)) | |
167 | schedule(); | |
168 | finish_wait(&dev_state->wq, &wait); | |
169 | ||
170 | free_device_state(dev_state); | |
171 | } | |
8736b2c3 | 172 | |
2d5503b6 JR |
173 | /* Must be called under dev_state->lock */ |
174 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
175 | int pasid, bool alloc) | |
176 | { | |
177 | struct pasid_state **root, **ptr; | |
178 | int level, index; | |
179 | ||
180 | level = dev_state->pasid_levels; | |
181 | root = dev_state->states; | |
182 | ||
183 | while (true) { | |
184 | ||
185 | index = (pasid >> (9 * level)) & 0x1ff; | |
186 | ptr = &root[index]; | |
187 | ||
188 | if (level == 0) | |
189 | break; | |
190 | ||
191 | if (*ptr == NULL) { | |
192 | if (!alloc) | |
193 | return NULL; | |
194 | ||
195 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
196 | if (*ptr == NULL) | |
197 | return NULL; | |
198 | } | |
199 | ||
200 | root = (struct pasid_state **)*ptr; | |
201 | level -= 1; | |
202 | } | |
203 | ||
204 | return ptr; | |
205 | } | |
206 | ||
207 | static int set_pasid_state(struct device_state *dev_state, | |
208 | struct pasid_state *pasid_state, | |
209 | int pasid) | |
210 | { | |
211 | struct pasid_state **ptr; | |
212 | unsigned long flags; | |
213 | int ret; | |
214 | ||
215 | spin_lock_irqsave(&dev_state->lock, flags); | |
216 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
217 | ||
218 | ret = -ENOMEM; | |
219 | if (ptr == NULL) | |
220 | goto out_unlock; | |
221 | ||
222 | ret = -ENOMEM; | |
223 | if (*ptr != NULL) | |
224 | goto out_unlock; | |
225 | ||
226 | *ptr = pasid_state; | |
227 | ||
228 | ret = 0; | |
229 | ||
230 | out_unlock: | |
231 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
236 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
237 | { | |
238 | struct pasid_state **ptr; | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&dev_state->lock, flags); | |
242 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
243 | ||
244 | if (ptr == NULL) | |
245 | goto out_unlock; | |
246 | ||
247 | *ptr = NULL; | |
248 | ||
249 | out_unlock: | |
250 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
251 | } | |
252 | ||
253 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
254 | int pasid) | |
255 | { | |
256 | struct pasid_state **ptr, *ret = NULL; | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&dev_state->lock, flags); | |
260 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
261 | ||
262 | if (ptr == NULL) | |
263 | goto out_unlock; | |
264 | ||
265 | ret = *ptr; | |
266 | if (ret) | |
267 | atomic_inc(&ret->count); | |
268 | ||
269 | out_unlock: | |
270 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
275 | static void free_pasid_state(struct pasid_state *pasid_state) | |
276 | { | |
277 | kfree(pasid_state); | |
278 | } | |
279 | ||
280 | static void put_pasid_state(struct pasid_state *pasid_state) | |
281 | { | |
282 | if (atomic_dec_and_test(&pasid_state->count)) { | |
283 | put_device_state(pasid_state->device_state); | |
028eeacc | 284 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
285 | } |
286 | } | |
287 | ||
028eeacc JR |
288 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
289 | { | |
290 | DEFINE_WAIT(wait); | |
291 | ||
292 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
293 | ||
294 | if (atomic_dec_and_test(&pasid_state->count)) | |
295 | put_device_state(pasid_state->device_state); | |
296 | else | |
297 | schedule(); | |
298 | ||
299 | finish_wait(&pasid_state->wq, &wait); | |
028eeacc JR |
300 | free_pasid_state(pasid_state); |
301 | } | |
302 | ||
61feb438 | 303 | static void unbind_pasid(struct pasid_state *pasid_state) |
8736b2c3 JR |
304 | { |
305 | struct iommu_domain *domain; | |
306 | ||
307 | domain = pasid_state->device_state->domain; | |
308 | ||
53d340ef JR |
309 | /* |
310 | * Mark pasid_state as invalid, no more faults will we added to the | |
311 | * work queue after this is visible everywhere. | |
312 | */ | |
313 | pasid_state->invalid = true; | |
314 | ||
315 | /* Make sure this is visible */ | |
316 | smp_wmb(); | |
317 | ||
318 | /* After this the device/pasid can't access the mm anymore */ | |
8736b2c3 | 319 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); |
8736b2c3 JR |
320 | |
321 | /* Make sure no more pending faults are in the queue */ | |
322 | flush_workqueue(iommu_wq); | |
8736b2c3 JR |
323 | } |
324 | ||
2d5503b6 JR |
325 | static void free_pasid_states_level1(struct pasid_state **tbl) |
326 | { | |
327 | int i; | |
328 | ||
329 | for (i = 0; i < 512; ++i) { | |
330 | if (tbl[i] == NULL) | |
331 | continue; | |
332 | ||
333 | free_page((unsigned long)tbl[i]); | |
334 | } | |
335 | } | |
336 | ||
337 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
338 | { | |
339 | struct pasid_state **ptr; | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < 512; ++i) { | |
343 | if (tbl[i] == NULL) | |
344 | continue; | |
345 | ||
346 | ptr = (struct pasid_state **)tbl[i]; | |
347 | free_pasid_states_level1(ptr); | |
348 | } | |
349 | } | |
350 | ||
351 | static void free_pasid_states(struct device_state *dev_state) | |
352 | { | |
353 | struct pasid_state *pasid_state; | |
354 | int i; | |
355 | ||
356 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
357 | pasid_state = get_pasid_state(dev_state, i); | |
358 | if (pasid_state == NULL) | |
359 | continue; | |
360 | ||
2d5503b6 | 361 | put_pasid_state(pasid_state); |
a40d4c67 JR |
362 | |
363 | /* | |
364 | * This will call the mn_release function and | |
365 | * unbind the PASID | |
366 | */ | |
367 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
c5db16ad JR |
368 | |
369 | put_pasid_state_wait(pasid_state); /* Reference taken in | |
daff2f9c | 370 | amd_iommu_bind_pasid */ |
75058a30 JR |
371 | |
372 | /* Drop reference taken in amd_iommu_bind_pasid */ | |
373 | put_device_state(dev_state); | |
2d5503b6 JR |
374 | } |
375 | ||
376 | if (dev_state->pasid_levels == 2) | |
377 | free_pasid_states_level2(dev_state->states); | |
378 | else if (dev_state->pasid_levels == 1) | |
379 | free_pasid_states_level1(dev_state->states); | |
380 | else if (dev_state->pasid_levels != 0) | |
381 | BUG(); | |
382 | ||
383 | free_page((unsigned long)dev_state->states); | |
384 | } | |
385 | ||
8736b2c3 JR |
386 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
387 | { | |
388 | return container_of(mn, struct pasid_state, mn); | |
389 | } | |
390 | ||
391 | static void __mn_flush_page(struct mmu_notifier *mn, | |
392 | unsigned long address) | |
393 | { | |
394 | struct pasid_state *pasid_state; | |
395 | struct device_state *dev_state; | |
396 | ||
397 | pasid_state = mn_to_state(mn); | |
398 | dev_state = pasid_state->device_state; | |
399 | ||
400 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
401 | } | |
402 | ||
403 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
404 | struct mm_struct *mm, | |
57128468 ALC |
405 | unsigned long start, |
406 | unsigned long end) | |
8736b2c3 | 407 | { |
57128468 ALC |
408 | for (; start < end; start += PAGE_SIZE) |
409 | __mn_flush_page(mn, start); | |
8736b2c3 JR |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
8736b2c3 JR |
414 | static void mn_invalidate_page(struct mmu_notifier *mn, |
415 | struct mm_struct *mm, | |
416 | unsigned long address) | |
417 | { | |
418 | __mn_flush_page(mn, address); | |
419 | } | |
420 | ||
421 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
422 | struct mm_struct *mm, | |
423 | unsigned long start, unsigned long end) | |
424 | { | |
425 | struct pasid_state *pasid_state; | |
426 | struct device_state *dev_state; | |
d73a6d72 | 427 | unsigned long flags; |
8736b2c3 JR |
428 | |
429 | pasid_state = mn_to_state(mn); | |
430 | dev_state = pasid_state->device_state; | |
431 | ||
d73a6d72 JR |
432 | spin_lock_irqsave(&pasid_state->lock, flags); |
433 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
434 | amd_iommu_domain_set_gcr3(dev_state->domain, |
435 | pasid_state->pasid, | |
436 | __pa(empty_page_table)); | |
437 | } | |
d73a6d72 JR |
438 | pasid_state->mmu_notifier_count += 1; |
439 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
8736b2c3 JR |
440 | } |
441 | ||
442 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
443 | struct mm_struct *mm, | |
444 | unsigned long start, unsigned long end) | |
445 | { | |
446 | struct pasid_state *pasid_state; | |
447 | struct device_state *dev_state; | |
d73a6d72 | 448 | unsigned long flags; |
8736b2c3 JR |
449 | |
450 | pasid_state = mn_to_state(mn); | |
451 | dev_state = pasid_state->device_state; | |
452 | ||
d73a6d72 JR |
453 | spin_lock_irqsave(&pasid_state->lock, flags); |
454 | pasid_state->mmu_notifier_count -= 1; | |
455 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
456 | amd_iommu_domain_set_gcr3(dev_state->domain, |
457 | pasid_state->pasid, | |
458 | __pa(pasid_state->mm->pgd)); | |
459 | } | |
d73a6d72 | 460 | spin_unlock_irqrestore(&pasid_state->lock, flags); |
8736b2c3 JR |
461 | } |
462 | ||
a40d4c67 JR |
463 | static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm) |
464 | { | |
465 | struct pasid_state *pasid_state; | |
466 | struct device_state *dev_state; | |
d9e1611e | 467 | bool run_inv_ctx_cb; |
a40d4c67 JR |
468 | |
469 | might_sleep(); | |
470 | ||
d9e1611e JR |
471 | pasid_state = mn_to_state(mn); |
472 | dev_state = pasid_state->device_state; | |
473 | run_inv_ctx_cb = !pasid_state->invalid; | |
a40d4c67 | 474 | |
d9e1611e | 475 | if (run_inv_ctx_cb && pasid_state->device_state->inv_ctx_cb) |
a40d4c67 JR |
476 | dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid); |
477 | ||
61feb438 | 478 | unbind_pasid(pasid_state); |
a40d4c67 JR |
479 | } |
480 | ||
8736b2c3 | 481 | static struct mmu_notifier_ops iommu_mn = { |
a40d4c67 | 482 | .release = mn_release, |
8736b2c3 | 483 | .clear_flush_young = mn_clear_flush_young, |
8736b2c3 JR |
484 | .invalidate_page = mn_invalidate_page, |
485 | .invalidate_range_start = mn_invalidate_range_start, | |
486 | .invalidate_range_end = mn_invalidate_range_end, | |
487 | }; | |
488 | ||
028eeacc JR |
489 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
490 | u16 tag, int status) | |
491 | { | |
492 | unsigned long flags; | |
493 | ||
494 | spin_lock_irqsave(&pasid_state->lock, flags); | |
495 | pasid_state->pri[tag].status = status; | |
496 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
497 | } | |
498 | ||
499 | static void finish_pri_tag(struct device_state *dev_state, | |
500 | struct pasid_state *pasid_state, | |
501 | u16 tag) | |
502 | { | |
503 | unsigned long flags; | |
504 | ||
505 | spin_lock_irqsave(&pasid_state->lock, flags); | |
506 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
507 | pasid_state->pri[tag].finish) { | |
508 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
509 | pasid_state->pri[tag].status, tag); | |
510 | pasid_state->pri[tag].finish = false; | |
511 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
512 | } | |
513 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
514 | } | |
515 | ||
516 | static void do_fault(struct work_struct *work) | |
517 | { | |
518 | struct fault *fault = container_of(work, struct fault, work); | |
519 | int npages, write; | |
520 | struct page *page; | |
521 | ||
522 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
523 | ||
4378d992 | 524 | down_read(&fault->state->mm->mmap_sem); |
dba3838d | 525 | npages = get_user_pages(NULL, fault->state->mm, |
028eeacc | 526 | fault->address, 1, write, 0, &page, NULL); |
4378d992 | 527 | up_read(&fault->state->mm->mmap_sem); |
028eeacc | 528 | |
175d6146 | 529 | if (npages == 1) { |
028eeacc | 530 | put_page(page); |
175d6146 JR |
531 | } else if (fault->dev_state->inv_ppr_cb) { |
532 | int status; | |
533 | ||
534 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
535 | fault->pasid, | |
536 | fault->address, | |
537 | fault->flags); | |
538 | switch (status) { | |
539 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
540 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
541 | break; | |
542 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
543 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
544 | break; | |
545 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
546 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
547 | break; | |
548 | default: | |
549 | BUG(); | |
550 | } | |
551 | } else { | |
028eeacc | 552 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); |
175d6146 | 553 | } |
028eeacc JR |
554 | |
555 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
556 | ||
557 | put_pasid_state(fault->state); | |
558 | ||
559 | kfree(fault); | |
560 | } | |
561 | ||
562 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
563 | { | |
564 | struct amd_iommu_fault *iommu_fault; | |
565 | struct pasid_state *pasid_state; | |
566 | struct device_state *dev_state; | |
567 | unsigned long flags; | |
568 | struct fault *fault; | |
569 | bool finish; | |
570 | u16 tag; | |
571 | int ret; | |
572 | ||
573 | iommu_fault = data; | |
574 | tag = iommu_fault->tag & 0x1ff; | |
575 | finish = (iommu_fault->tag >> 9) & 1; | |
576 | ||
577 | ret = NOTIFY_DONE; | |
578 | dev_state = get_device_state(iommu_fault->device_id); | |
579 | if (dev_state == NULL) | |
580 | goto out; | |
581 | ||
582 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
53d340ef | 583 | if (pasid_state == NULL || pasid_state->invalid) { |
028eeacc JR |
584 | /* We know the device but not the PASID -> send INVALID */ |
585 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
586 | PPR_INVALID, tag); | |
587 | goto out_drop_state; | |
588 | } | |
589 | ||
590 | spin_lock_irqsave(&pasid_state->lock, flags); | |
591 | atomic_inc(&pasid_state->pri[tag].inflight); | |
592 | if (finish) | |
593 | pasid_state->pri[tag].finish = true; | |
594 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
595 | ||
596 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
597 | if (fault == NULL) { | |
598 | /* We are OOM - send success and let the device re-fault */ | |
599 | finish_pri_tag(dev_state, pasid_state, tag); | |
600 | goto out_drop_state; | |
601 | } | |
602 | ||
603 | fault->dev_state = dev_state; | |
604 | fault->address = iommu_fault->address; | |
605 | fault->state = pasid_state; | |
606 | fault->tag = tag; | |
607 | fault->finish = finish; | |
b00675b8 | 608 | fault->pasid = iommu_fault->pasid; |
028eeacc JR |
609 | fault->flags = iommu_fault->flags; |
610 | INIT_WORK(&fault->work, do_fault); | |
611 | ||
612 | queue_work(iommu_wq, &fault->work); | |
613 | ||
614 | ret = NOTIFY_OK; | |
615 | ||
616 | out_drop_state: | |
dc88db7e JR |
617 | |
618 | if (ret != NOTIFY_OK && pasid_state) | |
619 | put_pasid_state(pasid_state); | |
620 | ||
028eeacc JR |
621 | put_device_state(dev_state); |
622 | ||
623 | out: | |
624 | return ret; | |
625 | } | |
626 | ||
627 | static struct notifier_block ppr_nb = { | |
628 | .notifier_call = ppr_notifier, | |
629 | }; | |
630 | ||
2d5503b6 JR |
631 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
632 | struct task_struct *task) | |
633 | { | |
634 | struct pasid_state *pasid_state; | |
635 | struct device_state *dev_state; | |
f0aac63b | 636 | struct mm_struct *mm; |
2d5503b6 JR |
637 | u16 devid; |
638 | int ret; | |
639 | ||
640 | might_sleep(); | |
641 | ||
642 | if (!amd_iommu_v2_supported()) | |
643 | return -ENODEV; | |
644 | ||
645 | devid = device_id(pdev); | |
646 | dev_state = get_device_state(devid); | |
647 | ||
648 | if (dev_state == NULL) | |
649 | return -EINVAL; | |
650 | ||
651 | ret = -EINVAL; | |
652 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
653 | goto out; | |
654 | ||
655 | ret = -ENOMEM; | |
656 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
657 | if (pasid_state == NULL) | |
658 | goto out; | |
659 | ||
f0aac63b | 660 | |
2d5503b6 | 661 | atomic_set(&pasid_state->count, 1); |
028eeacc | 662 | init_waitqueue_head(&pasid_state->wq); |
2c13d47a JR |
663 | spin_lock_init(&pasid_state->lock); |
664 | ||
f0aac63b | 665 | mm = get_task_mm(task); |
f0aac63b | 666 | pasid_state->mm = mm; |
2d5503b6 JR |
667 | pasid_state->device_state = dev_state; |
668 | pasid_state->pasid = pasid; | |
d9e1611e JR |
669 | pasid_state->invalid = true; /* Mark as valid only if we are |
670 | done with setting up the pasid */ | |
8736b2c3 | 671 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
672 | |
673 | if (pasid_state->mm == NULL) | |
674 | goto out_free; | |
675 | ||
f0aac63b | 676 | mmu_notifier_register(&pasid_state->mn, mm); |
8736b2c3 | 677 | |
2d5503b6 JR |
678 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
679 | if (ret) | |
8736b2c3 | 680 | goto out_unregister; |
2d5503b6 JR |
681 | |
682 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
683 | __pa(pasid_state->mm->pgd)); | |
684 | if (ret) | |
685 | goto out_clear_state; | |
686 | ||
d9e1611e JR |
687 | /* Now we are ready to handle faults */ |
688 | pasid_state->invalid = false; | |
689 | ||
f0aac63b JR |
690 | /* |
691 | * Drop the reference to the mm_struct here. We rely on the | |
692 | * mmu_notifier release call-back to inform us when the mm | |
693 | * is going away. | |
694 | */ | |
695 | mmput(mm); | |
696 | ||
2d5503b6 JR |
697 | return 0; |
698 | ||
699 | out_clear_state: | |
700 | clear_pasid_state(dev_state, pasid); | |
701 | ||
8736b2c3 | 702 | out_unregister: |
f0aac63b | 703 | mmu_notifier_unregister(&pasid_state->mn, mm); |
8736b2c3 | 704 | |
2d5503b6 | 705 | out_free: |
f0aac63b | 706 | mmput(mm); |
028eeacc | 707 | free_pasid_state(pasid_state); |
2d5503b6 JR |
708 | |
709 | out: | |
710 | put_device_state(dev_state); | |
711 | ||
712 | return ret; | |
713 | } | |
714 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
715 | ||
716 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
717 | { | |
a40d4c67 | 718 | struct pasid_state *pasid_state; |
2d5503b6 JR |
719 | struct device_state *dev_state; |
720 | u16 devid; | |
721 | ||
722 | might_sleep(); | |
723 | ||
724 | if (!amd_iommu_v2_supported()) | |
725 | return; | |
726 | ||
727 | devid = device_id(pdev); | |
728 | dev_state = get_device_state(devid); | |
729 | if (dev_state == NULL) | |
730 | return; | |
731 | ||
732 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
733 | goto out; | |
734 | ||
a40d4c67 JR |
735 | pasid_state = get_pasid_state(dev_state, pasid); |
736 | if (pasid_state == NULL) | |
737 | goto out; | |
738 | /* | |
739 | * Drop reference taken here. We are safe because we still hold | |
740 | * the reference taken in the amd_iommu_bind_pasid function. | |
741 | */ | |
742 | put_pasid_state(pasid_state); | |
743 | ||
53d340ef JR |
744 | /* Clear the pasid state so that the pasid can be re-used */ |
745 | clear_pasid_state(dev_state, pasid_state->pasid); | |
746 | ||
f0aac63b | 747 | /* |
fcaa9606 JR |
748 | * Call mmu_notifier_unregister to drop our reference |
749 | * to pasid_state->mm | |
f0aac63b | 750 | */ |
fcaa9606 | 751 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); |
2d5503b6 | 752 | |
c5db16ad | 753 | put_pasid_state_wait(pasid_state); /* Reference taken in |
daff2f9c | 754 | amd_iommu_bind_pasid */ |
2d5503b6 | 755 | out: |
75058a30 JR |
756 | /* Drop reference taken in this function */ |
757 | put_device_state(dev_state); | |
758 | ||
759 | /* Drop reference taken in amd_iommu_bind_pasid */ | |
2d5503b6 JR |
760 | put_device_state(dev_state); |
761 | } | |
762 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
763 | ||
ed96f228 JR |
764 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
765 | { | |
766 | struct device_state *dev_state; | |
767 | unsigned long flags; | |
768 | int ret, tmp; | |
769 | u16 devid; | |
770 | ||
771 | might_sleep(); | |
772 | ||
773 | if (!amd_iommu_v2_supported()) | |
774 | return -ENODEV; | |
775 | ||
776 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
777 | return -EINVAL; | |
778 | ||
779 | devid = device_id(pdev); | |
780 | ||
781 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
782 | if (dev_state == NULL) | |
783 | return -ENOMEM; | |
784 | ||
785 | spin_lock_init(&dev_state->lock); | |
028eeacc | 786 | init_waitqueue_head(&dev_state->wq); |
741669c7 JR |
787 | dev_state->pdev = pdev; |
788 | dev_state->devid = devid; | |
ed96f228 JR |
789 | |
790 | tmp = pasids; | |
791 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
792 | dev_state->pasid_levels += 1; | |
793 | ||
794 | atomic_set(&dev_state->count, 1); | |
795 | dev_state->max_pasids = pasids; | |
796 | ||
797 | ret = -ENOMEM; | |
798 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
799 | if (dev_state->states == NULL) | |
800 | goto out_free_dev_state; | |
801 | ||
802 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
803 | if (dev_state->domain == NULL) | |
804 | goto out_free_states; | |
805 | ||
806 | amd_iommu_domain_direct_map(dev_state->domain); | |
807 | ||
808 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
809 | if (ret) | |
810 | goto out_free_domain; | |
811 | ||
812 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
813 | if (ret != 0) | |
814 | goto out_free_domain; | |
815 | ||
816 | spin_lock_irqsave(&state_lock, flags); | |
817 | ||
741669c7 | 818 | if (__get_device_state(devid) != NULL) { |
ed96f228 JR |
819 | spin_unlock_irqrestore(&state_lock, flags); |
820 | ret = -EBUSY; | |
821 | goto out_free_domain; | |
822 | } | |
823 | ||
741669c7 | 824 | list_add_tail(&dev_state->list, &state_list); |
ed96f228 JR |
825 | |
826 | spin_unlock_irqrestore(&state_lock, flags); | |
827 | ||
828 | return 0; | |
829 | ||
830 | out_free_domain: | |
831 | iommu_domain_free(dev_state->domain); | |
832 | ||
833 | out_free_states: | |
834 | free_page((unsigned long)dev_state->states); | |
835 | ||
836 | out_free_dev_state: | |
837 | kfree(dev_state); | |
838 | ||
839 | return ret; | |
840 | } | |
841 | EXPORT_SYMBOL(amd_iommu_init_device); | |
842 | ||
843 | void amd_iommu_free_device(struct pci_dev *pdev) | |
844 | { | |
845 | struct device_state *dev_state; | |
846 | unsigned long flags; | |
847 | u16 devid; | |
848 | ||
849 | if (!amd_iommu_v2_supported()) | |
850 | return; | |
851 | ||
852 | devid = device_id(pdev); | |
853 | ||
854 | spin_lock_irqsave(&state_lock, flags); | |
855 | ||
b87d2d7c | 856 | dev_state = __get_device_state(devid); |
ed96f228 JR |
857 | if (dev_state == NULL) { |
858 | spin_unlock_irqrestore(&state_lock, flags); | |
859 | return; | |
860 | } | |
861 | ||
741669c7 | 862 | list_del(&dev_state->list); |
ed96f228 JR |
863 | |
864 | spin_unlock_irqrestore(&state_lock, flags); | |
865 | ||
2d5503b6 JR |
866 | /* Get rid of any remaining pasid states */ |
867 | free_pasid_states(dev_state); | |
868 | ||
028eeacc | 869 | put_device_state_wait(dev_state); |
ed96f228 JR |
870 | } |
871 | EXPORT_SYMBOL(amd_iommu_free_device); | |
872 | ||
175d6146 JR |
873 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
874 | amd_iommu_invalid_ppr_cb cb) | |
875 | { | |
876 | struct device_state *dev_state; | |
877 | unsigned long flags; | |
878 | u16 devid; | |
879 | int ret; | |
880 | ||
881 | if (!amd_iommu_v2_supported()) | |
882 | return -ENODEV; | |
883 | ||
884 | devid = device_id(pdev); | |
885 | ||
886 | spin_lock_irqsave(&state_lock, flags); | |
887 | ||
888 | ret = -EINVAL; | |
b87d2d7c | 889 | dev_state = __get_device_state(devid); |
175d6146 JR |
890 | if (dev_state == NULL) |
891 | goto out_unlock; | |
892 | ||
893 | dev_state->inv_ppr_cb = cb; | |
894 | ||
895 | ret = 0; | |
896 | ||
897 | out_unlock: | |
898 | spin_unlock_irqrestore(&state_lock, flags); | |
899 | ||
900 | return ret; | |
901 | } | |
902 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
903 | ||
bc21662f JR |
904 | int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
905 | amd_iommu_invalidate_ctx cb) | |
906 | { | |
907 | struct device_state *dev_state; | |
908 | unsigned long flags; | |
909 | u16 devid; | |
910 | int ret; | |
911 | ||
912 | if (!amd_iommu_v2_supported()) | |
913 | return -ENODEV; | |
914 | ||
915 | devid = device_id(pdev); | |
916 | ||
917 | spin_lock_irqsave(&state_lock, flags); | |
918 | ||
919 | ret = -EINVAL; | |
b87d2d7c | 920 | dev_state = __get_device_state(devid); |
bc21662f JR |
921 | if (dev_state == NULL) |
922 | goto out_unlock; | |
923 | ||
924 | dev_state->inv_ctx_cb = cb; | |
925 | ||
926 | ret = 0; | |
927 | ||
928 | out_unlock: | |
929 | spin_unlock_irqrestore(&state_lock, flags); | |
930 | ||
931 | return ret; | |
932 | } | |
933 | EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb); | |
934 | ||
e3c495c7 JR |
935 | static int __init amd_iommu_v2_init(void) |
936 | { | |
028eeacc | 937 | int ret; |
ed96f228 | 938 | |
474d567d JR |
939 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n"); |
940 | ||
941 | if (!amd_iommu_v2_supported()) { | |
07db0409 | 942 | pr_info("AMD IOMMUv2 functionality not available on this system\n"); |
474d567d JR |
943 | /* |
944 | * Load anyway to provide the symbols to other modules | |
945 | * which may use AMD IOMMUv2 optionally. | |
946 | */ | |
947 | return 0; | |
948 | } | |
e3c495c7 | 949 | |
ed96f228 JR |
950 | spin_lock_init(&state_lock); |
951 | ||
028eeacc JR |
952 | ret = -ENOMEM; |
953 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 954 | if (iommu_wq == NULL) |
741669c7 | 955 | goto out; |
8736b2c3 JR |
956 | |
957 | ret = -ENOMEM; | |
958 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
959 | if (empty_page_table == NULL) | |
960 | goto out_destroy_wq; | |
028eeacc JR |
961 | |
962 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
963 | ||
e3c495c7 | 964 | return 0; |
028eeacc | 965 | |
8736b2c3 JR |
966 | out_destroy_wq: |
967 | destroy_workqueue(iommu_wq); | |
968 | ||
741669c7 | 969 | out: |
028eeacc | 970 | return ret; |
e3c495c7 JR |
971 | } |
972 | ||
973 | static void __exit amd_iommu_v2_exit(void) | |
974 | { | |
ed96f228 | 975 | struct device_state *dev_state; |
ed96f228 JR |
976 | int i; |
977 | ||
474d567d JR |
978 | if (!amd_iommu_v2_supported()) |
979 | return; | |
980 | ||
028eeacc JR |
981 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
982 | ||
983 | flush_workqueue(iommu_wq); | |
984 | ||
985 | /* | |
986 | * The loop below might call flush_workqueue(), so call | |
987 | * destroy_workqueue() after it | |
988 | */ | |
ed96f228 JR |
989 | for (i = 0; i < MAX_DEVICES; ++i) { |
990 | dev_state = get_device_state(i); | |
991 | ||
992 | if (dev_state == NULL) | |
993 | continue; | |
994 | ||
995 | WARN_ON_ONCE(1); | |
996 | ||
ed96f228 | 997 | put_device_state(dev_state); |
028eeacc | 998 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
999 | } |
1000 | ||
028eeacc JR |
1001 | destroy_workqueue(iommu_wq); |
1002 | ||
8736b2c3 | 1003 | free_page((unsigned long)empty_page_table); |
e3c495c7 JR |
1004 | } |
1005 | ||
1006 | module_init(amd_iommu_v2_init); | |
1007 | module_exit(amd_iommu_v2_exit); |