Commit | Line | Data |
---|---|---|
45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
45ae7cff WD |
26 | * - Context fault reporting |
27 | */ | |
28 | ||
29 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
30 | ||
31 | #include <linux/delay.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/err.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/iommu.h> | |
859a732e | 37 | #include <linux/iopoll.h> |
45ae7cff WD |
38 | #include <linux/module.h> |
39 | #include <linux/of.h> | |
bae2c2d4 | 40 | #include <linux/of_address.h> |
a9a1b0b5 | 41 | #include <linux/pci.h> |
45ae7cff WD |
42 | #include <linux/platform_device.h> |
43 | #include <linux/slab.h> | |
44 | #include <linux/spinlock.h> | |
45 | ||
46 | #include <linux/amba/bus.h> | |
47 | ||
518f7136 | 48 | #include "io-pgtable.h" |
45ae7cff WD |
49 | |
50 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 51 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
52 | |
53 | /* Maximum number of context banks per SMMU */ | |
54 | #define ARM_SMMU_MAX_CBS 128 | |
55 | ||
56 | /* Maximum number of mapping groups per SMMU */ | |
57 | #define ARM_SMMU_MAX_SMRS 128 | |
58 | ||
45ae7cff WD |
59 | /* SMMU global address space */ |
60 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
c757e852 | 61 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) |
45ae7cff | 62 | |
3a5df8ff AH |
63 | /* |
64 | * SMMU global address space with conditional offset to access secure | |
65 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
66 | * nsGFSYNR0: 0x450) | |
67 | */ | |
68 | #define ARM_SMMU_GR0_NS(smmu) \ | |
69 | ((smmu)->base + \ | |
70 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
71 | ? 0x400 : 0)) | |
72 | ||
668b4ada TC |
73 | #ifdef CONFIG_64BIT |
74 | #define smmu_writeq writeq_relaxed | |
75 | #else | |
76 | #define smmu_writeq(reg64, addr) \ | |
77 | do { \ | |
78 | u64 __val = (reg64); \ | |
79 | void __iomem *__addr = (addr); \ | |
80 | writel_relaxed(__val >> 32, __addr + 4); \ | |
81 | writel_relaxed(__val, __addr); \ | |
82 | } while (0) | |
83 | #endif | |
84 | ||
45ae7cff WD |
85 | /* Configuration registers */ |
86 | #define ARM_SMMU_GR0_sCR0 0x0 | |
87 | #define sCR0_CLIENTPD (1 << 0) | |
88 | #define sCR0_GFRE (1 << 1) | |
89 | #define sCR0_GFIE (1 << 2) | |
90 | #define sCR0_GCFGFRE (1 << 4) | |
91 | #define sCR0_GCFGFIE (1 << 5) | |
92 | #define sCR0_USFCFG (1 << 10) | |
93 | #define sCR0_VMIDPNE (1 << 11) | |
94 | #define sCR0_PTM (1 << 12) | |
95 | #define sCR0_FB (1 << 13) | |
96 | #define sCR0_BSU_SHIFT 14 | |
97 | #define sCR0_BSU_MASK 0x3 | |
98 | ||
99 | /* Identification registers */ | |
100 | #define ARM_SMMU_GR0_ID0 0x20 | |
101 | #define ARM_SMMU_GR0_ID1 0x24 | |
102 | #define ARM_SMMU_GR0_ID2 0x28 | |
103 | #define ARM_SMMU_GR0_ID3 0x2c | |
104 | #define ARM_SMMU_GR0_ID4 0x30 | |
105 | #define ARM_SMMU_GR0_ID5 0x34 | |
106 | #define ARM_SMMU_GR0_ID6 0x38 | |
107 | #define ARM_SMMU_GR0_ID7 0x3c | |
108 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
109 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
110 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
111 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
45ae7cff WD |
112 | |
113 | #define ID0_S1TS (1 << 30) | |
114 | #define ID0_S2TS (1 << 29) | |
115 | #define ID0_NTS (1 << 28) | |
116 | #define ID0_SMS (1 << 27) | |
859a732e | 117 | #define ID0_ATOSNS (1 << 26) |
45ae7cff WD |
118 | #define ID0_CTTW (1 << 14) |
119 | #define ID0_NUMIRPT_SHIFT 16 | |
120 | #define ID0_NUMIRPT_MASK 0xff | |
3c8766d0 OH |
121 | #define ID0_NUMSIDB_SHIFT 9 |
122 | #define ID0_NUMSIDB_MASK 0xf | |
45ae7cff WD |
123 | #define ID0_NUMSMRG_SHIFT 0 |
124 | #define ID0_NUMSMRG_MASK 0xff | |
125 | ||
126 | #define ID1_PAGESIZE (1 << 31) | |
127 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
128 | #define ID1_NUMPAGENDXB_MASK 7 | |
129 | #define ID1_NUMS2CB_SHIFT 16 | |
130 | #define ID1_NUMS2CB_MASK 0xff | |
131 | #define ID1_NUMCB_SHIFT 0 | |
132 | #define ID1_NUMCB_MASK 0xff | |
133 | ||
134 | #define ID2_OAS_SHIFT 4 | |
135 | #define ID2_OAS_MASK 0xf | |
136 | #define ID2_IAS_SHIFT 0 | |
137 | #define ID2_IAS_MASK 0xf | |
138 | #define ID2_UBS_SHIFT 8 | |
139 | #define ID2_UBS_MASK 0xf | |
140 | #define ID2_PTFS_4K (1 << 12) | |
141 | #define ID2_PTFS_16K (1 << 13) | |
142 | #define ID2_PTFS_64K (1 << 14) | |
143 | ||
45ae7cff | 144 | /* Global TLB invalidation */ |
45ae7cff WD |
145 | #define ARM_SMMU_GR0_TLBIVMID 0x64 |
146 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
147 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
148 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
149 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
150 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
151 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
152 | ||
153 | /* Stream mapping registers */ | |
154 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
155 | #define SMR_VALID (1 << 31) | |
156 | #define SMR_MASK_SHIFT 16 | |
157 | #define SMR_MASK_MASK 0x7fff | |
158 | #define SMR_ID_SHIFT 0 | |
159 | #define SMR_ID_MASK 0x7fff | |
160 | ||
161 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
162 | #define S2CR_CBNDX_SHIFT 0 | |
163 | #define S2CR_CBNDX_MASK 0xff | |
164 | #define S2CR_TYPE_SHIFT 16 | |
165 | #define S2CR_TYPE_MASK 0x3 | |
166 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
167 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
168 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
169 | ||
170 | /* Context bank attribute registers */ | |
171 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
172 | #define CBAR_VMID_SHIFT 0 | |
173 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
174 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
175 | #define CBAR_S1_BPSHCFG_MASK 3 | |
176 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
177 | #define CBAR_S1_MEMATTR_SHIFT 12 |
178 | #define CBAR_S1_MEMATTR_MASK 0xf | |
179 | #define CBAR_S1_MEMATTR_WB 0xf | |
180 | #define CBAR_TYPE_SHIFT 16 | |
181 | #define CBAR_TYPE_MASK 0x3 | |
182 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
183 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
184 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
185 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
186 | #define CBAR_IRPTNDX_SHIFT 24 | |
187 | #define CBAR_IRPTNDX_MASK 0xff | |
188 | ||
189 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
190 | #define CBA2R_RW64_32BIT (0 << 0) | |
191 | #define CBA2R_RW64_64BIT (1 << 0) | |
192 | ||
193 | /* Translation context bank */ | |
194 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
c757e852 | 195 | #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) |
45ae7cff WD |
196 | |
197 | #define ARM_SMMU_CB_SCTLR 0x0 | |
198 | #define ARM_SMMU_CB_RESUME 0x8 | |
199 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
668b4ada TC |
200 | #define ARM_SMMU_CB_TTBR0 0x20 |
201 | #define ARM_SMMU_CB_TTBR1 0x28 | |
45ae7cff WD |
202 | #define ARM_SMMU_CB_TTBCR 0x30 |
203 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
518f7136 | 204 | #define ARM_SMMU_CB_S1_MAIR1 0x3c |
859a732e MH |
205 | #define ARM_SMMU_CB_PAR_LO 0x50 |
206 | #define ARM_SMMU_CB_PAR_HI 0x54 | |
45ae7cff WD |
207 | #define ARM_SMMU_CB_FSR 0x58 |
208 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
209 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
210 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
518f7136 | 211 | #define ARM_SMMU_CB_S1_TLBIVA 0x600 |
1463fe44 | 212 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
518f7136 WD |
213 | #define ARM_SMMU_CB_S1_TLBIVAL 0x620 |
214 | #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 | |
215 | #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 | |
661d962f | 216 | #define ARM_SMMU_CB_ATS1PR 0x800 |
859a732e | 217 | #define ARM_SMMU_CB_ATSR 0x8f0 |
45ae7cff WD |
218 | |
219 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
220 | #define SCTLR_CFCFG (1 << 7) | |
221 | #define SCTLR_CFIE (1 << 6) | |
222 | #define SCTLR_CFRE (1 << 5) | |
223 | #define SCTLR_E (1 << 4) | |
224 | #define SCTLR_AFE (1 << 2) | |
225 | #define SCTLR_TRE (1 << 1) | |
226 | #define SCTLR_M (1 << 0) | |
227 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
228 | ||
859a732e MH |
229 | #define CB_PAR_F (1 << 0) |
230 | ||
231 | #define ATSR_ACTIVE (1 << 0) | |
232 | ||
45ae7cff WD |
233 | #define RESUME_RETRY (0 << 0) |
234 | #define RESUME_TERMINATE (1 << 0) | |
235 | ||
45ae7cff | 236 | #define TTBCR2_SEP_SHIFT 15 |
5dc5616e | 237 | #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) |
45ae7cff | 238 | |
668b4ada | 239 | #define TTBRn_ASID_SHIFT 48 |
45ae7cff WD |
240 | |
241 | #define FSR_MULTI (1 << 31) | |
242 | #define FSR_SS (1 << 30) | |
243 | #define FSR_UUT (1 << 8) | |
244 | #define FSR_ASF (1 << 7) | |
245 | #define FSR_TLBLKF (1 << 6) | |
246 | #define FSR_TLBMCF (1 << 5) | |
247 | #define FSR_EF (1 << 4) | |
248 | #define FSR_PF (1 << 3) | |
249 | #define FSR_AFF (1 << 2) | |
250 | #define FSR_TF (1 << 1) | |
251 | ||
2907320d MH |
252 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
253 | FSR_TLBMCF | FSR_TLBLKF) | |
254 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 255 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
256 | |
257 | #define FSYNR0_WNR (1 << 4) | |
258 | ||
4cf740b0 | 259 | static int force_stage; |
e3ce0c94 | 260 | module_param_named(force_stage, force_stage, int, S_IRUGO); |
4cf740b0 WD |
261 | MODULE_PARM_DESC(force_stage, |
262 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); | |
263 | ||
09360403 RM |
264 | enum arm_smmu_arch_version { |
265 | ARM_SMMU_V1 = 1, | |
266 | ARM_SMMU_V2, | |
267 | }; | |
268 | ||
45ae7cff WD |
269 | struct arm_smmu_smr { |
270 | u8 idx; | |
271 | u16 mask; | |
272 | u16 id; | |
273 | }; | |
274 | ||
a9a1b0b5 | 275 | struct arm_smmu_master_cfg { |
45ae7cff WD |
276 | int num_streamids; |
277 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
278 | struct arm_smmu_smr *smrs; |
279 | }; | |
280 | ||
a9a1b0b5 WD |
281 | struct arm_smmu_master { |
282 | struct device_node *of_node; | |
a9a1b0b5 WD |
283 | struct rb_node node; |
284 | struct arm_smmu_master_cfg cfg; | |
285 | }; | |
286 | ||
45ae7cff WD |
287 | struct arm_smmu_device { |
288 | struct device *dev; | |
45ae7cff WD |
289 | |
290 | void __iomem *base; | |
291 | unsigned long size; | |
c757e852 | 292 | unsigned long pgshift; |
45ae7cff WD |
293 | |
294 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
295 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
296 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
297 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
298 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
859a732e | 299 | #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5) |
45ae7cff | 300 | u32 features; |
3a5df8ff AH |
301 | |
302 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
303 | u32 options; | |
09360403 | 304 | enum arm_smmu_arch_version version; |
45ae7cff WD |
305 | |
306 | u32 num_context_banks; | |
307 | u32 num_s2_context_banks; | |
308 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
309 | atomic_t irptndx; | |
310 | ||
311 | u32 num_mapping_groups; | |
312 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
313 | ||
518f7136 WD |
314 | unsigned long va_size; |
315 | unsigned long ipa_size; | |
316 | unsigned long pa_size; | |
45ae7cff WD |
317 | |
318 | u32 num_global_irqs; | |
319 | u32 num_context_irqs; | |
320 | unsigned int *irqs; | |
321 | ||
45ae7cff WD |
322 | struct list_head list; |
323 | struct rb_root masters; | |
324 | }; | |
325 | ||
326 | struct arm_smmu_cfg { | |
45ae7cff WD |
327 | u8 cbndx; |
328 | u8 irptndx; | |
329 | u32 cbar; | |
45ae7cff | 330 | }; |
faea13b7 | 331 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 332 | |
ecfadb6e WD |
333 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
334 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
335 | ||
c752ce45 WD |
336 | enum arm_smmu_domain_stage { |
337 | ARM_SMMU_DOMAIN_S1 = 0, | |
338 | ARM_SMMU_DOMAIN_S2, | |
339 | ARM_SMMU_DOMAIN_NESTED, | |
340 | }; | |
341 | ||
45ae7cff | 342 | struct arm_smmu_domain { |
44680eed | 343 | struct arm_smmu_device *smmu; |
518f7136 WD |
344 | struct io_pgtable_ops *pgtbl_ops; |
345 | spinlock_t pgtbl_lock; | |
44680eed | 346 | struct arm_smmu_cfg cfg; |
c752ce45 | 347 | enum arm_smmu_domain_stage stage; |
518f7136 | 348 | struct mutex init_mutex; /* Protects smmu pointer */ |
1d672638 | 349 | struct iommu_domain domain; |
45ae7cff WD |
350 | }; |
351 | ||
518f7136 WD |
352 | static struct iommu_ops arm_smmu_ops; |
353 | ||
45ae7cff WD |
354 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); |
355 | static LIST_HEAD(arm_smmu_devices); | |
356 | ||
3a5df8ff AH |
357 | struct arm_smmu_option_prop { |
358 | u32 opt; | |
359 | const char *prop; | |
360 | }; | |
361 | ||
2907320d | 362 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
363 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
364 | { 0, NULL}, | |
365 | }; | |
366 | ||
1d672638 JR |
367 | static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) |
368 | { | |
369 | return container_of(dom, struct arm_smmu_domain, domain); | |
370 | } | |
371 | ||
3a5df8ff AH |
372 | static void parse_driver_options(struct arm_smmu_device *smmu) |
373 | { | |
374 | int i = 0; | |
2907320d | 375 | |
3a5df8ff AH |
376 | do { |
377 | if (of_property_read_bool(smmu->dev->of_node, | |
378 | arm_smmu_options[i].prop)) { | |
379 | smmu->options |= arm_smmu_options[i].opt; | |
380 | dev_notice(smmu->dev, "option %s\n", | |
381 | arm_smmu_options[i].prop); | |
382 | } | |
383 | } while (arm_smmu_options[++i].opt); | |
384 | } | |
385 | ||
8f68f8e2 | 386 | static struct device_node *dev_get_dev_node(struct device *dev) |
a9a1b0b5 WD |
387 | { |
388 | if (dev_is_pci(dev)) { | |
389 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 390 | |
a9a1b0b5 WD |
391 | while (!pci_is_root_bus(bus)) |
392 | bus = bus->parent; | |
8f68f8e2 | 393 | return bus->bridge->parent->of_node; |
a9a1b0b5 WD |
394 | } |
395 | ||
8f68f8e2 | 396 | return dev->of_node; |
a9a1b0b5 WD |
397 | } |
398 | ||
45ae7cff WD |
399 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
400 | struct device_node *dev_node) | |
401 | { | |
402 | struct rb_node *node = smmu->masters.rb_node; | |
403 | ||
404 | while (node) { | |
405 | struct arm_smmu_master *master; | |
2907320d | 406 | |
45ae7cff WD |
407 | master = container_of(node, struct arm_smmu_master, node); |
408 | ||
409 | if (dev_node < master->of_node) | |
410 | node = node->rb_left; | |
411 | else if (dev_node > master->of_node) | |
412 | node = node->rb_right; | |
413 | else | |
414 | return master; | |
415 | } | |
416 | ||
417 | return NULL; | |
418 | } | |
419 | ||
a9a1b0b5 | 420 | static struct arm_smmu_master_cfg * |
8f68f8e2 | 421 | find_smmu_master_cfg(struct device *dev) |
a9a1b0b5 | 422 | { |
8f68f8e2 WD |
423 | struct arm_smmu_master_cfg *cfg = NULL; |
424 | struct iommu_group *group = iommu_group_get(dev); | |
a9a1b0b5 | 425 | |
8f68f8e2 WD |
426 | if (group) { |
427 | cfg = iommu_group_get_iommudata(group); | |
428 | iommu_group_put(group); | |
429 | } | |
a9a1b0b5 | 430 | |
8f68f8e2 | 431 | return cfg; |
a9a1b0b5 WD |
432 | } |
433 | ||
45ae7cff WD |
434 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
435 | struct arm_smmu_master *master) | |
436 | { | |
437 | struct rb_node **new, *parent; | |
438 | ||
439 | new = &smmu->masters.rb_node; | |
440 | parent = NULL; | |
441 | while (*new) { | |
2907320d MH |
442 | struct arm_smmu_master *this |
443 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
444 | |
445 | parent = *new; | |
446 | if (master->of_node < this->of_node) | |
447 | new = &((*new)->rb_left); | |
448 | else if (master->of_node > this->of_node) | |
449 | new = &((*new)->rb_right); | |
450 | else | |
451 | return -EEXIST; | |
452 | } | |
453 | ||
454 | rb_link_node(&master->node, parent, new); | |
455 | rb_insert_color(&master->node, &smmu->masters); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
460 | struct device *dev, | |
461 | struct of_phandle_args *masterspec) | |
462 | { | |
463 | int i; | |
464 | struct arm_smmu_master *master; | |
465 | ||
466 | master = find_smmu_master(smmu, masterspec->np); | |
467 | if (master) { | |
468 | dev_err(dev, | |
469 | "rejecting multiple registrations for master device %s\n", | |
470 | masterspec->np->name); | |
471 | return -EBUSY; | |
472 | } | |
473 | ||
474 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
475 | dev_err(dev, | |
476 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
477 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
478 | return -ENOSPC; | |
479 | } | |
480 | ||
481 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
482 | if (!master) | |
483 | return -ENOMEM; | |
484 | ||
a9a1b0b5 WD |
485 | master->of_node = masterspec->np; |
486 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 487 | |
3c8766d0 OH |
488 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
489 | u16 streamid = masterspec->args[i]; | |
45ae7cff | 490 | |
3c8766d0 OH |
491 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
492 | (streamid >= smmu->num_mapping_groups)) { | |
493 | dev_err(dev, | |
494 | "stream ID for master device %s greater than maximum allowed (%d)\n", | |
495 | masterspec->np->name, smmu->num_mapping_groups); | |
496 | return -ERANGE; | |
497 | } | |
498 | master->cfg.streamids[i] = streamid; | |
499 | } | |
45ae7cff WD |
500 | return insert_smmu_master(smmu, master); |
501 | } | |
502 | ||
44680eed | 503 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 504 | { |
44680eed | 505 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 506 | struct arm_smmu_master *master = NULL; |
8f68f8e2 | 507 | struct device_node *dev_node = dev_get_dev_node(dev); |
45ae7cff WD |
508 | |
509 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 510 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
511 | master = find_smmu_master(smmu, dev_node); |
512 | if (master) | |
513 | break; | |
514 | } | |
45ae7cff | 515 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 516 | |
a9a1b0b5 | 517 | return master ? smmu : NULL; |
45ae7cff WD |
518 | } |
519 | ||
520 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
521 | { | |
522 | int idx; | |
523 | ||
524 | do { | |
525 | idx = find_next_zero_bit(map, end, start); | |
526 | if (idx == end) | |
527 | return -ENOSPC; | |
528 | } while (test_and_set_bit(idx, map)); | |
529 | ||
530 | return idx; | |
531 | } | |
532 | ||
533 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
534 | { | |
535 | clear_bit(idx, map); | |
536 | } | |
537 | ||
538 | /* Wait for any pending TLB invalidations to complete */ | |
518f7136 | 539 | static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) |
45ae7cff WD |
540 | { |
541 | int count = 0; | |
542 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
543 | ||
544 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
545 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
546 | & sTLBGSTATUS_GSACTIVE) { | |
547 | cpu_relax(); | |
548 | if (++count == TLB_LOOP_TIMEOUT) { | |
549 | dev_err_ratelimited(smmu->dev, | |
550 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
551 | return; | |
552 | } | |
553 | udelay(1); | |
554 | } | |
555 | } | |
556 | ||
518f7136 WD |
557 | static void arm_smmu_tlb_sync(void *cookie) |
558 | { | |
559 | struct arm_smmu_domain *smmu_domain = cookie; | |
560 | __arm_smmu_tlb_sync(smmu_domain->smmu); | |
561 | } | |
562 | ||
563 | static void arm_smmu_tlb_inv_context(void *cookie) | |
1463fe44 | 564 | { |
518f7136 | 565 | struct arm_smmu_domain *smmu_domain = cookie; |
44680eed WD |
566 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
567 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 | 568 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
518f7136 | 569 | void __iomem *base; |
1463fe44 WD |
570 | |
571 | if (stage1) { | |
572 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
573 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
574 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
575 | } else { |
576 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
577 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
578 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
579 | } |
580 | ||
518f7136 WD |
581 | __arm_smmu_tlb_sync(smmu); |
582 | } | |
583 | ||
584 | static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, | |
585 | bool leaf, void *cookie) | |
586 | { | |
587 | struct arm_smmu_domain *smmu_domain = cookie; | |
588 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
589 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
590 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
591 | void __iomem *reg; | |
592 | ||
593 | if (stage1) { | |
594 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
595 | reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; | |
596 | ||
597 | if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { | |
598 | iova &= ~12UL; | |
599 | iova |= ARM_SMMU_CB_ASID(cfg); | |
600 | writel_relaxed(iova, reg); | |
601 | #ifdef CONFIG_64BIT | |
602 | } else { | |
603 | iova >>= 12; | |
604 | iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; | |
605 | writeq_relaxed(iova, reg); | |
606 | #endif | |
607 | } | |
608 | #ifdef CONFIG_64BIT | |
609 | } else if (smmu->version == ARM_SMMU_V2) { | |
610 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
611 | reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L : | |
612 | ARM_SMMU_CB_S2_TLBIIPAS2; | |
613 | writeq_relaxed(iova >> 12, reg); | |
614 | #endif | |
615 | } else { | |
616 | reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; | |
617 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); | |
618 | } | |
619 | } | |
620 | ||
518f7136 WD |
621 | static struct iommu_gather_ops arm_smmu_gather_ops = { |
622 | .tlb_flush_all = arm_smmu_tlb_inv_context, | |
623 | .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, | |
624 | .tlb_sync = arm_smmu_tlb_sync, | |
518f7136 WD |
625 | }; |
626 | ||
45ae7cff WD |
627 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
628 | { | |
629 | int flags, ret; | |
630 | u32 fsr, far, fsynr, resume; | |
631 | unsigned long iova; | |
632 | struct iommu_domain *domain = dev; | |
1d672638 | 633 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
44680eed WD |
634 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
635 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
636 | void __iomem *cb_base; |
637 | ||
44680eed | 638 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
639 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
640 | ||
641 | if (!(fsr & FSR_FAULT)) | |
642 | return IRQ_NONE; | |
643 | ||
644 | if (fsr & FSR_IGN) | |
645 | dev_err_ratelimited(smmu->dev, | |
70c9a7db | 646 | "Unexpected context fault (fsr 0x%x)\n", |
45ae7cff WD |
647 | fsr); |
648 | ||
649 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
650 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
651 | ||
652 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
653 | iova = far; | |
654 | #ifdef CONFIG_64BIT | |
655 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
656 | iova |= ((unsigned long)far << 32); | |
657 | #endif | |
658 | ||
659 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
660 | ret = IRQ_HANDLED; | |
661 | resume = RESUME_RETRY; | |
662 | } else { | |
2ef0f031 AH |
663 | dev_err_ratelimited(smmu->dev, |
664 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 665 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
666 | ret = IRQ_NONE; |
667 | resume = RESUME_TERMINATE; | |
668 | } | |
669 | ||
670 | /* Clear the faulting FSR */ | |
671 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
672 | ||
673 | /* Retry or terminate any stalled transactions */ | |
674 | if (fsr & FSR_SS) | |
675 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
676 | ||
677 | return ret; | |
678 | } | |
679 | ||
680 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
681 | { | |
682 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
683 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 684 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
685 | |
686 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
687 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
688 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
689 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
690 | ||
3a5df8ff AH |
691 | if (!gfsr) |
692 | return IRQ_NONE; | |
693 | ||
45ae7cff WD |
694 | dev_err_ratelimited(smmu->dev, |
695 | "Unexpected global fault, this could be serious\n"); | |
696 | dev_err_ratelimited(smmu->dev, | |
697 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
698 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
699 | ||
700 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 701 | return IRQ_HANDLED; |
45ae7cff WD |
702 | } |
703 | ||
518f7136 WD |
704 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, |
705 | struct io_pgtable_cfg *pgtbl_cfg) | |
45ae7cff WD |
706 | { |
707 | u32 reg; | |
668b4ada | 708 | u64 reg64; |
45ae7cff | 709 | bool stage1; |
44680eed WD |
710 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
711 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
c88ae5de | 712 | void __iomem *cb_base, *gr1_base; |
45ae7cff | 713 | |
45ae7cff | 714 | gr1_base = ARM_SMMU_GR1(smmu); |
44680eed WD |
715 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
716 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff | 717 | |
4a1c93cb WD |
718 | if (smmu->version > ARM_SMMU_V1) { |
719 | /* | |
720 | * CBA2R. | |
721 | * *Must* be initialised before CBAR thanks to VMID16 | |
722 | * architectural oversight affected some implementations. | |
723 | */ | |
724 | #ifdef CONFIG_64BIT | |
725 | reg = CBA2R_RW64_64BIT; | |
726 | #else | |
727 | reg = CBA2R_RW64_32BIT; | |
728 | #endif | |
729 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); | |
730 | } | |
731 | ||
45ae7cff | 732 | /* CBAR */ |
44680eed | 733 | reg = cfg->cbar; |
09360403 | 734 | if (smmu->version == ARM_SMMU_V1) |
2907320d | 735 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 736 | |
57ca90f6 WD |
737 | /* |
738 | * Use the weakest shareability/memory types, so they are | |
739 | * overridden by the ttbcr/pte. | |
740 | */ | |
741 | if (stage1) { | |
742 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
743 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
744 | } else { | |
44680eed | 745 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 746 | } |
44680eed | 747 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff | 748 | |
518f7136 WD |
749 | /* TTBRs */ |
750 | if (stage1) { | |
668b4ada TC |
751 | reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; |
752 | ||
753 | reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; | |
754 | smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0); | |
755 | ||
756 | reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; | |
757 | reg64 |= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT; | |
758 | smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1); | |
518f7136 | 759 | } else { |
668b4ada TC |
760 | reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; |
761 | smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0); | |
518f7136 | 762 | } |
a65217a4 | 763 | |
518f7136 WD |
764 | /* TTBCR */ |
765 | if (stage1) { | |
766 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; | |
767 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
768 | if (smmu->version > ARM_SMMU_V1) { | |
769 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; | |
5dc5616e | 770 | reg |= TTBCR2_SEP_UPSTREAM; |
518f7136 | 771 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); |
45ae7cff WD |
772 | } |
773 | } else { | |
518f7136 WD |
774 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; |
775 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
45ae7cff WD |
776 | } |
777 | ||
518f7136 | 778 | /* MAIRs (stage-1 only) */ |
45ae7cff | 779 | if (stage1) { |
518f7136 | 780 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; |
45ae7cff | 781 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); |
518f7136 WD |
782 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; |
783 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1); | |
45ae7cff WD |
784 | } |
785 | ||
45ae7cff WD |
786 | /* SCTLR */ |
787 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
788 | if (stage1) | |
789 | reg |= SCTLR_S1_ASIDPNE; | |
790 | #ifdef __BIG_ENDIAN | |
791 | reg |= SCTLR_E; | |
792 | #endif | |
25724841 | 793 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
794 | } |
795 | ||
796 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 797 | struct arm_smmu_device *smmu) |
45ae7cff | 798 | { |
a18037b2 | 799 | int irq, start, ret = 0; |
518f7136 WD |
800 | unsigned long ias, oas; |
801 | struct io_pgtable_ops *pgtbl_ops; | |
802 | struct io_pgtable_cfg pgtbl_cfg; | |
803 | enum io_pgtable_fmt fmt; | |
1d672638 | 804 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
44680eed | 805 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 806 | |
518f7136 | 807 | mutex_lock(&smmu_domain->init_mutex); |
a18037b2 MH |
808 | if (smmu_domain->smmu) |
809 | goto out_unlock; | |
810 | ||
c752ce45 WD |
811 | /* |
812 | * Mapping the requested stage onto what we support is surprisingly | |
813 | * complicated, mainly because the spec allows S1+S2 SMMUs without | |
814 | * support for nested translation. That means we end up with the | |
815 | * following table: | |
816 | * | |
817 | * Requested Supported Actual | |
818 | * S1 N S1 | |
819 | * S1 S1+S2 S1 | |
820 | * S1 S2 S2 | |
821 | * S1 S1 S1 | |
822 | * N N N | |
823 | * N S1+S2 S2 | |
824 | * N S2 S2 | |
825 | * N S1 S1 | |
826 | * | |
827 | * Note that you can't actually request stage-2 mappings. | |
828 | */ | |
829 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) | |
830 | smmu_domain->stage = ARM_SMMU_DOMAIN_S2; | |
831 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) | |
832 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; | |
833 | ||
834 | switch (smmu_domain->stage) { | |
835 | case ARM_SMMU_DOMAIN_S1: | |
836 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; | |
837 | start = smmu->num_s2_context_banks; | |
518f7136 WD |
838 | ias = smmu->va_size; |
839 | oas = smmu->ipa_size; | |
840 | if (IS_ENABLED(CONFIG_64BIT)) | |
841 | fmt = ARM_64_LPAE_S1; | |
842 | else | |
843 | fmt = ARM_32_LPAE_S1; | |
c752ce45 WD |
844 | break; |
845 | case ARM_SMMU_DOMAIN_NESTED: | |
45ae7cff WD |
846 | /* |
847 | * We will likely want to change this if/when KVM gets | |
848 | * involved. | |
849 | */ | |
c752ce45 | 850 | case ARM_SMMU_DOMAIN_S2: |
9c5c92e3 WD |
851 | cfg->cbar = CBAR_TYPE_S2_TRANS; |
852 | start = 0; | |
518f7136 WD |
853 | ias = smmu->ipa_size; |
854 | oas = smmu->pa_size; | |
855 | if (IS_ENABLED(CONFIG_64BIT)) | |
856 | fmt = ARM_64_LPAE_S2; | |
857 | else | |
858 | fmt = ARM_32_LPAE_S2; | |
c752ce45 WD |
859 | break; |
860 | default: | |
861 | ret = -EINVAL; | |
862 | goto out_unlock; | |
45ae7cff WD |
863 | } |
864 | ||
865 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
866 | smmu->num_context_banks); | |
867 | if (IS_ERR_VALUE(ret)) | |
a18037b2 | 868 | goto out_unlock; |
45ae7cff | 869 | |
44680eed | 870 | cfg->cbndx = ret; |
09360403 | 871 | if (smmu->version == ARM_SMMU_V1) { |
44680eed WD |
872 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
873 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 874 | } else { |
44680eed | 875 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
876 | } |
877 | ||
518f7136 WD |
878 | pgtbl_cfg = (struct io_pgtable_cfg) { |
879 | .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, | |
880 | .ias = ias, | |
881 | .oas = oas, | |
882 | .tlb = &arm_smmu_gather_ops, | |
2df7a25c | 883 | .iommu_dev = smmu->dev, |
518f7136 WD |
884 | }; |
885 | ||
886 | smmu_domain->smmu = smmu; | |
887 | pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); | |
888 | if (!pgtbl_ops) { | |
889 | ret = -ENOMEM; | |
890 | goto out_clear_smmu; | |
891 | } | |
892 | ||
893 | /* Update our support page sizes to reflect the page table format */ | |
894 | arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; | |
a18037b2 | 895 | |
518f7136 WD |
896 | /* Initialise the context bank with our page table cfg */ |
897 | arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); | |
898 | ||
899 | /* | |
900 | * Request context fault interrupt. Do this last to avoid the | |
901 | * handler seeing a half-initialised domain state. | |
902 | */ | |
44680eed | 903 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
904 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
905 | "arm-smmu-context-fault", domain); | |
906 | if (IS_ERR_VALUE(ret)) { | |
907 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
908 | cfg->irptndx, irq); |
909 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
910 | } |
911 | ||
518f7136 WD |
912 | mutex_unlock(&smmu_domain->init_mutex); |
913 | ||
914 | /* Publish page table ops for map/unmap */ | |
915 | smmu_domain->pgtbl_ops = pgtbl_ops; | |
a9a1b0b5 | 916 | return 0; |
45ae7cff | 917 | |
518f7136 WD |
918 | out_clear_smmu: |
919 | smmu_domain->smmu = NULL; | |
a18037b2 | 920 | out_unlock: |
518f7136 | 921 | mutex_unlock(&smmu_domain->init_mutex); |
45ae7cff WD |
922 | return ret; |
923 | } | |
924 | ||
925 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
926 | { | |
1d672638 | 927 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
44680eed WD |
928 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
929 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 930 | void __iomem *cb_base; |
45ae7cff WD |
931 | int irq; |
932 | ||
933 | if (!smmu) | |
934 | return; | |
935 | ||
518f7136 WD |
936 | /* |
937 | * Disable the context bank and free the page tables before freeing | |
938 | * it. | |
939 | */ | |
44680eed | 940 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 941 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
1463fe44 | 942 | |
44680eed WD |
943 | if (cfg->irptndx != INVALID_IRPTNDX) { |
944 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
945 | free_irq(irq, domain); |
946 | } | |
947 | ||
44830b0c | 948 | free_io_pgtable_ops(smmu_domain->pgtbl_ops); |
44680eed | 949 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
950 | } |
951 | ||
1d672638 | 952 | static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) |
45ae7cff WD |
953 | { |
954 | struct arm_smmu_domain *smmu_domain; | |
45ae7cff | 955 | |
1d672638 JR |
956 | if (type != IOMMU_DOMAIN_UNMANAGED) |
957 | return NULL; | |
45ae7cff WD |
958 | /* |
959 | * Allocate the domain and initialise some of its data structures. | |
960 | * We can't really do anything meaningful until we've added a | |
961 | * master. | |
962 | */ | |
963 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
964 | if (!smmu_domain) | |
1d672638 | 965 | return NULL; |
45ae7cff | 966 | |
518f7136 WD |
967 | mutex_init(&smmu_domain->init_mutex); |
968 | spin_lock_init(&smmu_domain->pgtbl_lock); | |
1d672638 JR |
969 | |
970 | return &smmu_domain->domain; | |
45ae7cff WD |
971 | } |
972 | ||
1d672638 | 973 | static void arm_smmu_domain_free(struct iommu_domain *domain) |
45ae7cff | 974 | { |
1d672638 | 975 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
1463fe44 WD |
976 | |
977 | /* | |
978 | * Free the domain resources. We assume that all devices have | |
979 | * already been detached. | |
980 | */ | |
45ae7cff | 981 | arm_smmu_destroy_domain_context(domain); |
45ae7cff WD |
982 | kfree(smmu_domain); |
983 | } | |
984 | ||
985 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 986 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
987 | { |
988 | int i; | |
989 | struct arm_smmu_smr *smrs; | |
990 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
991 | ||
992 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
993 | return 0; | |
994 | ||
a9a1b0b5 | 995 | if (cfg->smrs) |
45ae7cff WD |
996 | return -EEXIST; |
997 | ||
2907320d | 998 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 999 | if (!smrs) { |
a9a1b0b5 WD |
1000 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1001 | cfg->num_streamids); | |
45ae7cff WD |
1002 | return -ENOMEM; |
1003 | } | |
1004 | ||
44680eed | 1005 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1006 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1007 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1008 | smmu->num_mapping_groups); | |
1009 | if (IS_ERR_VALUE(idx)) { | |
1010 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1011 | goto err_free_smrs; | |
1012 | } | |
1013 | ||
1014 | smrs[i] = (struct arm_smmu_smr) { | |
1015 | .idx = idx, | |
1016 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1017 | .id = cfg->streamids[i], |
45ae7cff WD |
1018 | }; |
1019 | } | |
1020 | ||
1021 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1022 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1023 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1024 | smrs[i].mask << SMR_MASK_SHIFT; | |
1025 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1026 | } | |
1027 | ||
a9a1b0b5 | 1028 | cfg->smrs = smrs; |
45ae7cff WD |
1029 | return 0; |
1030 | ||
1031 | err_free_smrs: | |
1032 | while (--i >= 0) | |
1033 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1034 | kfree(smrs); | |
1035 | return -ENOSPC; | |
1036 | } | |
1037 | ||
1038 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1039 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1040 | { |
1041 | int i; | |
1042 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1043 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff | 1044 | |
43b412be WD |
1045 | if (!smrs) |
1046 | return; | |
1047 | ||
45ae7cff | 1048 | /* Invalidate the SMRs before freeing back to the allocator */ |
a9a1b0b5 | 1049 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1050 | u8 idx = smrs[i].idx; |
2907320d | 1051 | |
45ae7cff WD |
1052 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1053 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1054 | } | |
1055 | ||
a9a1b0b5 | 1056 | cfg->smrs = NULL; |
45ae7cff WD |
1057 | kfree(smrs); |
1058 | } | |
1059 | ||
45ae7cff | 1060 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
a9a1b0b5 | 1061 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1062 | { |
1063 | int i, ret; | |
44680eed | 1064 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1065 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1066 | ||
8f68f8e2 | 1067 | /* Devices in an IOMMU group may already be configured */ |
a9a1b0b5 | 1068 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff | 1069 | if (ret) |
8f68f8e2 | 1070 | return ret == -EEXIST ? 0 : ret; |
45ae7cff | 1071 | |
a9a1b0b5 | 1072 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1073 | u32 idx, s2cr; |
2907320d | 1074 | |
a9a1b0b5 | 1075 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1076 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1077 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1078 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1079 | } | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1085 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1086 | { |
43b412be | 1087 | int i; |
44680eed | 1088 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
43b412be | 1089 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
45ae7cff | 1090 | |
8f68f8e2 WD |
1091 | /* An IOMMU group is torn down by the first device to be removed */ |
1092 | if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) | |
1093 | return; | |
45ae7cff WD |
1094 | |
1095 | /* | |
1096 | * We *must* clear the S2CR first, because freeing the SMR means | |
1097 | * that it can be re-allocated immediately. | |
1098 | */ | |
43b412be WD |
1099 | for (i = 0; i < cfg->num_streamids; ++i) { |
1100 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; | |
1101 | ||
1102 | writel_relaxed(S2CR_TYPE_BYPASS, | |
1103 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); | |
1104 | } | |
1105 | ||
a9a1b0b5 | 1106 | arm_smmu_master_free_smrs(smmu, cfg); |
45ae7cff WD |
1107 | } |
1108 | ||
1109 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1110 | { | |
a18037b2 | 1111 | int ret; |
1d672638 | 1112 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
518f7136 | 1113 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 1114 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1115 | |
8f68f8e2 | 1116 | smmu = find_smmu_for_device(dev); |
44680eed | 1117 | if (!smmu) { |
45ae7cff WD |
1118 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1119 | return -ENXIO; | |
1120 | } | |
1121 | ||
844e35bd WD |
1122 | if (dev->archdata.iommu) { |
1123 | dev_err(dev, "already attached to IOMMU domain\n"); | |
1124 | return -EEXIST; | |
1125 | } | |
1126 | ||
518f7136 WD |
1127 | /* Ensure that the domain is finalised */ |
1128 | ret = arm_smmu_init_domain_context(domain, smmu); | |
1129 | if (IS_ERR_VALUE(ret)) | |
1130 | return ret; | |
1131 | ||
45ae7cff | 1132 | /* |
44680eed WD |
1133 | * Sanity check the domain. We don't support domains across |
1134 | * different SMMUs. | |
45ae7cff | 1135 | */ |
518f7136 | 1136 | if (smmu_domain->smmu != smmu) { |
45ae7cff WD |
1137 | dev_err(dev, |
1138 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
a18037b2 MH |
1139 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
1140 | return -EINVAL; | |
45ae7cff | 1141 | } |
45ae7cff WD |
1142 | |
1143 | /* Looks ok, so add the device to the domain */ | |
8f68f8e2 | 1144 | cfg = find_smmu_master_cfg(dev); |
a9a1b0b5 | 1145 | if (!cfg) |
45ae7cff WD |
1146 | return -ENODEV; |
1147 | ||
844e35bd WD |
1148 | ret = arm_smmu_domain_add_master(smmu_domain, cfg); |
1149 | if (!ret) | |
1150 | dev->archdata.iommu = domain; | |
45ae7cff WD |
1151 | return ret; |
1152 | } | |
1153 | ||
1154 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1155 | { | |
1d672638 | 1156 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
a9a1b0b5 | 1157 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1158 | |
8f68f8e2 | 1159 | cfg = find_smmu_master_cfg(dev); |
844e35bd WD |
1160 | if (!cfg) |
1161 | return; | |
1162 | ||
1163 | dev->archdata.iommu = NULL; | |
1164 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1165 | } |
1166 | ||
45ae7cff | 1167 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, |
b410aed9 | 1168 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff | 1169 | { |
518f7136 WD |
1170 | int ret; |
1171 | unsigned long flags; | |
1d672638 | 1172 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
518f7136 | 1173 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1174 | |
518f7136 | 1175 | if (!ops) |
45ae7cff WD |
1176 | return -ENODEV; |
1177 | ||
518f7136 WD |
1178 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
1179 | ret = ops->map(ops, iova, paddr, size, prot); | |
1180 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); | |
1181 | return ret; | |
45ae7cff WD |
1182 | } |
1183 | ||
1184 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1185 | size_t size) | |
1186 | { | |
518f7136 WD |
1187 | size_t ret; |
1188 | unsigned long flags; | |
1d672638 | 1189 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
518f7136 | 1190 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1191 | |
518f7136 WD |
1192 | if (!ops) |
1193 | return 0; | |
1194 | ||
1195 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); | |
1196 | ret = ops->unmap(ops, iova, size); | |
1197 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); | |
1198 | return ret; | |
45ae7cff WD |
1199 | } |
1200 | ||
859a732e MH |
1201 | static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, |
1202 | dma_addr_t iova) | |
1203 | { | |
1d672638 | 1204 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
859a732e MH |
1205 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1206 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1207 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; | |
1208 | struct device *dev = smmu->dev; | |
1209 | void __iomem *cb_base; | |
1210 | u32 tmp; | |
1211 | u64 phys; | |
661d962f | 1212 | unsigned long va; |
859a732e MH |
1213 | |
1214 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
1215 | ||
661d962f RM |
1216 | /* ATS1 registers can only be written atomically */ |
1217 | va = iova & ~0xfffUL; | |
661d962f | 1218 | if (smmu->version == ARM_SMMU_V2) |
668b4ada | 1219 | smmu_writeq(va, cb_base + ARM_SMMU_CB_ATS1PR); |
661d962f | 1220 | else |
661d962f | 1221 | writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR); |
859a732e MH |
1222 | |
1223 | if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp, | |
1224 | !(tmp & ATSR_ACTIVE), 5, 50)) { | |
1225 | dev_err(dev, | |
077124c9 | 1226 | "iova to phys timed out on %pad. Falling back to software table walk.\n", |
859a732e MH |
1227 | &iova); |
1228 | return ops->iova_to_phys(ops, iova); | |
1229 | } | |
1230 | ||
1231 | phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO); | |
1232 | phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32; | |
1233 | ||
1234 | if (phys & CB_PAR_F) { | |
1235 | dev_err(dev, "translation fault!\n"); | |
1236 | dev_err(dev, "PAR = 0x%llx\n", phys); | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff); | |
1241 | } | |
1242 | ||
45ae7cff | 1243 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, |
859a732e | 1244 | dma_addr_t iova) |
45ae7cff | 1245 | { |
518f7136 WD |
1246 | phys_addr_t ret; |
1247 | unsigned long flags; | |
1d672638 | 1248 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
518f7136 | 1249 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1250 | |
518f7136 | 1251 | if (!ops) |
a44a9791 | 1252 | return 0; |
45ae7cff | 1253 | |
518f7136 | 1254 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
83a60ed8 BR |
1255 | if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && |
1256 | smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { | |
859a732e | 1257 | ret = arm_smmu_iova_to_phys_hard(domain, iova); |
83a60ed8 | 1258 | } else { |
859a732e | 1259 | ret = ops->iova_to_phys(ops, iova); |
83a60ed8 BR |
1260 | } |
1261 | ||
518f7136 | 1262 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
859a732e | 1263 | |
518f7136 | 1264 | return ret; |
45ae7cff WD |
1265 | } |
1266 | ||
1fd0c775 | 1267 | static bool arm_smmu_capable(enum iommu_cap cap) |
45ae7cff | 1268 | { |
d0948945 WD |
1269 | switch (cap) { |
1270 | case IOMMU_CAP_CACHE_COHERENCY: | |
1fd0c775 JR |
1271 | /* |
1272 | * Return true here as the SMMU can always send out coherent | |
1273 | * requests. | |
1274 | */ | |
1275 | return true; | |
d0948945 | 1276 | case IOMMU_CAP_INTR_REMAP: |
1fd0c775 | 1277 | return true; /* MSIs are just memory writes */ |
0029a8dd AM |
1278 | case IOMMU_CAP_NOEXEC: |
1279 | return true; | |
d0948945 | 1280 | default: |
1fd0c775 | 1281 | return false; |
d0948945 | 1282 | } |
45ae7cff | 1283 | } |
45ae7cff | 1284 | |
a9a1b0b5 WD |
1285 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1286 | { | |
1287 | *((u16 *)data) = alias; | |
1288 | return 0; /* Continue walking */ | |
45ae7cff WD |
1289 | } |
1290 | ||
8f68f8e2 WD |
1291 | static void __arm_smmu_release_pci_iommudata(void *data) |
1292 | { | |
1293 | kfree(data); | |
1294 | } | |
1295 | ||
af659932 JR |
1296 | static int arm_smmu_init_pci_device(struct pci_dev *pdev, |
1297 | struct iommu_group *group) | |
45ae7cff | 1298 | { |
03edb226 | 1299 | struct arm_smmu_master_cfg *cfg; |
af659932 JR |
1300 | u16 sid; |
1301 | int i; | |
a9a1b0b5 | 1302 | |
03edb226 WD |
1303 | cfg = iommu_group_get_iommudata(group); |
1304 | if (!cfg) { | |
a9a1b0b5 | 1305 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); |
af659932 JR |
1306 | if (!cfg) |
1307 | return -ENOMEM; | |
a9a1b0b5 | 1308 | |
03edb226 WD |
1309 | iommu_group_set_iommudata(group, cfg, |
1310 | __arm_smmu_release_pci_iommudata); | |
1311 | } | |
8f68f8e2 | 1312 | |
af659932 JR |
1313 | if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) |
1314 | return -ENOSPC; | |
a9a1b0b5 | 1315 | |
03edb226 WD |
1316 | /* |
1317 | * Assume Stream ID == Requester ID for now. | |
1318 | * We need a way to describe the ID mappings in FDT. | |
1319 | */ | |
1320 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); | |
1321 | for (i = 0; i < cfg->num_streamids; ++i) | |
1322 | if (cfg->streamids[i] == sid) | |
1323 | break; | |
1324 | ||
1325 | /* Avoid duplicate SIDs, as this can lead to SMR conflicts */ | |
1326 | if (i == cfg->num_streamids) | |
1327 | cfg->streamids[cfg->num_streamids++] = sid; | |
5fc63a7c | 1328 | |
03edb226 | 1329 | return 0; |
45ae7cff WD |
1330 | } |
1331 | ||
af659932 JR |
1332 | static int arm_smmu_init_platform_device(struct device *dev, |
1333 | struct iommu_group *group) | |
03edb226 | 1334 | { |
03edb226 | 1335 | struct arm_smmu_device *smmu = find_smmu_for_device(dev); |
af659932 | 1336 | struct arm_smmu_master *master; |
03edb226 WD |
1337 | |
1338 | if (!smmu) | |
1339 | return -ENODEV; | |
1340 | ||
1341 | master = find_smmu_master(smmu, dev->of_node); | |
1342 | if (!master) | |
1343 | return -ENODEV; | |
1344 | ||
03edb226 | 1345 | iommu_group_set_iommudata(group, &master->cfg, NULL); |
af659932 JR |
1346 | |
1347 | return 0; | |
03edb226 WD |
1348 | } |
1349 | ||
1350 | static int arm_smmu_add_device(struct device *dev) | |
1351 | { | |
af659932 | 1352 | struct iommu_group *group; |
03edb226 | 1353 | |
af659932 JR |
1354 | group = iommu_group_get_for_dev(dev); |
1355 | if (IS_ERR(group)) | |
1356 | return PTR_ERR(group); | |
03edb226 | 1357 | |
af659932 | 1358 | return 0; |
03edb226 WD |
1359 | } |
1360 | ||
45ae7cff WD |
1361 | static void arm_smmu_remove_device(struct device *dev) |
1362 | { | |
5fc63a7c | 1363 | iommu_group_remove_device(dev); |
45ae7cff WD |
1364 | } |
1365 | ||
af659932 JR |
1366 | static struct iommu_group *arm_smmu_device_group(struct device *dev) |
1367 | { | |
1368 | struct iommu_group *group; | |
1369 | int ret; | |
1370 | ||
1371 | if (dev_is_pci(dev)) | |
1372 | group = pci_device_group(dev); | |
1373 | else | |
1374 | group = generic_device_group(dev); | |
1375 | ||
1376 | if (IS_ERR(group)) | |
1377 | return group; | |
1378 | ||
1379 | if (dev_is_pci(dev)) | |
1380 | ret = arm_smmu_init_pci_device(to_pci_dev(dev), group); | |
1381 | else | |
1382 | ret = arm_smmu_init_platform_device(dev, group); | |
1383 | ||
1384 | if (ret) { | |
1385 | iommu_group_put(group); | |
1386 | group = ERR_PTR(ret); | |
1387 | } | |
1388 | ||
1389 | return group; | |
1390 | } | |
1391 | ||
c752ce45 WD |
1392 | static int arm_smmu_domain_get_attr(struct iommu_domain *domain, |
1393 | enum iommu_attr attr, void *data) | |
1394 | { | |
1d672638 | 1395 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
c752ce45 WD |
1396 | |
1397 | switch (attr) { | |
1398 | case DOMAIN_ATTR_NESTING: | |
1399 | *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); | |
1400 | return 0; | |
1401 | default: | |
1402 | return -ENODEV; | |
1403 | } | |
1404 | } | |
1405 | ||
1406 | static int arm_smmu_domain_set_attr(struct iommu_domain *domain, | |
1407 | enum iommu_attr attr, void *data) | |
1408 | { | |
518f7136 | 1409 | int ret = 0; |
1d672638 | 1410 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
c752ce45 | 1411 | |
518f7136 WD |
1412 | mutex_lock(&smmu_domain->init_mutex); |
1413 | ||
c752ce45 WD |
1414 | switch (attr) { |
1415 | case DOMAIN_ATTR_NESTING: | |
518f7136 WD |
1416 | if (smmu_domain->smmu) { |
1417 | ret = -EPERM; | |
1418 | goto out_unlock; | |
1419 | } | |
1420 | ||
c752ce45 WD |
1421 | if (*(int *)data) |
1422 | smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; | |
1423 | else | |
1424 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; | |
1425 | ||
518f7136 | 1426 | break; |
c752ce45 | 1427 | default: |
518f7136 | 1428 | ret = -ENODEV; |
c752ce45 | 1429 | } |
518f7136 WD |
1430 | |
1431 | out_unlock: | |
1432 | mutex_unlock(&smmu_domain->init_mutex); | |
1433 | return ret; | |
c752ce45 WD |
1434 | } |
1435 | ||
518f7136 | 1436 | static struct iommu_ops arm_smmu_ops = { |
c752ce45 | 1437 | .capable = arm_smmu_capable, |
1d672638 JR |
1438 | .domain_alloc = arm_smmu_domain_alloc, |
1439 | .domain_free = arm_smmu_domain_free, | |
c752ce45 WD |
1440 | .attach_dev = arm_smmu_attach_dev, |
1441 | .detach_dev = arm_smmu_detach_dev, | |
1442 | .map = arm_smmu_map, | |
1443 | .unmap = arm_smmu_unmap, | |
76771c93 | 1444 | .map_sg = default_iommu_map_sg, |
c752ce45 WD |
1445 | .iova_to_phys = arm_smmu_iova_to_phys, |
1446 | .add_device = arm_smmu_add_device, | |
1447 | .remove_device = arm_smmu_remove_device, | |
af659932 | 1448 | .device_group = arm_smmu_device_group, |
c752ce45 WD |
1449 | .domain_get_attr = arm_smmu_domain_get_attr, |
1450 | .domain_set_attr = arm_smmu_domain_set_attr, | |
518f7136 | 1451 | .pgsize_bitmap = -1UL, /* Restricted during device attach */ |
45ae7cff WD |
1452 | }; |
1453 | ||
1454 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1455 | { | |
1456 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1457 | void __iomem *cb_base; |
45ae7cff | 1458 | int i = 0; |
659db6f6 AH |
1459 | u32 reg; |
1460 | ||
3a5df8ff AH |
1461 | /* clear global FSR */ |
1462 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1463 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1464 | |
1465 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1466 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
3c8766d0 | 1467 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
2907320d MH |
1468 | writel_relaxed(S2CR_TYPE_BYPASS, |
1469 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1470 | } |
1471 | ||
659db6f6 AH |
1472 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1473 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1474 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1475 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1476 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1477 | } | |
1463fe44 | 1478 | |
45ae7cff | 1479 | /* Invalidate the TLB, just in case */ |
45ae7cff WD |
1480 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); |
1481 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1482 | ||
3a5df8ff | 1483 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1484 | |
45ae7cff | 1485 | /* Enable fault reporting */ |
659db6f6 | 1486 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1487 | |
1488 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1489 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1490 | |
1491 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1492 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1493 | |
1494 | /* Disable forced broadcasting */ | |
659db6f6 | 1495 | reg &= ~sCR0_FB; |
45ae7cff WD |
1496 | |
1497 | /* Don't upgrade barriers */ | |
659db6f6 | 1498 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1499 | |
1500 | /* Push the button */ | |
518f7136 | 1501 | __arm_smmu_tlb_sync(smmu); |
3a5df8ff | 1502 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1503 | } |
1504 | ||
1505 | static int arm_smmu_id_size_to_bits(int size) | |
1506 | { | |
1507 | switch (size) { | |
1508 | case 0: | |
1509 | return 32; | |
1510 | case 1: | |
1511 | return 36; | |
1512 | case 2: | |
1513 | return 40; | |
1514 | case 3: | |
1515 | return 42; | |
1516 | case 4: | |
1517 | return 44; | |
1518 | case 5: | |
1519 | default: | |
1520 | return 48; | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1525 | { | |
1526 | unsigned long size; | |
1527 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1528 | u32 id; | |
bae2c2d4 | 1529 | bool cttw_dt, cttw_reg; |
45ae7cff WD |
1530 | |
1531 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
45ae7cff WD |
1532 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); |
1533 | ||
1534 | /* ID0 */ | |
1535 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
4cf740b0 WD |
1536 | |
1537 | /* Restrict available stages based on module parameter */ | |
1538 | if (force_stage == 1) | |
1539 | id &= ~(ID0_S2TS | ID0_NTS); | |
1540 | else if (force_stage == 2) | |
1541 | id &= ~(ID0_S1TS | ID0_NTS); | |
1542 | ||
45ae7cff WD |
1543 | if (id & ID0_S1TS) { |
1544 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1545 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1546 | } | |
1547 | ||
1548 | if (id & ID0_S2TS) { | |
1549 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1550 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1551 | } | |
1552 | ||
1553 | if (id & ID0_NTS) { | |
1554 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1555 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1556 | } | |
1557 | ||
1558 | if (!(smmu->features & | |
4cf740b0 | 1559 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
45ae7cff WD |
1560 | dev_err(smmu->dev, "\tno translation support!\n"); |
1561 | return -ENODEV; | |
1562 | } | |
1563 | ||
d38f0ff9 | 1564 | if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) { |
859a732e MH |
1565 | smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; |
1566 | dev_notice(smmu->dev, "\taddress translation ops\n"); | |
1567 | } | |
1568 | ||
bae2c2d4 RM |
1569 | /* |
1570 | * In order for DMA API calls to work properly, we must defer to what | |
1571 | * the DT says about coherency, regardless of what the hardware claims. | |
1572 | * Fortunately, this also opens up a workaround for systems where the | |
1573 | * ID register value has ended up configured incorrectly. | |
1574 | */ | |
1575 | cttw_dt = of_dma_is_coherent(smmu->dev->of_node); | |
1576 | cttw_reg = !!(id & ID0_CTTW); | |
1577 | if (cttw_dt) | |
45ae7cff | 1578 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; |
bae2c2d4 RM |
1579 | if (cttw_dt || cttw_reg) |
1580 | dev_notice(smmu->dev, "\t%scoherent table walk\n", | |
1581 | cttw_dt ? "" : "non-"); | |
1582 | if (cttw_dt != cttw_reg) | |
1583 | dev_notice(smmu->dev, | |
1584 | "\t(IDR0.CTTW overridden by dma-coherent property)\n"); | |
45ae7cff WD |
1585 | |
1586 | if (id & ID0_SMS) { | |
1587 | u32 smr, sid, mask; | |
1588 | ||
1589 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1590 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1591 | ID0_NUMSMRG_MASK; | |
1592 | if (smmu->num_mapping_groups == 0) { | |
1593 | dev_err(smmu->dev, | |
1594 | "stream-matching supported, but no SMRs present!\n"); | |
1595 | return -ENODEV; | |
1596 | } | |
1597 | ||
1598 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1599 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1600 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1601 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1602 | ||
1603 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1604 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1605 | if ((mask & sid) != sid) { | |
1606 | dev_err(smmu->dev, | |
1607 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1608 | mask, sid); | |
1609 | return -ENODEV; | |
1610 | } | |
1611 | ||
1612 | dev_notice(smmu->dev, | |
1613 | "\tstream matching with %u register groups, mask 0x%x", | |
1614 | smmu->num_mapping_groups, mask); | |
3c8766d0 OH |
1615 | } else { |
1616 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & | |
1617 | ID0_NUMSIDB_MASK; | |
45ae7cff WD |
1618 | } |
1619 | ||
1620 | /* ID1 */ | |
1621 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
c757e852 | 1622 | smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12; |
45ae7cff | 1623 | |
c55af7f7 | 1624 | /* Check for size mismatch of SMMU address space from mapped region */ |
518f7136 | 1625 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
c757e852 | 1626 | size *= 2 << smmu->pgshift; |
c55af7f7 | 1627 | if (smmu->size != size) |
2907320d MH |
1628 | dev_warn(smmu->dev, |
1629 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1630 | size, smmu->size); | |
45ae7cff | 1631 | |
518f7136 | 1632 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK; |
45ae7cff WD |
1633 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; |
1634 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1635 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1636 | return -ENODEV; | |
1637 | } | |
1638 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1639 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1640 | ||
1641 | /* ID2 */ | |
1642 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1643 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
518f7136 | 1644 | smmu->ipa_size = size; |
45ae7cff | 1645 | |
518f7136 | 1646 | /* The output mask is also applied for bypass */ |
45ae7cff | 1647 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); |
518f7136 | 1648 | smmu->pa_size = size; |
45ae7cff | 1649 | |
f1d84548 RM |
1650 | /* |
1651 | * What the page table walker can address actually depends on which | |
1652 | * descriptor format is in use, but since a) we don't know that yet, | |
1653 | * and b) it can vary per context bank, this will have to do... | |
1654 | */ | |
1655 | if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) | |
1656 | dev_warn(smmu->dev, | |
1657 | "failed to set DMA mask for table walker\n"); | |
1658 | ||
09360403 | 1659 | if (smmu->version == ARM_SMMU_V1) { |
518f7136 WD |
1660 | smmu->va_size = smmu->ipa_size; |
1661 | size = SZ_4K | SZ_2M | SZ_1G; | |
45ae7cff | 1662 | } else { |
45ae7cff | 1663 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; |
518f7136 WD |
1664 | smmu->va_size = arm_smmu_id_size_to_bits(size); |
1665 | #ifndef CONFIG_64BIT | |
1666 | smmu->va_size = min(32UL, smmu->va_size); | |
45ae7cff | 1667 | #endif |
518f7136 WD |
1668 | size = 0; |
1669 | if (id & ID2_PTFS_4K) | |
1670 | size |= SZ_4K | SZ_2M | SZ_1G; | |
1671 | if (id & ID2_PTFS_16K) | |
1672 | size |= SZ_16K | SZ_32M; | |
1673 | if (id & ID2_PTFS_64K) | |
1674 | size |= SZ_64K | SZ_512M; | |
45ae7cff WD |
1675 | } |
1676 | ||
518f7136 WD |
1677 | arm_smmu_ops.pgsize_bitmap &= size; |
1678 | dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size); | |
1679 | ||
28d6007b WD |
1680 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) |
1681 | dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", | |
518f7136 | 1682 | smmu->va_size, smmu->ipa_size); |
28d6007b WD |
1683 | |
1684 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) | |
1685 | dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", | |
518f7136 | 1686 | smmu->ipa_size, smmu->pa_size); |
28d6007b | 1687 | |
45ae7cff WD |
1688 | return 0; |
1689 | } | |
1690 | ||
09b5269a | 1691 | static const struct of_device_id arm_smmu_of_match[] = { |
09360403 RM |
1692 | { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 }, |
1693 | { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 }, | |
1694 | { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, | |
d3aba046 | 1695 | { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, |
09360403 RM |
1696 | { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, |
1697 | { }, | |
1698 | }; | |
1699 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
1700 | ||
45ae7cff WD |
1701 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
1702 | { | |
09360403 | 1703 | const struct of_device_id *of_id; |
45ae7cff WD |
1704 | struct resource *res; |
1705 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1706 | struct device *dev = &pdev->dev; |
1707 | struct rb_node *node; | |
1708 | struct of_phandle_args masterspec; | |
1709 | int num_irqs, i, err; | |
1710 | ||
1711 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1712 | if (!smmu) { | |
1713 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1714 | return -ENOMEM; | |
1715 | } | |
1716 | smmu->dev = dev; | |
1717 | ||
09360403 RM |
1718 | of_id = of_match_node(arm_smmu_of_match, dev->of_node); |
1719 | smmu->version = (enum arm_smmu_arch_version)of_id->data; | |
1720 | ||
45ae7cff | 1721 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8a7f4312 JL |
1722 | smmu->base = devm_ioremap_resource(dev, res); |
1723 | if (IS_ERR(smmu->base)) | |
1724 | return PTR_ERR(smmu->base); | |
45ae7cff | 1725 | smmu->size = resource_size(res); |
45ae7cff WD |
1726 | |
1727 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1728 | &smmu->num_global_irqs)) { | |
1729 | dev_err(dev, "missing #global-interrupts property\n"); | |
1730 | return -ENODEV; | |
1731 | } | |
1732 | ||
1733 | num_irqs = 0; | |
1734 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1735 | num_irqs++; | |
1736 | if (num_irqs > smmu->num_global_irqs) | |
1737 | smmu->num_context_irqs++; | |
1738 | } | |
1739 | ||
44a08de2 AH |
1740 | if (!smmu->num_context_irqs) { |
1741 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1742 | num_irqs, smmu->num_global_irqs + 1); | |
1743 | return -ENODEV; | |
45ae7cff | 1744 | } |
45ae7cff WD |
1745 | |
1746 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1747 | GFP_KERNEL); | |
1748 | if (!smmu->irqs) { | |
1749 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1750 | return -ENOMEM; | |
1751 | } | |
1752 | ||
1753 | for (i = 0; i < num_irqs; ++i) { | |
1754 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1755 | |
45ae7cff WD |
1756 | if (irq < 0) { |
1757 | dev_err(dev, "failed to get irq index %d\n", i); | |
1758 | return -ENODEV; | |
1759 | } | |
1760 | smmu->irqs[i] = irq; | |
1761 | } | |
1762 | ||
3c8766d0 OH |
1763 | err = arm_smmu_device_cfg_probe(smmu); |
1764 | if (err) | |
1765 | return err; | |
1766 | ||
45ae7cff WD |
1767 | i = 0; |
1768 | smmu->masters = RB_ROOT; | |
1769 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1770 | "#stream-id-cells", i, | |
1771 | &masterspec)) { | |
1772 | err = register_smmu_master(smmu, dev, &masterspec); | |
1773 | if (err) { | |
1774 | dev_err(dev, "failed to add master %s\n", | |
1775 | masterspec.np->name); | |
1776 | goto out_put_masters; | |
1777 | } | |
1778 | ||
1779 | i++; | |
1780 | } | |
1781 | dev_notice(dev, "registered %d master devices\n", i); | |
1782 | ||
3a5df8ff AH |
1783 | parse_driver_options(smmu); |
1784 | ||
09360403 | 1785 | if (smmu->version > ARM_SMMU_V1 && |
45ae7cff WD |
1786 | smmu->num_context_banks != smmu->num_context_irqs) { |
1787 | dev_err(dev, | |
1788 | "found only %d context interrupt(s) but %d required\n", | |
1789 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1790 | err = -ENODEV; |
44680eed | 1791 | goto out_put_masters; |
45ae7cff WD |
1792 | } |
1793 | ||
45ae7cff WD |
1794 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1795 | err = request_irq(smmu->irqs[i], | |
1796 | arm_smmu_global_fault, | |
1797 | IRQF_SHARED, | |
1798 | "arm-smmu global fault", | |
1799 | smmu); | |
1800 | if (err) { | |
1801 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1802 | i, smmu->irqs[i]); | |
1803 | goto out_free_irqs; | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | INIT_LIST_HEAD(&smmu->list); | |
1808 | spin_lock(&arm_smmu_devices_lock); | |
1809 | list_add(&smmu->list, &arm_smmu_devices); | |
1810 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1811 | |
1812 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1813 | return 0; |
1814 | ||
1815 | out_free_irqs: | |
1816 | while (i--) | |
1817 | free_irq(smmu->irqs[i], smmu); | |
1818 | ||
45ae7cff WD |
1819 | out_put_masters: |
1820 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
1821 | struct arm_smmu_master *master |
1822 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1823 | of_node_put(master->of_node); |
1824 | } | |
1825 | ||
1826 | return err; | |
1827 | } | |
1828 | ||
1829 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1830 | { | |
1831 | int i; | |
1832 | struct device *dev = &pdev->dev; | |
1833 | struct arm_smmu_device *curr, *smmu = NULL; | |
1834 | struct rb_node *node; | |
1835 | ||
1836 | spin_lock(&arm_smmu_devices_lock); | |
1837 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1838 | if (curr->dev == dev) { | |
1839 | smmu = curr; | |
1840 | list_del(&smmu->list); | |
1841 | break; | |
1842 | } | |
1843 | } | |
1844 | spin_unlock(&arm_smmu_devices_lock); | |
1845 | ||
1846 | if (!smmu) | |
1847 | return -ENODEV; | |
1848 | ||
45ae7cff | 1849 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
1850 | struct arm_smmu_master *master |
1851 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1852 | of_node_put(master->of_node); |
1853 | } | |
1854 | ||
ecfadb6e | 1855 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
1856 | dev_err(dev, "removing device with active domains!\n"); |
1857 | ||
1858 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
1859 | free_irq(smmu->irqs[i], smmu); | |
1860 | ||
1861 | /* Turn the thing off */ | |
2907320d | 1862 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1863 | return 0; |
1864 | } | |
1865 | ||
45ae7cff WD |
1866 | static struct platform_driver arm_smmu_driver = { |
1867 | .driver = { | |
45ae7cff WD |
1868 | .name = "arm-smmu", |
1869 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
1870 | }, | |
1871 | .probe = arm_smmu_device_dt_probe, | |
1872 | .remove = arm_smmu_device_remove, | |
1873 | }; | |
1874 | ||
1875 | static int __init arm_smmu_init(void) | |
1876 | { | |
0e7d37ad | 1877 | struct device_node *np; |
45ae7cff WD |
1878 | int ret; |
1879 | ||
0e7d37ad TR |
1880 | /* |
1881 | * Play nice with systems that don't have an ARM SMMU by checking that | |
1882 | * an ARM SMMU exists in the system before proceeding with the driver | |
1883 | * and IOMMU bus operation registration. | |
1884 | */ | |
1885 | np = of_find_matching_node(NULL, arm_smmu_of_match); | |
1886 | if (!np) | |
1887 | return 0; | |
1888 | ||
1889 | of_node_put(np); | |
1890 | ||
45ae7cff WD |
1891 | ret = platform_driver_register(&arm_smmu_driver); |
1892 | if (ret) | |
1893 | return ret; | |
1894 | ||
1895 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 1896 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
1897 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
1898 | ||
d123cf82 | 1899 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 1900 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 1901 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 1902 | #endif |
45ae7cff | 1903 | |
a9a1b0b5 WD |
1904 | #ifdef CONFIG_PCI |
1905 | if (!iommu_present(&pci_bus_type)) | |
1906 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
1907 | #endif | |
1908 | ||
45ae7cff WD |
1909 | return 0; |
1910 | } | |
1911 | ||
1912 | static void __exit arm_smmu_exit(void) | |
1913 | { | |
1914 | return platform_driver_unregister(&arm_smmu_driver); | |
1915 | } | |
1916 | ||
b1950b27 | 1917 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
1918 | module_exit(arm_smmu_exit); |
1919 | ||
1920 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
1921 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
1922 | MODULE_LICENSE("GPL v2"); |