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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 21 | * |
e61d98d8 | 22 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
23 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
24 | * tables. | |
e61d98d8 SS |
25 | * |
26 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
27 | */ |
28 | ||
e9071b0b DD |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt /* has to precede printk.h */ |
30 | ||
10e5247f KA |
31 | #include <linux/pci.h> |
32 | #include <linux/dmar.h> | |
38717946 KA |
33 | #include <linux/iova.h> |
34 | #include <linux/intel-iommu.h> | |
fe962e90 | 35 | #include <linux/timer.h> |
0ac2491f SS |
36 | #include <linux/irq.h> |
37 | #include <linux/interrupt.h> | |
69575d38 | 38 | #include <linux/tboot.h> |
eb27cae8 | 39 | #include <linux/dmi.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
8a8f422d | 41 | #include <asm/irq_remapping.h> |
4db77ff3 | 42 | #include <asm/iommu_table.h> |
10e5247f | 43 | |
078e1ee2 JR |
44 | #include "irq_remapping.h" |
45 | ||
3a5670e8 JL |
46 | /* |
47 | * Assumptions: | |
48 | * 1) The hotplug framework guarentees that DMAR unit will be hot-added | |
49 | * before IO devices managed by that unit. | |
50 | * 2) The hotplug framework guarantees that DMAR unit will be hot-removed | |
51 | * after IO devices managed by that unit. | |
52 | * 3) Hotplug events are rare. | |
53 | * | |
54 | * Locking rules for DMA and interrupt remapping related global data structures: | |
55 | * 1) Use dmar_global_lock in process context | |
56 | * 2) Use RCU in interrupt context | |
10e5247f | 57 | */ |
3a5670e8 | 58 | DECLARE_RWSEM(dmar_global_lock); |
10e5247f | 59 | LIST_HEAD(dmar_drhd_units); |
10e5247f | 60 | |
41750d31 | 61 | struct acpi_table_header * __initdata dmar_tbl; |
8e1568f3 | 62 | static acpi_size dmar_tbl_size; |
10e5247f | 63 | |
694835dc | 64 | static int alloc_iommu(struct dmar_drhd_unit *drhd); |
a868e6b7 | 65 | static void free_iommu(struct intel_iommu *iommu); |
694835dc | 66 | |
10e5247f KA |
67 | static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) |
68 | { | |
69 | /* | |
70 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
71 | * the very end. | |
72 | */ | |
73 | if (drhd->include_all) | |
0e242612 | 74 | list_add_tail_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f | 75 | else |
0e242612 | 76 | list_add_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f KA |
77 | } |
78 | ||
10e5247f | 79 | static int __init dmar_parse_one_dev_scope(struct acpi_dmar_device_scope *scope, |
0e242612 | 80 | struct pci_dev __rcu **dev, u16 segment) |
10e5247f KA |
81 | { |
82 | struct pci_bus *bus; | |
83 | struct pci_dev *pdev = NULL; | |
84 | struct acpi_dmar_pci_path *path; | |
85 | int count; | |
86 | ||
87 | bus = pci_find_bus(segment, scope->bus); | |
88 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
89 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
90 | / sizeof(struct acpi_dmar_pci_path); | |
91 | ||
92 | while (count) { | |
93 | if (pdev) | |
94 | pci_dev_put(pdev); | |
95 | /* | |
96 | * Some BIOSes list non-exist devices in DMAR table, just | |
97 | * ignore it | |
98 | */ | |
99 | if (!bus) { | |
e9071b0b | 100 | pr_warn("Device scope bus [%d] not found\n", scope->bus); |
10e5247f KA |
101 | break; |
102 | } | |
fa5f508f | 103 | pdev = pci_get_slot(bus, PCI_DEVFN(path->device, path->function)); |
10e5247f | 104 | if (!pdev) { |
e9071b0b | 105 | /* warning will be printed below */ |
10e5247f KA |
106 | break; |
107 | } | |
108 | path ++; | |
109 | count --; | |
110 | bus = pdev->subordinate; | |
111 | } | |
112 | if (!pdev) { | |
e9071b0b | 113 | pr_warn("Device scope device [%04x:%02x:%02x.%02x] not found\n", |
fa5f508f | 114 | segment, scope->bus, path->device, path->function); |
10e5247f KA |
115 | return 0; |
116 | } | |
117 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && \ | |
118 | pdev->subordinate) || (scope->entry_type == \ | |
119 | ACPI_DMAR_SCOPE_TYPE_BRIDGE && !pdev->subordinate)) { | |
120 | pci_dev_put(pdev); | |
e9071b0b DD |
121 | pr_warn("Device scope type does not match for %s\n", |
122 | pci_name(pdev)); | |
10e5247f KA |
123 | return -EINVAL; |
124 | } | |
0e242612 JL |
125 | |
126 | rcu_assign_pointer(*dev, pdev); | |
127 | ||
10e5247f KA |
128 | return 0; |
129 | } | |
130 | ||
bb3a6b78 | 131 | void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) |
10e5247f KA |
132 | { |
133 | struct acpi_dmar_device_scope *scope; | |
10e5247f KA |
134 | |
135 | *cnt = 0; | |
136 | while (start < end) { | |
137 | scope = start; | |
138 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || | |
139 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
140 | (*cnt)++; | |
ae3e7f3a LC |
141 | else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && |
142 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { | |
e9071b0b | 143 | pr_warn("Unsupported device scope\n"); |
5715f0f9 | 144 | } |
10e5247f KA |
145 | start += scope->length; |
146 | } | |
147 | if (*cnt == 0) | |
bb3a6b78 JL |
148 | return NULL; |
149 | ||
150 | return kcalloc(*cnt, sizeof(struct pci_dev *), GFP_KERNEL); | |
151 | } | |
152 | ||
153 | int __init dmar_parse_dev_scope(void *start, void *end, int *cnt, | |
0e242612 | 154 | struct pci_dev __rcu ***devices, u16 segment) |
bb3a6b78 JL |
155 | { |
156 | struct acpi_dmar_device_scope *scope; | |
157 | int index, ret; | |
10e5247f | 158 | |
bb3a6b78 JL |
159 | *devices = dmar_alloc_dev_scope(start, end, cnt); |
160 | if (*cnt == 0) | |
161 | return 0; | |
162 | else if (!*devices) | |
10e5247f KA |
163 | return -ENOMEM; |
164 | ||
bb3a6b78 | 165 | for (index = 0; start < end; start += scope->length) { |
10e5247f KA |
166 | scope = start; |
167 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || | |
168 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) { | |
169 | ret = dmar_parse_one_dev_scope(scope, | |
170 | &(*devices)[index], segment); | |
171 | if (ret) { | |
ada4d4b2 | 172 | dmar_free_dev_scope(devices, cnt); |
10e5247f KA |
173 | return ret; |
174 | } | |
175 | index ++; | |
176 | } | |
10e5247f KA |
177 | } |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
0e242612 | 182 | void dmar_free_dev_scope(struct pci_dev __rcu ***devices, int *cnt) |
ada4d4b2 | 183 | { |
b683b230 JL |
184 | int i; |
185 | struct pci_dev *tmp_dev; | |
186 | ||
ada4d4b2 | 187 | if (*devices && *cnt) { |
b683b230 JL |
188 | for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) |
189 | pci_dev_put(tmp_dev); | |
ada4d4b2 | 190 | kfree(*devices); |
ada4d4b2 | 191 | } |
0e242612 JL |
192 | |
193 | *devices = NULL; | |
194 | *cnt = 0; | |
ada4d4b2 JL |
195 | } |
196 | ||
59ce0515 JL |
197 | /* Optimize out kzalloc()/kfree() for normal cases */ |
198 | static char dmar_pci_notify_info_buf[64]; | |
199 | ||
200 | static struct dmar_pci_notify_info * | |
201 | dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) | |
202 | { | |
203 | int level = 0; | |
204 | size_t size; | |
205 | struct pci_dev *tmp; | |
206 | struct dmar_pci_notify_info *info; | |
207 | ||
208 | BUG_ON(dev->is_virtfn); | |
209 | ||
210 | /* Only generate path[] for device addition event */ | |
211 | if (event == BUS_NOTIFY_ADD_DEVICE) | |
212 | for (tmp = dev; tmp; tmp = tmp->bus->self) | |
213 | level++; | |
214 | ||
215 | size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path); | |
216 | if (size <= sizeof(dmar_pci_notify_info_buf)) { | |
217 | info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; | |
218 | } else { | |
219 | info = kzalloc(size, GFP_KERNEL); | |
220 | if (!info) { | |
221 | pr_warn("Out of memory when allocating notify_info " | |
222 | "for %s.\n", pci_name(dev)); | |
223 | return NULL; | |
224 | } | |
225 | } | |
226 | ||
227 | info->event = event; | |
228 | info->dev = dev; | |
229 | info->seg = pci_domain_nr(dev->bus); | |
230 | info->level = level; | |
231 | if (event == BUS_NOTIFY_ADD_DEVICE) { | |
232 | for (tmp = dev, level--; tmp; tmp = tmp->bus->self) { | |
233 | info->path[level].device = PCI_SLOT(tmp->devfn); | |
234 | info->path[level].function = PCI_FUNC(tmp->devfn); | |
235 | if (pci_is_root_bus(tmp->bus)) | |
236 | info->bus = tmp->bus->number; | |
237 | } | |
238 | } | |
239 | ||
240 | return info; | |
241 | } | |
242 | ||
243 | static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) | |
244 | { | |
245 | if ((void *)info != dmar_pci_notify_info_buf) | |
246 | kfree(info); | |
247 | } | |
248 | ||
249 | static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, | |
250 | struct acpi_dmar_pci_path *path, int count) | |
251 | { | |
252 | int i; | |
253 | ||
254 | if (info->bus != bus) | |
255 | return false; | |
256 | if (info->level != count) | |
257 | return false; | |
258 | ||
259 | for (i = 0; i < count; i++) { | |
260 | if (path[i].device != info->path[i].device || | |
261 | path[i].function != info->path[i].function) | |
262 | return false; | |
263 | } | |
264 | ||
265 | return true; | |
266 | } | |
267 | ||
268 | /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ | |
269 | int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, | |
270 | void *start, void*end, u16 segment, | |
271 | struct pci_dev __rcu **devices, int devices_cnt) | |
272 | { | |
273 | int i, level; | |
274 | struct pci_dev *tmp, *dev = info->dev; | |
275 | struct acpi_dmar_device_scope *scope; | |
276 | struct acpi_dmar_pci_path *path; | |
277 | ||
278 | if (segment != info->seg) | |
279 | return 0; | |
280 | ||
281 | for (; start < end; start += scope->length) { | |
282 | scope = start; | |
283 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
284 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
285 | continue; | |
286 | ||
287 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
288 | level = (scope->length - sizeof(*scope)) / sizeof(*path); | |
289 | if (!dmar_match_pci_path(info, scope->bus, path, level)) | |
290 | continue; | |
291 | ||
292 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT) ^ | |
293 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL)) { | |
294 | pr_warn("Device scope type does not match for %s\n", | |
295 | pci_name(dev)); | |
296 | return -EINVAL; | |
297 | } | |
298 | ||
299 | for_each_dev_scope(devices, devices_cnt, i, tmp) | |
300 | if (tmp == NULL) { | |
301 | rcu_assign_pointer(devices[i], | |
302 | pci_dev_get(dev)); | |
303 | return 1; | |
304 | } | |
305 | BUG_ON(i >= devices_cnt); | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, | |
312 | struct pci_dev __rcu **devices, int count) | |
313 | { | |
314 | int index; | |
315 | struct pci_dev *tmp; | |
316 | ||
317 | if (info->seg != segment) | |
318 | return 0; | |
319 | ||
320 | for_each_active_dev_scope(devices, count, index, tmp) | |
321 | if (tmp == info->dev) { | |
322 | rcu_assign_pointer(devices[index], NULL); | |
323 | synchronize_rcu(); | |
324 | pci_dev_put(tmp); | |
325 | return 1; | |
326 | } | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) | |
332 | { | |
333 | int ret = 0; | |
334 | struct dmar_drhd_unit *dmaru; | |
335 | struct acpi_dmar_hardware_unit *drhd; | |
336 | ||
337 | for_each_drhd_unit(dmaru) { | |
338 | if (dmaru->include_all) | |
339 | continue; | |
340 | ||
341 | drhd = container_of(dmaru->hdr, | |
342 | struct acpi_dmar_hardware_unit, header); | |
343 | ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), | |
344 | ((void *)drhd) + drhd->header.length, | |
345 | dmaru->segment, | |
346 | dmaru->devices, dmaru->devices_cnt); | |
347 | if (ret != 0) | |
348 | break; | |
349 | } | |
350 | if (ret >= 0) | |
351 | ret = dmar_iommu_notify_scope_dev(info); | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) | |
357 | { | |
358 | struct dmar_drhd_unit *dmaru; | |
359 | ||
360 | for_each_drhd_unit(dmaru) | |
361 | if (dmar_remove_dev_scope(info, dmaru->segment, | |
362 | dmaru->devices, dmaru->devices_cnt)) | |
363 | break; | |
364 | dmar_iommu_notify_scope_dev(info); | |
365 | } | |
366 | ||
367 | static int dmar_pci_bus_notifier(struct notifier_block *nb, | |
368 | unsigned long action, void *data) | |
369 | { | |
370 | struct pci_dev *pdev = to_pci_dev(data); | |
371 | struct dmar_pci_notify_info *info; | |
372 | ||
373 | /* Only care about add/remove events for physical functions */ | |
374 | if (pdev->is_virtfn) | |
375 | return NOTIFY_DONE; | |
376 | if (action != BUS_NOTIFY_ADD_DEVICE && action != BUS_NOTIFY_DEL_DEVICE) | |
377 | return NOTIFY_DONE; | |
378 | ||
379 | info = dmar_alloc_pci_notify_info(pdev, action); | |
380 | if (!info) | |
381 | return NOTIFY_DONE; | |
382 | ||
383 | down_write(&dmar_global_lock); | |
384 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
385 | dmar_pci_bus_add_dev(info); | |
386 | else if (action == BUS_NOTIFY_DEL_DEVICE) | |
387 | dmar_pci_bus_del_dev(info); | |
388 | up_write(&dmar_global_lock); | |
389 | ||
390 | dmar_free_pci_notify_info(info); | |
391 | ||
392 | return NOTIFY_OK; | |
393 | } | |
394 | ||
395 | static struct notifier_block dmar_pci_bus_nb = { | |
396 | .notifier_call = dmar_pci_bus_notifier, | |
397 | .priority = INT_MIN, | |
398 | }; | |
399 | ||
10e5247f KA |
400 | /** |
401 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition | |
402 | * structure which uniquely represent one DMA remapping hardware unit | |
403 | * present in the platform | |
404 | */ | |
405 | static int __init | |
406 | dmar_parse_one_drhd(struct acpi_dmar_header *header) | |
407 | { | |
408 | struct acpi_dmar_hardware_unit *drhd; | |
409 | struct dmar_drhd_unit *dmaru; | |
410 | int ret = 0; | |
10e5247f | 411 | |
e523b38e | 412 | drhd = (struct acpi_dmar_hardware_unit *)header; |
10e5247f KA |
413 | dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL); |
414 | if (!dmaru) | |
415 | return -ENOMEM; | |
416 | ||
1886e8a9 | 417 | dmaru->hdr = header; |
10e5247f | 418 | dmaru->reg_base_addr = drhd->address; |
276dbf99 | 419 | dmaru->segment = drhd->segment; |
10e5247f KA |
420 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ |
421 | ||
1886e8a9 SS |
422 | ret = alloc_iommu(dmaru); |
423 | if (ret) { | |
424 | kfree(dmaru); | |
425 | return ret; | |
426 | } | |
427 | dmar_register_drhd_unit(dmaru); | |
428 | return 0; | |
429 | } | |
430 | ||
a868e6b7 JL |
431 | static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) |
432 | { | |
433 | if (dmaru->devices && dmaru->devices_cnt) | |
434 | dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); | |
435 | if (dmaru->iommu) | |
436 | free_iommu(dmaru->iommu); | |
437 | kfree(dmaru); | |
438 | } | |
439 | ||
f82851a8 | 440 | static int __init dmar_parse_dev(struct dmar_drhd_unit *dmaru) |
1886e8a9 SS |
441 | { |
442 | struct acpi_dmar_hardware_unit *drhd; | |
1886e8a9 SS |
443 | |
444 | drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr; | |
445 | ||
2e824f79 YZ |
446 | if (dmaru->include_all) |
447 | return 0; | |
448 | ||
a868e6b7 JL |
449 | return dmar_parse_dev_scope((void *)(drhd + 1), |
450 | ((void *)drhd) + drhd->header.length, | |
451 | &dmaru->devices_cnt, &dmaru->devices, | |
452 | drhd->segment); | |
10e5247f KA |
453 | } |
454 | ||
aa697079 | 455 | #ifdef CONFIG_ACPI_NUMA |
ee34b32d SS |
456 | static int __init |
457 | dmar_parse_one_rhsa(struct acpi_dmar_header *header) | |
458 | { | |
459 | struct acpi_dmar_rhsa *rhsa; | |
460 | struct dmar_drhd_unit *drhd; | |
461 | ||
462 | rhsa = (struct acpi_dmar_rhsa *)header; | |
aa697079 | 463 | for_each_drhd_unit(drhd) { |
ee34b32d SS |
464 | if (drhd->reg_base_addr == rhsa->base_address) { |
465 | int node = acpi_map_pxm_to_node(rhsa->proximity_domain); | |
466 | ||
467 | if (!node_online(node)) | |
468 | node = -1; | |
469 | drhd->iommu->node = node; | |
aa697079 DW |
470 | return 0; |
471 | } | |
ee34b32d | 472 | } |
fd0c8894 BH |
473 | WARN_TAINT( |
474 | 1, TAINT_FIRMWARE_WORKAROUND, | |
475 | "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" | |
476 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
477 | drhd->reg_base_addr, | |
478 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
479 | dmi_get_system_info(DMI_BIOS_VERSION), | |
480 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
ee34b32d | 481 | |
aa697079 | 482 | return 0; |
ee34b32d | 483 | } |
aa697079 | 484 | #endif |
ee34b32d | 485 | |
10e5247f KA |
486 | static void __init |
487 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) | |
488 | { | |
489 | struct acpi_dmar_hardware_unit *drhd; | |
490 | struct acpi_dmar_reserved_memory *rmrr; | |
aa5d2b51 | 491 | struct acpi_dmar_atsr *atsr; |
17b60977 | 492 | struct acpi_dmar_rhsa *rhsa; |
10e5247f KA |
493 | |
494 | switch (header->type) { | |
495 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
aa5d2b51 YZ |
496 | drhd = container_of(header, struct acpi_dmar_hardware_unit, |
497 | header); | |
e9071b0b | 498 | pr_info("DRHD base: %#016Lx flags: %#x\n", |
aa5d2b51 | 499 | (unsigned long long)drhd->address, drhd->flags); |
10e5247f KA |
500 | break; |
501 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aa5d2b51 YZ |
502 | rmrr = container_of(header, struct acpi_dmar_reserved_memory, |
503 | header); | |
e9071b0b | 504 | pr_info("RMRR base: %#016Lx end: %#016Lx\n", |
5b6985ce FY |
505 | (unsigned long long)rmrr->base_address, |
506 | (unsigned long long)rmrr->end_address); | |
10e5247f | 507 | break; |
aa5d2b51 YZ |
508 | case ACPI_DMAR_TYPE_ATSR: |
509 | atsr = container_of(header, struct acpi_dmar_atsr, header); | |
e9071b0b | 510 | pr_info("ATSR flags: %#x\n", atsr->flags); |
aa5d2b51 | 511 | break; |
17b60977 RD |
512 | case ACPI_DMAR_HARDWARE_AFFINITY: |
513 | rhsa = container_of(header, struct acpi_dmar_rhsa, header); | |
e9071b0b | 514 | pr_info("RHSA base: %#016Lx proximity domain: %#x\n", |
17b60977 RD |
515 | (unsigned long long)rhsa->base_address, |
516 | rhsa->proximity_domain); | |
517 | break; | |
10e5247f KA |
518 | } |
519 | } | |
520 | ||
f6dd5c31 YL |
521 | /** |
522 | * dmar_table_detect - checks to see if the platform supports DMAR devices | |
523 | */ | |
524 | static int __init dmar_table_detect(void) | |
525 | { | |
526 | acpi_status status = AE_OK; | |
527 | ||
528 | /* if we could find DMAR table, then there are DMAR devices */ | |
8e1568f3 YL |
529 | status = acpi_get_table_with_size(ACPI_SIG_DMAR, 0, |
530 | (struct acpi_table_header **)&dmar_tbl, | |
531 | &dmar_tbl_size); | |
f6dd5c31 YL |
532 | |
533 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
e9071b0b | 534 | pr_warn("Unable to map DMAR\n"); |
f6dd5c31 YL |
535 | status = AE_NOT_FOUND; |
536 | } | |
537 | ||
538 | return (ACPI_SUCCESS(status) ? 1 : 0); | |
539 | } | |
aaa9d1dd | 540 | |
10e5247f KA |
541 | /** |
542 | * parse_dmar_table - parses the DMA reporting table | |
543 | */ | |
544 | static int __init | |
545 | parse_dmar_table(void) | |
546 | { | |
547 | struct acpi_table_dmar *dmar; | |
548 | struct acpi_dmar_header *entry_header; | |
549 | int ret = 0; | |
7cef3347 | 550 | int drhd_count = 0; |
10e5247f | 551 | |
f6dd5c31 YL |
552 | /* |
553 | * Do it again, earlier dmar_tbl mapping could be mapped with | |
554 | * fixed map. | |
555 | */ | |
556 | dmar_table_detect(); | |
557 | ||
a59b50e9 JC |
558 | /* |
559 | * ACPI tables may not be DMA protected by tboot, so use DMAR copy | |
560 | * SINIT saved in SinitMleData in TXT heap (which is DMA protected) | |
561 | */ | |
562 | dmar_tbl = tboot_get_dmar_table(dmar_tbl); | |
563 | ||
10e5247f KA |
564 | dmar = (struct acpi_table_dmar *)dmar_tbl; |
565 | if (!dmar) | |
566 | return -ENODEV; | |
567 | ||
5b6985ce | 568 | if (dmar->width < PAGE_SHIFT - 1) { |
e9071b0b | 569 | pr_warn("Invalid DMAR haw\n"); |
10e5247f KA |
570 | return -EINVAL; |
571 | } | |
572 | ||
e9071b0b | 573 | pr_info("Host address width %d\n", dmar->width + 1); |
10e5247f KA |
574 | |
575 | entry_header = (struct acpi_dmar_header *)(dmar + 1); | |
576 | while (((unsigned long)entry_header) < | |
577 | (((unsigned long)dmar) + dmar_tbl->length)) { | |
084eb960 TB |
578 | /* Avoid looping forever on bad ACPI tables */ |
579 | if (entry_header->length == 0) { | |
e9071b0b | 580 | pr_warn("Invalid 0-length structure\n"); |
084eb960 TB |
581 | ret = -EINVAL; |
582 | break; | |
583 | } | |
584 | ||
10e5247f KA |
585 | dmar_table_print_dmar_entry(entry_header); |
586 | ||
587 | switch (entry_header->type) { | |
588 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
7cef3347 | 589 | drhd_count++; |
10e5247f KA |
590 | ret = dmar_parse_one_drhd(entry_header); |
591 | break; | |
592 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
593 | ret = dmar_parse_one_rmrr(entry_header); | |
aa5d2b51 YZ |
594 | break; |
595 | case ACPI_DMAR_TYPE_ATSR: | |
aa5d2b51 | 596 | ret = dmar_parse_one_atsr(entry_header); |
10e5247f | 597 | break; |
17b60977 | 598 | case ACPI_DMAR_HARDWARE_AFFINITY: |
aa697079 | 599 | #ifdef CONFIG_ACPI_NUMA |
ee34b32d | 600 | ret = dmar_parse_one_rhsa(entry_header); |
aa697079 | 601 | #endif |
17b60977 | 602 | break; |
10e5247f | 603 | default: |
e9071b0b | 604 | pr_warn("Unknown DMAR structure type %d\n", |
4de75cf9 | 605 | entry_header->type); |
10e5247f KA |
606 | ret = 0; /* for forward compatibility */ |
607 | break; | |
608 | } | |
609 | if (ret) | |
610 | break; | |
611 | ||
612 | entry_header = ((void *)entry_header + entry_header->length); | |
613 | } | |
7cef3347 LZH |
614 | if (drhd_count == 0) |
615 | pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); | |
10e5247f KA |
616 | return ret; |
617 | } | |
618 | ||
0e242612 | 619 | static int dmar_pci_device_match(struct pci_dev __rcu *devices[], int cnt, |
e61d98d8 SS |
620 | struct pci_dev *dev) |
621 | { | |
622 | int index; | |
b683b230 | 623 | struct pci_dev *tmp; |
e61d98d8 SS |
624 | |
625 | while (dev) { | |
b683b230 JL |
626 | for_each_active_dev_scope(devices, cnt, index, tmp) |
627 | if (dev == tmp) | |
e61d98d8 SS |
628 | return 1; |
629 | ||
630 | /* Check our parent */ | |
631 | dev = dev->bus->self; | |
632 | } | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | struct dmar_drhd_unit * | |
638 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
639 | { | |
0e242612 | 640 | struct dmar_drhd_unit *dmaru; |
2e824f79 YZ |
641 | struct acpi_dmar_hardware_unit *drhd; |
642 | ||
dda56549 Y |
643 | dev = pci_physfn(dev); |
644 | ||
0e242612 | 645 | rcu_read_lock(); |
8b161f0e | 646 | for_each_drhd_unit(dmaru) { |
2e824f79 YZ |
647 | drhd = container_of(dmaru->hdr, |
648 | struct acpi_dmar_hardware_unit, | |
649 | header); | |
650 | ||
651 | if (dmaru->include_all && | |
652 | drhd->segment == pci_domain_nr(dev->bus)) | |
0e242612 | 653 | goto out; |
e61d98d8 | 654 | |
2e824f79 YZ |
655 | if (dmar_pci_device_match(dmaru->devices, |
656 | dmaru->devices_cnt, dev)) | |
0e242612 | 657 | goto out; |
e61d98d8 | 658 | } |
0e242612 JL |
659 | dmaru = NULL; |
660 | out: | |
661 | rcu_read_unlock(); | |
e61d98d8 | 662 | |
0e242612 | 663 | return dmaru; |
e61d98d8 SS |
664 | } |
665 | ||
1886e8a9 SS |
666 | int __init dmar_dev_scope_init(void) |
667 | { | |
c2c7286a | 668 | static int dmar_dev_scope_initialized; |
a868e6b7 | 669 | struct dmar_drhd_unit *drhd; |
1886e8a9 SS |
670 | int ret = -ENODEV; |
671 | ||
c2c7286a SS |
672 | if (dmar_dev_scope_initialized) |
673 | return dmar_dev_scope_initialized; | |
674 | ||
318fe7df SS |
675 | if (list_empty(&dmar_drhd_units)) |
676 | goto fail; | |
677 | ||
b683b230 | 678 | for_each_drhd_unit(drhd) { |
1886e8a9 SS |
679 | ret = dmar_parse_dev(drhd); |
680 | if (ret) | |
c2c7286a | 681 | goto fail; |
1886e8a9 SS |
682 | } |
683 | ||
318fe7df SS |
684 | ret = dmar_parse_rmrr_atsr_dev(); |
685 | if (ret) | |
686 | goto fail; | |
1886e8a9 | 687 | |
59ce0515 JL |
688 | bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); |
689 | ||
c2c7286a SS |
690 | dmar_dev_scope_initialized = 1; |
691 | return 0; | |
692 | ||
693 | fail: | |
694 | dmar_dev_scope_initialized = ret; | |
1886e8a9 SS |
695 | return ret; |
696 | } | |
697 | ||
10e5247f KA |
698 | |
699 | int __init dmar_table_init(void) | |
700 | { | |
1886e8a9 | 701 | static int dmar_table_initialized; |
093f87d2 FY |
702 | int ret; |
703 | ||
cc05301f JL |
704 | if (dmar_table_initialized == 0) { |
705 | ret = parse_dmar_table(); | |
706 | if (ret < 0) { | |
707 | if (ret != -ENODEV) | |
708 | pr_info("parse DMAR table failure.\n"); | |
709 | } else if (list_empty(&dmar_drhd_units)) { | |
710 | pr_info("No DMAR devices found\n"); | |
711 | ret = -ENODEV; | |
712 | } | |
093f87d2 | 713 | |
cc05301f JL |
714 | if (ret < 0) |
715 | dmar_table_initialized = ret; | |
716 | else | |
717 | dmar_table_initialized = 1; | |
10e5247f | 718 | } |
093f87d2 | 719 | |
cc05301f | 720 | return dmar_table_initialized < 0 ? dmar_table_initialized : 0; |
10e5247f KA |
721 | } |
722 | ||
3a8663ee BH |
723 | static void warn_invalid_dmar(u64 addr, const char *message) |
724 | { | |
fd0c8894 BH |
725 | WARN_TAINT_ONCE( |
726 | 1, TAINT_FIRMWARE_WORKAROUND, | |
727 | "Your BIOS is broken; DMAR reported at address %llx%s!\n" | |
728 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
729 | addr, message, | |
730 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
731 | dmi_get_system_info(DMI_BIOS_VERSION), | |
732 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
3a8663ee | 733 | } |
6ecbf01c | 734 | |
21004dcd | 735 | static int __init check_zero_address(void) |
86cf898e DW |
736 | { |
737 | struct acpi_table_dmar *dmar; | |
738 | struct acpi_dmar_header *entry_header; | |
739 | struct acpi_dmar_hardware_unit *drhd; | |
740 | ||
741 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
742 | entry_header = (struct acpi_dmar_header *)(dmar + 1); | |
743 | ||
744 | while (((unsigned long)entry_header) < | |
745 | (((unsigned long)dmar) + dmar_tbl->length)) { | |
746 | /* Avoid looping forever on bad ACPI tables */ | |
747 | if (entry_header->length == 0) { | |
e9071b0b | 748 | pr_warn("Invalid 0-length structure\n"); |
86cf898e DW |
749 | return 0; |
750 | } | |
751 | ||
752 | if (entry_header->type == ACPI_DMAR_TYPE_HARDWARE_UNIT) { | |
2c992208 CW |
753 | void __iomem *addr; |
754 | u64 cap, ecap; | |
755 | ||
86cf898e DW |
756 | drhd = (void *)entry_header; |
757 | if (!drhd->address) { | |
3a8663ee | 758 | warn_invalid_dmar(0, ""); |
2c992208 CW |
759 | goto failed; |
760 | } | |
761 | ||
762 | addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); | |
763 | if (!addr ) { | |
764 | printk("IOMMU: can't validate: %llx\n", drhd->address); | |
765 | goto failed; | |
766 | } | |
767 | cap = dmar_readq(addr + DMAR_CAP_REG); | |
768 | ecap = dmar_readq(addr + DMAR_ECAP_REG); | |
769 | early_iounmap(addr, VTD_PAGE_SIZE); | |
770 | if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { | |
3a8663ee BH |
771 | warn_invalid_dmar(drhd->address, |
772 | " returns all ones"); | |
2c992208 | 773 | goto failed; |
86cf898e | 774 | } |
86cf898e DW |
775 | } |
776 | ||
777 | entry_header = ((void *)entry_header + entry_header->length); | |
778 | } | |
779 | return 1; | |
2c992208 CW |
780 | |
781 | failed: | |
2c992208 | 782 | return 0; |
86cf898e DW |
783 | } |
784 | ||
480125ba | 785 | int __init detect_intel_iommu(void) |
2ae21010 SS |
786 | { |
787 | int ret; | |
788 | ||
3a5670e8 | 789 | down_write(&dmar_global_lock); |
f6dd5c31 | 790 | ret = dmar_table_detect(); |
86cf898e DW |
791 | if (ret) |
792 | ret = check_zero_address(); | |
2ae21010 | 793 | { |
11bd04f6 | 794 | if (ret && !no_iommu && !iommu_detected && !dmar_disabled) { |
2ae21010 | 795 | iommu_detected = 1; |
5d990b62 CW |
796 | /* Make sure ACS will be enabled */ |
797 | pci_request_acs(); | |
798 | } | |
f5d1b97b | 799 | |
9d5ce73a FT |
800 | #ifdef CONFIG_X86 |
801 | if (ret) | |
802 | x86_init.iommu.iommu_init = intel_iommu_init; | |
2ae21010 | 803 | #endif |
cacd4213 | 804 | } |
b707cb02 | 805 | early_acpi_os_unmap_memory((void __iomem *)dmar_tbl, dmar_tbl_size); |
f6dd5c31 | 806 | dmar_tbl = NULL; |
3a5670e8 | 807 | up_write(&dmar_global_lock); |
480125ba | 808 | |
4db77ff3 | 809 | return ret ? 1 : -ENODEV; |
2ae21010 SS |
810 | } |
811 | ||
812 | ||
6f5cf521 DD |
813 | static void unmap_iommu(struct intel_iommu *iommu) |
814 | { | |
815 | iounmap(iommu->reg); | |
816 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
817 | } | |
818 | ||
819 | /** | |
820 | * map_iommu: map the iommu's registers | |
821 | * @iommu: the iommu to map | |
822 | * @phys_addr: the physical address of the base resgister | |
e9071b0b | 823 | * |
6f5cf521 | 824 | * Memory map the iommu's registers. Start w/ a single page, and |
e9071b0b | 825 | * possibly expand if that turns out to be insufficent. |
6f5cf521 DD |
826 | */ |
827 | static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) | |
828 | { | |
829 | int map_size, err=0; | |
830 | ||
831 | iommu->reg_phys = phys_addr; | |
832 | iommu->reg_size = VTD_PAGE_SIZE; | |
833 | ||
834 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { | |
835 | pr_err("IOMMU: can't reserve memory\n"); | |
836 | err = -EBUSY; | |
837 | goto out; | |
838 | } | |
839 | ||
840 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
841 | if (!iommu->reg) { | |
842 | pr_err("IOMMU: can't map the region\n"); | |
843 | err = -ENOMEM; | |
844 | goto release; | |
845 | } | |
846 | ||
847 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
848 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
849 | ||
850 | if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { | |
851 | err = -EINVAL; | |
852 | warn_invalid_dmar(phys_addr, " returns all ones"); | |
853 | goto unmap; | |
854 | } | |
855 | ||
856 | /* the registers might be more than one page */ | |
857 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
858 | cap_max_fault_reg_offset(iommu->cap)); | |
859 | map_size = VTD_PAGE_ALIGN(map_size); | |
860 | if (map_size > iommu->reg_size) { | |
861 | iounmap(iommu->reg); | |
862 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
863 | iommu->reg_size = map_size; | |
864 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, | |
865 | iommu->name)) { | |
866 | pr_err("IOMMU: can't reserve memory\n"); | |
867 | err = -EBUSY; | |
868 | goto out; | |
869 | } | |
870 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
871 | if (!iommu->reg) { | |
872 | pr_err("IOMMU: can't map the region\n"); | |
873 | err = -ENOMEM; | |
874 | goto release; | |
875 | } | |
876 | } | |
877 | err = 0; | |
878 | goto out; | |
879 | ||
880 | unmap: | |
881 | iounmap(iommu->reg); | |
882 | release: | |
883 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
884 | out: | |
885 | return err; | |
886 | } | |
887 | ||
694835dc | 888 | static int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 889 | { |
c42d9f32 | 890 | struct intel_iommu *iommu; |
3a93c841 | 891 | u32 ver, sts; |
c42d9f32 | 892 | static int iommu_allocated = 0; |
43f7392b | 893 | int agaw = 0; |
4ed0d3e6 | 894 | int msagaw = 0; |
6f5cf521 | 895 | int err; |
c42d9f32 | 896 | |
6ecbf01c | 897 | if (!drhd->reg_base_addr) { |
3a8663ee | 898 | warn_invalid_dmar(0, ""); |
6ecbf01c DW |
899 | return -EINVAL; |
900 | } | |
901 | ||
c42d9f32 SS |
902 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
903 | if (!iommu) | |
1886e8a9 | 904 | return -ENOMEM; |
c42d9f32 SS |
905 | |
906 | iommu->seq_id = iommu_allocated++; | |
9d783ba0 | 907 | sprintf (iommu->name, "dmar%d", iommu->seq_id); |
e61d98d8 | 908 | |
6f5cf521 DD |
909 | err = map_iommu(iommu, drhd->reg_base_addr); |
910 | if (err) { | |
911 | pr_err("IOMMU: failed to map %s\n", iommu->name); | |
e61d98d8 SS |
912 | goto error; |
913 | } | |
0815565a | 914 | |
6f5cf521 | 915 | err = -EINVAL; |
1b573683 WH |
916 | agaw = iommu_calculate_agaw(iommu); |
917 | if (agaw < 0) { | |
bf947fcb DD |
918 | pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", |
919 | iommu->seq_id); | |
0815565a | 920 | goto err_unmap; |
4ed0d3e6 FY |
921 | } |
922 | msagaw = iommu_calculate_max_sagaw(iommu); | |
923 | if (msagaw < 0) { | |
bf947fcb | 924 | pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", |
1b573683 | 925 | iommu->seq_id); |
0815565a | 926 | goto err_unmap; |
1b573683 WH |
927 | } |
928 | iommu->agaw = agaw; | |
4ed0d3e6 | 929 | iommu->msagaw = msagaw; |
1b573683 | 930 | |
ee34b32d SS |
931 | iommu->node = -1; |
932 | ||
e61d98d8 | 933 | ver = readl(iommu->reg + DMAR_VER_REG); |
680a7524 YL |
934 | pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", |
935 | iommu->seq_id, | |
5b6985ce FY |
936 | (unsigned long long)drhd->reg_base_addr, |
937 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
938 | (unsigned long long)iommu->cap, | |
939 | (unsigned long long)iommu->ecap); | |
e61d98d8 | 940 | |
3a93c841 TI |
941 | /* Reflect status in gcmd */ |
942 | sts = readl(iommu->reg + DMAR_GSTS_REG); | |
943 | if (sts & DMA_GSTS_IRES) | |
944 | iommu->gcmd |= DMA_GCMD_IRE; | |
945 | if (sts & DMA_GSTS_TES) | |
946 | iommu->gcmd |= DMA_GCMD_TE; | |
947 | if (sts & DMA_GSTS_QIES) | |
948 | iommu->gcmd |= DMA_GCMD_QIE; | |
949 | ||
1f5b3c3f | 950 | raw_spin_lock_init(&iommu->register_lock); |
e61d98d8 SS |
951 | |
952 | drhd->iommu = iommu; | |
1886e8a9 | 953 | return 0; |
0815565a DW |
954 | |
955 | err_unmap: | |
6f5cf521 | 956 | unmap_iommu(iommu); |
0815565a | 957 | error: |
e61d98d8 | 958 | kfree(iommu); |
6f5cf521 | 959 | return err; |
e61d98d8 SS |
960 | } |
961 | ||
a868e6b7 | 962 | static void free_iommu(struct intel_iommu *iommu) |
e61d98d8 | 963 | { |
a868e6b7 JL |
964 | if (iommu->irq) { |
965 | free_irq(iommu->irq, iommu); | |
966 | irq_set_handler_data(iommu->irq, NULL); | |
967 | destroy_irq(iommu->irq); | |
968 | } | |
e61d98d8 | 969 | |
a84da70b JL |
970 | if (iommu->qi) { |
971 | free_page((unsigned long)iommu->qi->desc); | |
972 | kfree(iommu->qi->desc_status); | |
973 | kfree(iommu->qi); | |
974 | } | |
975 | ||
e61d98d8 | 976 | if (iommu->reg) |
6f5cf521 DD |
977 | unmap_iommu(iommu); |
978 | ||
e61d98d8 SS |
979 | kfree(iommu); |
980 | } | |
fe962e90 SS |
981 | |
982 | /* | |
983 | * Reclaim all the submitted descriptors which have completed its work. | |
984 | */ | |
985 | static inline void reclaim_free_desc(struct q_inval *qi) | |
986 | { | |
6ba6c3a4 YZ |
987 | while (qi->desc_status[qi->free_tail] == QI_DONE || |
988 | qi->desc_status[qi->free_tail] == QI_ABORT) { | |
fe962e90 SS |
989 | qi->desc_status[qi->free_tail] = QI_FREE; |
990 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
991 | qi->free_cnt++; | |
992 | } | |
993 | } | |
994 | ||
704126ad YZ |
995 | static int qi_check_fault(struct intel_iommu *iommu, int index) |
996 | { | |
997 | u32 fault; | |
6ba6c3a4 | 998 | int head, tail; |
704126ad YZ |
999 | struct q_inval *qi = iommu->qi; |
1000 | int wait_index = (index + 1) % QI_LENGTH; | |
1001 | ||
6ba6c3a4 YZ |
1002 | if (qi->desc_status[wait_index] == QI_ABORT) |
1003 | return -EAGAIN; | |
1004 | ||
704126ad YZ |
1005 | fault = readl(iommu->reg + DMAR_FSTS_REG); |
1006 | ||
1007 | /* | |
1008 | * If IQE happens, the head points to the descriptor associated | |
1009 | * with the error. No new descriptors are fetched until the IQE | |
1010 | * is cleared. | |
1011 | */ | |
1012 | if (fault & DMA_FSTS_IQE) { | |
1013 | head = readl(iommu->reg + DMAR_IQH_REG); | |
6ba6c3a4 | 1014 | if ((head >> DMAR_IQ_SHIFT) == index) { |
bf947fcb | 1015 | pr_err("VT-d detected invalid descriptor: " |
6ba6c3a4 YZ |
1016 | "low=%llx, high=%llx\n", |
1017 | (unsigned long long)qi->desc[index].low, | |
1018 | (unsigned long long)qi->desc[index].high); | |
704126ad YZ |
1019 | memcpy(&qi->desc[index], &qi->desc[wait_index], |
1020 | sizeof(struct qi_desc)); | |
1021 | __iommu_flush_cache(iommu, &qi->desc[index], | |
1022 | sizeof(struct qi_desc)); | |
1023 | writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); | |
1024 | return -EINVAL; | |
1025 | } | |
1026 | } | |
1027 | ||
6ba6c3a4 YZ |
1028 | /* |
1029 | * If ITE happens, all pending wait_desc commands are aborted. | |
1030 | * No new descriptors are fetched until the ITE is cleared. | |
1031 | */ | |
1032 | if (fault & DMA_FSTS_ITE) { | |
1033 | head = readl(iommu->reg + DMAR_IQH_REG); | |
1034 | head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH; | |
1035 | head |= 1; | |
1036 | tail = readl(iommu->reg + DMAR_IQT_REG); | |
1037 | tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH; | |
1038 | ||
1039 | writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); | |
1040 | ||
1041 | do { | |
1042 | if (qi->desc_status[head] == QI_IN_USE) | |
1043 | qi->desc_status[head] = QI_ABORT; | |
1044 | head = (head - 2 + QI_LENGTH) % QI_LENGTH; | |
1045 | } while (head != tail); | |
1046 | ||
1047 | if (qi->desc_status[wait_index] == QI_ABORT) | |
1048 | return -EAGAIN; | |
1049 | } | |
1050 | ||
1051 | if (fault & DMA_FSTS_ICE) | |
1052 | writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); | |
1053 | ||
704126ad YZ |
1054 | return 0; |
1055 | } | |
1056 | ||
fe962e90 SS |
1057 | /* |
1058 | * Submit the queued invalidation descriptor to the remapping | |
1059 | * hardware unit and wait for its completion. | |
1060 | */ | |
704126ad | 1061 | int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) |
fe962e90 | 1062 | { |
6ba6c3a4 | 1063 | int rc; |
fe962e90 SS |
1064 | struct q_inval *qi = iommu->qi; |
1065 | struct qi_desc *hw, wait_desc; | |
1066 | int wait_index, index; | |
1067 | unsigned long flags; | |
1068 | ||
1069 | if (!qi) | |
704126ad | 1070 | return 0; |
fe962e90 SS |
1071 | |
1072 | hw = qi->desc; | |
1073 | ||
6ba6c3a4 YZ |
1074 | restart: |
1075 | rc = 0; | |
1076 | ||
3b8f4048 | 1077 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 | 1078 | while (qi->free_cnt < 3) { |
3b8f4048 | 1079 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
fe962e90 | 1080 | cpu_relax(); |
3b8f4048 | 1081 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 SS |
1082 | } |
1083 | ||
1084 | index = qi->free_head; | |
1085 | wait_index = (index + 1) % QI_LENGTH; | |
1086 | ||
1087 | qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE; | |
1088 | ||
1089 | hw[index] = *desc; | |
1090 | ||
704126ad YZ |
1091 | wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) | |
1092 | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; | |
fe962e90 SS |
1093 | wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]); |
1094 | ||
1095 | hw[wait_index] = wait_desc; | |
1096 | ||
1097 | __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc)); | |
1098 | __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc)); | |
1099 | ||
1100 | qi->free_head = (qi->free_head + 2) % QI_LENGTH; | |
1101 | qi->free_cnt -= 2; | |
1102 | ||
fe962e90 SS |
1103 | /* |
1104 | * update the HW tail register indicating the presence of | |
1105 | * new descriptors. | |
1106 | */ | |
6ba6c3a4 | 1107 | writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG); |
fe962e90 SS |
1108 | |
1109 | while (qi->desc_status[wait_index] != QI_DONE) { | |
f05810c9 SS |
1110 | /* |
1111 | * We will leave the interrupts disabled, to prevent interrupt | |
1112 | * context to queue another cmd while a cmd is already submitted | |
1113 | * and waiting for completion on this cpu. This is to avoid | |
1114 | * a deadlock where the interrupt context can wait indefinitely | |
1115 | * for free slots in the queue. | |
1116 | */ | |
704126ad YZ |
1117 | rc = qi_check_fault(iommu, index); |
1118 | if (rc) | |
6ba6c3a4 | 1119 | break; |
704126ad | 1120 | |
3b8f4048 | 1121 | raw_spin_unlock(&qi->q_lock); |
fe962e90 | 1122 | cpu_relax(); |
3b8f4048 | 1123 | raw_spin_lock(&qi->q_lock); |
fe962e90 | 1124 | } |
6ba6c3a4 YZ |
1125 | |
1126 | qi->desc_status[index] = QI_DONE; | |
fe962e90 SS |
1127 | |
1128 | reclaim_free_desc(qi); | |
3b8f4048 | 1129 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
704126ad | 1130 | |
6ba6c3a4 YZ |
1131 | if (rc == -EAGAIN) |
1132 | goto restart; | |
1133 | ||
704126ad | 1134 | return rc; |
fe962e90 SS |
1135 | } |
1136 | ||
1137 | /* | |
1138 | * Flush the global interrupt entry cache. | |
1139 | */ | |
1140 | void qi_global_iec(struct intel_iommu *iommu) | |
1141 | { | |
1142 | struct qi_desc desc; | |
1143 | ||
1144 | desc.low = QI_IEC_TYPE; | |
1145 | desc.high = 0; | |
1146 | ||
704126ad | 1147 | /* should never fail */ |
fe962e90 SS |
1148 | qi_submit_sync(&desc, iommu); |
1149 | } | |
1150 | ||
4c25a2c1 DW |
1151 | void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, |
1152 | u64 type) | |
3481f210 | 1153 | { |
3481f210 YS |
1154 | struct qi_desc desc; |
1155 | ||
3481f210 YS |
1156 | desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) |
1157 | | QI_CC_GRAN(type) | QI_CC_TYPE; | |
1158 | desc.high = 0; | |
1159 | ||
4c25a2c1 | 1160 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1161 | } |
1162 | ||
1f0ef2aa DW |
1163 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
1164 | unsigned int size_order, u64 type) | |
3481f210 YS |
1165 | { |
1166 | u8 dw = 0, dr = 0; | |
1167 | ||
1168 | struct qi_desc desc; | |
1169 | int ih = 0; | |
1170 | ||
3481f210 YS |
1171 | if (cap_write_drain(iommu->cap)) |
1172 | dw = 1; | |
1173 | ||
1174 | if (cap_read_drain(iommu->cap)) | |
1175 | dr = 1; | |
1176 | ||
1177 | desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) | |
1178 | | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; | |
1179 | desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) | |
1180 | | QI_IOTLB_AM(size_order); | |
1181 | ||
1f0ef2aa | 1182 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1183 | } |
1184 | ||
6ba6c3a4 YZ |
1185 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep, |
1186 | u64 addr, unsigned mask) | |
1187 | { | |
1188 | struct qi_desc desc; | |
1189 | ||
1190 | if (mask) { | |
1191 | BUG_ON(addr & ((1 << (VTD_PAGE_SHIFT + mask)) - 1)); | |
1192 | addr |= (1 << (VTD_PAGE_SHIFT + mask - 1)) - 1; | |
1193 | desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; | |
1194 | } else | |
1195 | desc.high = QI_DEV_IOTLB_ADDR(addr); | |
1196 | ||
1197 | if (qdep >= QI_DEV_IOTLB_MAX_INVS) | |
1198 | qdep = 0; | |
1199 | ||
1200 | desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | | |
1201 | QI_DIOTLB_TYPE; | |
1202 | ||
1203 | qi_submit_sync(&desc, iommu); | |
1204 | } | |
1205 | ||
eba67e5d SS |
1206 | /* |
1207 | * Disable Queued Invalidation interface. | |
1208 | */ | |
1209 | void dmar_disable_qi(struct intel_iommu *iommu) | |
1210 | { | |
1211 | unsigned long flags; | |
1212 | u32 sts; | |
1213 | cycles_t start_time = get_cycles(); | |
1214 | ||
1215 | if (!ecap_qis(iommu->ecap)) | |
1216 | return; | |
1217 | ||
1f5b3c3f | 1218 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
1219 | |
1220 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
1221 | if (!(sts & DMA_GSTS_QIES)) | |
1222 | goto end; | |
1223 | ||
1224 | /* | |
1225 | * Give a chance to HW to complete the pending invalidation requests. | |
1226 | */ | |
1227 | while ((readl(iommu->reg + DMAR_IQT_REG) != | |
1228 | readl(iommu->reg + DMAR_IQH_REG)) && | |
1229 | (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) | |
1230 | cpu_relax(); | |
1231 | ||
1232 | iommu->gcmd &= ~DMA_GCMD_QIE; | |
eba67e5d SS |
1233 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
1234 | ||
1235 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | |
1236 | !(sts & DMA_GSTS_QIES), sts); | |
1237 | end: | |
1f5b3c3f | 1238 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
1239 | } |
1240 | ||
eb4a52bc FY |
1241 | /* |
1242 | * Enable queued invalidation. | |
1243 | */ | |
1244 | static void __dmar_enable_qi(struct intel_iommu *iommu) | |
1245 | { | |
c416daa9 | 1246 | u32 sts; |
eb4a52bc FY |
1247 | unsigned long flags; |
1248 | struct q_inval *qi = iommu->qi; | |
1249 | ||
1250 | qi->free_head = qi->free_tail = 0; | |
1251 | qi->free_cnt = QI_LENGTH; | |
1252 | ||
1f5b3c3f | 1253 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eb4a52bc FY |
1254 | |
1255 | /* write zero to the tail reg */ | |
1256 | writel(0, iommu->reg + DMAR_IQT_REG); | |
1257 | ||
1258 | dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); | |
1259 | ||
eb4a52bc | 1260 | iommu->gcmd |= DMA_GCMD_QIE; |
c416daa9 | 1261 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
eb4a52bc FY |
1262 | |
1263 | /* Make sure hardware complete it */ | |
1264 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
1265 | ||
1f5b3c3f | 1266 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eb4a52bc FY |
1267 | } |
1268 | ||
fe962e90 SS |
1269 | /* |
1270 | * Enable Queued Invalidation interface. This is a must to support | |
1271 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
1272 | * register based IOTLB invalidation. | |
1273 | */ | |
1274 | int dmar_enable_qi(struct intel_iommu *iommu) | |
1275 | { | |
fe962e90 | 1276 | struct q_inval *qi; |
751cafe3 | 1277 | struct page *desc_page; |
fe962e90 SS |
1278 | |
1279 | if (!ecap_qis(iommu->ecap)) | |
1280 | return -ENOENT; | |
1281 | ||
1282 | /* | |
1283 | * queued invalidation is already setup and enabled. | |
1284 | */ | |
1285 | if (iommu->qi) | |
1286 | return 0; | |
1287 | ||
fa4b57cc | 1288 | iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); |
fe962e90 SS |
1289 | if (!iommu->qi) |
1290 | return -ENOMEM; | |
1291 | ||
1292 | qi = iommu->qi; | |
1293 | ||
751cafe3 SS |
1294 | |
1295 | desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0); | |
1296 | if (!desc_page) { | |
fe962e90 | 1297 | kfree(qi); |
b707cb02 | 1298 | iommu->qi = NULL; |
fe962e90 SS |
1299 | return -ENOMEM; |
1300 | } | |
1301 | ||
751cafe3 SS |
1302 | qi->desc = page_address(desc_page); |
1303 | ||
37a40710 | 1304 | qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC); |
fe962e90 SS |
1305 | if (!qi->desc_status) { |
1306 | free_page((unsigned long) qi->desc); | |
1307 | kfree(qi); | |
b707cb02 | 1308 | iommu->qi = NULL; |
fe962e90 SS |
1309 | return -ENOMEM; |
1310 | } | |
1311 | ||
1312 | qi->free_head = qi->free_tail = 0; | |
1313 | qi->free_cnt = QI_LENGTH; | |
1314 | ||
3b8f4048 | 1315 | raw_spin_lock_init(&qi->q_lock); |
fe962e90 | 1316 | |
eb4a52bc | 1317 | __dmar_enable_qi(iommu); |
fe962e90 SS |
1318 | |
1319 | return 0; | |
1320 | } | |
0ac2491f SS |
1321 | |
1322 | /* iommu interrupt handling. Most stuff are MSI-like. */ | |
1323 | ||
9d783ba0 SS |
1324 | enum faulttype { |
1325 | DMA_REMAP, | |
1326 | INTR_REMAP, | |
1327 | UNKNOWN, | |
1328 | }; | |
1329 | ||
1330 | static const char *dma_remap_fault_reasons[] = | |
0ac2491f SS |
1331 | { |
1332 | "Software", | |
1333 | "Present bit in root entry is clear", | |
1334 | "Present bit in context entry is clear", | |
1335 | "Invalid context entry", | |
1336 | "Access beyond MGAW", | |
1337 | "PTE Write access is not set", | |
1338 | "PTE Read access is not set", | |
1339 | "Next page table ptr is invalid", | |
1340 | "Root table address invalid", | |
1341 | "Context table ptr is invalid", | |
1342 | "non-zero reserved fields in RTP", | |
1343 | "non-zero reserved fields in CTP", | |
1344 | "non-zero reserved fields in PTE", | |
4ecccd9e | 1345 | "PCE for translation request specifies blocking", |
0ac2491f | 1346 | }; |
9d783ba0 | 1347 | |
95a02e97 | 1348 | static const char *irq_remap_fault_reasons[] = |
9d783ba0 SS |
1349 | { |
1350 | "Detected reserved fields in the decoded interrupt-remapped request", | |
1351 | "Interrupt index exceeded the interrupt-remapping table size", | |
1352 | "Present field in the IRTE entry is clear", | |
1353 | "Error accessing interrupt-remapping table pointed by IRTA_REG", | |
1354 | "Detected reserved fields in the IRTE entry", | |
1355 | "Blocked a compatibility format interrupt request", | |
1356 | "Blocked an interrupt request due to source-id verification failure", | |
1357 | }; | |
1358 | ||
21004dcd | 1359 | static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) |
0ac2491f | 1360 | { |
fefe1ed1 DC |
1361 | if (fault_reason >= 0x20 && (fault_reason - 0x20 < |
1362 | ARRAY_SIZE(irq_remap_fault_reasons))) { | |
9d783ba0 | 1363 | *fault_type = INTR_REMAP; |
95a02e97 | 1364 | return irq_remap_fault_reasons[fault_reason - 0x20]; |
9d783ba0 SS |
1365 | } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { |
1366 | *fault_type = DMA_REMAP; | |
1367 | return dma_remap_fault_reasons[fault_reason]; | |
1368 | } else { | |
1369 | *fault_type = UNKNOWN; | |
0ac2491f | 1370 | return "Unknown"; |
9d783ba0 | 1371 | } |
0ac2491f SS |
1372 | } |
1373 | ||
5c2837fb | 1374 | void dmar_msi_unmask(struct irq_data *data) |
0ac2491f | 1375 | { |
dced35ae | 1376 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
0ac2491f SS |
1377 | unsigned long flag; |
1378 | ||
1379 | /* unmask it */ | |
1f5b3c3f | 1380 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f SS |
1381 | writel(0, iommu->reg + DMAR_FECTL_REG); |
1382 | /* Read a reg to force flush the post write */ | |
1383 | readl(iommu->reg + DMAR_FECTL_REG); | |
1f5b3c3f | 1384 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1385 | } |
1386 | ||
5c2837fb | 1387 | void dmar_msi_mask(struct irq_data *data) |
0ac2491f SS |
1388 | { |
1389 | unsigned long flag; | |
dced35ae | 1390 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
0ac2491f SS |
1391 | |
1392 | /* mask it */ | |
1f5b3c3f | 1393 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f SS |
1394 | writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG); |
1395 | /* Read a reg to force flush the post write */ | |
1396 | readl(iommu->reg + DMAR_FECTL_REG); | |
1f5b3c3f | 1397 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1398 | } |
1399 | ||
1400 | void dmar_msi_write(int irq, struct msi_msg *msg) | |
1401 | { | |
dced35ae | 1402 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
0ac2491f SS |
1403 | unsigned long flag; |
1404 | ||
1f5b3c3f | 1405 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f SS |
1406 | writel(msg->data, iommu->reg + DMAR_FEDATA_REG); |
1407 | writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG); | |
1408 | writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG); | |
1f5b3c3f | 1409 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1410 | } |
1411 | ||
1412 | void dmar_msi_read(int irq, struct msi_msg *msg) | |
1413 | { | |
dced35ae | 1414 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
0ac2491f SS |
1415 | unsigned long flag; |
1416 | ||
1f5b3c3f | 1417 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f SS |
1418 | msg->data = readl(iommu->reg + DMAR_FEDATA_REG); |
1419 | msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG); | |
1420 | msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG); | |
1f5b3c3f | 1421 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1422 | } |
1423 | ||
1424 | static int dmar_fault_do_one(struct intel_iommu *iommu, int type, | |
1425 | u8 fault_reason, u16 source_id, unsigned long long addr) | |
1426 | { | |
1427 | const char *reason; | |
9d783ba0 | 1428 | int fault_type; |
0ac2491f | 1429 | |
9d783ba0 | 1430 | reason = dmar_get_fault_reason(fault_reason, &fault_type); |
0ac2491f | 1431 | |
9d783ba0 | 1432 | if (fault_type == INTR_REMAP) |
bf947fcb | 1433 | pr_err("INTR-REMAP: Request device [[%02x:%02x.%d] " |
9d783ba0 SS |
1434 | "fault index %llx\n" |
1435 | "INTR-REMAP:[fault reason %02d] %s\n", | |
1436 | (source_id >> 8), PCI_SLOT(source_id & 0xFF), | |
1437 | PCI_FUNC(source_id & 0xFF), addr >> 48, | |
1438 | fault_reason, reason); | |
1439 | else | |
bf947fcb | 1440 | pr_err("DMAR:[%s] Request device [%02x:%02x.%d] " |
9d783ba0 SS |
1441 | "fault addr %llx \n" |
1442 | "DMAR:[fault reason %02d] %s\n", | |
1443 | (type ? "DMA Read" : "DMA Write"), | |
1444 | (source_id >> 8), PCI_SLOT(source_id & 0xFF), | |
1445 | PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason); | |
0ac2491f SS |
1446 | return 0; |
1447 | } | |
1448 | ||
1449 | #define PRIMARY_FAULT_REG_LEN (16) | |
1531a6a6 | 1450 | irqreturn_t dmar_fault(int irq, void *dev_id) |
0ac2491f SS |
1451 | { |
1452 | struct intel_iommu *iommu = dev_id; | |
1453 | int reg, fault_index; | |
1454 | u32 fault_status; | |
1455 | unsigned long flag; | |
1456 | ||
1f5b3c3f | 1457 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1458 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
9d783ba0 | 1459 | if (fault_status) |
bf947fcb | 1460 | pr_err("DRHD: handling fault status reg %x\n", fault_status); |
0ac2491f SS |
1461 | |
1462 | /* TBD: ignore advanced fault log currently */ | |
1463 | if (!(fault_status & DMA_FSTS_PPF)) | |
bd5cdad0 | 1464 | goto unlock_exit; |
0ac2491f SS |
1465 | |
1466 | fault_index = dma_fsts_fault_record_index(fault_status); | |
1467 | reg = cap_fault_reg_offset(iommu->cap); | |
1468 | while (1) { | |
1469 | u8 fault_reason; | |
1470 | u16 source_id; | |
1471 | u64 guest_addr; | |
1472 | int type; | |
1473 | u32 data; | |
1474 | ||
1475 | /* highest 32 bits */ | |
1476 | data = readl(iommu->reg + reg + | |
1477 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1478 | if (!(data & DMA_FRCD_F)) | |
1479 | break; | |
1480 | ||
1481 | fault_reason = dma_frcd_fault_reason(data); | |
1482 | type = dma_frcd_type(data); | |
1483 | ||
1484 | data = readl(iommu->reg + reg + | |
1485 | fault_index * PRIMARY_FAULT_REG_LEN + 8); | |
1486 | source_id = dma_frcd_source_id(data); | |
1487 | ||
1488 | guest_addr = dmar_readq(iommu->reg + reg + | |
1489 | fault_index * PRIMARY_FAULT_REG_LEN); | |
1490 | guest_addr = dma_frcd_page_addr(guest_addr); | |
1491 | /* clear the fault */ | |
1492 | writel(DMA_FRCD_F, iommu->reg + reg + | |
1493 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1494 | ||
1f5b3c3f | 1495 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1496 | |
1497 | dmar_fault_do_one(iommu, type, fault_reason, | |
1498 | source_id, guest_addr); | |
1499 | ||
1500 | fault_index++; | |
8211a7b5 | 1501 | if (fault_index >= cap_num_fault_regs(iommu->cap)) |
0ac2491f | 1502 | fault_index = 0; |
1f5b3c3f | 1503 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1504 | } |
0ac2491f | 1505 | |
bd5cdad0 LZH |
1506 | writel(DMA_FSTS_PFO | DMA_FSTS_PPF, iommu->reg + DMAR_FSTS_REG); |
1507 | ||
1508 | unlock_exit: | |
1f5b3c3f | 1509 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1510 | return IRQ_HANDLED; |
1511 | } | |
1512 | ||
1513 | int dmar_set_interrupt(struct intel_iommu *iommu) | |
1514 | { | |
1515 | int irq, ret; | |
1516 | ||
9d783ba0 SS |
1517 | /* |
1518 | * Check if the fault interrupt is already initialized. | |
1519 | */ | |
1520 | if (iommu->irq) | |
1521 | return 0; | |
1522 | ||
0ac2491f SS |
1523 | irq = create_irq(); |
1524 | if (!irq) { | |
bf947fcb | 1525 | pr_err("IOMMU: no free vectors\n"); |
0ac2491f SS |
1526 | return -EINVAL; |
1527 | } | |
1528 | ||
dced35ae | 1529 | irq_set_handler_data(irq, iommu); |
0ac2491f SS |
1530 | iommu->irq = irq; |
1531 | ||
1532 | ret = arch_setup_dmar_msi(irq); | |
1533 | if (ret) { | |
dced35ae | 1534 | irq_set_handler_data(irq, NULL); |
0ac2491f SS |
1535 | iommu->irq = 0; |
1536 | destroy_irq(irq); | |
dd726435 | 1537 | return ret; |
0ac2491f SS |
1538 | } |
1539 | ||
477694e7 | 1540 | ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); |
0ac2491f | 1541 | if (ret) |
bf947fcb | 1542 | pr_err("IOMMU: can't request irq\n"); |
0ac2491f SS |
1543 | return ret; |
1544 | } | |
9d783ba0 SS |
1545 | |
1546 | int __init enable_drhd_fault_handling(void) | |
1547 | { | |
1548 | struct dmar_drhd_unit *drhd; | |
7c919779 | 1549 | struct intel_iommu *iommu; |
9d783ba0 SS |
1550 | |
1551 | /* | |
1552 | * Enable fault control interrupt. | |
1553 | */ | |
7c919779 | 1554 | for_each_iommu(iommu, drhd) { |
bd5cdad0 | 1555 | u32 fault_status; |
7c919779 | 1556 | int ret = dmar_set_interrupt(iommu); |
9d783ba0 SS |
1557 | |
1558 | if (ret) { | |
e9071b0b | 1559 | pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", |
9d783ba0 SS |
1560 | (unsigned long long)drhd->reg_base_addr, ret); |
1561 | return -1; | |
1562 | } | |
7f99d946 SS |
1563 | |
1564 | /* | |
1565 | * Clear any previous faults. | |
1566 | */ | |
1567 | dmar_fault(iommu->irq, iommu); | |
bd5cdad0 LZH |
1568 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
1569 | writel(fault_status, iommu->reg + DMAR_FSTS_REG); | |
9d783ba0 SS |
1570 | } |
1571 | ||
1572 | return 0; | |
1573 | } | |
eb4a52bc FY |
1574 | |
1575 | /* | |
1576 | * Re-enable Queued Invalidation interface. | |
1577 | */ | |
1578 | int dmar_reenable_qi(struct intel_iommu *iommu) | |
1579 | { | |
1580 | if (!ecap_qis(iommu->ecap)) | |
1581 | return -ENOENT; | |
1582 | ||
1583 | if (!iommu->qi) | |
1584 | return -ENOENT; | |
1585 | ||
1586 | /* | |
1587 | * First disable queued invalidation. | |
1588 | */ | |
1589 | dmar_disable_qi(iommu); | |
1590 | /* | |
1591 | * Then enable queued invalidation again. Since there is no pending | |
1592 | * invalidation requests now, it's safe to re-enable queued | |
1593 | * invalidation. | |
1594 | */ | |
1595 | __dmar_enable_qi(iommu); | |
1596 | ||
1597 | return 0; | |
1598 | } | |
074835f0 YS |
1599 | |
1600 | /* | |
1601 | * Check interrupt remapping support in DMAR table description. | |
1602 | */ | |
0b8973a8 | 1603 | int __init dmar_ir_support(void) |
074835f0 YS |
1604 | { |
1605 | struct acpi_table_dmar *dmar; | |
1606 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
4f506e07 AP |
1607 | if (!dmar) |
1608 | return 0; | |
074835f0 YS |
1609 | return dmar->flags & 0x1; |
1610 | } | |
694835dc | 1611 | |
a868e6b7 JL |
1612 | static int __init dmar_free_unused_resources(void) |
1613 | { | |
1614 | struct dmar_drhd_unit *dmaru, *dmaru_n; | |
1615 | ||
1616 | /* DMAR units are in use */ | |
1617 | if (irq_remapping_enabled || intel_iommu_enabled) | |
1618 | return 0; | |
1619 | ||
59ce0515 JL |
1620 | bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); |
1621 | ||
3a5670e8 | 1622 | down_write(&dmar_global_lock); |
a868e6b7 JL |
1623 | list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { |
1624 | list_del(&dmaru->list); | |
1625 | dmar_free_drhd(dmaru); | |
1626 | } | |
3a5670e8 | 1627 | up_write(&dmar_global_lock); |
a868e6b7 JL |
1628 | |
1629 | return 0; | |
1630 | } | |
1631 | ||
1632 | late_initcall(dmar_free_unused_resources); | |
4db77ff3 | 1633 | IOMMU_INIT_POST(detect_intel_iommu); |