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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
2a96536e | 15 | #include <linux/clk.h> |
8ed55c81 | 16 | #include <linux/dma-mapping.h> |
2a96536e | 17 | #include <linux/err.h> |
312900c6 | 18 | #include <linux/io.h> |
2a96536e | 19 | #include <linux/iommu.h> |
312900c6 | 20 | #include <linux/interrupt.h> |
2a96536e | 21 | #include <linux/list.h> |
8ed55c81 MS |
22 | #include <linux/of.h> |
23 | #include <linux/of_iommu.h> | |
24 | #include <linux/of_platform.h> | |
312900c6 MS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
2a96536e KC |
28 | |
29 | #include <asm/cacheflush.h> | |
8ed55c81 | 30 | #include <asm/dma-iommu.h> |
2a96536e KC |
31 | #include <asm/pgtable.h> |
32 | ||
d09d78fc CK |
33 | typedef u32 sysmmu_iova_t; |
34 | typedef u32 sysmmu_pte_t; | |
35 | ||
f171abab | 36 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
37 | #define SECT_ORDER 20 |
38 | #define LPAGE_ORDER 16 | |
39 | #define SPAGE_ORDER 12 | |
40 | ||
41 | #define SECT_SIZE (1 << SECT_ORDER) | |
42 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
43 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
44 | ||
45 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
46 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
47 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
48 | ||
66a7ed84 CK |
49 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
50 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
51 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
52 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
53 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
54 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
55 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
56 | ||
57 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
58 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
59 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
60 | ||
d09d78fc CK |
61 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
62 | { | |
63 | return iova & (size - 1); | |
64 | } | |
65 | ||
2a96536e | 66 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 67 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 68 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 69 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 70 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 71 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
72 | |
73 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 74 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 75 | |
d09d78fc CK |
76 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
77 | { | |
78 | return iova >> SECT_ORDER; | |
79 | } | |
80 | ||
81 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
82 | { | |
83 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
84 | } | |
85 | ||
86 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
87 | |
88 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
89 | ||
90 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
91 | ||
92 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
93 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
94 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
95 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
96 | ||
97 | #define CTRL_ENABLE 0x5 | |
98 | #define CTRL_BLOCK 0x7 | |
99 | #define CTRL_DISABLE 0x0 | |
100 | ||
eeb5184b CK |
101 | #define CFG_LRU 0x1 |
102 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
103 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
104 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
105 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
106 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
107 | ||
2a96536e KC |
108 | #define REG_MMU_CTRL 0x000 |
109 | #define REG_MMU_CFG 0x004 | |
110 | #define REG_MMU_STATUS 0x008 | |
111 | #define REG_MMU_FLUSH 0x00C | |
112 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
113 | #define REG_PT_BASE_ADDR 0x014 | |
114 | #define REG_INT_STATUS 0x018 | |
115 | #define REG_INT_CLEAR 0x01C | |
116 | ||
117 | #define REG_PAGE_FAULT_ADDR 0x024 | |
118 | #define REG_AW_FAULT_ADDR 0x028 | |
119 | #define REG_AR_FAULT_ADDR 0x02C | |
120 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
121 | ||
122 | #define REG_MMU_VERSION 0x034 | |
123 | ||
eeb5184b CK |
124 | #define MMU_MAJ_VER(val) ((val) >> 7) |
125 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
126 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
127 | ||
128 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
129 | ||
2a96536e KC |
130 | #define REG_PB0_SADDR 0x04C |
131 | #define REG_PB0_EADDR 0x050 | |
132 | #define REG_PB1_SADDR 0x054 | |
133 | #define REG_PB1_EADDR 0x058 | |
134 | ||
6b21a5db CK |
135 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
136 | ||
734c3c73 | 137 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
138 | static sysmmu_pte_t *zero_lv2_table; |
139 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 140 | |
d09d78fc | 141 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
142 | { |
143 | return pgtable + lv1ent_offset(iova); | |
144 | } | |
145 | ||
d09d78fc | 146 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 147 | { |
d09d78fc | 148 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 149 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
150 | } |
151 | ||
152 | enum exynos_sysmmu_inttype { | |
153 | SYSMMU_PAGEFAULT, | |
154 | SYSMMU_AR_MULTIHIT, | |
155 | SYSMMU_AW_MULTIHIT, | |
156 | SYSMMU_BUSERROR, | |
157 | SYSMMU_AR_SECURITY, | |
158 | SYSMMU_AR_ACCESS, | |
159 | SYSMMU_AW_SECURITY, | |
160 | SYSMMU_AW_PROTECTION, /* 7 */ | |
161 | SYSMMU_FAULT_UNKNOWN, | |
162 | SYSMMU_FAULTS_NUM | |
163 | }; | |
164 | ||
2a96536e KC |
165 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
166 | REG_PAGE_FAULT_ADDR, | |
167 | REG_AR_FAULT_ADDR, | |
168 | REG_AW_FAULT_ADDR, | |
169 | REG_DEFAULT_SLAVE_ADDR, | |
170 | REG_AR_FAULT_ADDR, | |
171 | REG_AR_FAULT_ADDR, | |
172 | REG_AW_FAULT_ADDR, | |
173 | REG_AW_FAULT_ADDR | |
174 | }; | |
175 | ||
176 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
177 | "PAGE FAULT", | |
178 | "AR MULTI-HIT FAULT", | |
179 | "AW MULTI-HIT FAULT", | |
180 | "BUS ERROR", | |
181 | "AR SECURITY PROTECTION FAULT", | |
182 | "AR ACCESS PROTECTION FAULT", | |
183 | "AW SECURITY PROTECTION FAULT", | |
184 | "AW ACCESS PROTECTION FAULT", | |
185 | "UNKNOWN FAULT" | |
186 | }; | |
187 | ||
2860af3c MS |
188 | /* |
189 | * This structure is attached to dev.archdata.iommu of the master device | |
190 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
191 | * which are bound to given master device. It is usually referenced by 'owner' | |
192 | * pointer. | |
193 | */ | |
6b21a5db | 194 | struct exynos_iommu_owner { |
1b092054 | 195 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
6b21a5db CK |
196 | }; |
197 | ||
2860af3c MS |
198 | /* |
199 | * This structure exynos specific generalization of struct iommu_domain. | |
200 | * It contains list of SYSMMU controllers from all master devices, which has | |
201 | * been attached to this domain and page tables of IO address space defined by | |
202 | * it. It is usually referenced by 'domain' pointer. | |
203 | */ | |
2a96536e | 204 | struct exynos_iommu_domain { |
2860af3c MS |
205 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
206 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
207 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
208 | spinlock_t lock; /* lock for modyfying list of clients */ | |
209 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 210 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
211 | }; |
212 | ||
2860af3c MS |
213 | /* |
214 | * This structure hold all data of a single SYSMMU controller, this includes | |
215 | * hw resources like registers and clocks, pointers and list nodes to connect | |
216 | * it to all other structures, internal state and parameters read from device | |
217 | * tree. It is usually referenced by 'data' pointer. | |
218 | */ | |
2a96536e | 219 | struct sysmmu_drvdata { |
2860af3c MS |
220 | struct device *sysmmu; /* SYSMMU controller device */ |
221 | struct device *master; /* master device (owner) */ | |
222 | void __iomem *sfrbase; /* our registers */ | |
223 | struct clk *clk; /* SYSMMU's clock */ | |
224 | struct clk *clk_master; /* master's device clock */ | |
225 | int activations; /* number of calls to sysmmu_enable */ | |
226 | spinlock_t lock; /* lock for modyfying state */ | |
227 | struct exynos_iommu_domain *domain; /* domain we belong to */ | |
228 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 229 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
230 | phys_addr_t pgtable; /* assigned page table structure */ |
231 | unsigned int version; /* our version */ | |
2a96536e KC |
232 | }; |
233 | ||
e1fd1eaa JR |
234 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
235 | { | |
236 | return container_of(dom, struct exynos_iommu_domain, domain); | |
237 | } | |
238 | ||
2a96536e KC |
239 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
240 | { | |
241 | /* return true if the System MMU was not active previously | |
242 | and it needs to be initialized */ | |
243 | return ++data->activations == 1; | |
244 | } | |
245 | ||
246 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
247 | { | |
248 | /* return true if the System MMU is needed to be disabled */ | |
249 | BUG_ON(data->activations < 1); | |
250 | return --data->activations == 0; | |
251 | } | |
252 | ||
253 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
254 | { | |
255 | return data->activations > 0; | |
256 | } | |
257 | ||
258 | static void sysmmu_unblock(void __iomem *sfrbase) | |
259 | { | |
260 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
261 | } | |
262 | ||
263 | static bool sysmmu_block(void __iomem *sfrbase) | |
264 | { | |
265 | int i = 120; | |
266 | ||
267 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
268 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
269 | --i; | |
270 | ||
271 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
272 | sysmmu_unblock(sfrbase); | |
273 | return false; | |
274 | } | |
275 | ||
276 | return true; | |
277 | } | |
278 | ||
279 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
280 | { | |
281 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
282 | } | |
283 | ||
284 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 285 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 286 | { |
3ad6b7f3 | 287 | unsigned int i; |
365409db | 288 | |
3ad6b7f3 CK |
289 | for (i = 0; i < num_inv; i++) { |
290 | __raw_writel((iova & SPAGE_MASK) | 1, | |
291 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
292 | iova += SPAGE_SIZE; | |
293 | } | |
2a96536e KC |
294 | } |
295 | ||
296 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 297 | phys_addr_t pgd) |
2a96536e | 298 | { |
2a96536e KC |
299 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
300 | ||
301 | __sysmmu_tlb_invalidate(sfrbase); | |
302 | } | |
303 | ||
1fab7fa7 CK |
304 | static void show_fault_information(const char *name, |
305 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 306 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 307 | { |
d09d78fc | 308 | sysmmu_pte_t *ent; |
2a96536e KC |
309 | |
310 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
311 | itype = SYSMMU_FAULT_UNKNOWN; | |
312 | ||
d09d78fc | 313 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 314 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 315 | |
7222e8db | 316 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 317 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
318 | |
319 | if (lv1ent_page(ent)) { | |
320 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 321 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 322 | } |
2a96536e KC |
323 | } |
324 | ||
325 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
326 | { | |
f171abab | 327 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 328 | struct sysmmu_drvdata *data = dev_id; |
2a96536e | 329 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 330 | sysmmu_iova_t addr = -1; |
7222e8db | 331 | int ret = -ENOSYS; |
2a96536e | 332 | |
2a96536e KC |
333 | WARN_ON(!is_sysmmu_active(data)); |
334 | ||
9d4e7a24 CK |
335 | spin_lock(&data->lock); |
336 | ||
70605870 CK |
337 | if (!IS_ERR(data->clk_master)) |
338 | clk_enable(data->clk_master); | |
9d4e7a24 | 339 | |
7222e8db CK |
340 | itype = (enum exynos_sysmmu_inttype) |
341 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
342 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 343 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
344 | else |
345 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 346 | |
1fab7fa7 CK |
347 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
348 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
349 | __func__, dev_name(data->sysmmu)); | |
350 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
351 | __func__); | |
352 | BUG(); | |
353 | } else { | |
d09d78fc | 354 | unsigned int base = |
1fab7fa7 CK |
355 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
356 | show_fault_information(dev_name(data->sysmmu), | |
357 | itype, base, addr); | |
358 | if (data->domain) | |
a9133b99 | 359 | ret = report_iommu_fault(&data->domain->domain, |
6b21a5db | 360 | data->master, addr, itype); |
2a96536e KC |
361 | } |
362 | ||
1fab7fa7 CK |
363 | /* fault is not recovered by fault handler */ |
364 | BUG_ON(ret != 0); | |
2a96536e | 365 | |
1fab7fa7 CK |
366 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
367 | ||
368 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 369 | |
70605870 CK |
370 | if (!IS_ERR(data->clk_master)) |
371 | clk_disable(data->clk_master); | |
372 | ||
9d4e7a24 | 373 | spin_unlock(&data->lock); |
2a96536e KC |
374 | |
375 | return IRQ_HANDLED; | |
376 | } | |
377 | ||
6b21a5db | 378 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 379 | { |
70605870 CK |
380 | if (!IS_ERR(data->clk_master)) |
381 | clk_enable(data->clk_master); | |
382 | ||
7222e8db | 383 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 384 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 385 | |
46c16d1e | 386 | clk_disable(data->clk); |
70605870 CK |
387 | if (!IS_ERR(data->clk_master)) |
388 | clk_disable(data->clk_master); | |
2a96536e KC |
389 | } |
390 | ||
6b21a5db | 391 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 392 | { |
6b21a5db | 393 | bool disabled; |
2a96536e KC |
394 | unsigned long flags; |
395 | ||
9d4e7a24 | 396 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 397 | |
6b21a5db CK |
398 | disabled = set_sysmmu_inactive(data); |
399 | ||
400 | if (disabled) { | |
401 | data->pgtable = 0; | |
402 | data->domain = NULL; | |
403 | ||
404 | __sysmmu_disable_nocount(data); | |
2a96536e | 405 | |
6b21a5db CK |
406 | dev_dbg(data->sysmmu, "Disabled\n"); |
407 | } else { | |
408 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
409 | data->activations); | |
2a96536e KC |
410 | } |
411 | ||
6b21a5db CK |
412 | spin_unlock_irqrestore(&data->lock, flags); |
413 | ||
414 | return disabled; | |
415 | } | |
2a96536e | 416 | |
6b21a5db CK |
417 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
418 | { | |
eeb5184b CK |
419 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
420 | unsigned int ver; | |
421 | ||
512bd0c6 | 422 | ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); |
eeb5184b CK |
423 | if (MMU_MAJ_VER(ver) == 3) { |
424 | if (MMU_MIN_VER(ver) >= 2) { | |
425 | cfg |= CFG_FLPDCACHE; | |
426 | if (MMU_MIN_VER(ver) == 3) { | |
427 | cfg |= CFG_ACGEN; | |
428 | cfg &= ~CFG_LRU; | |
429 | } else { | |
430 | cfg |= CFG_SYSSEL; | |
431 | } | |
432 | } | |
433 | } | |
6b21a5db CK |
434 | |
435 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
512bd0c6 | 436 | data->version = ver; |
6b21a5db CK |
437 | } |
438 | ||
439 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
440 | { | |
70605870 CK |
441 | if (!IS_ERR(data->clk_master)) |
442 | clk_enable(data->clk_master); | |
443 | clk_enable(data->clk); | |
444 | ||
6b21a5db CK |
445 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
446 | ||
447 | __sysmmu_init_config(data); | |
448 | ||
449 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 450 | |
7222e8db CK |
451 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
452 | ||
70605870 CK |
453 | if (!IS_ERR(data->clk_master)) |
454 | clk_disable(data->clk_master); | |
6b21a5db | 455 | } |
70605870 | 456 | |
bfa00489 | 457 | static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable, |
a9133b99 | 458 | struct exynos_iommu_domain *domain) |
6b21a5db CK |
459 | { |
460 | int ret = 0; | |
461 | unsigned long flags; | |
462 | ||
463 | spin_lock_irqsave(&data->lock, flags); | |
464 | if (set_sysmmu_active(data)) { | |
465 | data->pgtable = pgtable; | |
a9133b99 | 466 | data->domain = domain; |
6b21a5db CK |
467 | |
468 | __sysmmu_enable_nocount(data); | |
469 | ||
470 | dev_dbg(data->sysmmu, "Enabled\n"); | |
471 | } else { | |
472 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
473 | ||
474 | dev_dbg(data->sysmmu, "already enabled\n"); | |
475 | } | |
476 | ||
477 | if (WARN_ON(ret < 0)) | |
478 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 479 | |
9d4e7a24 | 480 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
481 | |
482 | return ret; | |
483 | } | |
484 | ||
66a7ed84 CK |
485 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
486 | sysmmu_iova_t iova) | |
487 | { | |
512bd0c6 | 488 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
489 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
490 | } | |
491 | ||
469acebe | 492 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
493 | sysmmu_iova_t iova) |
494 | { | |
495 | unsigned long flags; | |
66a7ed84 CK |
496 | |
497 | if (!IS_ERR(data->clk_master)) | |
498 | clk_enable(data->clk_master); | |
499 | ||
500 | spin_lock_irqsave(&data->lock, flags); | |
501 | if (is_sysmmu_active(data)) | |
502 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
503 | spin_unlock_irqrestore(&data->lock, flags); | |
504 | ||
505 | if (!IS_ERR(data->clk_master)) | |
506 | clk_disable(data->clk_master); | |
507 | } | |
508 | ||
469acebe MS |
509 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
510 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
511 | { |
512 | unsigned long flags; | |
2a96536e | 513 | |
6b21a5db | 514 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 515 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 516 | unsigned int num_inv = 1; |
70605870 CK |
517 | |
518 | if (!IS_ERR(data->clk_master)) | |
519 | clk_enable(data->clk_master); | |
520 | ||
3ad6b7f3 CK |
521 | /* |
522 | * L2TLB invalidation required | |
523 | * 4KB page: 1 invalidation | |
f171abab SK |
524 | * 64KB page: 16 invalidations |
525 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
526 | * because it is set-associative TLB |
527 | * with 8-way and 64 sets. | |
528 | * 1MB page can be cached in one of all sets. | |
529 | * 64KB page can be one of 16 consecutive sets. | |
530 | */ | |
512bd0c6 | 531 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
532 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
533 | ||
7222e8db CK |
534 | if (sysmmu_block(data->sfrbase)) { |
535 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 536 | data->sfrbase, iova, num_inv); |
7222e8db | 537 | sysmmu_unblock(data->sfrbase); |
2a96536e | 538 | } |
70605870 CK |
539 | if (!IS_ERR(data->clk_master)) |
540 | clk_disable(data->clk_master); | |
2a96536e | 541 | } else { |
469acebe MS |
542 | dev_dbg(data->master, |
543 | "disabled. Skipping TLB invalidation @ %#x\n", iova); | |
2a96536e | 544 | } |
9d4e7a24 | 545 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
546 | } |
547 | ||
6b21a5db | 548 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 549 | { |
46c16d1e | 550 | int irq, ret; |
7222e8db | 551 | struct device *dev = &pdev->dev; |
2a96536e | 552 | struct sysmmu_drvdata *data; |
7222e8db | 553 | struct resource *res; |
2a96536e | 554 | |
46c16d1e CK |
555 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
556 | if (!data) | |
557 | return -ENOMEM; | |
2a96536e | 558 | |
7222e8db | 559 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
560 | data->sfrbase = devm_ioremap_resource(dev, res); |
561 | if (IS_ERR(data->sfrbase)) | |
562 | return PTR_ERR(data->sfrbase); | |
2a96536e | 563 | |
46c16d1e CK |
564 | irq = platform_get_irq(pdev, 0); |
565 | if (irq <= 0) { | |
0bf4e54d | 566 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 567 | return irq; |
2a96536e KC |
568 | } |
569 | ||
46c16d1e | 570 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
571 | dev_name(dev), data); |
572 | if (ret) { | |
46c16d1e CK |
573 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
574 | return ret; | |
2a96536e KC |
575 | } |
576 | ||
46c16d1e CK |
577 | data->clk = devm_clk_get(dev, "sysmmu"); |
578 | if (IS_ERR(data->clk)) { | |
579 | dev_err(dev, "Failed to get clock!\n"); | |
580 | return PTR_ERR(data->clk); | |
581 | } else { | |
582 | ret = clk_prepare(data->clk); | |
583 | if (ret) { | |
584 | dev_err(dev, "Failed to prepare clk\n"); | |
585 | return ret; | |
586 | } | |
2a96536e KC |
587 | } |
588 | ||
70605870 CK |
589 | data->clk_master = devm_clk_get(dev, "master"); |
590 | if (!IS_ERR(data->clk_master)) { | |
591 | ret = clk_prepare(data->clk_master); | |
592 | if (ret) { | |
593 | clk_unprepare(data->clk); | |
594 | dev_err(dev, "Failed to prepare master's clk\n"); | |
595 | return ret; | |
596 | } | |
597 | } | |
598 | ||
2a96536e | 599 | data->sysmmu = dev; |
9d4e7a24 | 600 | spin_lock_init(&data->lock); |
2a96536e | 601 | |
7222e8db CK |
602 | platform_set_drvdata(pdev, data); |
603 | ||
f4723ec1 | 604 | pm_runtime_enable(dev); |
2a96536e | 605 | |
2a96536e | 606 | return 0; |
2a96536e KC |
607 | } |
608 | ||
622015e4 MS |
609 | #ifdef CONFIG_PM_SLEEP |
610 | static int exynos_sysmmu_suspend(struct device *dev) | |
611 | { | |
612 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
613 | ||
614 | dev_dbg(dev, "suspend\n"); | |
615 | if (is_sysmmu_active(data)) { | |
616 | __sysmmu_disable_nocount(data); | |
617 | pm_runtime_put(dev); | |
618 | } | |
619 | return 0; | |
620 | } | |
621 | ||
622 | static int exynos_sysmmu_resume(struct device *dev) | |
623 | { | |
624 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
625 | ||
626 | dev_dbg(dev, "resume\n"); | |
627 | if (is_sysmmu_active(data)) { | |
628 | pm_runtime_get_sync(dev); | |
629 | __sysmmu_enable_nocount(data); | |
630 | } | |
631 | return 0; | |
632 | } | |
633 | #endif | |
634 | ||
635 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
636 | SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume) | |
637 | }; | |
638 | ||
6b21a5db CK |
639 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
640 | { .compatible = "samsung,exynos-sysmmu", }, | |
641 | { }, | |
642 | }; | |
643 | ||
644 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
645 | .probe = exynos_sysmmu_probe, | |
646 | .driver = { | |
2a96536e | 647 | .name = "exynos-sysmmu", |
6b21a5db | 648 | .of_match_table = sysmmu_of_match, |
622015e4 | 649 | .pm = &sysmmu_pm_ops, |
2a96536e KC |
650 | } |
651 | }; | |
652 | ||
653 | static inline void pgtable_flush(void *vastart, void *vaend) | |
654 | { | |
655 | dmac_flush_range(vastart, vaend); | |
656 | outer_flush_range(virt_to_phys(vastart), | |
657 | virt_to_phys(vaend)); | |
658 | } | |
659 | ||
e1fd1eaa | 660 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 661 | { |
bfa00489 | 662 | struct exynos_iommu_domain *domain; |
66a7ed84 | 663 | int i; |
2a96536e | 664 | |
e1fd1eaa JR |
665 | if (type != IOMMU_DOMAIN_UNMANAGED) |
666 | return NULL; | |
667 | ||
bfa00489 MS |
668 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
669 | if (!domain) | |
e1fd1eaa | 670 | return NULL; |
2a96536e | 671 | |
bfa00489 MS |
672 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
673 | if (!domain->pgtable) | |
2a96536e KC |
674 | goto err_pgtable; |
675 | ||
bfa00489 MS |
676 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
677 | if (!domain->lv2entcnt) | |
2a96536e KC |
678 | goto err_counter; |
679 | ||
f171abab | 680 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 681 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
682 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
683 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
684 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
685 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
686 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
687 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
688 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
689 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
690 | } |
691 | ||
bfa00489 | 692 | pgtable_flush(domain->pgtable, domain->pgtable + NUM_LV1ENTRIES); |
2a96536e | 693 | |
bfa00489 MS |
694 | spin_lock_init(&domain->lock); |
695 | spin_lock_init(&domain->pgtablelock); | |
696 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 697 | |
bfa00489 MS |
698 | domain->domain.geometry.aperture_start = 0; |
699 | domain->domain.geometry.aperture_end = ~0UL; | |
700 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 701 | |
bfa00489 | 702 | return &domain->domain; |
2a96536e KC |
703 | |
704 | err_counter: | |
bfa00489 | 705 | free_pages((unsigned long)domain->pgtable, 2); |
2a96536e | 706 | err_pgtable: |
bfa00489 | 707 | kfree(domain); |
e1fd1eaa | 708 | return NULL; |
2a96536e KC |
709 | } |
710 | ||
bfa00489 | 711 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 712 | { |
bfa00489 | 713 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 714 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
715 | unsigned long flags; |
716 | int i; | |
717 | ||
bfa00489 | 718 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 719 | |
bfa00489 | 720 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 721 | |
bfa00489 | 722 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
723 | if (__sysmmu_disable(data)) |
724 | data->master = NULL; | |
725 | list_del_init(&data->domain_node); | |
2a96536e KC |
726 | } |
727 | ||
bfa00489 | 728 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e KC |
729 | |
730 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
bfa00489 | 731 | if (lv1ent_page(domain->pgtable + i)) |
734c3c73 | 732 | kmem_cache_free(lv2table_kmem_cache, |
bfa00489 | 733 | phys_to_virt(lv2table_base(domain->pgtable + i))); |
2a96536e | 734 | |
bfa00489 MS |
735 | free_pages((unsigned long)domain->pgtable, 2); |
736 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
737 | kfree(domain); | |
2a96536e KC |
738 | } |
739 | ||
bfa00489 | 740 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
741 | struct device *dev) |
742 | { | |
6b21a5db | 743 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 744 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 745 | struct sysmmu_drvdata *data; |
bfa00489 | 746 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 747 | unsigned long flags; |
469acebe | 748 | int ret = -ENODEV; |
2a96536e | 749 | |
469acebe MS |
750 | if (!has_sysmmu(dev)) |
751 | return -ENODEV; | |
2a96536e | 752 | |
1b092054 | 753 | list_for_each_entry(data, &owner->controllers, owner_node) { |
ce70ca56 | 754 | pm_runtime_get_sync(data->sysmmu); |
a9133b99 | 755 | ret = __sysmmu_enable(data, pagetable, domain); |
469acebe MS |
756 | if (ret >= 0) { |
757 | data->master = dev; | |
758 | ||
bfa00489 MS |
759 | spin_lock_irqsave(&domain->lock, flags); |
760 | list_add_tail(&data->domain_node, &domain->clients); | |
761 | spin_unlock_irqrestore(&domain->lock, flags); | |
469acebe MS |
762 | } |
763 | } | |
2a96536e KC |
764 | |
765 | if (ret < 0) { | |
7222e8db CK |
766 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
767 | __func__, &pagetable); | |
7222e8db | 768 | return ret; |
2a96536e KC |
769 | } |
770 | ||
7222e8db CK |
771 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
772 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
773 | ||
2a96536e KC |
774 | return ret; |
775 | } | |
776 | ||
bfa00489 | 777 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
778 | struct device *dev) |
779 | { | |
bfa00489 MS |
780 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
781 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
1b092054 | 782 | struct sysmmu_drvdata *data, *next; |
2a96536e | 783 | unsigned long flags; |
469acebe | 784 | bool found = false; |
2a96536e | 785 | |
469acebe MS |
786 | if (!has_sysmmu(dev)) |
787 | return; | |
2a96536e | 788 | |
bfa00489 | 789 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 790 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
791 | if (data->master == dev) { |
792 | if (__sysmmu_disable(data)) { | |
793 | data->master = NULL; | |
794 | list_del_init(&data->domain_node); | |
795 | } | |
ce70ca56 | 796 | pm_runtime_put(data->sysmmu); |
469acebe | 797 | found = true; |
2a96536e KC |
798 | } |
799 | } | |
bfa00489 | 800 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 801 | |
469acebe | 802 | if (found) |
7222e8db CK |
803 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
804 | __func__, &pagetable); | |
6b21a5db CK |
805 | else |
806 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
807 | } |
808 | ||
bfa00489 | 809 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 810 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 811 | { |
61128f08 | 812 | if (lv1ent_section(sent)) { |
d09d78fc | 813 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
814 | return ERR_PTR(-EADDRINUSE); |
815 | } | |
816 | ||
2a96536e | 817 | if (lv1ent_fault(sent)) { |
d09d78fc | 818 | sysmmu_pte_t *pent; |
66a7ed84 | 819 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 820 | |
734c3c73 | 821 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 822 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 823 | if (!pent) |
61128f08 | 824 | return ERR_PTR(-ENOMEM); |
2a96536e | 825 | |
7222e8db | 826 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
dc3814f4 | 827 | kmemleak_ignore(pent); |
2a96536e KC |
828 | *pgcounter = NUM_LV2ENTRIES; |
829 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
830 | pgtable_flush(sent, sent + 1); | |
66a7ed84 CK |
831 | |
832 | /* | |
f171abab SK |
833 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
834 | * FLPD cache may cache the address of zero_l2_table. This | |
835 | * function replaces the zero_l2_table with new L2 page table | |
836 | * to write valid mappings. | |
66a7ed84 | 837 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
838 | * cache may still cache zero_l2_table for the valid area |
839 | * instead of new L2 page table that has the mapping | |
840 | * information of the valid area. | |
66a7ed84 CK |
841 | * Thus any replacement of zero_l2_table with other valid L2 |
842 | * page table must involve FLPD cache invalidation for System | |
843 | * MMU v3.3. | |
844 | * FLPD cache invalidation is performed with TLB invalidation | |
845 | * by VPN without blocking. It is safe to invalidate TLB without | |
846 | * blocking because the target address of TLB invalidation is | |
847 | * not currently mapped. | |
848 | */ | |
849 | if (need_flush_flpd_cache) { | |
469acebe | 850 | struct sysmmu_drvdata *data; |
365409db | 851 | |
bfa00489 MS |
852 | spin_lock(&domain->lock); |
853 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 854 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 855 | spin_unlock(&domain->lock); |
66a7ed84 | 856 | } |
2a96536e KC |
857 | } |
858 | ||
859 | return page_entry(sent, iova); | |
860 | } | |
861 | ||
bfa00489 | 862 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 863 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 864 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 865 | { |
61128f08 | 866 | if (lv1ent_section(sent)) { |
d09d78fc | 867 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 868 | iova); |
2a96536e | 869 | return -EADDRINUSE; |
61128f08 | 870 | } |
2a96536e KC |
871 | |
872 | if (lv1ent_page(sent)) { | |
61128f08 | 873 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 874 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 875 | iova); |
2a96536e | 876 | return -EADDRINUSE; |
61128f08 | 877 | } |
2a96536e | 878 | |
734c3c73 | 879 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
880 | *pgcnt = 0; |
881 | } | |
882 | ||
883 | *sent = mk_lv1ent_sect(paddr); | |
884 | ||
885 | pgtable_flush(sent, sent + 1); | |
886 | ||
bfa00489 | 887 | spin_lock(&domain->lock); |
66a7ed84 | 888 | if (lv1ent_page_zero(sent)) { |
469acebe | 889 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
890 | /* |
891 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
892 | * entry by speculative prefetch of SLPD which has no mapping. | |
893 | */ | |
bfa00489 | 894 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 895 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 896 | } |
bfa00489 | 897 | spin_unlock(&domain->lock); |
66a7ed84 | 898 | |
2a96536e KC |
899 | return 0; |
900 | } | |
901 | ||
d09d78fc | 902 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
903 | short *pgcnt) |
904 | { | |
905 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 906 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
907 | return -EADDRINUSE; |
908 | ||
909 | *pent = mk_lv2ent_spage(paddr); | |
910 | pgtable_flush(pent, pent + 1); | |
911 | *pgcnt -= 1; | |
912 | } else { /* size == LPAGE_SIZE */ | |
913 | int i; | |
365409db | 914 | |
2a96536e | 915 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 916 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
917 | if (i > 0) |
918 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
919 | return -EADDRINUSE; |
920 | } | |
921 | ||
922 | *pent = mk_lv2ent_lpage(paddr); | |
923 | } | |
924 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
925 | *pgcnt -= SPAGES_PER_LPAGE; | |
926 | } | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
66a7ed84 CK |
931 | /* |
932 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
933 | * | |
f171abab | 934 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 935 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
936 | * However, the logic has a bug that while caching faulty page table entries, |
937 | * System MMU reports page fault if the cached fault entry is hit even though | |
938 | * the fault entry is updated to a valid entry after the entry is cached. | |
939 | * To prevent caching faulty page table entries which may be updated to valid | |
940 | * entries later, the virtual memory manager should care about the workaround | |
941 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
942 | * |
943 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 944 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 945 | * |
f171abab | 946 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
947 | * the following sizes for System MMU v3.1 and v3.2. |
948 | * System MMU v3.1: 128KiB | |
949 | * System MMU v3.2: 256KiB | |
950 | * | |
951 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
952 | * more workarounds. |
953 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
954 | * than or equal to 128KiB. | |
66a7ed84 CK |
955 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
956 | */ | |
bfa00489 MS |
957 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
958 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
959 | int prot) | |
2a96536e | 960 | { |
bfa00489 | 961 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
962 | sysmmu_pte_t *entry; |
963 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
964 | unsigned long flags; |
965 | int ret = -ENOMEM; | |
966 | ||
bfa00489 | 967 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 968 | |
bfa00489 | 969 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 970 | |
bfa00489 | 971 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
972 | |
973 | if (size == SECT_SIZE) { | |
bfa00489 MS |
974 | ret = lv1set_section(domain, entry, iova, paddr, |
975 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 976 | } else { |
d09d78fc | 977 | sysmmu_pte_t *pent; |
2a96536e | 978 | |
bfa00489 MS |
979 | pent = alloc_lv2entry(domain, entry, iova, |
980 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 981 | |
61128f08 CK |
982 | if (IS_ERR(pent)) |
983 | ret = PTR_ERR(pent); | |
2a96536e KC |
984 | else |
985 | ret = lv2set_page(pent, paddr, size, | |
bfa00489 | 986 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
987 | } |
988 | ||
61128f08 | 989 | if (ret) |
0bf4e54d CK |
990 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
991 | __func__, ret, size, iova); | |
2a96536e | 992 | |
bfa00489 | 993 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
994 | |
995 | return ret; | |
996 | } | |
997 | ||
bfa00489 MS |
998 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
999 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1000 | { |
469acebe | 1001 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1002 | unsigned long flags; |
1003 | ||
bfa00489 | 1004 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1005 | |
bfa00489 | 1006 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1007 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1008 | |
bfa00489 | 1009 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1010 | } |
1011 | ||
bfa00489 MS |
1012 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1013 | unsigned long l_iova, size_t size) | |
2a96536e | 1014 | { |
bfa00489 | 1015 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1016 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1017 | sysmmu_pte_t *ent; | |
61128f08 | 1018 | size_t err_pgsize; |
d09d78fc | 1019 | unsigned long flags; |
2a96536e | 1020 | |
bfa00489 | 1021 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1022 | |
bfa00489 | 1023 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1024 | |
bfa00489 | 1025 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1026 | |
1027 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1028 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1029 | err_pgsize = SECT_SIZE; |
1030 | goto err; | |
1031 | } | |
2a96536e | 1032 | |
f171abab SK |
1033 | /* workaround for h/w bug in System MMU v3.3 */ |
1034 | *ent = ZERO_LV2LINK; | |
2a96536e KC |
1035 | pgtable_flush(ent, ent + 1); |
1036 | size = SECT_SIZE; | |
1037 | goto done; | |
1038 | } | |
1039 | ||
1040 | if (unlikely(lv1ent_fault(ent))) { | |
1041 | if (size > SECT_SIZE) | |
1042 | size = SECT_SIZE; | |
1043 | goto done; | |
1044 | } | |
1045 | ||
1046 | /* lv1ent_page(sent) == true here */ | |
1047 | ||
1048 | ent = page_entry(ent, iova); | |
1049 | ||
1050 | if (unlikely(lv2ent_fault(ent))) { | |
1051 | size = SPAGE_SIZE; | |
1052 | goto done; | |
1053 | } | |
1054 | ||
1055 | if (lv2ent_small(ent)) { | |
1056 | *ent = 0; | |
1057 | size = SPAGE_SIZE; | |
6cb47ed7 | 1058 | pgtable_flush(ent, ent + 1); |
bfa00489 | 1059 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1060 | goto done; |
1061 | } | |
1062 | ||
1063 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1064 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1065 | err_pgsize = LPAGE_SIZE; |
1066 | goto err; | |
1067 | } | |
2a96536e KC |
1068 | |
1069 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 1070 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
1071 | |
1072 | size = LPAGE_SIZE; | |
bfa00489 | 1073 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1074 | done: |
bfa00489 | 1075 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1076 | |
bfa00489 | 1077 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1078 | |
2a96536e | 1079 | return size; |
61128f08 | 1080 | err: |
bfa00489 | 1081 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1082 | |
0bf4e54d CK |
1083 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1084 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1085 | |
1086 | return 0; | |
2a96536e KC |
1087 | } |
1088 | ||
bfa00489 | 1089 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1090 | dma_addr_t iova) |
2a96536e | 1091 | { |
bfa00489 | 1092 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1093 | sysmmu_pte_t *entry; |
2a96536e KC |
1094 | unsigned long flags; |
1095 | phys_addr_t phys = 0; | |
1096 | ||
bfa00489 | 1097 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1098 | |
bfa00489 | 1099 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1100 | |
1101 | if (lv1ent_section(entry)) { | |
1102 | phys = section_phys(entry) + section_offs(iova); | |
1103 | } else if (lv1ent_page(entry)) { | |
1104 | entry = page_entry(entry, iova); | |
1105 | ||
1106 | if (lv2ent_large(entry)) | |
1107 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1108 | else if (lv2ent_small(entry)) | |
1109 | phys = spage_phys(entry) + spage_offs(iova); | |
1110 | } | |
1111 | ||
bfa00489 | 1112 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1113 | |
1114 | return phys; | |
1115 | } | |
1116 | ||
bf4a1c92 AM |
1117 | static int exynos_iommu_add_device(struct device *dev) |
1118 | { | |
1119 | struct iommu_group *group; | |
1120 | int ret; | |
1121 | ||
06801db0 MS |
1122 | if (!has_sysmmu(dev)) |
1123 | return -ENODEV; | |
1124 | ||
bf4a1c92 AM |
1125 | group = iommu_group_get(dev); |
1126 | ||
1127 | if (!group) { | |
1128 | group = iommu_group_alloc(); | |
1129 | if (IS_ERR(group)) { | |
1130 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1131 | return PTR_ERR(group); | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | ret = iommu_group_add_device(group, dev); | |
1136 | iommu_group_put(group); | |
1137 | ||
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | static void exynos_iommu_remove_device(struct device *dev) | |
1142 | { | |
06801db0 MS |
1143 | if (!has_sysmmu(dev)) |
1144 | return; | |
1145 | ||
bf4a1c92 AM |
1146 | iommu_group_remove_device(dev); |
1147 | } | |
1148 | ||
aa759fd3 MS |
1149 | static int exynos_iommu_of_xlate(struct device *dev, |
1150 | struct of_phandle_args *spec) | |
1151 | { | |
1152 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1153 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
1154 | struct sysmmu_drvdata *data; | |
1155 | ||
1156 | if (!sysmmu) | |
1157 | return -ENODEV; | |
1158 | ||
1159 | data = platform_get_drvdata(sysmmu); | |
1160 | if (!data) | |
1161 | return -ENODEV; | |
1162 | ||
1163 | if (!owner) { | |
1164 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1165 | if (!owner) | |
1166 | return -ENOMEM; | |
1167 | ||
1168 | INIT_LIST_HEAD(&owner->controllers); | |
1169 | dev->archdata.iommu = owner; | |
1170 | } | |
1171 | ||
1172 | list_add_tail(&data->owner_node, &owner->controllers); | |
1173 | return 0; | |
1174 | } | |
1175 | ||
8ed55c81 | 1176 | static struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1177 | .domain_alloc = exynos_iommu_domain_alloc, |
1178 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1179 | .attach_dev = exynos_iommu_attach_device, |
1180 | .detach_dev = exynos_iommu_detach_device, | |
1181 | .map = exynos_iommu_map, | |
1182 | .unmap = exynos_iommu_unmap, | |
315786eb | 1183 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 BH |
1184 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1185 | .add_device = exynos_iommu_add_device, | |
1186 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1187 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1188 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1189 | }; |
1190 | ||
8ed55c81 MS |
1191 | static bool init_done; |
1192 | ||
2a96536e KC |
1193 | static int __init exynos_iommu_init(void) |
1194 | { | |
1195 | int ret; | |
1196 | ||
734c3c73 CK |
1197 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1198 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1199 | if (!lv2table_kmem_cache) { | |
1200 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1201 | return -ENOMEM; | |
1202 | } | |
1203 | ||
2a96536e | 1204 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1205 | if (ret) { |
1206 | pr_err("%s: Failed to register driver\n", __func__); | |
1207 | goto err_reg_driver; | |
1208 | } | |
2a96536e | 1209 | |
66a7ed84 CK |
1210 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1211 | if (zero_lv2_table == NULL) { | |
1212 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1213 | __func__); | |
1214 | ret = -ENOMEM; | |
1215 | goto err_zero_lv2; | |
1216 | } | |
1217 | ||
734c3c73 CK |
1218 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1219 | if (ret) { | |
1220 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1221 | __func__); | |
1222 | goto err_set_iommu; | |
1223 | } | |
2a96536e | 1224 | |
8ed55c81 MS |
1225 | init_done = true; |
1226 | ||
734c3c73 CK |
1227 | return 0; |
1228 | err_set_iommu: | |
66a7ed84 CK |
1229 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1230 | err_zero_lv2: | |
734c3c73 CK |
1231 | platform_driver_unregister(&exynos_sysmmu_driver); |
1232 | err_reg_driver: | |
1233 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1234 | return ret; |
1235 | } | |
8ed55c81 MS |
1236 | |
1237 | static int __init exynos_iommu_of_setup(struct device_node *np) | |
1238 | { | |
1239 | struct platform_device *pdev; | |
1240 | ||
1241 | if (!init_done) | |
1242 | exynos_iommu_init(); | |
1243 | ||
1244 | pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); | |
1245 | if (IS_ERR(pdev)) | |
1246 | return PTR_ERR(pdev); | |
1247 | ||
1248 | of_iommu_set_ops(np, &exynos_iommu_ops); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", | |
1253 | exynos_iommu_of_setup); |