Commit | Line | Data |
---|---|---|
2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
2a96536e KC |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
312900c6 | 17 | #include <linux/io.h> |
2a96536e | 18 | #include <linux/iommu.h> |
312900c6 | 19 | #include <linux/interrupt.h> |
2a96536e | 20 | #include <linux/list.h> |
312900c6 MS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
2a96536e KC |
24 | |
25 | #include <asm/cacheflush.h> | |
26 | #include <asm/pgtable.h> | |
27 | ||
d09d78fc CK |
28 | typedef u32 sysmmu_iova_t; |
29 | typedef u32 sysmmu_pte_t; | |
30 | ||
f171abab | 31 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
32 | #define SECT_ORDER 20 |
33 | #define LPAGE_ORDER 16 | |
34 | #define SPAGE_ORDER 12 | |
35 | ||
36 | #define SECT_SIZE (1 << SECT_ORDER) | |
37 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
38 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
39 | ||
40 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
41 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
42 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
43 | ||
66a7ed84 CK |
44 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
45 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
47 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
48 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
49 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
50 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
51 | ||
52 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
53 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
54 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
55 | ||
d09d78fc CK |
56 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
57 | { | |
58 | return iova & (size - 1); | |
59 | } | |
60 | ||
2a96536e | 61 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 62 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 63 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 64 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 65 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 66 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
67 | |
68 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 69 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 70 | |
d09d78fc CK |
71 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
72 | { | |
73 | return iova >> SECT_ORDER; | |
74 | } | |
75 | ||
76 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
77 | { | |
78 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
79 | } | |
80 | ||
81 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
82 | |
83 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
84 | ||
85 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
86 | ||
87 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
88 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
89 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
90 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
91 | ||
92 | #define CTRL_ENABLE 0x5 | |
93 | #define CTRL_BLOCK 0x7 | |
94 | #define CTRL_DISABLE 0x0 | |
95 | ||
eeb5184b CK |
96 | #define CFG_LRU 0x1 |
97 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
98 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
99 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
100 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
101 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
102 | ||
2a96536e KC |
103 | #define REG_MMU_CTRL 0x000 |
104 | #define REG_MMU_CFG 0x004 | |
105 | #define REG_MMU_STATUS 0x008 | |
106 | #define REG_MMU_FLUSH 0x00C | |
107 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
108 | #define REG_PT_BASE_ADDR 0x014 | |
109 | #define REG_INT_STATUS 0x018 | |
110 | #define REG_INT_CLEAR 0x01C | |
111 | ||
112 | #define REG_PAGE_FAULT_ADDR 0x024 | |
113 | #define REG_AW_FAULT_ADDR 0x028 | |
114 | #define REG_AR_FAULT_ADDR 0x02C | |
115 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
116 | ||
117 | #define REG_MMU_VERSION 0x034 | |
118 | ||
eeb5184b CK |
119 | #define MMU_MAJ_VER(val) ((val) >> 7) |
120 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
121 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
122 | ||
123 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
124 | ||
2a96536e KC |
125 | #define REG_PB0_SADDR 0x04C |
126 | #define REG_PB0_EADDR 0x050 | |
127 | #define REG_PB1_SADDR 0x054 | |
128 | #define REG_PB1_EADDR 0x058 | |
129 | ||
6b21a5db CK |
130 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
131 | ||
734c3c73 | 132 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
133 | static sysmmu_pte_t *zero_lv2_table; |
134 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 135 | |
d09d78fc | 136 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
137 | { |
138 | return pgtable + lv1ent_offset(iova); | |
139 | } | |
140 | ||
d09d78fc | 141 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 142 | { |
d09d78fc | 143 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 144 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
145 | } |
146 | ||
147 | enum exynos_sysmmu_inttype { | |
148 | SYSMMU_PAGEFAULT, | |
149 | SYSMMU_AR_MULTIHIT, | |
150 | SYSMMU_AW_MULTIHIT, | |
151 | SYSMMU_BUSERROR, | |
152 | SYSMMU_AR_SECURITY, | |
153 | SYSMMU_AR_ACCESS, | |
154 | SYSMMU_AW_SECURITY, | |
155 | SYSMMU_AW_PROTECTION, /* 7 */ | |
156 | SYSMMU_FAULT_UNKNOWN, | |
157 | SYSMMU_FAULTS_NUM | |
158 | }; | |
159 | ||
2a96536e KC |
160 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
161 | REG_PAGE_FAULT_ADDR, | |
162 | REG_AR_FAULT_ADDR, | |
163 | REG_AW_FAULT_ADDR, | |
164 | REG_DEFAULT_SLAVE_ADDR, | |
165 | REG_AR_FAULT_ADDR, | |
166 | REG_AR_FAULT_ADDR, | |
167 | REG_AW_FAULT_ADDR, | |
168 | REG_AW_FAULT_ADDR | |
169 | }; | |
170 | ||
171 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
172 | "PAGE FAULT", | |
173 | "AR MULTI-HIT FAULT", | |
174 | "AW MULTI-HIT FAULT", | |
175 | "BUS ERROR", | |
176 | "AR SECURITY PROTECTION FAULT", | |
177 | "AR ACCESS PROTECTION FAULT", | |
178 | "AW SECURITY PROTECTION FAULT", | |
179 | "AW ACCESS PROTECTION FAULT", | |
180 | "UNKNOWN FAULT" | |
181 | }; | |
182 | ||
2860af3c MS |
183 | /* |
184 | * This structure is attached to dev.archdata.iommu of the master device | |
185 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
186 | * which are bound to given master device. It is usually referenced by 'owner' | |
187 | * pointer. | |
188 | */ | |
6b21a5db | 189 | struct exynos_iommu_owner { |
1b092054 | 190 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
6b21a5db CK |
191 | }; |
192 | ||
2860af3c MS |
193 | /* |
194 | * This structure exynos specific generalization of struct iommu_domain. | |
195 | * It contains list of SYSMMU controllers from all master devices, which has | |
196 | * been attached to this domain and page tables of IO address space defined by | |
197 | * it. It is usually referenced by 'domain' pointer. | |
198 | */ | |
2a96536e | 199 | struct exynos_iommu_domain { |
2860af3c MS |
200 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
201 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
202 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
203 | spinlock_t lock; /* lock for modyfying list of clients */ | |
204 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 205 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
206 | }; |
207 | ||
2860af3c MS |
208 | /* |
209 | * This structure hold all data of a single SYSMMU controller, this includes | |
210 | * hw resources like registers and clocks, pointers and list nodes to connect | |
211 | * it to all other structures, internal state and parameters read from device | |
212 | * tree. It is usually referenced by 'data' pointer. | |
213 | */ | |
2a96536e | 214 | struct sysmmu_drvdata { |
2860af3c MS |
215 | struct device *sysmmu; /* SYSMMU controller device */ |
216 | struct device *master; /* master device (owner) */ | |
217 | void __iomem *sfrbase; /* our registers */ | |
218 | struct clk *clk; /* SYSMMU's clock */ | |
219 | struct clk *clk_master; /* master's device clock */ | |
220 | int activations; /* number of calls to sysmmu_enable */ | |
221 | spinlock_t lock; /* lock for modyfying state */ | |
222 | struct exynos_iommu_domain *domain; /* domain we belong to */ | |
223 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 224 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
225 | phys_addr_t pgtable; /* assigned page table structure */ |
226 | unsigned int version; /* our version */ | |
2a96536e KC |
227 | }; |
228 | ||
e1fd1eaa JR |
229 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
230 | { | |
231 | return container_of(dom, struct exynos_iommu_domain, domain); | |
232 | } | |
233 | ||
2a96536e KC |
234 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
235 | { | |
236 | /* return true if the System MMU was not active previously | |
237 | and it needs to be initialized */ | |
238 | return ++data->activations == 1; | |
239 | } | |
240 | ||
241 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
242 | { | |
243 | /* return true if the System MMU is needed to be disabled */ | |
244 | BUG_ON(data->activations < 1); | |
245 | return --data->activations == 0; | |
246 | } | |
247 | ||
248 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
249 | { | |
250 | return data->activations > 0; | |
251 | } | |
252 | ||
253 | static void sysmmu_unblock(void __iomem *sfrbase) | |
254 | { | |
255 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
256 | } | |
257 | ||
258 | static bool sysmmu_block(void __iomem *sfrbase) | |
259 | { | |
260 | int i = 120; | |
261 | ||
262 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
263 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
264 | --i; | |
265 | ||
266 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
267 | sysmmu_unblock(sfrbase); | |
268 | return false; | |
269 | } | |
270 | ||
271 | return true; | |
272 | } | |
273 | ||
274 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
275 | { | |
276 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
277 | } | |
278 | ||
279 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 280 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 281 | { |
3ad6b7f3 | 282 | unsigned int i; |
365409db | 283 | |
3ad6b7f3 CK |
284 | for (i = 0; i < num_inv; i++) { |
285 | __raw_writel((iova & SPAGE_MASK) | 1, | |
286 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
287 | iova += SPAGE_SIZE; | |
288 | } | |
2a96536e KC |
289 | } |
290 | ||
291 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 292 | phys_addr_t pgd) |
2a96536e | 293 | { |
2a96536e KC |
294 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
295 | ||
296 | __sysmmu_tlb_invalidate(sfrbase); | |
297 | } | |
298 | ||
1fab7fa7 CK |
299 | static void show_fault_information(const char *name, |
300 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 301 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 302 | { |
d09d78fc | 303 | sysmmu_pte_t *ent; |
2a96536e KC |
304 | |
305 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
306 | itype = SYSMMU_FAULT_UNKNOWN; | |
307 | ||
d09d78fc | 308 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 309 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 310 | |
7222e8db | 311 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 312 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
313 | |
314 | if (lv1ent_page(ent)) { | |
315 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 316 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 317 | } |
2a96536e KC |
318 | } |
319 | ||
320 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
321 | { | |
f171abab | 322 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 323 | struct sysmmu_drvdata *data = dev_id; |
2a96536e | 324 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 325 | sysmmu_iova_t addr = -1; |
7222e8db | 326 | int ret = -ENOSYS; |
2a96536e | 327 | |
2a96536e KC |
328 | WARN_ON(!is_sysmmu_active(data)); |
329 | ||
9d4e7a24 CK |
330 | spin_lock(&data->lock); |
331 | ||
70605870 CK |
332 | if (!IS_ERR(data->clk_master)) |
333 | clk_enable(data->clk_master); | |
9d4e7a24 | 334 | |
7222e8db CK |
335 | itype = (enum exynos_sysmmu_inttype) |
336 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
337 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 338 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
339 | else |
340 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 341 | |
1fab7fa7 CK |
342 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
343 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
344 | __func__, dev_name(data->sysmmu)); | |
345 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
346 | __func__); | |
347 | BUG(); | |
348 | } else { | |
d09d78fc | 349 | unsigned int base = |
1fab7fa7 CK |
350 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
351 | show_fault_information(dev_name(data->sysmmu), | |
352 | itype, base, addr); | |
353 | if (data->domain) | |
a9133b99 | 354 | ret = report_iommu_fault(&data->domain->domain, |
6b21a5db | 355 | data->master, addr, itype); |
2a96536e KC |
356 | } |
357 | ||
1fab7fa7 CK |
358 | /* fault is not recovered by fault handler */ |
359 | BUG_ON(ret != 0); | |
2a96536e | 360 | |
1fab7fa7 CK |
361 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
362 | ||
363 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 364 | |
70605870 CK |
365 | if (!IS_ERR(data->clk_master)) |
366 | clk_disable(data->clk_master); | |
367 | ||
9d4e7a24 | 368 | spin_unlock(&data->lock); |
2a96536e KC |
369 | |
370 | return IRQ_HANDLED; | |
371 | } | |
372 | ||
6b21a5db | 373 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 374 | { |
70605870 CK |
375 | if (!IS_ERR(data->clk_master)) |
376 | clk_enable(data->clk_master); | |
377 | ||
7222e8db | 378 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 379 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 380 | |
46c16d1e | 381 | clk_disable(data->clk); |
70605870 CK |
382 | if (!IS_ERR(data->clk_master)) |
383 | clk_disable(data->clk_master); | |
2a96536e KC |
384 | } |
385 | ||
6b21a5db | 386 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 387 | { |
6b21a5db | 388 | bool disabled; |
2a96536e KC |
389 | unsigned long flags; |
390 | ||
9d4e7a24 | 391 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 392 | |
6b21a5db CK |
393 | disabled = set_sysmmu_inactive(data); |
394 | ||
395 | if (disabled) { | |
396 | data->pgtable = 0; | |
397 | data->domain = NULL; | |
398 | ||
399 | __sysmmu_disable_nocount(data); | |
2a96536e | 400 | |
6b21a5db CK |
401 | dev_dbg(data->sysmmu, "Disabled\n"); |
402 | } else { | |
403 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
404 | data->activations); | |
2a96536e KC |
405 | } |
406 | ||
6b21a5db CK |
407 | spin_unlock_irqrestore(&data->lock, flags); |
408 | ||
409 | return disabled; | |
410 | } | |
2a96536e | 411 | |
6b21a5db CK |
412 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
413 | { | |
eeb5184b CK |
414 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
415 | unsigned int ver; | |
416 | ||
512bd0c6 | 417 | ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); |
eeb5184b CK |
418 | if (MMU_MAJ_VER(ver) == 3) { |
419 | if (MMU_MIN_VER(ver) >= 2) { | |
420 | cfg |= CFG_FLPDCACHE; | |
421 | if (MMU_MIN_VER(ver) == 3) { | |
422 | cfg |= CFG_ACGEN; | |
423 | cfg &= ~CFG_LRU; | |
424 | } else { | |
425 | cfg |= CFG_SYSSEL; | |
426 | } | |
427 | } | |
428 | } | |
6b21a5db CK |
429 | |
430 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
512bd0c6 | 431 | data->version = ver; |
6b21a5db CK |
432 | } |
433 | ||
434 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
435 | { | |
70605870 CK |
436 | if (!IS_ERR(data->clk_master)) |
437 | clk_enable(data->clk_master); | |
438 | clk_enable(data->clk); | |
439 | ||
6b21a5db CK |
440 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
441 | ||
442 | __sysmmu_init_config(data); | |
443 | ||
444 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 445 | |
7222e8db CK |
446 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
447 | ||
70605870 CK |
448 | if (!IS_ERR(data->clk_master)) |
449 | clk_disable(data->clk_master); | |
6b21a5db | 450 | } |
70605870 | 451 | |
bfa00489 | 452 | static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable, |
a9133b99 | 453 | struct exynos_iommu_domain *domain) |
6b21a5db CK |
454 | { |
455 | int ret = 0; | |
456 | unsigned long flags; | |
457 | ||
458 | spin_lock_irqsave(&data->lock, flags); | |
459 | if (set_sysmmu_active(data)) { | |
460 | data->pgtable = pgtable; | |
a9133b99 | 461 | data->domain = domain; |
6b21a5db CK |
462 | |
463 | __sysmmu_enable_nocount(data); | |
464 | ||
465 | dev_dbg(data->sysmmu, "Enabled\n"); | |
466 | } else { | |
467 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
468 | ||
469 | dev_dbg(data->sysmmu, "already enabled\n"); | |
470 | } | |
471 | ||
472 | if (WARN_ON(ret < 0)) | |
473 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 474 | |
9d4e7a24 | 475 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
476 | |
477 | return ret; | |
478 | } | |
479 | ||
66a7ed84 CK |
480 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
481 | sysmmu_iova_t iova) | |
482 | { | |
512bd0c6 | 483 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
484 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
485 | } | |
486 | ||
469acebe | 487 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
488 | sysmmu_iova_t iova) |
489 | { | |
490 | unsigned long flags; | |
66a7ed84 CK |
491 | |
492 | if (!IS_ERR(data->clk_master)) | |
493 | clk_enable(data->clk_master); | |
494 | ||
495 | spin_lock_irqsave(&data->lock, flags); | |
496 | if (is_sysmmu_active(data)) | |
497 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
498 | spin_unlock_irqrestore(&data->lock, flags); | |
499 | ||
500 | if (!IS_ERR(data->clk_master)) | |
501 | clk_disable(data->clk_master); | |
502 | } | |
503 | ||
469acebe MS |
504 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
505 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
506 | { |
507 | unsigned long flags; | |
2a96536e | 508 | |
6b21a5db | 509 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 510 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 511 | unsigned int num_inv = 1; |
70605870 CK |
512 | |
513 | if (!IS_ERR(data->clk_master)) | |
514 | clk_enable(data->clk_master); | |
515 | ||
3ad6b7f3 CK |
516 | /* |
517 | * L2TLB invalidation required | |
518 | * 4KB page: 1 invalidation | |
f171abab SK |
519 | * 64KB page: 16 invalidations |
520 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
521 | * because it is set-associative TLB |
522 | * with 8-way and 64 sets. | |
523 | * 1MB page can be cached in one of all sets. | |
524 | * 64KB page can be one of 16 consecutive sets. | |
525 | */ | |
512bd0c6 | 526 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
527 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
528 | ||
7222e8db CK |
529 | if (sysmmu_block(data->sfrbase)) { |
530 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 531 | data->sfrbase, iova, num_inv); |
7222e8db | 532 | sysmmu_unblock(data->sfrbase); |
2a96536e | 533 | } |
70605870 CK |
534 | if (!IS_ERR(data->clk_master)) |
535 | clk_disable(data->clk_master); | |
2a96536e | 536 | } else { |
469acebe MS |
537 | dev_dbg(data->master, |
538 | "disabled. Skipping TLB invalidation @ %#x\n", iova); | |
2a96536e | 539 | } |
9d4e7a24 | 540 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
541 | } |
542 | ||
6b21a5db | 543 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 544 | { |
46c16d1e | 545 | int irq, ret; |
7222e8db | 546 | struct device *dev = &pdev->dev; |
2a96536e | 547 | struct sysmmu_drvdata *data; |
7222e8db | 548 | struct resource *res; |
2a96536e | 549 | |
46c16d1e CK |
550 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
551 | if (!data) | |
552 | return -ENOMEM; | |
2a96536e | 553 | |
7222e8db | 554 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
555 | data->sfrbase = devm_ioremap_resource(dev, res); |
556 | if (IS_ERR(data->sfrbase)) | |
557 | return PTR_ERR(data->sfrbase); | |
2a96536e | 558 | |
46c16d1e CK |
559 | irq = platform_get_irq(pdev, 0); |
560 | if (irq <= 0) { | |
0bf4e54d | 561 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 562 | return irq; |
2a96536e KC |
563 | } |
564 | ||
46c16d1e | 565 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
566 | dev_name(dev), data); |
567 | if (ret) { | |
46c16d1e CK |
568 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
569 | return ret; | |
2a96536e KC |
570 | } |
571 | ||
46c16d1e CK |
572 | data->clk = devm_clk_get(dev, "sysmmu"); |
573 | if (IS_ERR(data->clk)) { | |
574 | dev_err(dev, "Failed to get clock!\n"); | |
575 | return PTR_ERR(data->clk); | |
576 | } else { | |
577 | ret = clk_prepare(data->clk); | |
578 | if (ret) { | |
579 | dev_err(dev, "Failed to prepare clk\n"); | |
580 | return ret; | |
581 | } | |
2a96536e KC |
582 | } |
583 | ||
70605870 CK |
584 | data->clk_master = devm_clk_get(dev, "master"); |
585 | if (!IS_ERR(data->clk_master)) { | |
586 | ret = clk_prepare(data->clk_master); | |
587 | if (ret) { | |
588 | clk_unprepare(data->clk); | |
589 | dev_err(dev, "Failed to prepare master's clk\n"); | |
590 | return ret; | |
591 | } | |
592 | } | |
593 | ||
2a96536e | 594 | data->sysmmu = dev; |
9d4e7a24 | 595 | spin_lock_init(&data->lock); |
2a96536e | 596 | |
7222e8db CK |
597 | platform_set_drvdata(pdev, data); |
598 | ||
f4723ec1 | 599 | pm_runtime_enable(dev); |
2a96536e | 600 | |
2a96536e | 601 | return 0; |
2a96536e KC |
602 | } |
603 | ||
622015e4 MS |
604 | #ifdef CONFIG_PM_SLEEP |
605 | static int exynos_sysmmu_suspend(struct device *dev) | |
606 | { | |
607 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
608 | ||
609 | dev_dbg(dev, "suspend\n"); | |
610 | if (is_sysmmu_active(data)) { | |
611 | __sysmmu_disable_nocount(data); | |
612 | pm_runtime_put(dev); | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static int exynos_sysmmu_resume(struct device *dev) | |
618 | { | |
619 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
620 | ||
621 | dev_dbg(dev, "resume\n"); | |
622 | if (is_sysmmu_active(data)) { | |
623 | pm_runtime_get_sync(dev); | |
624 | __sysmmu_enable_nocount(data); | |
625 | } | |
626 | return 0; | |
627 | } | |
628 | #endif | |
629 | ||
630 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
631 | SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume) | |
632 | }; | |
633 | ||
6b21a5db CK |
634 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
635 | { .compatible = "samsung,exynos-sysmmu", }, | |
636 | { }, | |
637 | }; | |
638 | ||
639 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
640 | .probe = exynos_sysmmu_probe, | |
641 | .driver = { | |
2a96536e | 642 | .name = "exynos-sysmmu", |
6b21a5db | 643 | .of_match_table = sysmmu_of_match, |
622015e4 | 644 | .pm = &sysmmu_pm_ops, |
2a96536e KC |
645 | } |
646 | }; | |
647 | ||
648 | static inline void pgtable_flush(void *vastart, void *vaend) | |
649 | { | |
650 | dmac_flush_range(vastart, vaend); | |
651 | outer_flush_range(virt_to_phys(vastart), | |
652 | virt_to_phys(vaend)); | |
653 | } | |
654 | ||
e1fd1eaa | 655 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 656 | { |
bfa00489 | 657 | struct exynos_iommu_domain *domain; |
66a7ed84 | 658 | int i; |
2a96536e | 659 | |
e1fd1eaa JR |
660 | if (type != IOMMU_DOMAIN_UNMANAGED) |
661 | return NULL; | |
662 | ||
bfa00489 MS |
663 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
664 | if (!domain) | |
e1fd1eaa | 665 | return NULL; |
2a96536e | 666 | |
bfa00489 MS |
667 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
668 | if (!domain->pgtable) | |
2a96536e KC |
669 | goto err_pgtable; |
670 | ||
bfa00489 MS |
671 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
672 | if (!domain->lv2entcnt) | |
2a96536e KC |
673 | goto err_counter; |
674 | ||
f171abab | 675 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 676 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
677 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
678 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
679 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
680 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
681 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
682 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
683 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
684 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
685 | } |
686 | ||
bfa00489 | 687 | pgtable_flush(domain->pgtable, domain->pgtable + NUM_LV1ENTRIES); |
2a96536e | 688 | |
bfa00489 MS |
689 | spin_lock_init(&domain->lock); |
690 | spin_lock_init(&domain->pgtablelock); | |
691 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 692 | |
bfa00489 MS |
693 | domain->domain.geometry.aperture_start = 0; |
694 | domain->domain.geometry.aperture_end = ~0UL; | |
695 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 696 | |
bfa00489 | 697 | return &domain->domain; |
2a96536e KC |
698 | |
699 | err_counter: | |
bfa00489 | 700 | free_pages((unsigned long)domain->pgtable, 2); |
2a96536e | 701 | err_pgtable: |
bfa00489 | 702 | kfree(domain); |
e1fd1eaa | 703 | return NULL; |
2a96536e KC |
704 | } |
705 | ||
bfa00489 | 706 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 707 | { |
bfa00489 | 708 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 709 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
710 | unsigned long flags; |
711 | int i; | |
712 | ||
bfa00489 | 713 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 714 | |
bfa00489 | 715 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 716 | |
bfa00489 | 717 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
718 | if (__sysmmu_disable(data)) |
719 | data->master = NULL; | |
720 | list_del_init(&data->domain_node); | |
2a96536e KC |
721 | } |
722 | ||
bfa00489 | 723 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e KC |
724 | |
725 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
bfa00489 | 726 | if (lv1ent_page(domain->pgtable + i)) |
734c3c73 | 727 | kmem_cache_free(lv2table_kmem_cache, |
bfa00489 | 728 | phys_to_virt(lv2table_base(domain->pgtable + i))); |
2a96536e | 729 | |
bfa00489 MS |
730 | free_pages((unsigned long)domain->pgtable, 2); |
731 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
732 | kfree(domain); | |
2a96536e KC |
733 | } |
734 | ||
bfa00489 | 735 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
736 | struct device *dev) |
737 | { | |
6b21a5db | 738 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 739 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 740 | struct sysmmu_drvdata *data; |
bfa00489 | 741 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 742 | unsigned long flags; |
469acebe | 743 | int ret = -ENODEV; |
2a96536e | 744 | |
469acebe MS |
745 | if (!has_sysmmu(dev)) |
746 | return -ENODEV; | |
2a96536e | 747 | |
1b092054 | 748 | list_for_each_entry(data, &owner->controllers, owner_node) { |
ce70ca56 | 749 | pm_runtime_get_sync(data->sysmmu); |
a9133b99 | 750 | ret = __sysmmu_enable(data, pagetable, domain); |
469acebe MS |
751 | if (ret >= 0) { |
752 | data->master = dev; | |
753 | ||
bfa00489 MS |
754 | spin_lock_irqsave(&domain->lock, flags); |
755 | list_add_tail(&data->domain_node, &domain->clients); | |
756 | spin_unlock_irqrestore(&domain->lock, flags); | |
469acebe MS |
757 | } |
758 | } | |
2a96536e KC |
759 | |
760 | if (ret < 0) { | |
7222e8db CK |
761 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
762 | __func__, &pagetable); | |
7222e8db | 763 | return ret; |
2a96536e KC |
764 | } |
765 | ||
7222e8db CK |
766 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
767 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
768 | ||
2a96536e KC |
769 | return ret; |
770 | } | |
771 | ||
bfa00489 | 772 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
773 | struct device *dev) |
774 | { | |
bfa00489 MS |
775 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
776 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
1b092054 | 777 | struct sysmmu_drvdata *data, *next; |
2a96536e | 778 | unsigned long flags; |
469acebe | 779 | bool found = false; |
2a96536e | 780 | |
469acebe MS |
781 | if (!has_sysmmu(dev)) |
782 | return; | |
2a96536e | 783 | |
bfa00489 | 784 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 785 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
786 | if (data->master == dev) { |
787 | if (__sysmmu_disable(data)) { | |
788 | data->master = NULL; | |
789 | list_del_init(&data->domain_node); | |
790 | } | |
ce70ca56 | 791 | pm_runtime_put(data->sysmmu); |
469acebe | 792 | found = true; |
2a96536e KC |
793 | } |
794 | } | |
bfa00489 | 795 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 796 | |
469acebe | 797 | if (found) |
7222e8db CK |
798 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
799 | __func__, &pagetable); | |
6b21a5db CK |
800 | else |
801 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
802 | } |
803 | ||
bfa00489 | 804 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 805 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 806 | { |
61128f08 | 807 | if (lv1ent_section(sent)) { |
d09d78fc | 808 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
809 | return ERR_PTR(-EADDRINUSE); |
810 | } | |
811 | ||
2a96536e | 812 | if (lv1ent_fault(sent)) { |
d09d78fc | 813 | sysmmu_pte_t *pent; |
66a7ed84 | 814 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 815 | |
734c3c73 | 816 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 817 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 818 | if (!pent) |
61128f08 | 819 | return ERR_PTR(-ENOMEM); |
2a96536e | 820 | |
7222e8db | 821 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
dc3814f4 | 822 | kmemleak_ignore(pent); |
2a96536e KC |
823 | *pgcounter = NUM_LV2ENTRIES; |
824 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
825 | pgtable_flush(sent, sent + 1); | |
66a7ed84 CK |
826 | |
827 | /* | |
f171abab SK |
828 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
829 | * FLPD cache may cache the address of zero_l2_table. This | |
830 | * function replaces the zero_l2_table with new L2 page table | |
831 | * to write valid mappings. | |
66a7ed84 | 832 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
833 | * cache may still cache zero_l2_table for the valid area |
834 | * instead of new L2 page table that has the mapping | |
835 | * information of the valid area. | |
66a7ed84 CK |
836 | * Thus any replacement of zero_l2_table with other valid L2 |
837 | * page table must involve FLPD cache invalidation for System | |
838 | * MMU v3.3. | |
839 | * FLPD cache invalidation is performed with TLB invalidation | |
840 | * by VPN without blocking. It is safe to invalidate TLB without | |
841 | * blocking because the target address of TLB invalidation is | |
842 | * not currently mapped. | |
843 | */ | |
844 | if (need_flush_flpd_cache) { | |
469acebe | 845 | struct sysmmu_drvdata *data; |
365409db | 846 | |
bfa00489 MS |
847 | spin_lock(&domain->lock); |
848 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 849 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 850 | spin_unlock(&domain->lock); |
66a7ed84 | 851 | } |
2a96536e KC |
852 | } |
853 | ||
854 | return page_entry(sent, iova); | |
855 | } | |
856 | ||
bfa00489 | 857 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 858 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 859 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 860 | { |
61128f08 | 861 | if (lv1ent_section(sent)) { |
d09d78fc | 862 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 863 | iova); |
2a96536e | 864 | return -EADDRINUSE; |
61128f08 | 865 | } |
2a96536e KC |
866 | |
867 | if (lv1ent_page(sent)) { | |
61128f08 | 868 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 869 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 870 | iova); |
2a96536e | 871 | return -EADDRINUSE; |
61128f08 | 872 | } |
2a96536e | 873 | |
734c3c73 | 874 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
875 | *pgcnt = 0; |
876 | } | |
877 | ||
878 | *sent = mk_lv1ent_sect(paddr); | |
879 | ||
880 | pgtable_flush(sent, sent + 1); | |
881 | ||
bfa00489 | 882 | spin_lock(&domain->lock); |
66a7ed84 | 883 | if (lv1ent_page_zero(sent)) { |
469acebe | 884 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
885 | /* |
886 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
887 | * entry by speculative prefetch of SLPD which has no mapping. | |
888 | */ | |
bfa00489 | 889 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 890 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 891 | } |
bfa00489 | 892 | spin_unlock(&domain->lock); |
66a7ed84 | 893 | |
2a96536e KC |
894 | return 0; |
895 | } | |
896 | ||
d09d78fc | 897 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
898 | short *pgcnt) |
899 | { | |
900 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 901 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
902 | return -EADDRINUSE; |
903 | ||
904 | *pent = mk_lv2ent_spage(paddr); | |
905 | pgtable_flush(pent, pent + 1); | |
906 | *pgcnt -= 1; | |
907 | } else { /* size == LPAGE_SIZE */ | |
908 | int i; | |
365409db | 909 | |
2a96536e | 910 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 911 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
912 | if (i > 0) |
913 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
914 | return -EADDRINUSE; |
915 | } | |
916 | ||
917 | *pent = mk_lv2ent_lpage(paddr); | |
918 | } | |
919 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
920 | *pgcnt -= SPAGES_PER_LPAGE; | |
921 | } | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
66a7ed84 CK |
926 | /* |
927 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
928 | * | |
f171abab | 929 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 930 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
931 | * However, the logic has a bug that while caching faulty page table entries, |
932 | * System MMU reports page fault if the cached fault entry is hit even though | |
933 | * the fault entry is updated to a valid entry after the entry is cached. | |
934 | * To prevent caching faulty page table entries which may be updated to valid | |
935 | * entries later, the virtual memory manager should care about the workaround | |
936 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
937 | * |
938 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 939 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 940 | * |
f171abab | 941 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
942 | * the following sizes for System MMU v3.1 and v3.2. |
943 | * System MMU v3.1: 128KiB | |
944 | * System MMU v3.2: 256KiB | |
945 | * | |
946 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
947 | * more workarounds. |
948 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
949 | * than or equal to 128KiB. | |
66a7ed84 CK |
950 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
951 | */ | |
bfa00489 MS |
952 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
953 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
954 | int prot) | |
2a96536e | 955 | { |
bfa00489 | 956 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
957 | sysmmu_pte_t *entry; |
958 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
959 | unsigned long flags; |
960 | int ret = -ENOMEM; | |
961 | ||
bfa00489 | 962 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 963 | |
bfa00489 | 964 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 965 | |
bfa00489 | 966 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
967 | |
968 | if (size == SECT_SIZE) { | |
bfa00489 MS |
969 | ret = lv1set_section(domain, entry, iova, paddr, |
970 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 971 | } else { |
d09d78fc | 972 | sysmmu_pte_t *pent; |
2a96536e | 973 | |
bfa00489 MS |
974 | pent = alloc_lv2entry(domain, entry, iova, |
975 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 976 | |
61128f08 CK |
977 | if (IS_ERR(pent)) |
978 | ret = PTR_ERR(pent); | |
2a96536e KC |
979 | else |
980 | ret = lv2set_page(pent, paddr, size, | |
bfa00489 | 981 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
982 | } |
983 | ||
61128f08 | 984 | if (ret) |
0bf4e54d CK |
985 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
986 | __func__, ret, size, iova); | |
2a96536e | 987 | |
bfa00489 | 988 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
989 | |
990 | return ret; | |
991 | } | |
992 | ||
bfa00489 MS |
993 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
994 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 995 | { |
469acebe | 996 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
997 | unsigned long flags; |
998 | ||
bfa00489 | 999 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1000 | |
bfa00489 | 1001 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1002 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1003 | |
bfa00489 | 1004 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1005 | } |
1006 | ||
bfa00489 MS |
1007 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1008 | unsigned long l_iova, size_t size) | |
2a96536e | 1009 | { |
bfa00489 | 1010 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1011 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1012 | sysmmu_pte_t *ent; | |
61128f08 | 1013 | size_t err_pgsize; |
d09d78fc | 1014 | unsigned long flags; |
2a96536e | 1015 | |
bfa00489 | 1016 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1017 | |
bfa00489 | 1018 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1019 | |
bfa00489 | 1020 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1021 | |
1022 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1023 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1024 | err_pgsize = SECT_SIZE; |
1025 | goto err; | |
1026 | } | |
2a96536e | 1027 | |
f171abab SK |
1028 | /* workaround for h/w bug in System MMU v3.3 */ |
1029 | *ent = ZERO_LV2LINK; | |
2a96536e KC |
1030 | pgtable_flush(ent, ent + 1); |
1031 | size = SECT_SIZE; | |
1032 | goto done; | |
1033 | } | |
1034 | ||
1035 | if (unlikely(lv1ent_fault(ent))) { | |
1036 | if (size > SECT_SIZE) | |
1037 | size = SECT_SIZE; | |
1038 | goto done; | |
1039 | } | |
1040 | ||
1041 | /* lv1ent_page(sent) == true here */ | |
1042 | ||
1043 | ent = page_entry(ent, iova); | |
1044 | ||
1045 | if (unlikely(lv2ent_fault(ent))) { | |
1046 | size = SPAGE_SIZE; | |
1047 | goto done; | |
1048 | } | |
1049 | ||
1050 | if (lv2ent_small(ent)) { | |
1051 | *ent = 0; | |
1052 | size = SPAGE_SIZE; | |
6cb47ed7 | 1053 | pgtable_flush(ent, ent + 1); |
bfa00489 | 1054 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1055 | goto done; |
1056 | } | |
1057 | ||
1058 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1059 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1060 | err_pgsize = LPAGE_SIZE; |
1061 | goto err; | |
1062 | } | |
2a96536e KC |
1063 | |
1064 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 1065 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
1066 | |
1067 | size = LPAGE_SIZE; | |
bfa00489 | 1068 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1069 | done: |
bfa00489 | 1070 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1071 | |
bfa00489 | 1072 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1073 | |
2a96536e | 1074 | return size; |
61128f08 | 1075 | err: |
bfa00489 | 1076 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1077 | |
0bf4e54d CK |
1078 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1079 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1080 | |
1081 | return 0; | |
2a96536e KC |
1082 | } |
1083 | ||
bfa00489 | 1084 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1085 | dma_addr_t iova) |
2a96536e | 1086 | { |
bfa00489 | 1087 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1088 | sysmmu_pte_t *entry; |
2a96536e KC |
1089 | unsigned long flags; |
1090 | phys_addr_t phys = 0; | |
1091 | ||
bfa00489 | 1092 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1093 | |
bfa00489 | 1094 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1095 | |
1096 | if (lv1ent_section(entry)) { | |
1097 | phys = section_phys(entry) + section_offs(iova); | |
1098 | } else if (lv1ent_page(entry)) { | |
1099 | entry = page_entry(entry, iova); | |
1100 | ||
1101 | if (lv2ent_large(entry)) | |
1102 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1103 | else if (lv2ent_small(entry)) | |
1104 | phys = spage_phys(entry) + spage_offs(iova); | |
1105 | } | |
1106 | ||
bfa00489 | 1107 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1108 | |
1109 | return phys; | |
1110 | } | |
1111 | ||
bf4a1c92 AM |
1112 | static int exynos_iommu_add_device(struct device *dev) |
1113 | { | |
1114 | struct iommu_group *group; | |
1115 | int ret; | |
1116 | ||
06801db0 MS |
1117 | if (!has_sysmmu(dev)) |
1118 | return -ENODEV; | |
1119 | ||
bf4a1c92 AM |
1120 | group = iommu_group_get(dev); |
1121 | ||
1122 | if (!group) { | |
1123 | group = iommu_group_alloc(); | |
1124 | if (IS_ERR(group)) { | |
1125 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1126 | return PTR_ERR(group); | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | ret = iommu_group_add_device(group, dev); | |
1131 | iommu_group_put(group); | |
1132 | ||
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | static void exynos_iommu_remove_device(struct device *dev) | |
1137 | { | |
06801db0 MS |
1138 | if (!has_sysmmu(dev)) |
1139 | return; | |
1140 | ||
bf4a1c92 AM |
1141 | iommu_group_remove_device(dev); |
1142 | } | |
1143 | ||
b22f6434 | 1144 | static const struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1145 | .domain_alloc = exynos_iommu_domain_alloc, |
1146 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1147 | .attach_dev = exynos_iommu_attach_device, |
1148 | .detach_dev = exynos_iommu_detach_device, | |
1149 | .map = exynos_iommu_map, | |
1150 | .unmap = exynos_iommu_unmap, | |
315786eb | 1151 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 BH |
1152 | .iova_to_phys = exynos_iommu_iova_to_phys, |
1153 | .add_device = exynos_iommu_add_device, | |
1154 | .remove_device = exynos_iommu_remove_device, | |
2a96536e KC |
1155 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
1156 | }; | |
1157 | ||
1158 | static int __init exynos_iommu_init(void) | |
1159 | { | |
a7b67cd5 | 1160 | struct device_node *np; |
2a96536e KC |
1161 | int ret; |
1162 | ||
a7b67cd5 TR |
1163 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1164 | if (!np) | |
1165 | return 0; | |
1166 | ||
1167 | of_node_put(np); | |
1168 | ||
734c3c73 CK |
1169 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1170 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1171 | if (!lv2table_kmem_cache) { | |
1172 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1173 | return -ENOMEM; | |
1174 | } | |
1175 | ||
2a96536e | 1176 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1177 | if (ret) { |
1178 | pr_err("%s: Failed to register driver\n", __func__); | |
1179 | goto err_reg_driver; | |
1180 | } | |
2a96536e | 1181 | |
66a7ed84 CK |
1182 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1183 | if (zero_lv2_table == NULL) { | |
1184 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1185 | __func__); | |
1186 | ret = -ENOMEM; | |
1187 | goto err_zero_lv2; | |
1188 | } | |
1189 | ||
734c3c73 CK |
1190 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1191 | if (ret) { | |
1192 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1193 | __func__); | |
1194 | goto err_set_iommu; | |
1195 | } | |
2a96536e | 1196 | |
734c3c73 CK |
1197 | return 0; |
1198 | err_set_iommu: | |
66a7ed84 CK |
1199 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1200 | err_zero_lv2: | |
734c3c73 CK |
1201 | platform_driver_unregister(&exynos_sysmmu_driver); |
1202 | err_reg_driver: | |
1203 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1204 | return ret; |
1205 | } | |
1206 | subsys_initcall(exynos_iommu_init); |