Commit | Line | Data |
---|---|---|
2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
2a96536e KC |
32 | /* We does not consider super section mapping (16MB) */ |
33 | #define SECT_ORDER 20 | |
34 | #define LPAGE_ORDER 16 | |
35 | #define SPAGE_ORDER 12 | |
36 | ||
37 | #define SECT_SIZE (1 << SECT_ORDER) | |
38 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
39 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
40 | ||
41 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
42 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
43 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
44 | ||
45 | #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
46 | #define lv1ent_page(sent) ((*(sent) & 3) == 1) | |
47 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) | |
48 | ||
49 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
50 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
51 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
52 | ||
53 | #define section_phys(sent) (*(sent) & SECT_MASK) | |
54 | #define section_offs(iova) ((iova) & 0xFFFFF) | |
55 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) | |
56 | #define lpage_offs(iova) ((iova) & 0xFFFF) | |
57 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) | |
58 | #define spage_offs(iova) ((iova) & 0xFFF) | |
59 | ||
60 | #define lv1ent_offset(iova) ((iova) >> SECT_ORDER) | |
61 | #define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER) | |
62 | ||
63 | #define NUM_LV1ENTRIES 4096 | |
64 | #define NUM_LV2ENTRIES 256 | |
65 | ||
66 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long)) | |
67 | ||
68 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
69 | ||
70 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
71 | ||
72 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
73 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
74 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
75 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
76 | ||
77 | #define CTRL_ENABLE 0x5 | |
78 | #define CTRL_BLOCK 0x7 | |
79 | #define CTRL_DISABLE 0x0 | |
80 | ||
81 | #define REG_MMU_CTRL 0x000 | |
82 | #define REG_MMU_CFG 0x004 | |
83 | #define REG_MMU_STATUS 0x008 | |
84 | #define REG_MMU_FLUSH 0x00C | |
85 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
86 | #define REG_PT_BASE_ADDR 0x014 | |
87 | #define REG_INT_STATUS 0x018 | |
88 | #define REG_INT_CLEAR 0x01C | |
89 | ||
90 | #define REG_PAGE_FAULT_ADDR 0x024 | |
91 | #define REG_AW_FAULT_ADDR 0x028 | |
92 | #define REG_AR_FAULT_ADDR 0x02C | |
93 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
94 | ||
95 | #define REG_MMU_VERSION 0x034 | |
96 | ||
97 | #define REG_PB0_SADDR 0x04C | |
98 | #define REG_PB0_EADDR 0x050 | |
99 | #define REG_PB1_SADDR 0x054 | |
100 | #define REG_PB1_EADDR 0x058 | |
101 | ||
734c3c73 CK |
102 | static struct kmem_cache *lv2table_kmem_cache; |
103 | ||
2a96536e KC |
104 | static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova) |
105 | { | |
106 | return pgtable + lv1ent_offset(iova); | |
107 | } | |
108 | ||
109 | static unsigned long *page_entry(unsigned long *sent, unsigned long iova) | |
110 | { | |
7222e8db CK |
111 | return (unsigned long *)phys_to_virt( |
112 | lv2table_base(sent)) + lv2ent_offset(iova); | |
2a96536e KC |
113 | } |
114 | ||
115 | enum exynos_sysmmu_inttype { | |
116 | SYSMMU_PAGEFAULT, | |
117 | SYSMMU_AR_MULTIHIT, | |
118 | SYSMMU_AW_MULTIHIT, | |
119 | SYSMMU_BUSERROR, | |
120 | SYSMMU_AR_SECURITY, | |
121 | SYSMMU_AR_ACCESS, | |
122 | SYSMMU_AW_SECURITY, | |
123 | SYSMMU_AW_PROTECTION, /* 7 */ | |
124 | SYSMMU_FAULT_UNKNOWN, | |
125 | SYSMMU_FAULTS_NUM | |
126 | }; | |
127 | ||
128 | /* | |
129 | * @itype: type of fault. | |
130 | * @pgtable_base: the physical address of page table base. This is 0 if @itype | |
131 | * is SYSMMU_BUSERROR. | |
132 | * @fault_addr: the device (virtual) address that the System MMU tried to | |
133 | * translated. This is 0 if @itype is SYSMMU_BUSERROR. | |
134 | */ | |
135 | typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype, | |
7222e8db | 136 | phys_addr_t pgtable_base, unsigned long fault_addr); |
2a96536e KC |
137 | |
138 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { | |
139 | REG_PAGE_FAULT_ADDR, | |
140 | REG_AR_FAULT_ADDR, | |
141 | REG_AW_FAULT_ADDR, | |
142 | REG_DEFAULT_SLAVE_ADDR, | |
143 | REG_AR_FAULT_ADDR, | |
144 | REG_AR_FAULT_ADDR, | |
145 | REG_AW_FAULT_ADDR, | |
146 | REG_AW_FAULT_ADDR | |
147 | }; | |
148 | ||
149 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
150 | "PAGE FAULT", | |
151 | "AR MULTI-HIT FAULT", | |
152 | "AW MULTI-HIT FAULT", | |
153 | "BUS ERROR", | |
154 | "AR SECURITY PROTECTION FAULT", | |
155 | "AR ACCESS PROTECTION FAULT", | |
156 | "AW SECURITY PROTECTION FAULT", | |
157 | "AW ACCESS PROTECTION FAULT", | |
158 | "UNKNOWN FAULT" | |
159 | }; | |
160 | ||
161 | struct exynos_iommu_domain { | |
162 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
163 | unsigned long *pgtable; /* lv1 page table, 16KB */ | |
164 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
165 | spinlock_t lock; /* lock for this structure */ | |
166 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
167 | }; | |
168 | ||
169 | struct sysmmu_drvdata { | |
170 | struct list_head node; /* entry of exynos_iommu_domain.clients */ | |
171 | struct device *sysmmu; /* System MMU's device descriptor */ | |
172 | struct device *dev; /* Owner of system MMU */ | |
173 | char *dbgname; | |
7222e8db CK |
174 | void __iomem *sfrbase; |
175 | struct clk *clk; | |
2a96536e KC |
176 | int activations; |
177 | rwlock_t lock; | |
178 | struct iommu_domain *domain; | |
179 | sysmmu_fault_handler_t fault_handler; | |
7222e8db | 180 | phys_addr_t pgtable; |
2a96536e KC |
181 | }; |
182 | ||
183 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) | |
184 | { | |
185 | /* return true if the System MMU was not active previously | |
186 | and it needs to be initialized */ | |
187 | return ++data->activations == 1; | |
188 | } | |
189 | ||
190 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
191 | { | |
192 | /* return true if the System MMU is needed to be disabled */ | |
193 | BUG_ON(data->activations < 1); | |
194 | return --data->activations == 0; | |
195 | } | |
196 | ||
197 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
198 | { | |
199 | return data->activations > 0; | |
200 | } | |
201 | ||
202 | static void sysmmu_unblock(void __iomem *sfrbase) | |
203 | { | |
204 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
205 | } | |
206 | ||
207 | static bool sysmmu_block(void __iomem *sfrbase) | |
208 | { | |
209 | int i = 120; | |
210 | ||
211 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
212 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
213 | --i; | |
214 | ||
215 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
216 | sysmmu_unblock(sfrbase); | |
217 | return false; | |
218 | } | |
219 | ||
220 | return true; | |
221 | } | |
222 | ||
223 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
224 | { | |
225 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
226 | } | |
227 | ||
228 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
229 | unsigned long iova) | |
230 | { | |
231 | __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY); | |
232 | } | |
233 | ||
234 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
235 | unsigned long pgd) | |
236 | { | |
237 | __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */ | |
238 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); | |
239 | ||
240 | __sysmmu_tlb_invalidate(sfrbase); | |
241 | } | |
242 | ||
243 | static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base, | |
244 | unsigned long size, int idx) | |
245 | { | |
246 | __raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8); | |
247 | __raw_writel(size - 1 + base, sfrbase + REG_PB0_EADDR + idx * 8); | |
248 | } | |
249 | ||
2a96536e KC |
250 | static void __set_fault_handler(struct sysmmu_drvdata *data, |
251 | sysmmu_fault_handler_t handler) | |
252 | { | |
253 | unsigned long flags; | |
254 | ||
255 | write_lock_irqsave(&data->lock, flags); | |
256 | data->fault_handler = handler; | |
257 | write_unlock_irqrestore(&data->lock, flags); | |
258 | } | |
259 | ||
260 | void exynos_sysmmu_set_fault_handler(struct device *dev, | |
261 | sysmmu_fault_handler_t handler) | |
262 | { | |
263 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
264 | ||
265 | __set_fault_handler(data, handler); | |
266 | } | |
267 | ||
268 | static int default_fault_handler(enum exynos_sysmmu_inttype itype, | |
7222e8db | 269 | phys_addr_t pgtable_base, unsigned long fault_addr) |
2a96536e KC |
270 | { |
271 | unsigned long *ent; | |
272 | ||
273 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
274 | itype = SYSMMU_FAULT_UNKNOWN; | |
275 | ||
7222e8db CK |
276 | pr_err("%s occurred at 0x%lx(Page table base: %pa)\n", |
277 | sysmmu_fault_name[itype], fault_addr, &pgtable_base); | |
2a96536e | 278 | |
7222e8db | 279 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
2a96536e KC |
280 | pr_err("\tLv1 entry: 0x%lx\n", *ent); |
281 | ||
282 | if (lv1ent_page(ent)) { | |
283 | ent = page_entry(ent, fault_addr); | |
284 | pr_err("\t Lv2 entry: 0x%lx\n", *ent); | |
285 | } | |
286 | ||
287 | pr_err("Generating Kernel OOPS... because it is unrecoverable.\n"); | |
288 | ||
289 | BUG(); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
295 | { | |
296 | /* SYSMMU is in blocked when interrupt occurred. */ | |
297 | struct sysmmu_drvdata *data = dev_id; | |
2a96536e KC |
298 | enum exynos_sysmmu_inttype itype; |
299 | unsigned long addr = -1; | |
7222e8db | 300 | int ret = -ENOSYS; |
2a96536e KC |
301 | |
302 | read_lock(&data->lock); | |
303 | ||
304 | WARN_ON(!is_sysmmu_active(data)); | |
305 | ||
7222e8db CK |
306 | itype = (enum exynos_sysmmu_inttype) |
307 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
308 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 309 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
310 | else |
311 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e KC |
312 | |
313 | if (data->domain) | |
7222e8db | 314 | ret = report_iommu_fault(data->domain, data->dev, addr, itype); |
2a96536e KC |
315 | |
316 | if ((ret == -ENOSYS) && data->fault_handler) { | |
317 | unsigned long base = data->pgtable; | |
318 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 319 | base = __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
2a96536e KC |
320 | ret = data->fault_handler(itype, base, addr); |
321 | } | |
322 | ||
323 | if (!ret && (itype != SYSMMU_FAULT_UNKNOWN)) | |
7222e8db | 324 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
2a96536e KC |
325 | else |
326 | dev_dbg(data->sysmmu, "(%s) %s is not handled.\n", | |
327 | data->dbgname, sysmmu_fault_name[itype]); | |
328 | ||
329 | if (itype != SYSMMU_FAULT_UNKNOWN) | |
7222e8db | 330 | sysmmu_unblock(data->sfrbase); |
2a96536e KC |
331 | |
332 | read_unlock(&data->lock); | |
333 | ||
334 | return IRQ_HANDLED; | |
335 | } | |
336 | ||
337 | static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data) | |
338 | { | |
339 | unsigned long flags; | |
340 | bool disabled = false; | |
2a96536e KC |
341 | |
342 | write_lock_irqsave(&data->lock, flags); | |
343 | ||
344 | if (!set_sysmmu_inactive(data)) | |
345 | goto finish; | |
346 | ||
7222e8db | 347 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e | 348 | |
7222e8db CK |
349 | if (!IS_ERR(data->clk)) |
350 | clk_disable(data->clk); | |
2a96536e KC |
351 | |
352 | disabled = true; | |
353 | data->pgtable = 0; | |
354 | data->domain = NULL; | |
355 | finish: | |
356 | write_unlock_irqrestore(&data->lock, flags); | |
357 | ||
358 | if (disabled) | |
359 | dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname); | |
360 | else | |
361 | dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n", | |
362 | data->dbgname, data->activations); | |
363 | ||
364 | return disabled; | |
365 | } | |
366 | ||
367 | /* __exynos_sysmmu_enable: Enables System MMU | |
368 | * | |
369 | * returns -error if an error occurred and System MMU is not enabled, | |
370 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
371 | * enabled before. | |
372 | */ | |
373 | static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data, | |
374 | unsigned long pgtable, struct iommu_domain *domain) | |
375 | { | |
7222e8db | 376 | int ret = 0; |
2a96536e KC |
377 | unsigned long flags; |
378 | ||
379 | write_lock_irqsave(&data->lock, flags); | |
380 | ||
381 | if (!set_sysmmu_active(data)) { | |
382 | if (WARN_ON(pgtable != data->pgtable)) { | |
383 | ret = -EBUSY; | |
384 | set_sysmmu_inactive(data); | |
385 | } else { | |
386 | ret = 1; | |
387 | } | |
388 | ||
389 | dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname); | |
390 | goto finish; | |
391 | } | |
392 | ||
7222e8db CK |
393 | if (!IS_ERR(data->clk)) |
394 | clk_enable(data->clk); | |
2a96536e KC |
395 | |
396 | data->pgtable = pgtable; | |
397 | ||
7222e8db CK |
398 | __sysmmu_set_ptbase(data->sfrbase, pgtable); |
399 | if ((readl(data->sfrbase + REG_MMU_VERSION) >> 28) == 3) { | |
400 | /* System MMU version is 3.x */ | |
401 | __raw_writel((1 << 12) | (2 << 28), | |
402 | data->sfrbase + REG_MMU_CFG); | |
403 | __sysmmu_set_prefbuf(data->sfrbase, 0, -1, 0); | |
404 | __sysmmu_set_prefbuf(data->sfrbase, 0, -1, 1); | |
2a96536e KC |
405 | } |
406 | ||
7222e8db CK |
407 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
408 | ||
2a96536e KC |
409 | data->domain = domain; |
410 | ||
411 | dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname); | |
412 | finish: | |
413 | write_unlock_irqrestore(&data->lock, flags); | |
414 | ||
415 | return ret; | |
416 | } | |
417 | ||
418 | int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable) | |
419 | { | |
420 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
421 | int ret; | |
422 | ||
423 | BUG_ON(!memblock_is_memory(pgtable)); | |
424 | ||
425 | ret = pm_runtime_get_sync(data->sysmmu); | |
426 | if (ret < 0) { | |
427 | dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname); | |
428 | return ret; | |
429 | } | |
430 | ||
431 | ret = __exynos_sysmmu_enable(data, pgtable, NULL); | |
432 | if (WARN_ON(ret < 0)) { | |
433 | pm_runtime_put(data->sysmmu); | |
434 | dev_err(data->sysmmu, | |
7222e8db | 435 | "(%s) Already enabled with page table %#x\n", |
2a96536e KC |
436 | data->dbgname, data->pgtable); |
437 | } else { | |
438 | data->dev = dev; | |
439 | } | |
440 | ||
441 | return ret; | |
442 | } | |
443 | ||
77e38350 | 444 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e KC |
445 | { |
446 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
447 | bool disabled; | |
448 | ||
449 | disabled = __exynos_sysmmu_disable(data); | |
450 | pm_runtime_put(data->sysmmu); | |
451 | ||
452 | return disabled; | |
453 | } | |
454 | ||
455 | static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova) | |
456 | { | |
457 | unsigned long flags; | |
458 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
459 | ||
460 | read_lock_irqsave(&data->lock, flags); | |
461 | ||
462 | if (is_sysmmu_active(data)) { | |
7222e8db CK |
463 | if (sysmmu_block(data->sfrbase)) { |
464 | __sysmmu_tlb_invalidate_entry( | |
465 | data->sfrbase, iova); | |
466 | sysmmu_unblock(data->sfrbase); | |
2a96536e KC |
467 | } |
468 | } else { | |
469 | dev_dbg(data->sysmmu, | |
470 | "(%s) Disabled. Skipping invalidating TLB.\n", | |
471 | data->dbgname); | |
472 | } | |
473 | ||
474 | read_unlock_irqrestore(&data->lock, flags); | |
475 | } | |
476 | ||
477 | void exynos_sysmmu_tlb_invalidate(struct device *dev) | |
478 | { | |
479 | unsigned long flags; | |
480 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
481 | ||
482 | read_lock_irqsave(&data->lock, flags); | |
483 | ||
484 | if (is_sysmmu_active(data)) { | |
7222e8db CK |
485 | if (sysmmu_block(data->sfrbase)) { |
486 | __sysmmu_tlb_invalidate(data->sfrbase); | |
487 | sysmmu_unblock(data->sfrbase); | |
2a96536e KC |
488 | } |
489 | } else { | |
490 | dev_dbg(data->sysmmu, | |
491 | "(%s) Disabled. Skipping invalidating TLB.\n", | |
492 | data->dbgname); | |
493 | } | |
494 | ||
495 | read_unlock_irqrestore(&data->lock, flags); | |
496 | } | |
497 | ||
498 | static int exynos_sysmmu_probe(struct platform_device *pdev) | |
499 | { | |
7222e8db CK |
500 | int ret; |
501 | struct device *dev = &pdev->dev; | |
2a96536e | 502 | struct sysmmu_drvdata *data; |
7222e8db | 503 | struct resource *res; |
2a96536e KC |
504 | |
505 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
506 | if (!data) { | |
507 | dev_dbg(dev, "Not enough memory\n"); | |
508 | ret = -ENOMEM; | |
509 | goto err_alloc; | |
510 | } | |
511 | ||
7222e8db CK |
512 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
513 | if (!res) { | |
514 | dev_dbg(dev, "Unable to find IOMEM region\n"); | |
515 | ret = -ENOENT; | |
2a96536e KC |
516 | goto err_init; |
517 | } | |
518 | ||
7222e8db CK |
519 | data->sfrbase = ioremap(res->start, resource_size(res)); |
520 | if (!data->sfrbase) { | |
521 | dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n", res->start); | |
522 | ret = -ENOENT; | |
523 | goto err_res; | |
2a96536e KC |
524 | } |
525 | ||
7222e8db CK |
526 | ret = platform_get_irq(pdev, 0); |
527 | if (ret <= 0) { | |
528 | dev_dbg(dev, "Unable to find IRQ resource\n"); | |
529 | goto err_irq; | |
2a96536e KC |
530 | } |
531 | ||
7222e8db CK |
532 | ret = request_irq(ret, exynos_sysmmu_irq, 0, |
533 | dev_name(dev), data); | |
534 | if (ret) { | |
535 | dev_dbg(dev, "Unabled to register interrupt handler\n"); | |
536 | goto err_irq; | |
2a96536e KC |
537 | } |
538 | ||
539 | if (dev_get_platdata(dev)) { | |
7222e8db CK |
540 | data->clk = clk_get(dev, "sysmmu"); |
541 | if (IS_ERR(data->clk)) | |
2a96536e | 542 | dev_dbg(dev, "No clock descriptor registered\n"); |
2a96536e KC |
543 | } |
544 | ||
545 | data->sysmmu = dev; | |
546 | rwlock_init(&data->lock); | |
547 | INIT_LIST_HEAD(&data->node); | |
548 | ||
549 | __set_fault_handler(data, &default_fault_handler); | |
550 | ||
7222e8db CK |
551 | platform_set_drvdata(pdev, data); |
552 | ||
2a96536e KC |
553 | if (dev->parent) |
554 | pm_runtime_enable(dev); | |
555 | ||
556 | dev_dbg(dev, "(%s) Initialized\n", data->dbgname); | |
557 | return 0; | |
558 | err_irq: | |
7222e8db | 559 | free_irq(platform_get_irq(pdev, 0), data); |
2a96536e | 560 | err_res: |
7222e8db | 561 | iounmap(data->sfrbase); |
2a96536e KC |
562 | err_init: |
563 | kfree(data); | |
564 | err_alloc: | |
565 | dev_err(dev, "Failed to initialize\n"); | |
566 | return ret; | |
567 | } | |
568 | ||
569 | static struct platform_driver exynos_sysmmu_driver = { | |
570 | .probe = exynos_sysmmu_probe, | |
571 | .driver = { | |
572 | .owner = THIS_MODULE, | |
573 | .name = "exynos-sysmmu", | |
574 | } | |
575 | }; | |
576 | ||
577 | static inline void pgtable_flush(void *vastart, void *vaend) | |
578 | { | |
579 | dmac_flush_range(vastart, vaend); | |
580 | outer_flush_range(virt_to_phys(vastart), | |
581 | virt_to_phys(vaend)); | |
582 | } | |
583 | ||
584 | static int exynos_iommu_domain_init(struct iommu_domain *domain) | |
585 | { | |
586 | struct exynos_iommu_domain *priv; | |
587 | ||
588 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
589 | if (!priv) | |
590 | return -ENOMEM; | |
591 | ||
592 | priv->pgtable = (unsigned long *)__get_free_pages( | |
593 | GFP_KERNEL | __GFP_ZERO, 2); | |
594 | if (!priv->pgtable) | |
595 | goto err_pgtable; | |
596 | ||
597 | priv->lv2entcnt = (short *)__get_free_pages( | |
598 | GFP_KERNEL | __GFP_ZERO, 1); | |
599 | if (!priv->lv2entcnt) | |
600 | goto err_counter; | |
601 | ||
602 | pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES); | |
603 | ||
604 | spin_lock_init(&priv->lock); | |
605 | spin_lock_init(&priv->pgtablelock); | |
606 | INIT_LIST_HEAD(&priv->clients); | |
607 | ||
eb51637b SK |
608 | domain->geometry.aperture_start = 0; |
609 | domain->geometry.aperture_end = ~0UL; | |
610 | domain->geometry.force_aperture = true; | |
3177bb76 | 611 | |
2a96536e KC |
612 | domain->priv = priv; |
613 | return 0; | |
614 | ||
615 | err_counter: | |
616 | free_pages((unsigned long)priv->pgtable, 2); | |
617 | err_pgtable: | |
618 | kfree(priv); | |
619 | return -ENOMEM; | |
620 | } | |
621 | ||
622 | static void exynos_iommu_domain_destroy(struct iommu_domain *domain) | |
623 | { | |
624 | struct exynos_iommu_domain *priv = domain->priv; | |
625 | struct sysmmu_drvdata *data; | |
626 | unsigned long flags; | |
627 | int i; | |
628 | ||
629 | WARN_ON(!list_empty(&priv->clients)); | |
630 | ||
631 | spin_lock_irqsave(&priv->lock, flags); | |
632 | ||
633 | list_for_each_entry(data, &priv->clients, node) { | |
634 | while (!exynos_sysmmu_disable(data->dev)) | |
635 | ; /* until System MMU is actually disabled */ | |
636 | } | |
637 | ||
638 | spin_unlock_irqrestore(&priv->lock, flags); | |
639 | ||
640 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
641 | if (lv1ent_page(priv->pgtable + i)) | |
734c3c73 CK |
642 | kmem_cache_free(lv2table_kmem_cache, |
643 | phys_to_virt(lv2table_base(priv->pgtable + i))); | |
2a96536e KC |
644 | |
645 | free_pages((unsigned long)priv->pgtable, 2); | |
646 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
647 | kfree(domain->priv); | |
648 | domain->priv = NULL; | |
649 | } | |
650 | ||
651 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
652 | struct device *dev) | |
653 | { | |
654 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
655 | struct exynos_iommu_domain *priv = domain->priv; | |
7222e8db | 656 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
657 | unsigned long flags; |
658 | int ret; | |
659 | ||
660 | ret = pm_runtime_get_sync(data->sysmmu); | |
661 | if (ret < 0) | |
662 | return ret; | |
663 | ||
664 | ret = 0; | |
665 | ||
666 | spin_lock_irqsave(&priv->lock, flags); | |
667 | ||
7222e8db | 668 | ret = __exynos_sysmmu_enable(data, pagetable, domain); |
2a96536e KC |
669 | |
670 | if (ret == 0) { | |
671 | /* 'data->node' must not be appeared in priv->clients */ | |
672 | BUG_ON(!list_empty(&data->node)); | |
673 | data->dev = dev; | |
674 | list_add_tail(&data->node, &priv->clients); | |
675 | } | |
676 | ||
677 | spin_unlock_irqrestore(&priv->lock, flags); | |
678 | ||
679 | if (ret < 0) { | |
7222e8db CK |
680 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
681 | __func__, &pagetable); | |
2a96536e | 682 | pm_runtime_put(data->sysmmu); |
7222e8db | 683 | return ret; |
2a96536e KC |
684 | } |
685 | ||
7222e8db CK |
686 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
687 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
688 | ||
2a96536e KC |
689 | return ret; |
690 | } | |
691 | ||
692 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
693 | struct device *dev) | |
694 | { | |
695 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
696 | struct exynos_iommu_domain *priv = domain->priv; | |
697 | struct list_head *pos; | |
7222e8db | 698 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
699 | unsigned long flags; |
700 | bool found = false; | |
701 | ||
702 | spin_lock_irqsave(&priv->lock, flags); | |
703 | ||
704 | list_for_each(pos, &priv->clients) { | |
705 | if (list_entry(pos, struct sysmmu_drvdata, node) == data) { | |
706 | found = true; | |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
711 | if (!found) | |
712 | goto finish; | |
713 | ||
714 | if (__exynos_sysmmu_disable(data)) { | |
7222e8db CK |
715 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
716 | __func__, &pagetable); | |
f8ffcc92 | 717 | list_del_init(&data->node); |
2a96536e KC |
718 | |
719 | } else { | |
7222e8db CK |
720 | dev_dbg(dev, "%s: Detaching IOMMU with pgtable %pa delayed", |
721 | __func__, &pagetable); | |
2a96536e KC |
722 | } |
723 | ||
724 | finish: | |
725 | spin_unlock_irqrestore(&priv->lock, flags); | |
726 | ||
727 | if (found) | |
728 | pm_runtime_put(data->sysmmu); | |
729 | } | |
730 | ||
731 | static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova, | |
732 | short *pgcounter) | |
733 | { | |
61128f08 CK |
734 | if (lv1ent_section(sent)) { |
735 | WARN(1, "Trying mapping on %#08lx mapped with 1MiB page", iova); | |
736 | return ERR_PTR(-EADDRINUSE); | |
737 | } | |
738 | ||
2a96536e KC |
739 | if (lv1ent_fault(sent)) { |
740 | unsigned long *pent; | |
741 | ||
734c3c73 | 742 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
2a96536e KC |
743 | BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1)); |
744 | if (!pent) | |
61128f08 | 745 | return ERR_PTR(-ENOMEM); |
2a96536e | 746 | |
7222e8db | 747 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
2a96536e KC |
748 | *pgcounter = NUM_LV2ENTRIES; |
749 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
750 | pgtable_flush(sent, sent + 1); | |
751 | } | |
752 | ||
753 | return page_entry(sent, iova); | |
754 | } | |
755 | ||
61128f08 CK |
756 | static int lv1set_section(unsigned long *sent, unsigned long iova, |
757 | phys_addr_t paddr, short *pgcnt) | |
2a96536e | 758 | { |
61128f08 CK |
759 | if (lv1ent_section(sent)) { |
760 | WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped", | |
761 | iova); | |
2a96536e | 762 | return -EADDRINUSE; |
61128f08 | 763 | } |
2a96536e KC |
764 | |
765 | if (lv1ent_page(sent)) { | |
61128f08 CK |
766 | if (*pgcnt != NUM_LV2ENTRIES) { |
767 | WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped", | |
768 | iova); | |
2a96536e | 769 | return -EADDRINUSE; |
61128f08 | 770 | } |
2a96536e | 771 | |
734c3c73 | 772 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
773 | *pgcnt = 0; |
774 | } | |
775 | ||
776 | *sent = mk_lv1ent_sect(paddr); | |
777 | ||
778 | pgtable_flush(sent, sent + 1); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size, | |
784 | short *pgcnt) | |
785 | { | |
786 | if (size == SPAGE_SIZE) { | |
61128f08 CK |
787 | if (!lv2ent_fault(pent)) { |
788 | WARN(1, "Trying mapping on 4KiB where mapping exists"); | |
2a96536e | 789 | return -EADDRINUSE; |
61128f08 | 790 | } |
2a96536e KC |
791 | |
792 | *pent = mk_lv2ent_spage(paddr); | |
793 | pgtable_flush(pent, pent + 1); | |
794 | *pgcnt -= 1; | |
795 | } else { /* size == LPAGE_SIZE */ | |
796 | int i; | |
797 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { | |
798 | if (!lv2ent_fault(pent)) { | |
61128f08 CK |
799 | WARN(1, |
800 | "Trying mapping on 64KiB where mapping exists"); | |
801 | if (i > 0) | |
802 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
803 | return -EADDRINUSE; |
804 | } | |
805 | ||
806 | *pent = mk_lv2ent_lpage(paddr); | |
807 | } | |
808 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
809 | *pgcnt -= SPAGES_PER_LPAGE; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
816 | phys_addr_t paddr, size_t size, int prot) | |
817 | { | |
818 | struct exynos_iommu_domain *priv = domain->priv; | |
819 | unsigned long *entry; | |
820 | unsigned long flags; | |
821 | int ret = -ENOMEM; | |
822 | ||
823 | BUG_ON(priv->pgtable == NULL); | |
824 | ||
825 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
826 | ||
827 | entry = section_entry(priv->pgtable, iova); | |
828 | ||
829 | if (size == SECT_SIZE) { | |
61128f08 | 830 | ret = lv1set_section(entry, iova, paddr, |
2a96536e KC |
831 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
832 | } else { | |
833 | unsigned long *pent; | |
834 | ||
835 | pent = alloc_lv2entry(entry, iova, | |
836 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
837 | ||
61128f08 CK |
838 | if (IS_ERR(pent)) |
839 | ret = PTR_ERR(pent); | |
2a96536e KC |
840 | else |
841 | ret = lv2set_page(pent, paddr, size, | |
842 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
843 | } | |
844 | ||
61128f08 | 845 | if (ret) |
2a96536e KC |
846 | pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n", |
847 | __func__, iova, size); | |
2a96536e KC |
848 | |
849 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
850 | ||
851 | return ret; | |
852 | } | |
853 | ||
854 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, | |
855 | unsigned long iova, size_t size) | |
856 | { | |
857 | struct exynos_iommu_domain *priv = domain->priv; | |
858 | struct sysmmu_drvdata *data; | |
859 | unsigned long flags; | |
860 | unsigned long *ent; | |
61128f08 | 861 | size_t err_pgsize; |
2a96536e KC |
862 | |
863 | BUG_ON(priv->pgtable == NULL); | |
864 | ||
865 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
866 | ||
867 | ent = section_entry(priv->pgtable, iova); | |
868 | ||
869 | if (lv1ent_section(ent)) { | |
61128f08 CK |
870 | if (size < SECT_SIZE) { |
871 | err_pgsize = SECT_SIZE; | |
872 | goto err; | |
873 | } | |
2a96536e KC |
874 | |
875 | *ent = 0; | |
876 | pgtable_flush(ent, ent + 1); | |
877 | size = SECT_SIZE; | |
878 | goto done; | |
879 | } | |
880 | ||
881 | if (unlikely(lv1ent_fault(ent))) { | |
882 | if (size > SECT_SIZE) | |
883 | size = SECT_SIZE; | |
884 | goto done; | |
885 | } | |
886 | ||
887 | /* lv1ent_page(sent) == true here */ | |
888 | ||
889 | ent = page_entry(ent, iova); | |
890 | ||
891 | if (unlikely(lv2ent_fault(ent))) { | |
892 | size = SPAGE_SIZE; | |
893 | goto done; | |
894 | } | |
895 | ||
896 | if (lv2ent_small(ent)) { | |
897 | *ent = 0; | |
898 | size = SPAGE_SIZE; | |
899 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; | |
900 | goto done; | |
901 | } | |
902 | ||
903 | /* lv1ent_large(ent) == true here */ | |
61128f08 CK |
904 | if (size < LPAGE_SIZE) { |
905 | err_pgsize = LPAGE_SIZE; | |
906 | goto err; | |
907 | } | |
2a96536e KC |
908 | |
909 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
910 | ||
911 | size = LPAGE_SIZE; | |
912 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
913 | done: | |
914 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
915 | ||
916 | spin_lock_irqsave(&priv->lock, flags); | |
917 | list_for_each_entry(data, &priv->clients, node) | |
918 | sysmmu_tlb_invalidate_entry(data->dev, iova); | |
919 | spin_unlock_irqrestore(&priv->lock, flags); | |
920 | ||
2a96536e | 921 | return size; |
61128f08 CK |
922 | err: |
923 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
924 | ||
925 | WARN(1, | |
926 | "%s: Failed due to size(%#x) @ %#08lx is smaller than page size %#x\n", | |
927 | __func__, size, iova, err_pgsize); | |
928 | ||
929 | return 0; | |
2a96536e KC |
930 | } |
931 | ||
932 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 933 | dma_addr_t iova) |
2a96536e KC |
934 | { |
935 | struct exynos_iommu_domain *priv = domain->priv; | |
936 | unsigned long *entry; | |
937 | unsigned long flags; | |
938 | phys_addr_t phys = 0; | |
939 | ||
940 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
941 | ||
942 | entry = section_entry(priv->pgtable, iova); | |
943 | ||
944 | if (lv1ent_section(entry)) { | |
945 | phys = section_phys(entry) + section_offs(iova); | |
946 | } else if (lv1ent_page(entry)) { | |
947 | entry = page_entry(entry, iova); | |
948 | ||
949 | if (lv2ent_large(entry)) | |
950 | phys = lpage_phys(entry) + lpage_offs(iova); | |
951 | else if (lv2ent_small(entry)) | |
952 | phys = spage_phys(entry) + spage_offs(iova); | |
953 | } | |
954 | ||
955 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
956 | ||
957 | return phys; | |
958 | } | |
959 | ||
960 | static struct iommu_ops exynos_iommu_ops = { | |
961 | .domain_init = &exynos_iommu_domain_init, | |
962 | .domain_destroy = &exynos_iommu_domain_destroy, | |
963 | .attach_dev = &exynos_iommu_attach_device, | |
964 | .detach_dev = &exynos_iommu_detach_device, | |
965 | .map = &exynos_iommu_map, | |
966 | .unmap = &exynos_iommu_unmap, | |
967 | .iova_to_phys = &exynos_iommu_iova_to_phys, | |
968 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, | |
969 | }; | |
970 | ||
971 | static int __init exynos_iommu_init(void) | |
972 | { | |
973 | int ret; | |
974 | ||
734c3c73 CK |
975 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
976 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
977 | if (!lv2table_kmem_cache) { | |
978 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
979 | return -ENOMEM; | |
980 | } | |
981 | ||
2a96536e | 982 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
983 | if (ret) { |
984 | pr_err("%s: Failed to register driver\n", __func__); | |
985 | goto err_reg_driver; | |
986 | } | |
2a96536e | 987 | |
734c3c73 CK |
988 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
989 | if (ret) { | |
990 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
991 | __func__); | |
992 | goto err_set_iommu; | |
993 | } | |
2a96536e | 994 | |
734c3c73 CK |
995 | return 0; |
996 | err_set_iommu: | |
997 | platform_driver_unregister(&exynos_sysmmu_driver); | |
998 | err_reg_driver: | |
999 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1000 | return ret; |
1001 | } | |
1002 | subsys_initcall(exynos_iommu_init); |