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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
d09d78fc CK |
32 | typedef u32 sysmmu_iova_t; |
33 | typedef u32 sysmmu_pte_t; | |
34 | ||
2a96536e KC |
35 | /* We does not consider super section mapping (16MB) */ |
36 | #define SECT_ORDER 20 | |
37 | #define LPAGE_ORDER 16 | |
38 | #define SPAGE_ORDER 12 | |
39 | ||
40 | #define SECT_SIZE (1 << SECT_ORDER) | |
41 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
42 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
43 | ||
44 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
45 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
46 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
47 | ||
48 | #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
49 | #define lv1ent_page(sent) ((*(sent) & 3) == 1) | |
50 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) | |
51 | ||
52 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
53 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
54 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
55 | ||
d09d78fc CK |
56 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
57 | { | |
58 | return iova & (size - 1); | |
59 | } | |
60 | ||
2a96536e | 61 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 62 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 63 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 64 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 65 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 66 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
67 | |
68 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 69 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 70 | |
d09d78fc CK |
71 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
72 | { | |
73 | return iova >> SECT_ORDER; | |
74 | } | |
75 | ||
76 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
77 | { | |
78 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
79 | } | |
80 | ||
81 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
82 | |
83 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
84 | ||
85 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
86 | ||
87 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
88 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
89 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
90 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
91 | ||
92 | #define CTRL_ENABLE 0x5 | |
93 | #define CTRL_BLOCK 0x7 | |
94 | #define CTRL_DISABLE 0x0 | |
95 | ||
96 | #define REG_MMU_CTRL 0x000 | |
97 | #define REG_MMU_CFG 0x004 | |
98 | #define REG_MMU_STATUS 0x008 | |
99 | #define REG_MMU_FLUSH 0x00C | |
100 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
101 | #define REG_PT_BASE_ADDR 0x014 | |
102 | #define REG_INT_STATUS 0x018 | |
103 | #define REG_INT_CLEAR 0x01C | |
104 | ||
105 | #define REG_PAGE_FAULT_ADDR 0x024 | |
106 | #define REG_AW_FAULT_ADDR 0x028 | |
107 | #define REG_AR_FAULT_ADDR 0x02C | |
108 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
109 | ||
110 | #define REG_MMU_VERSION 0x034 | |
111 | ||
112 | #define REG_PB0_SADDR 0x04C | |
113 | #define REG_PB0_EADDR 0x050 | |
114 | #define REG_PB1_SADDR 0x054 | |
115 | #define REG_PB1_EADDR 0x058 | |
116 | ||
734c3c73 CK |
117 | static struct kmem_cache *lv2table_kmem_cache; |
118 | ||
d09d78fc | 119 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
120 | { |
121 | return pgtable + lv1ent_offset(iova); | |
122 | } | |
123 | ||
d09d78fc | 124 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 125 | { |
d09d78fc | 126 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 127 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
128 | } |
129 | ||
130 | enum exynos_sysmmu_inttype { | |
131 | SYSMMU_PAGEFAULT, | |
132 | SYSMMU_AR_MULTIHIT, | |
133 | SYSMMU_AW_MULTIHIT, | |
134 | SYSMMU_BUSERROR, | |
135 | SYSMMU_AR_SECURITY, | |
136 | SYSMMU_AR_ACCESS, | |
137 | SYSMMU_AW_SECURITY, | |
138 | SYSMMU_AW_PROTECTION, /* 7 */ | |
139 | SYSMMU_FAULT_UNKNOWN, | |
140 | SYSMMU_FAULTS_NUM | |
141 | }; | |
142 | ||
2a96536e KC |
143 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
144 | REG_PAGE_FAULT_ADDR, | |
145 | REG_AR_FAULT_ADDR, | |
146 | REG_AW_FAULT_ADDR, | |
147 | REG_DEFAULT_SLAVE_ADDR, | |
148 | REG_AR_FAULT_ADDR, | |
149 | REG_AR_FAULT_ADDR, | |
150 | REG_AW_FAULT_ADDR, | |
151 | REG_AW_FAULT_ADDR | |
152 | }; | |
153 | ||
154 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
155 | "PAGE FAULT", | |
156 | "AR MULTI-HIT FAULT", | |
157 | "AW MULTI-HIT FAULT", | |
158 | "BUS ERROR", | |
159 | "AR SECURITY PROTECTION FAULT", | |
160 | "AR ACCESS PROTECTION FAULT", | |
161 | "AW SECURITY PROTECTION FAULT", | |
162 | "AW ACCESS PROTECTION FAULT", | |
163 | "UNKNOWN FAULT" | |
164 | }; | |
165 | ||
166 | struct exynos_iommu_domain { | |
167 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
d09d78fc | 168 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ |
2a96536e KC |
169 | short *lv2entcnt; /* free lv2 entry counter for each section */ |
170 | spinlock_t lock; /* lock for this structure */ | |
171 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
172 | }; | |
173 | ||
174 | struct sysmmu_drvdata { | |
175 | struct list_head node; /* entry of exynos_iommu_domain.clients */ | |
176 | struct device *sysmmu; /* System MMU's device descriptor */ | |
177 | struct device *dev; /* Owner of system MMU */ | |
7222e8db CK |
178 | void __iomem *sfrbase; |
179 | struct clk *clk; | |
70605870 | 180 | struct clk *clk_master; |
2a96536e | 181 | int activations; |
9d4e7a24 | 182 | spinlock_t lock; |
2a96536e | 183 | struct iommu_domain *domain; |
7222e8db | 184 | phys_addr_t pgtable; |
2a96536e KC |
185 | }; |
186 | ||
187 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) | |
188 | { | |
189 | /* return true if the System MMU was not active previously | |
190 | and it needs to be initialized */ | |
191 | return ++data->activations == 1; | |
192 | } | |
193 | ||
194 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
195 | { | |
196 | /* return true if the System MMU is needed to be disabled */ | |
197 | BUG_ON(data->activations < 1); | |
198 | return --data->activations == 0; | |
199 | } | |
200 | ||
201 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
202 | { | |
203 | return data->activations > 0; | |
204 | } | |
205 | ||
206 | static void sysmmu_unblock(void __iomem *sfrbase) | |
207 | { | |
208 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
209 | } | |
210 | ||
211 | static bool sysmmu_block(void __iomem *sfrbase) | |
212 | { | |
213 | int i = 120; | |
214 | ||
215 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
216 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
217 | --i; | |
218 | ||
219 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
220 | sysmmu_unblock(sfrbase); | |
221 | return false; | |
222 | } | |
223 | ||
224 | return true; | |
225 | } | |
226 | ||
227 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
228 | { | |
229 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
230 | } | |
231 | ||
232 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 233 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 234 | { |
3ad6b7f3 CK |
235 | unsigned int i; |
236 | for (i = 0; i < num_inv; i++) { | |
237 | __raw_writel((iova & SPAGE_MASK) | 1, | |
238 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
239 | iova += SPAGE_SIZE; | |
240 | } | |
2a96536e KC |
241 | } |
242 | ||
243 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 244 | phys_addr_t pgd) |
2a96536e KC |
245 | { |
246 | __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */ | |
247 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); | |
248 | ||
249 | __sysmmu_tlb_invalidate(sfrbase); | |
250 | } | |
251 | ||
1fab7fa7 CK |
252 | static void show_fault_information(const char *name, |
253 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 254 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 255 | { |
d09d78fc | 256 | sysmmu_pte_t *ent; |
2a96536e KC |
257 | |
258 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
259 | itype = SYSMMU_FAULT_UNKNOWN; | |
260 | ||
d09d78fc | 261 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 262 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 263 | |
7222e8db | 264 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 265 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
266 | |
267 | if (lv1ent_page(ent)) { | |
268 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 269 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 270 | } |
2a96536e KC |
271 | } |
272 | ||
273 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
274 | { | |
275 | /* SYSMMU is in blocked when interrupt occurred. */ | |
276 | struct sysmmu_drvdata *data = dev_id; | |
2a96536e | 277 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 278 | sysmmu_iova_t addr = -1; |
7222e8db | 279 | int ret = -ENOSYS; |
2a96536e | 280 | |
2a96536e KC |
281 | WARN_ON(!is_sysmmu_active(data)); |
282 | ||
9d4e7a24 CK |
283 | spin_lock(&data->lock); |
284 | ||
70605870 CK |
285 | if (!IS_ERR(data->clk_master)) |
286 | clk_enable(data->clk_master); | |
9d4e7a24 | 287 | |
7222e8db CK |
288 | itype = (enum exynos_sysmmu_inttype) |
289 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
290 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 291 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
292 | else |
293 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 294 | |
1fab7fa7 CK |
295 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
296 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
297 | __func__, dev_name(data->sysmmu)); | |
298 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
299 | __func__); | |
300 | BUG(); | |
301 | } else { | |
d09d78fc | 302 | unsigned int base = |
1fab7fa7 CK |
303 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
304 | show_fault_information(dev_name(data->sysmmu), | |
305 | itype, base, addr); | |
306 | if (data->domain) | |
307 | ret = report_iommu_fault(data->domain, | |
308 | data->dev, addr, itype); | |
2a96536e KC |
309 | } |
310 | ||
1fab7fa7 CK |
311 | /* fault is not recovered by fault handler */ |
312 | BUG_ON(ret != 0); | |
2a96536e | 313 | |
1fab7fa7 CK |
314 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
315 | ||
316 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 317 | |
70605870 CK |
318 | if (!IS_ERR(data->clk_master)) |
319 | clk_disable(data->clk_master); | |
320 | ||
9d4e7a24 | 321 | spin_unlock(&data->lock); |
2a96536e KC |
322 | |
323 | return IRQ_HANDLED; | |
324 | } | |
325 | ||
326 | static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data) | |
327 | { | |
328 | unsigned long flags; | |
329 | bool disabled = false; | |
2a96536e | 330 | |
9d4e7a24 | 331 | spin_lock_irqsave(&data->lock, flags); |
2a96536e KC |
332 | |
333 | if (!set_sysmmu_inactive(data)) | |
334 | goto finish; | |
335 | ||
70605870 CK |
336 | if (!IS_ERR(data->clk_master)) |
337 | clk_enable(data->clk_master); | |
338 | ||
7222e8db | 339 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e | 340 | |
46c16d1e | 341 | clk_disable(data->clk); |
70605870 CK |
342 | if (!IS_ERR(data->clk_master)) |
343 | clk_disable(data->clk_master); | |
2a96536e KC |
344 | |
345 | disabled = true; | |
346 | data->pgtable = 0; | |
347 | data->domain = NULL; | |
348 | finish: | |
9d4e7a24 | 349 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
350 | |
351 | if (disabled) | |
e5cf63c3 | 352 | dev_dbg(data->sysmmu, "Disabled\n"); |
2a96536e | 353 | else |
e5cf63c3 CK |
354 | dev_dbg(data->sysmmu, "%d times left to be disabled\n", |
355 | data->activations); | |
2a96536e KC |
356 | |
357 | return disabled; | |
358 | } | |
359 | ||
360 | /* __exynos_sysmmu_enable: Enables System MMU | |
361 | * | |
362 | * returns -error if an error occurred and System MMU is not enabled, | |
363 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
364 | * enabled before. | |
365 | */ | |
366 | static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data, | |
d09d78fc | 367 | phys_addr_t pgtable, struct iommu_domain *domain) |
2a96536e | 368 | { |
7222e8db | 369 | int ret = 0; |
2a96536e KC |
370 | unsigned long flags; |
371 | ||
9d4e7a24 | 372 | spin_lock_irqsave(&data->lock, flags); |
2a96536e KC |
373 | |
374 | if (!set_sysmmu_active(data)) { | |
375 | if (WARN_ON(pgtable != data->pgtable)) { | |
376 | ret = -EBUSY; | |
377 | set_sysmmu_inactive(data); | |
378 | } else { | |
379 | ret = 1; | |
380 | } | |
381 | ||
e5cf63c3 | 382 | dev_dbg(data->sysmmu, "Already enabled\n"); |
2a96536e KC |
383 | goto finish; |
384 | } | |
385 | ||
2a96536e KC |
386 | data->pgtable = pgtable; |
387 | ||
70605870 CK |
388 | if (!IS_ERR(data->clk_master)) |
389 | clk_enable(data->clk_master); | |
390 | clk_enable(data->clk); | |
391 | ||
7222e8db | 392 | __sysmmu_set_ptbase(data->sfrbase, pgtable); |
2a96536e | 393 | |
7222e8db CK |
394 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
395 | ||
70605870 CK |
396 | if (!IS_ERR(data->clk_master)) |
397 | clk_disable(data->clk_master); | |
398 | ||
2a96536e KC |
399 | data->domain = domain; |
400 | ||
e5cf63c3 | 401 | dev_dbg(data->sysmmu, "Enabled\n"); |
2a96536e | 402 | finish: |
9d4e7a24 | 403 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
404 | |
405 | return ret; | |
406 | } | |
407 | ||
d09d78fc | 408 | int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable) |
2a96536e KC |
409 | { |
410 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
411 | int ret; | |
412 | ||
413 | BUG_ON(!memblock_is_memory(pgtable)); | |
414 | ||
415 | ret = pm_runtime_get_sync(data->sysmmu); | |
416 | if (ret < 0) { | |
e5cf63c3 | 417 | dev_dbg(data->sysmmu, "Failed to enable\n"); |
2a96536e KC |
418 | return ret; |
419 | } | |
420 | ||
421 | ret = __exynos_sysmmu_enable(data, pgtable, NULL); | |
422 | if (WARN_ON(ret < 0)) { | |
423 | pm_runtime_put(data->sysmmu); | |
e5cf63c3 CK |
424 | dev_err(data->sysmmu, "Already enabled with page table %#x\n", |
425 | data->pgtable); | |
2a96536e KC |
426 | } else { |
427 | data->dev = dev; | |
428 | } | |
429 | ||
430 | return ret; | |
431 | } | |
432 | ||
77e38350 | 433 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e KC |
434 | { |
435 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
436 | bool disabled; | |
437 | ||
438 | disabled = __exynos_sysmmu_disable(data); | |
439 | pm_runtime_put(data->sysmmu); | |
440 | ||
441 | return disabled; | |
442 | } | |
443 | ||
d09d78fc | 444 | static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova, |
3ad6b7f3 | 445 | size_t size) |
2a96536e KC |
446 | { |
447 | unsigned long flags; | |
448 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
449 | ||
9d4e7a24 | 450 | spin_lock_irqsave(&data->lock, flags); |
2a96536e KC |
451 | |
452 | if (is_sysmmu_active(data)) { | |
3ad6b7f3 CK |
453 | unsigned int maj; |
454 | unsigned int num_inv = 1; | |
70605870 CK |
455 | |
456 | if (!IS_ERR(data->clk_master)) | |
457 | clk_enable(data->clk_master); | |
458 | ||
3ad6b7f3 CK |
459 | maj = __raw_readl(data->sfrbase + REG_MMU_VERSION); |
460 | /* | |
461 | * L2TLB invalidation required | |
462 | * 4KB page: 1 invalidation | |
463 | * 64KB page: 16 invalidation | |
464 | * 1MB page: 64 invalidation | |
465 | * because it is set-associative TLB | |
466 | * with 8-way and 64 sets. | |
467 | * 1MB page can be cached in one of all sets. | |
468 | * 64KB page can be one of 16 consecutive sets. | |
469 | */ | |
470 | if ((maj >> 28) == 2) /* major version number */ | |
471 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); | |
472 | ||
7222e8db CK |
473 | if (sysmmu_block(data->sfrbase)) { |
474 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 475 | data->sfrbase, iova, num_inv); |
7222e8db | 476 | sysmmu_unblock(data->sfrbase); |
2a96536e | 477 | } |
70605870 CK |
478 | if (!IS_ERR(data->clk_master)) |
479 | clk_disable(data->clk_master); | |
2a96536e | 480 | } else { |
e5cf63c3 | 481 | dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n"); |
2a96536e KC |
482 | } |
483 | ||
9d4e7a24 | 484 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
485 | } |
486 | ||
487 | void exynos_sysmmu_tlb_invalidate(struct device *dev) | |
488 | { | |
489 | unsigned long flags; | |
490 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
491 | ||
9d4e7a24 | 492 | spin_lock_irqsave(&data->lock, flags); |
2a96536e KC |
493 | |
494 | if (is_sysmmu_active(data)) { | |
70605870 CK |
495 | if (!IS_ERR(data->clk_master)) |
496 | clk_enable(data->clk_master); | |
7222e8db CK |
497 | if (sysmmu_block(data->sfrbase)) { |
498 | __sysmmu_tlb_invalidate(data->sfrbase); | |
499 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 500 | } |
70605870 CK |
501 | if (!IS_ERR(data->clk_master)) |
502 | clk_disable(data->clk_master); | |
2a96536e | 503 | } else { |
e5cf63c3 | 504 | dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n"); |
2a96536e KC |
505 | } |
506 | ||
9d4e7a24 | 507 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
508 | } |
509 | ||
510 | static int exynos_sysmmu_probe(struct platform_device *pdev) | |
511 | { | |
46c16d1e | 512 | int irq, ret; |
7222e8db | 513 | struct device *dev = &pdev->dev; |
2a96536e | 514 | struct sysmmu_drvdata *data; |
7222e8db | 515 | struct resource *res; |
2a96536e | 516 | |
46c16d1e CK |
517 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
518 | if (!data) | |
519 | return -ENOMEM; | |
2a96536e | 520 | |
7222e8db | 521 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
522 | data->sfrbase = devm_ioremap_resource(dev, res); |
523 | if (IS_ERR(data->sfrbase)) | |
524 | return PTR_ERR(data->sfrbase); | |
2a96536e | 525 | |
46c16d1e CK |
526 | irq = platform_get_irq(pdev, 0); |
527 | if (irq <= 0) { | |
7222e8db | 528 | dev_dbg(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 529 | return irq; |
2a96536e KC |
530 | } |
531 | ||
46c16d1e | 532 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
533 | dev_name(dev), data); |
534 | if (ret) { | |
46c16d1e CK |
535 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
536 | return ret; | |
2a96536e KC |
537 | } |
538 | ||
46c16d1e CK |
539 | data->clk = devm_clk_get(dev, "sysmmu"); |
540 | if (IS_ERR(data->clk)) { | |
541 | dev_err(dev, "Failed to get clock!\n"); | |
542 | return PTR_ERR(data->clk); | |
543 | } else { | |
544 | ret = clk_prepare(data->clk); | |
545 | if (ret) { | |
546 | dev_err(dev, "Failed to prepare clk\n"); | |
547 | return ret; | |
548 | } | |
2a96536e KC |
549 | } |
550 | ||
70605870 CK |
551 | data->clk_master = devm_clk_get(dev, "master"); |
552 | if (!IS_ERR(data->clk_master)) { | |
553 | ret = clk_prepare(data->clk_master); | |
554 | if (ret) { | |
555 | clk_unprepare(data->clk); | |
556 | dev_err(dev, "Failed to prepare master's clk\n"); | |
557 | return ret; | |
558 | } | |
559 | } | |
560 | ||
2a96536e | 561 | data->sysmmu = dev; |
9d4e7a24 | 562 | spin_lock_init(&data->lock); |
2a96536e KC |
563 | INIT_LIST_HEAD(&data->node); |
564 | ||
7222e8db CK |
565 | platform_set_drvdata(pdev, data); |
566 | ||
f4723ec1 | 567 | pm_runtime_enable(dev); |
2a96536e | 568 | |
2a96536e | 569 | return 0; |
2a96536e KC |
570 | } |
571 | ||
572 | static struct platform_driver exynos_sysmmu_driver = { | |
573 | .probe = exynos_sysmmu_probe, | |
574 | .driver = { | |
575 | .owner = THIS_MODULE, | |
576 | .name = "exynos-sysmmu", | |
577 | } | |
578 | }; | |
579 | ||
580 | static inline void pgtable_flush(void *vastart, void *vaend) | |
581 | { | |
582 | dmac_flush_range(vastart, vaend); | |
583 | outer_flush_range(virt_to_phys(vastart), | |
584 | virt_to_phys(vaend)); | |
585 | } | |
586 | ||
587 | static int exynos_iommu_domain_init(struct iommu_domain *domain) | |
588 | { | |
589 | struct exynos_iommu_domain *priv; | |
590 | ||
591 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
592 | if (!priv) | |
593 | return -ENOMEM; | |
594 | ||
d09d78fc | 595 | priv->pgtable = (sysmmu_pte_t *)__get_free_pages( |
2a96536e KC |
596 | GFP_KERNEL | __GFP_ZERO, 2); |
597 | if (!priv->pgtable) | |
598 | goto err_pgtable; | |
599 | ||
600 | priv->lv2entcnt = (short *)__get_free_pages( | |
601 | GFP_KERNEL | __GFP_ZERO, 1); | |
602 | if (!priv->lv2entcnt) | |
603 | goto err_counter; | |
604 | ||
605 | pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES); | |
606 | ||
607 | spin_lock_init(&priv->lock); | |
608 | spin_lock_init(&priv->pgtablelock); | |
609 | INIT_LIST_HEAD(&priv->clients); | |
610 | ||
eb51637b SK |
611 | domain->geometry.aperture_start = 0; |
612 | domain->geometry.aperture_end = ~0UL; | |
613 | domain->geometry.force_aperture = true; | |
3177bb76 | 614 | |
2a96536e KC |
615 | domain->priv = priv; |
616 | return 0; | |
617 | ||
618 | err_counter: | |
619 | free_pages((unsigned long)priv->pgtable, 2); | |
620 | err_pgtable: | |
621 | kfree(priv); | |
622 | return -ENOMEM; | |
623 | } | |
624 | ||
625 | static void exynos_iommu_domain_destroy(struct iommu_domain *domain) | |
626 | { | |
627 | struct exynos_iommu_domain *priv = domain->priv; | |
628 | struct sysmmu_drvdata *data; | |
629 | unsigned long flags; | |
630 | int i; | |
631 | ||
632 | WARN_ON(!list_empty(&priv->clients)); | |
633 | ||
634 | spin_lock_irqsave(&priv->lock, flags); | |
635 | ||
636 | list_for_each_entry(data, &priv->clients, node) { | |
637 | while (!exynos_sysmmu_disable(data->dev)) | |
638 | ; /* until System MMU is actually disabled */ | |
639 | } | |
640 | ||
641 | spin_unlock_irqrestore(&priv->lock, flags); | |
642 | ||
643 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
644 | if (lv1ent_page(priv->pgtable + i)) | |
734c3c73 CK |
645 | kmem_cache_free(lv2table_kmem_cache, |
646 | phys_to_virt(lv2table_base(priv->pgtable + i))); | |
2a96536e KC |
647 | |
648 | free_pages((unsigned long)priv->pgtable, 2); | |
649 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
650 | kfree(domain->priv); | |
651 | domain->priv = NULL; | |
652 | } | |
653 | ||
654 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
655 | struct device *dev) | |
656 | { | |
657 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
658 | struct exynos_iommu_domain *priv = domain->priv; | |
7222e8db | 659 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
660 | unsigned long flags; |
661 | int ret; | |
662 | ||
663 | ret = pm_runtime_get_sync(data->sysmmu); | |
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
667 | ret = 0; | |
668 | ||
669 | spin_lock_irqsave(&priv->lock, flags); | |
670 | ||
7222e8db | 671 | ret = __exynos_sysmmu_enable(data, pagetable, domain); |
2a96536e KC |
672 | |
673 | if (ret == 0) { | |
674 | /* 'data->node' must not be appeared in priv->clients */ | |
675 | BUG_ON(!list_empty(&data->node)); | |
676 | data->dev = dev; | |
677 | list_add_tail(&data->node, &priv->clients); | |
678 | } | |
679 | ||
680 | spin_unlock_irqrestore(&priv->lock, flags); | |
681 | ||
682 | if (ret < 0) { | |
7222e8db CK |
683 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
684 | __func__, &pagetable); | |
2a96536e | 685 | pm_runtime_put(data->sysmmu); |
7222e8db | 686 | return ret; |
2a96536e KC |
687 | } |
688 | ||
7222e8db CK |
689 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
690 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
691 | ||
2a96536e KC |
692 | return ret; |
693 | } | |
694 | ||
695 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
696 | struct device *dev) | |
697 | { | |
698 | struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu); | |
699 | struct exynos_iommu_domain *priv = domain->priv; | |
700 | struct list_head *pos; | |
7222e8db | 701 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
702 | unsigned long flags; |
703 | bool found = false; | |
704 | ||
705 | spin_lock_irqsave(&priv->lock, flags); | |
706 | ||
707 | list_for_each(pos, &priv->clients) { | |
708 | if (list_entry(pos, struct sysmmu_drvdata, node) == data) { | |
709 | found = true; | |
710 | break; | |
711 | } | |
712 | } | |
713 | ||
714 | if (!found) | |
715 | goto finish; | |
716 | ||
717 | if (__exynos_sysmmu_disable(data)) { | |
7222e8db CK |
718 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
719 | __func__, &pagetable); | |
f8ffcc92 | 720 | list_del_init(&data->node); |
2a96536e KC |
721 | |
722 | } else { | |
7222e8db CK |
723 | dev_dbg(dev, "%s: Detaching IOMMU with pgtable %pa delayed", |
724 | __func__, &pagetable); | |
2a96536e KC |
725 | } |
726 | ||
727 | finish: | |
728 | spin_unlock_irqrestore(&priv->lock, flags); | |
729 | ||
730 | if (found) | |
731 | pm_runtime_put(data->sysmmu); | |
732 | } | |
733 | ||
d09d78fc | 734 | static sysmmu_pte_t *alloc_lv2entry(sysmmu_pte_t *sent, sysmmu_iova_t iova, |
2a96536e KC |
735 | short *pgcounter) |
736 | { | |
61128f08 | 737 | if (lv1ent_section(sent)) { |
d09d78fc | 738 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
739 | return ERR_PTR(-EADDRINUSE); |
740 | } | |
741 | ||
2a96536e | 742 | if (lv1ent_fault(sent)) { |
d09d78fc | 743 | sysmmu_pte_t *pent; |
2a96536e | 744 | |
734c3c73 | 745 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 746 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 747 | if (!pent) |
61128f08 | 748 | return ERR_PTR(-ENOMEM); |
2a96536e | 749 | |
7222e8db | 750 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
2a96536e KC |
751 | *pgcounter = NUM_LV2ENTRIES; |
752 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
753 | pgtable_flush(sent, sent + 1); | |
754 | } | |
755 | ||
756 | return page_entry(sent, iova); | |
757 | } | |
758 | ||
d09d78fc | 759 | static int lv1set_section(sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 760 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 761 | { |
61128f08 | 762 | if (lv1ent_section(sent)) { |
d09d78fc | 763 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 764 | iova); |
2a96536e | 765 | return -EADDRINUSE; |
61128f08 | 766 | } |
2a96536e KC |
767 | |
768 | if (lv1ent_page(sent)) { | |
61128f08 | 769 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 770 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 771 | iova); |
2a96536e | 772 | return -EADDRINUSE; |
61128f08 | 773 | } |
2a96536e | 774 | |
734c3c73 | 775 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
776 | *pgcnt = 0; |
777 | } | |
778 | ||
779 | *sent = mk_lv1ent_sect(paddr); | |
780 | ||
781 | pgtable_flush(sent, sent + 1); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
d09d78fc | 786 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
787 | short *pgcnt) |
788 | { | |
789 | if (size == SPAGE_SIZE) { | |
61128f08 CK |
790 | if (!lv2ent_fault(pent)) { |
791 | WARN(1, "Trying mapping on 4KiB where mapping exists"); | |
2a96536e | 792 | return -EADDRINUSE; |
61128f08 | 793 | } |
2a96536e KC |
794 | |
795 | *pent = mk_lv2ent_spage(paddr); | |
796 | pgtable_flush(pent, pent + 1); | |
797 | *pgcnt -= 1; | |
798 | } else { /* size == LPAGE_SIZE */ | |
799 | int i; | |
800 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { | |
801 | if (!lv2ent_fault(pent)) { | |
61128f08 CK |
802 | WARN(1, |
803 | "Trying mapping on 64KiB where mapping exists"); | |
804 | if (i > 0) | |
805 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
806 | return -EADDRINUSE; |
807 | } | |
808 | ||
809 | *pent = mk_lv2ent_lpage(paddr); | |
810 | } | |
811 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
812 | *pgcnt -= SPAGES_PER_LPAGE; | |
813 | } | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
d09d78fc | 818 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova, |
2a96536e KC |
819 | phys_addr_t paddr, size_t size, int prot) |
820 | { | |
821 | struct exynos_iommu_domain *priv = domain->priv; | |
d09d78fc CK |
822 | sysmmu_pte_t *entry; |
823 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
824 | unsigned long flags; |
825 | int ret = -ENOMEM; | |
826 | ||
827 | BUG_ON(priv->pgtable == NULL); | |
828 | ||
829 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
830 | ||
831 | entry = section_entry(priv->pgtable, iova); | |
832 | ||
833 | if (size == SECT_SIZE) { | |
61128f08 | 834 | ret = lv1set_section(entry, iova, paddr, |
2a96536e KC |
835 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
836 | } else { | |
d09d78fc | 837 | sysmmu_pte_t *pent; |
2a96536e KC |
838 | |
839 | pent = alloc_lv2entry(entry, iova, | |
840 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
841 | ||
61128f08 CK |
842 | if (IS_ERR(pent)) |
843 | ret = PTR_ERR(pent); | |
2a96536e KC |
844 | else |
845 | ret = lv2set_page(pent, paddr, size, | |
846 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
847 | } | |
848 | ||
61128f08 | 849 | if (ret) |
d09d78fc | 850 | pr_debug("%s: Failed to map iova %#x/%#zx bytes\n", |
2a96536e | 851 | __func__, iova, size); |
2a96536e KC |
852 | |
853 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
854 | ||
855 | return ret; | |
856 | } | |
857 | ||
858 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, | |
d09d78fc | 859 | unsigned long l_iova, size_t size) |
2a96536e KC |
860 | { |
861 | struct exynos_iommu_domain *priv = domain->priv; | |
862 | struct sysmmu_drvdata *data; | |
d09d78fc CK |
863 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
864 | sysmmu_pte_t *ent; | |
61128f08 | 865 | size_t err_pgsize; |
d09d78fc | 866 | unsigned long flags; |
2a96536e KC |
867 | |
868 | BUG_ON(priv->pgtable == NULL); | |
869 | ||
870 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
871 | ||
872 | ent = section_entry(priv->pgtable, iova); | |
873 | ||
874 | if (lv1ent_section(ent)) { | |
61128f08 CK |
875 | if (size < SECT_SIZE) { |
876 | err_pgsize = SECT_SIZE; | |
877 | goto err; | |
878 | } | |
2a96536e KC |
879 | |
880 | *ent = 0; | |
881 | pgtable_flush(ent, ent + 1); | |
882 | size = SECT_SIZE; | |
883 | goto done; | |
884 | } | |
885 | ||
886 | if (unlikely(lv1ent_fault(ent))) { | |
887 | if (size > SECT_SIZE) | |
888 | size = SECT_SIZE; | |
889 | goto done; | |
890 | } | |
891 | ||
892 | /* lv1ent_page(sent) == true here */ | |
893 | ||
894 | ent = page_entry(ent, iova); | |
895 | ||
896 | if (unlikely(lv2ent_fault(ent))) { | |
897 | size = SPAGE_SIZE; | |
898 | goto done; | |
899 | } | |
900 | ||
901 | if (lv2ent_small(ent)) { | |
902 | *ent = 0; | |
903 | size = SPAGE_SIZE; | |
6cb47ed7 | 904 | pgtable_flush(ent, ent + 1); |
2a96536e KC |
905 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; |
906 | goto done; | |
907 | } | |
908 | ||
909 | /* lv1ent_large(ent) == true here */ | |
61128f08 CK |
910 | if (size < LPAGE_SIZE) { |
911 | err_pgsize = LPAGE_SIZE; | |
912 | goto err; | |
913 | } | |
2a96536e KC |
914 | |
915 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 916 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
917 | |
918 | size = LPAGE_SIZE; | |
919 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
920 | done: | |
921 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
922 | ||
923 | spin_lock_irqsave(&priv->lock, flags); | |
924 | list_for_each_entry(data, &priv->clients, node) | |
3ad6b7f3 | 925 | sysmmu_tlb_invalidate_entry(data->dev, iova, size); |
2a96536e KC |
926 | spin_unlock_irqrestore(&priv->lock, flags); |
927 | ||
2a96536e | 928 | return size; |
61128f08 CK |
929 | err: |
930 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
931 | ||
932 | WARN(1, | |
d09d78fc | 933 | "%s: Failed due to size(%#zx) @ %#x is smaller than page size %#zx\n", |
61128f08 CK |
934 | __func__, size, iova, err_pgsize); |
935 | ||
936 | return 0; | |
2a96536e KC |
937 | } |
938 | ||
939 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 940 | dma_addr_t iova) |
2a96536e KC |
941 | { |
942 | struct exynos_iommu_domain *priv = domain->priv; | |
d09d78fc | 943 | sysmmu_pte_t *entry; |
2a96536e KC |
944 | unsigned long flags; |
945 | phys_addr_t phys = 0; | |
946 | ||
947 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
948 | ||
949 | entry = section_entry(priv->pgtable, iova); | |
950 | ||
951 | if (lv1ent_section(entry)) { | |
952 | phys = section_phys(entry) + section_offs(iova); | |
953 | } else if (lv1ent_page(entry)) { | |
954 | entry = page_entry(entry, iova); | |
955 | ||
956 | if (lv2ent_large(entry)) | |
957 | phys = lpage_phys(entry) + lpage_offs(iova); | |
958 | else if (lv2ent_small(entry)) | |
959 | phys = spage_phys(entry) + spage_offs(iova); | |
960 | } | |
961 | ||
962 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
963 | ||
964 | return phys; | |
965 | } | |
966 | ||
967 | static struct iommu_ops exynos_iommu_ops = { | |
968 | .domain_init = &exynos_iommu_domain_init, | |
969 | .domain_destroy = &exynos_iommu_domain_destroy, | |
970 | .attach_dev = &exynos_iommu_attach_device, | |
971 | .detach_dev = &exynos_iommu_detach_device, | |
972 | .map = &exynos_iommu_map, | |
973 | .unmap = &exynos_iommu_unmap, | |
974 | .iova_to_phys = &exynos_iommu_iova_to_phys, | |
975 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, | |
976 | }; | |
977 | ||
978 | static int __init exynos_iommu_init(void) | |
979 | { | |
980 | int ret; | |
981 | ||
734c3c73 CK |
982 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
983 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
984 | if (!lv2table_kmem_cache) { | |
985 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
986 | return -ENOMEM; | |
987 | } | |
988 | ||
2a96536e | 989 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
990 | if (ret) { |
991 | pr_err("%s: Failed to register driver\n", __func__); | |
992 | goto err_reg_driver; | |
993 | } | |
2a96536e | 994 | |
734c3c73 CK |
995 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
996 | if (ret) { | |
997 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
998 | __func__); | |
999 | goto err_set_iommu; | |
1000 | } | |
2a96536e | 1001 | |
734c3c73 CK |
1002 | return 0; |
1003 | err_set_iommu: | |
1004 | platform_driver_unregister(&exynos_sysmmu_driver); | |
1005 | err_reg_driver: | |
1006 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1007 | return ret; |
1008 | } | |
1009 | subsys_initcall(exynos_iommu_init); |