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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_runtime.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/memblock.h> | |
27 | #include <linux/export.h> | |
28 | ||
29 | #include <asm/cacheflush.h> | |
30 | #include <asm/pgtable.h> | |
31 | ||
d09d78fc CK |
32 | typedef u32 sysmmu_iova_t; |
33 | typedef u32 sysmmu_pte_t; | |
34 | ||
2a96536e KC |
35 | /* We does not consider super section mapping (16MB) */ |
36 | #define SECT_ORDER 20 | |
37 | #define LPAGE_ORDER 16 | |
38 | #define SPAGE_ORDER 12 | |
39 | ||
40 | #define SECT_SIZE (1 << SECT_ORDER) | |
41 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
42 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
43 | ||
44 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
45 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
46 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
47 | ||
48 | #define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
49 | #define lv1ent_page(sent) ((*(sent) & 3) == 1) | |
50 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) | |
51 | ||
52 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
53 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
54 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
55 | ||
d09d78fc CK |
56 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
57 | { | |
58 | return iova & (size - 1); | |
59 | } | |
60 | ||
2a96536e | 61 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 62 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 63 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 64 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 65 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 66 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
67 | |
68 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 69 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 70 | |
d09d78fc CK |
71 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
72 | { | |
73 | return iova >> SECT_ORDER; | |
74 | } | |
75 | ||
76 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
77 | { | |
78 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
79 | } | |
80 | ||
81 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) | |
2a96536e KC |
82 | |
83 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
84 | ||
85 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
86 | ||
87 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
88 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
89 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
90 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
91 | ||
92 | #define CTRL_ENABLE 0x5 | |
93 | #define CTRL_BLOCK 0x7 | |
94 | #define CTRL_DISABLE 0x0 | |
95 | ||
eeb5184b CK |
96 | #define CFG_LRU 0x1 |
97 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
98 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
99 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
100 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
101 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
102 | ||
2a96536e KC |
103 | #define REG_MMU_CTRL 0x000 |
104 | #define REG_MMU_CFG 0x004 | |
105 | #define REG_MMU_STATUS 0x008 | |
106 | #define REG_MMU_FLUSH 0x00C | |
107 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
108 | #define REG_PT_BASE_ADDR 0x014 | |
109 | #define REG_INT_STATUS 0x018 | |
110 | #define REG_INT_CLEAR 0x01C | |
111 | ||
112 | #define REG_PAGE_FAULT_ADDR 0x024 | |
113 | #define REG_AW_FAULT_ADDR 0x028 | |
114 | #define REG_AR_FAULT_ADDR 0x02C | |
115 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
116 | ||
117 | #define REG_MMU_VERSION 0x034 | |
118 | ||
eeb5184b CK |
119 | #define MMU_MAJ_VER(val) ((val) >> 7) |
120 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
121 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
122 | ||
123 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
124 | ||
2a96536e KC |
125 | #define REG_PB0_SADDR 0x04C |
126 | #define REG_PB0_EADDR 0x050 | |
127 | #define REG_PB1_SADDR 0x054 | |
128 | #define REG_PB1_EADDR 0x058 | |
129 | ||
6b21a5db CK |
130 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
131 | ||
734c3c73 CK |
132 | static struct kmem_cache *lv2table_kmem_cache; |
133 | ||
d09d78fc | 134 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
135 | { |
136 | return pgtable + lv1ent_offset(iova); | |
137 | } | |
138 | ||
d09d78fc | 139 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 140 | { |
d09d78fc | 141 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 142 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
143 | } |
144 | ||
145 | enum exynos_sysmmu_inttype { | |
146 | SYSMMU_PAGEFAULT, | |
147 | SYSMMU_AR_MULTIHIT, | |
148 | SYSMMU_AW_MULTIHIT, | |
149 | SYSMMU_BUSERROR, | |
150 | SYSMMU_AR_SECURITY, | |
151 | SYSMMU_AR_ACCESS, | |
152 | SYSMMU_AW_SECURITY, | |
153 | SYSMMU_AW_PROTECTION, /* 7 */ | |
154 | SYSMMU_FAULT_UNKNOWN, | |
155 | SYSMMU_FAULTS_NUM | |
156 | }; | |
157 | ||
2a96536e KC |
158 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
159 | REG_PAGE_FAULT_ADDR, | |
160 | REG_AR_FAULT_ADDR, | |
161 | REG_AW_FAULT_ADDR, | |
162 | REG_DEFAULT_SLAVE_ADDR, | |
163 | REG_AR_FAULT_ADDR, | |
164 | REG_AR_FAULT_ADDR, | |
165 | REG_AW_FAULT_ADDR, | |
166 | REG_AW_FAULT_ADDR | |
167 | }; | |
168 | ||
169 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
170 | "PAGE FAULT", | |
171 | "AR MULTI-HIT FAULT", | |
172 | "AW MULTI-HIT FAULT", | |
173 | "BUS ERROR", | |
174 | "AR SECURITY PROTECTION FAULT", | |
175 | "AR ACCESS PROTECTION FAULT", | |
176 | "AW SECURITY PROTECTION FAULT", | |
177 | "AW ACCESS PROTECTION FAULT", | |
178 | "UNKNOWN FAULT" | |
179 | }; | |
180 | ||
6b21a5db CK |
181 | /* attached to dev.archdata.iommu of the master device */ |
182 | struct exynos_iommu_owner { | |
183 | struct list_head client; /* entry of exynos_iommu_domain.clients */ | |
184 | struct device *dev; | |
185 | struct device *sysmmu; | |
186 | struct iommu_domain *domain; | |
187 | void *vmm_data; /* IO virtual memory manager's data */ | |
188 | spinlock_t lock; /* Lock to preserve consistency of System MMU */ | |
189 | }; | |
190 | ||
2a96536e KC |
191 | struct exynos_iommu_domain { |
192 | struct list_head clients; /* list of sysmmu_drvdata.node */ | |
d09d78fc | 193 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ |
2a96536e KC |
194 | short *lv2entcnt; /* free lv2 entry counter for each section */ |
195 | spinlock_t lock; /* lock for this structure */ | |
196 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
197 | }; | |
198 | ||
199 | struct sysmmu_drvdata { | |
2a96536e | 200 | struct device *sysmmu; /* System MMU's device descriptor */ |
6b21a5db | 201 | struct device *master; /* Owner of system MMU */ |
7222e8db CK |
202 | void __iomem *sfrbase; |
203 | struct clk *clk; | |
70605870 | 204 | struct clk *clk_master; |
2a96536e | 205 | int activations; |
9d4e7a24 | 206 | spinlock_t lock; |
2a96536e | 207 | struct iommu_domain *domain; |
7222e8db | 208 | phys_addr_t pgtable; |
2a96536e KC |
209 | }; |
210 | ||
211 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) | |
212 | { | |
213 | /* return true if the System MMU was not active previously | |
214 | and it needs to be initialized */ | |
215 | return ++data->activations == 1; | |
216 | } | |
217 | ||
218 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
219 | { | |
220 | /* return true if the System MMU is needed to be disabled */ | |
221 | BUG_ON(data->activations < 1); | |
222 | return --data->activations == 0; | |
223 | } | |
224 | ||
225 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
226 | { | |
227 | return data->activations > 0; | |
228 | } | |
229 | ||
230 | static void sysmmu_unblock(void __iomem *sfrbase) | |
231 | { | |
232 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
233 | } | |
234 | ||
eeb5184b CK |
235 | static unsigned int __raw_sysmmu_version(struct sysmmu_drvdata *data) |
236 | { | |
237 | return MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); | |
238 | } | |
239 | ||
2a96536e KC |
240 | static bool sysmmu_block(void __iomem *sfrbase) |
241 | { | |
242 | int i = 120; | |
243 | ||
244 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
245 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
246 | --i; | |
247 | ||
248 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
249 | sysmmu_unblock(sfrbase); | |
250 | return false; | |
251 | } | |
252 | ||
253 | return true; | |
254 | } | |
255 | ||
256 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
257 | { | |
258 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
259 | } | |
260 | ||
261 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 262 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 263 | { |
3ad6b7f3 CK |
264 | unsigned int i; |
265 | for (i = 0; i < num_inv; i++) { | |
266 | __raw_writel((iova & SPAGE_MASK) | 1, | |
267 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
268 | iova += SPAGE_SIZE; | |
269 | } | |
2a96536e KC |
270 | } |
271 | ||
272 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 273 | phys_addr_t pgd) |
2a96536e | 274 | { |
2a96536e KC |
275 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
276 | ||
277 | __sysmmu_tlb_invalidate(sfrbase); | |
278 | } | |
279 | ||
1fab7fa7 CK |
280 | static void show_fault_information(const char *name, |
281 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 282 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 283 | { |
d09d78fc | 284 | sysmmu_pte_t *ent; |
2a96536e KC |
285 | |
286 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
287 | itype = SYSMMU_FAULT_UNKNOWN; | |
288 | ||
d09d78fc | 289 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 290 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 291 | |
7222e8db | 292 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 293 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
294 | |
295 | if (lv1ent_page(ent)) { | |
296 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 297 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 298 | } |
2a96536e KC |
299 | } |
300 | ||
301 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
302 | { | |
303 | /* SYSMMU is in blocked when interrupt occurred. */ | |
304 | struct sysmmu_drvdata *data = dev_id; | |
2a96536e | 305 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 306 | sysmmu_iova_t addr = -1; |
7222e8db | 307 | int ret = -ENOSYS; |
2a96536e | 308 | |
2a96536e KC |
309 | WARN_ON(!is_sysmmu_active(data)); |
310 | ||
9d4e7a24 CK |
311 | spin_lock(&data->lock); |
312 | ||
70605870 CK |
313 | if (!IS_ERR(data->clk_master)) |
314 | clk_enable(data->clk_master); | |
9d4e7a24 | 315 | |
7222e8db CK |
316 | itype = (enum exynos_sysmmu_inttype) |
317 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
318 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 319 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
320 | else |
321 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 322 | |
1fab7fa7 CK |
323 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
324 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
325 | __func__, dev_name(data->sysmmu)); | |
326 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
327 | __func__); | |
328 | BUG(); | |
329 | } else { | |
d09d78fc | 330 | unsigned int base = |
1fab7fa7 CK |
331 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
332 | show_fault_information(dev_name(data->sysmmu), | |
333 | itype, base, addr); | |
334 | if (data->domain) | |
335 | ret = report_iommu_fault(data->domain, | |
6b21a5db | 336 | data->master, addr, itype); |
2a96536e KC |
337 | } |
338 | ||
1fab7fa7 CK |
339 | /* fault is not recovered by fault handler */ |
340 | BUG_ON(ret != 0); | |
2a96536e | 341 | |
1fab7fa7 CK |
342 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
343 | ||
344 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 345 | |
70605870 CK |
346 | if (!IS_ERR(data->clk_master)) |
347 | clk_disable(data->clk_master); | |
348 | ||
9d4e7a24 | 349 | spin_unlock(&data->lock); |
2a96536e KC |
350 | |
351 | return IRQ_HANDLED; | |
352 | } | |
353 | ||
6b21a5db | 354 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 355 | { |
70605870 CK |
356 | if (!IS_ERR(data->clk_master)) |
357 | clk_enable(data->clk_master); | |
358 | ||
7222e8db | 359 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 360 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 361 | |
46c16d1e | 362 | clk_disable(data->clk); |
70605870 CK |
363 | if (!IS_ERR(data->clk_master)) |
364 | clk_disable(data->clk_master); | |
2a96536e KC |
365 | } |
366 | ||
6b21a5db | 367 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 368 | { |
6b21a5db | 369 | bool disabled; |
2a96536e KC |
370 | unsigned long flags; |
371 | ||
9d4e7a24 | 372 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 373 | |
6b21a5db CK |
374 | disabled = set_sysmmu_inactive(data); |
375 | ||
376 | if (disabled) { | |
377 | data->pgtable = 0; | |
378 | data->domain = NULL; | |
379 | ||
380 | __sysmmu_disable_nocount(data); | |
2a96536e | 381 | |
6b21a5db CK |
382 | dev_dbg(data->sysmmu, "Disabled\n"); |
383 | } else { | |
384 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
385 | data->activations); | |
2a96536e KC |
386 | } |
387 | ||
6b21a5db CK |
388 | spin_unlock_irqrestore(&data->lock, flags); |
389 | ||
390 | return disabled; | |
391 | } | |
2a96536e | 392 | |
6b21a5db CK |
393 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
394 | { | |
eeb5184b CK |
395 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
396 | unsigned int ver; | |
397 | ||
398 | ver = __raw_sysmmu_version(data); | |
399 | if (MMU_MAJ_VER(ver) == 3) { | |
400 | if (MMU_MIN_VER(ver) >= 2) { | |
401 | cfg |= CFG_FLPDCACHE; | |
402 | if (MMU_MIN_VER(ver) == 3) { | |
403 | cfg |= CFG_ACGEN; | |
404 | cfg &= ~CFG_LRU; | |
405 | } else { | |
406 | cfg |= CFG_SYSSEL; | |
407 | } | |
408 | } | |
409 | } | |
6b21a5db CK |
410 | |
411 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
412 | } | |
413 | ||
414 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
415 | { | |
70605870 CK |
416 | if (!IS_ERR(data->clk_master)) |
417 | clk_enable(data->clk_master); | |
418 | clk_enable(data->clk); | |
419 | ||
6b21a5db CK |
420 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
421 | ||
422 | __sysmmu_init_config(data); | |
423 | ||
424 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 425 | |
7222e8db CK |
426 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
427 | ||
70605870 CK |
428 | if (!IS_ERR(data->clk_master)) |
429 | clk_disable(data->clk_master); | |
6b21a5db | 430 | } |
70605870 | 431 | |
6b21a5db CK |
432 | static int __sysmmu_enable(struct sysmmu_drvdata *data, |
433 | phys_addr_t pgtable, struct iommu_domain *domain) | |
434 | { | |
435 | int ret = 0; | |
436 | unsigned long flags; | |
437 | ||
438 | spin_lock_irqsave(&data->lock, flags); | |
439 | if (set_sysmmu_active(data)) { | |
440 | data->pgtable = pgtable; | |
441 | data->domain = domain; | |
442 | ||
443 | __sysmmu_enable_nocount(data); | |
444 | ||
445 | dev_dbg(data->sysmmu, "Enabled\n"); | |
446 | } else { | |
447 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
448 | ||
449 | dev_dbg(data->sysmmu, "already enabled\n"); | |
450 | } | |
451 | ||
452 | if (WARN_ON(ret < 0)) | |
453 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 454 | |
9d4e7a24 | 455 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
456 | |
457 | return ret; | |
458 | } | |
459 | ||
6b21a5db CK |
460 | /* __exynos_sysmmu_enable: Enables System MMU |
461 | * | |
462 | * returns -error if an error occurred and System MMU is not enabled, | |
463 | * 0 if the System MMU has been just enabled and 1 if System MMU was already | |
464 | * enabled before. | |
465 | */ | |
466 | static int __exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable, | |
467 | struct iommu_domain *domain) | |
2a96536e | 468 | { |
6b21a5db CK |
469 | int ret = 0; |
470 | unsigned long flags; | |
471 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
472 | struct sysmmu_drvdata *data; | |
2a96536e | 473 | |
6b21a5db | 474 | BUG_ON(!has_sysmmu(dev)); |
2a96536e | 475 | |
6b21a5db | 476 | spin_lock_irqsave(&owner->lock, flags); |
2a96536e | 477 | |
6b21a5db CK |
478 | data = dev_get_drvdata(owner->sysmmu); |
479 | ||
480 | ret = __sysmmu_enable(data, pgtable, domain); | |
481 | if (ret >= 0) | |
482 | data->master = dev; | |
483 | ||
484 | spin_unlock_irqrestore(&owner->lock, flags); | |
2a96536e KC |
485 | |
486 | return ret; | |
487 | } | |
488 | ||
6b21a5db CK |
489 | int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable) |
490 | { | |
491 | BUG_ON(!memblock_is_memory(pgtable)); | |
492 | ||
493 | return __exynos_sysmmu_enable(dev, pgtable, NULL); | |
494 | } | |
495 | ||
77e38350 | 496 | static bool exynos_sysmmu_disable(struct device *dev) |
2a96536e | 497 | { |
6b21a5db CK |
498 | unsigned long flags; |
499 | bool disabled = true; | |
500 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
501 | struct sysmmu_drvdata *data; | |
502 | ||
503 | BUG_ON(!has_sysmmu(dev)); | |
2a96536e | 504 | |
6b21a5db CK |
505 | spin_lock_irqsave(&owner->lock, flags); |
506 | ||
507 | data = dev_get_drvdata(owner->sysmmu); | |
508 | ||
509 | disabled = __sysmmu_disable(data); | |
510 | if (disabled) | |
511 | data->master = NULL; | |
512 | ||
513 | spin_unlock_irqrestore(&owner->lock, flags); | |
2a96536e KC |
514 | |
515 | return disabled; | |
516 | } | |
517 | ||
d09d78fc | 518 | static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova, |
3ad6b7f3 | 519 | size_t size) |
2a96536e | 520 | { |
6b21a5db | 521 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
2a96536e | 522 | unsigned long flags; |
6b21a5db | 523 | struct sysmmu_drvdata *data; |
2a96536e | 524 | |
6b21a5db | 525 | data = dev_get_drvdata(owner->sysmmu); |
2a96536e | 526 | |
6b21a5db | 527 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 528 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 529 | unsigned int num_inv = 1; |
70605870 CK |
530 | |
531 | if (!IS_ERR(data->clk_master)) | |
532 | clk_enable(data->clk_master); | |
533 | ||
3ad6b7f3 CK |
534 | /* |
535 | * L2TLB invalidation required | |
536 | * 4KB page: 1 invalidation | |
537 | * 64KB page: 16 invalidation | |
538 | * 1MB page: 64 invalidation | |
539 | * because it is set-associative TLB | |
540 | * with 8-way and 64 sets. | |
541 | * 1MB page can be cached in one of all sets. | |
542 | * 64KB page can be one of 16 consecutive sets. | |
543 | */ | |
eeb5184b | 544 | if (MMU_MAJ_VER(__raw_sysmmu_version(data)) == 2) |
3ad6b7f3 CK |
545 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
546 | ||
7222e8db CK |
547 | if (sysmmu_block(data->sfrbase)) { |
548 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 549 | data->sfrbase, iova, num_inv); |
7222e8db | 550 | sysmmu_unblock(data->sfrbase); |
2a96536e | 551 | } |
70605870 CK |
552 | if (!IS_ERR(data->clk_master)) |
553 | clk_disable(data->clk_master); | |
2a96536e | 554 | } else { |
6b21a5db CK |
555 | dev_dbg(dev, "disabled. Skipping TLB invalidation @ %#x\n", |
556 | iova); | |
2a96536e | 557 | } |
9d4e7a24 | 558 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
559 | } |
560 | ||
561 | void exynos_sysmmu_tlb_invalidate(struct device *dev) | |
562 | { | |
6b21a5db | 563 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
2a96536e | 564 | unsigned long flags; |
6b21a5db | 565 | struct sysmmu_drvdata *data; |
2a96536e | 566 | |
6b21a5db | 567 | data = dev_get_drvdata(owner->sysmmu); |
2a96536e | 568 | |
6b21a5db | 569 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 570 | if (is_sysmmu_active(data)) { |
70605870 CK |
571 | if (!IS_ERR(data->clk_master)) |
572 | clk_enable(data->clk_master); | |
7222e8db CK |
573 | if (sysmmu_block(data->sfrbase)) { |
574 | __sysmmu_tlb_invalidate(data->sfrbase); | |
575 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 576 | } |
70605870 CK |
577 | if (!IS_ERR(data->clk_master)) |
578 | clk_disable(data->clk_master); | |
2a96536e | 579 | } else { |
6b21a5db | 580 | dev_dbg(dev, "disabled. Skipping TLB invalidation\n"); |
2a96536e | 581 | } |
9d4e7a24 | 582 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
583 | } |
584 | ||
6b21a5db | 585 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 586 | { |
46c16d1e | 587 | int irq, ret; |
7222e8db | 588 | struct device *dev = &pdev->dev; |
2a96536e | 589 | struct sysmmu_drvdata *data; |
7222e8db | 590 | struct resource *res; |
2a96536e | 591 | |
46c16d1e CK |
592 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
593 | if (!data) | |
594 | return -ENOMEM; | |
2a96536e | 595 | |
7222e8db | 596 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
597 | data->sfrbase = devm_ioremap_resource(dev, res); |
598 | if (IS_ERR(data->sfrbase)) | |
599 | return PTR_ERR(data->sfrbase); | |
2a96536e | 600 | |
46c16d1e CK |
601 | irq = platform_get_irq(pdev, 0); |
602 | if (irq <= 0) { | |
0bf4e54d | 603 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 604 | return irq; |
2a96536e KC |
605 | } |
606 | ||
46c16d1e | 607 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
608 | dev_name(dev), data); |
609 | if (ret) { | |
46c16d1e CK |
610 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
611 | return ret; | |
2a96536e KC |
612 | } |
613 | ||
46c16d1e CK |
614 | data->clk = devm_clk_get(dev, "sysmmu"); |
615 | if (IS_ERR(data->clk)) { | |
616 | dev_err(dev, "Failed to get clock!\n"); | |
617 | return PTR_ERR(data->clk); | |
618 | } else { | |
619 | ret = clk_prepare(data->clk); | |
620 | if (ret) { | |
621 | dev_err(dev, "Failed to prepare clk\n"); | |
622 | return ret; | |
623 | } | |
2a96536e KC |
624 | } |
625 | ||
70605870 CK |
626 | data->clk_master = devm_clk_get(dev, "master"); |
627 | if (!IS_ERR(data->clk_master)) { | |
628 | ret = clk_prepare(data->clk_master); | |
629 | if (ret) { | |
630 | clk_unprepare(data->clk); | |
631 | dev_err(dev, "Failed to prepare master's clk\n"); | |
632 | return ret; | |
633 | } | |
634 | } | |
635 | ||
2a96536e | 636 | data->sysmmu = dev; |
9d4e7a24 | 637 | spin_lock_init(&data->lock); |
2a96536e | 638 | |
7222e8db CK |
639 | platform_set_drvdata(pdev, data); |
640 | ||
f4723ec1 | 641 | pm_runtime_enable(dev); |
2a96536e | 642 | |
2a96536e | 643 | return 0; |
2a96536e KC |
644 | } |
645 | ||
6b21a5db CK |
646 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
647 | { .compatible = "samsung,exynos-sysmmu", }, | |
648 | { }, | |
649 | }; | |
650 | ||
651 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
652 | .probe = exynos_sysmmu_probe, | |
653 | .driver = { | |
2a96536e KC |
654 | .owner = THIS_MODULE, |
655 | .name = "exynos-sysmmu", | |
6b21a5db | 656 | .of_match_table = sysmmu_of_match, |
2a96536e KC |
657 | } |
658 | }; | |
659 | ||
660 | static inline void pgtable_flush(void *vastart, void *vaend) | |
661 | { | |
662 | dmac_flush_range(vastart, vaend); | |
663 | outer_flush_range(virt_to_phys(vastart), | |
664 | virt_to_phys(vaend)); | |
665 | } | |
666 | ||
667 | static int exynos_iommu_domain_init(struct iommu_domain *domain) | |
668 | { | |
669 | struct exynos_iommu_domain *priv; | |
670 | ||
671 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
672 | if (!priv) | |
673 | return -ENOMEM; | |
674 | ||
d09d78fc | 675 | priv->pgtable = (sysmmu_pte_t *)__get_free_pages( |
2a96536e KC |
676 | GFP_KERNEL | __GFP_ZERO, 2); |
677 | if (!priv->pgtable) | |
678 | goto err_pgtable; | |
679 | ||
680 | priv->lv2entcnt = (short *)__get_free_pages( | |
681 | GFP_KERNEL | __GFP_ZERO, 1); | |
682 | if (!priv->lv2entcnt) | |
683 | goto err_counter; | |
684 | ||
685 | pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES); | |
686 | ||
687 | spin_lock_init(&priv->lock); | |
688 | spin_lock_init(&priv->pgtablelock); | |
689 | INIT_LIST_HEAD(&priv->clients); | |
690 | ||
eb51637b SK |
691 | domain->geometry.aperture_start = 0; |
692 | domain->geometry.aperture_end = ~0UL; | |
693 | domain->geometry.force_aperture = true; | |
3177bb76 | 694 | |
2a96536e KC |
695 | domain->priv = priv; |
696 | return 0; | |
697 | ||
698 | err_counter: | |
699 | free_pages((unsigned long)priv->pgtable, 2); | |
700 | err_pgtable: | |
701 | kfree(priv); | |
702 | return -ENOMEM; | |
703 | } | |
704 | ||
705 | static void exynos_iommu_domain_destroy(struct iommu_domain *domain) | |
706 | { | |
707 | struct exynos_iommu_domain *priv = domain->priv; | |
6b21a5db | 708 | struct exynos_iommu_owner *owner; |
2a96536e KC |
709 | unsigned long flags; |
710 | int i; | |
711 | ||
712 | WARN_ON(!list_empty(&priv->clients)); | |
713 | ||
714 | spin_lock_irqsave(&priv->lock, flags); | |
715 | ||
6b21a5db CK |
716 | list_for_each_entry(owner, &priv->clients, client) { |
717 | while (!exynos_sysmmu_disable(owner->dev)) | |
2a96536e KC |
718 | ; /* until System MMU is actually disabled */ |
719 | } | |
720 | ||
6b21a5db CK |
721 | while (!list_empty(&priv->clients)) |
722 | list_del_init(priv->clients.next); | |
723 | ||
2a96536e KC |
724 | spin_unlock_irqrestore(&priv->lock, flags); |
725 | ||
726 | for (i = 0; i < NUM_LV1ENTRIES; i++) | |
727 | if (lv1ent_page(priv->pgtable + i)) | |
734c3c73 CK |
728 | kmem_cache_free(lv2table_kmem_cache, |
729 | phys_to_virt(lv2table_base(priv->pgtable + i))); | |
2a96536e KC |
730 | |
731 | free_pages((unsigned long)priv->pgtable, 2); | |
732 | free_pages((unsigned long)priv->lv2entcnt, 1); | |
733 | kfree(domain->priv); | |
734 | domain->priv = NULL; | |
735 | } | |
736 | ||
737 | static int exynos_iommu_attach_device(struct iommu_domain *domain, | |
738 | struct device *dev) | |
739 | { | |
6b21a5db | 740 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
2a96536e | 741 | struct exynos_iommu_domain *priv = domain->priv; |
7222e8db | 742 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e KC |
743 | unsigned long flags; |
744 | int ret; | |
745 | ||
2a96536e KC |
746 | spin_lock_irqsave(&priv->lock, flags); |
747 | ||
6b21a5db | 748 | ret = __exynos_sysmmu_enable(dev, pagetable, domain); |
2a96536e | 749 | if (ret == 0) { |
6b21a5db CK |
750 | list_add_tail(&owner->client, &priv->clients); |
751 | owner->domain = domain; | |
2a96536e KC |
752 | } |
753 | ||
754 | spin_unlock_irqrestore(&priv->lock, flags); | |
755 | ||
756 | if (ret < 0) { | |
7222e8db CK |
757 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
758 | __func__, &pagetable); | |
7222e8db | 759 | return ret; |
2a96536e KC |
760 | } |
761 | ||
7222e8db CK |
762 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
763 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
764 | ||
2a96536e KC |
765 | return ret; |
766 | } | |
767 | ||
768 | static void exynos_iommu_detach_device(struct iommu_domain *domain, | |
769 | struct device *dev) | |
770 | { | |
6b21a5db | 771 | struct exynos_iommu_owner *owner; |
2a96536e | 772 | struct exynos_iommu_domain *priv = domain->priv; |
7222e8db | 773 | phys_addr_t pagetable = virt_to_phys(priv->pgtable); |
2a96536e | 774 | unsigned long flags; |
2a96536e KC |
775 | |
776 | spin_lock_irqsave(&priv->lock, flags); | |
777 | ||
6b21a5db CK |
778 | list_for_each_entry(owner, &priv->clients, client) { |
779 | if (owner == dev->archdata.iommu) { | |
780 | if (exynos_sysmmu_disable(dev)) { | |
781 | list_del_init(&owner->client); | |
782 | owner->domain = NULL; | |
783 | } | |
2a96536e KC |
784 | break; |
785 | } | |
786 | } | |
787 | ||
6b21a5db | 788 | spin_unlock_irqrestore(&priv->lock, flags); |
2a96536e | 789 | |
6b21a5db | 790 | if (owner == dev->archdata.iommu) |
7222e8db CK |
791 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
792 | __func__, &pagetable); | |
6b21a5db CK |
793 | else |
794 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
795 | } |
796 | ||
d09d78fc | 797 | static sysmmu_pte_t *alloc_lv2entry(sysmmu_pte_t *sent, sysmmu_iova_t iova, |
2a96536e KC |
798 | short *pgcounter) |
799 | { | |
61128f08 | 800 | if (lv1ent_section(sent)) { |
d09d78fc | 801 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
802 | return ERR_PTR(-EADDRINUSE); |
803 | } | |
804 | ||
2a96536e | 805 | if (lv1ent_fault(sent)) { |
d09d78fc | 806 | sysmmu_pte_t *pent; |
2a96536e | 807 | |
734c3c73 | 808 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 809 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 810 | if (!pent) |
61128f08 | 811 | return ERR_PTR(-ENOMEM); |
2a96536e | 812 | |
7222e8db | 813 | *sent = mk_lv1ent_page(virt_to_phys(pent)); |
2a96536e KC |
814 | *pgcounter = NUM_LV2ENTRIES; |
815 | pgtable_flush(pent, pent + NUM_LV2ENTRIES); | |
816 | pgtable_flush(sent, sent + 1); | |
817 | } | |
818 | ||
819 | return page_entry(sent, iova); | |
820 | } | |
821 | ||
d09d78fc | 822 | static int lv1set_section(sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 823 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 824 | { |
61128f08 | 825 | if (lv1ent_section(sent)) { |
d09d78fc | 826 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 827 | iova); |
2a96536e | 828 | return -EADDRINUSE; |
61128f08 | 829 | } |
2a96536e KC |
830 | |
831 | if (lv1ent_page(sent)) { | |
61128f08 | 832 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 833 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 834 | iova); |
2a96536e | 835 | return -EADDRINUSE; |
61128f08 | 836 | } |
2a96536e | 837 | |
734c3c73 | 838 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
839 | *pgcnt = 0; |
840 | } | |
841 | ||
842 | *sent = mk_lv1ent_sect(paddr); | |
843 | ||
844 | pgtable_flush(sent, sent + 1); | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
d09d78fc | 849 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
850 | short *pgcnt) |
851 | { | |
852 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 853 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
854 | return -EADDRINUSE; |
855 | ||
856 | *pent = mk_lv2ent_spage(paddr); | |
857 | pgtable_flush(pent, pent + 1); | |
858 | *pgcnt -= 1; | |
859 | } else { /* size == LPAGE_SIZE */ | |
860 | int i; | |
861 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { | |
0bf4e54d | 862 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
863 | if (i > 0) |
864 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
865 | return -EADDRINUSE; |
866 | } | |
867 | ||
868 | *pent = mk_lv2ent_lpage(paddr); | |
869 | } | |
870 | pgtable_flush(pent - SPAGES_PER_LPAGE, pent); | |
871 | *pgcnt -= SPAGES_PER_LPAGE; | |
872 | } | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
d09d78fc | 877 | static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova, |
2a96536e KC |
878 | phys_addr_t paddr, size_t size, int prot) |
879 | { | |
880 | struct exynos_iommu_domain *priv = domain->priv; | |
d09d78fc CK |
881 | sysmmu_pte_t *entry; |
882 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
883 | unsigned long flags; |
884 | int ret = -ENOMEM; | |
885 | ||
886 | BUG_ON(priv->pgtable == NULL); | |
887 | ||
888 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
889 | ||
890 | entry = section_entry(priv->pgtable, iova); | |
891 | ||
892 | if (size == SECT_SIZE) { | |
61128f08 | 893 | ret = lv1set_section(entry, iova, paddr, |
2a96536e KC |
894 | &priv->lv2entcnt[lv1ent_offset(iova)]); |
895 | } else { | |
d09d78fc | 896 | sysmmu_pte_t *pent; |
2a96536e KC |
897 | |
898 | pent = alloc_lv2entry(entry, iova, | |
899 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
900 | ||
61128f08 CK |
901 | if (IS_ERR(pent)) |
902 | ret = PTR_ERR(pent); | |
2a96536e KC |
903 | else |
904 | ret = lv2set_page(pent, paddr, size, | |
905 | &priv->lv2entcnt[lv1ent_offset(iova)]); | |
906 | } | |
907 | ||
61128f08 | 908 | if (ret) |
0bf4e54d CK |
909 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
910 | __func__, ret, size, iova); | |
2a96536e KC |
911 | |
912 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
913 | ||
914 | return ret; | |
915 | } | |
916 | ||
917 | static size_t exynos_iommu_unmap(struct iommu_domain *domain, | |
d09d78fc | 918 | unsigned long l_iova, size_t size) |
2a96536e KC |
919 | { |
920 | struct exynos_iommu_domain *priv = domain->priv; | |
6b21a5db | 921 | struct exynos_iommu_owner *owner; |
d09d78fc CK |
922 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
923 | sysmmu_pte_t *ent; | |
61128f08 | 924 | size_t err_pgsize; |
d09d78fc | 925 | unsigned long flags; |
2a96536e KC |
926 | |
927 | BUG_ON(priv->pgtable == NULL); | |
928 | ||
929 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
930 | ||
931 | ent = section_entry(priv->pgtable, iova); | |
932 | ||
933 | if (lv1ent_section(ent)) { | |
0bf4e54d | 934 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
935 | err_pgsize = SECT_SIZE; |
936 | goto err; | |
937 | } | |
2a96536e KC |
938 | |
939 | *ent = 0; | |
940 | pgtable_flush(ent, ent + 1); | |
941 | size = SECT_SIZE; | |
942 | goto done; | |
943 | } | |
944 | ||
945 | if (unlikely(lv1ent_fault(ent))) { | |
946 | if (size > SECT_SIZE) | |
947 | size = SECT_SIZE; | |
948 | goto done; | |
949 | } | |
950 | ||
951 | /* lv1ent_page(sent) == true here */ | |
952 | ||
953 | ent = page_entry(ent, iova); | |
954 | ||
955 | if (unlikely(lv2ent_fault(ent))) { | |
956 | size = SPAGE_SIZE; | |
957 | goto done; | |
958 | } | |
959 | ||
960 | if (lv2ent_small(ent)) { | |
961 | *ent = 0; | |
962 | size = SPAGE_SIZE; | |
6cb47ed7 | 963 | pgtable_flush(ent, ent + 1); |
2a96536e KC |
964 | priv->lv2entcnt[lv1ent_offset(iova)] += 1; |
965 | goto done; | |
966 | } | |
967 | ||
968 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 969 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
970 | err_pgsize = LPAGE_SIZE; |
971 | goto err; | |
972 | } | |
2a96536e KC |
973 | |
974 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); | |
6cb47ed7 | 975 | pgtable_flush(ent, ent + SPAGES_PER_LPAGE); |
2a96536e KC |
976 | |
977 | size = LPAGE_SIZE; | |
978 | priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; | |
979 | done: | |
980 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
981 | ||
982 | spin_lock_irqsave(&priv->lock, flags); | |
6b21a5db CK |
983 | list_for_each_entry(owner, &priv->clients, client) |
984 | sysmmu_tlb_invalidate_entry(owner->dev, iova, size); | |
2a96536e KC |
985 | spin_unlock_irqrestore(&priv->lock, flags); |
986 | ||
2a96536e | 987 | return size; |
61128f08 CK |
988 | err: |
989 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
990 | ||
0bf4e54d CK |
991 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
992 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
993 | |
994 | return 0; | |
2a96536e KC |
995 | } |
996 | ||
997 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 998 | dma_addr_t iova) |
2a96536e KC |
999 | { |
1000 | struct exynos_iommu_domain *priv = domain->priv; | |
d09d78fc | 1001 | sysmmu_pte_t *entry; |
2a96536e KC |
1002 | unsigned long flags; |
1003 | phys_addr_t phys = 0; | |
1004 | ||
1005 | spin_lock_irqsave(&priv->pgtablelock, flags); | |
1006 | ||
1007 | entry = section_entry(priv->pgtable, iova); | |
1008 | ||
1009 | if (lv1ent_section(entry)) { | |
1010 | phys = section_phys(entry) + section_offs(iova); | |
1011 | } else if (lv1ent_page(entry)) { | |
1012 | entry = page_entry(entry, iova); | |
1013 | ||
1014 | if (lv2ent_large(entry)) | |
1015 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1016 | else if (lv2ent_small(entry)) | |
1017 | phys = spage_phys(entry) + spage_offs(iova); | |
1018 | } | |
1019 | ||
1020 | spin_unlock_irqrestore(&priv->pgtablelock, flags); | |
1021 | ||
1022 | return phys; | |
1023 | } | |
1024 | ||
bf4a1c92 AM |
1025 | static int exynos_iommu_add_device(struct device *dev) |
1026 | { | |
1027 | struct iommu_group *group; | |
1028 | int ret; | |
1029 | ||
1030 | group = iommu_group_get(dev); | |
1031 | ||
1032 | if (!group) { | |
1033 | group = iommu_group_alloc(); | |
1034 | if (IS_ERR(group)) { | |
1035 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1036 | return PTR_ERR(group); | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | ret = iommu_group_add_device(group, dev); | |
1041 | iommu_group_put(group); | |
1042 | ||
1043 | return ret; | |
1044 | } | |
1045 | ||
1046 | static void exynos_iommu_remove_device(struct device *dev) | |
1047 | { | |
1048 | iommu_group_remove_device(dev); | |
1049 | } | |
1050 | ||
2a96536e KC |
1051 | static struct iommu_ops exynos_iommu_ops = { |
1052 | .domain_init = &exynos_iommu_domain_init, | |
1053 | .domain_destroy = &exynos_iommu_domain_destroy, | |
1054 | .attach_dev = &exynos_iommu_attach_device, | |
1055 | .detach_dev = &exynos_iommu_detach_device, | |
1056 | .map = &exynos_iommu_map, | |
1057 | .unmap = &exynos_iommu_unmap, | |
1058 | .iova_to_phys = &exynos_iommu_iova_to_phys, | |
bf4a1c92 AM |
1059 | .add_device = &exynos_iommu_add_device, |
1060 | .remove_device = &exynos_iommu_remove_device, | |
2a96536e KC |
1061 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
1062 | }; | |
1063 | ||
1064 | static int __init exynos_iommu_init(void) | |
1065 | { | |
1066 | int ret; | |
1067 | ||
734c3c73 CK |
1068 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1069 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1070 | if (!lv2table_kmem_cache) { | |
1071 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1072 | return -ENOMEM; | |
1073 | } | |
1074 | ||
2a96536e | 1075 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1076 | if (ret) { |
1077 | pr_err("%s: Failed to register driver\n", __func__); | |
1078 | goto err_reg_driver; | |
1079 | } | |
2a96536e | 1080 | |
734c3c73 CK |
1081 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1082 | if (ret) { | |
1083 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1084 | __func__); | |
1085 | goto err_set_iommu; | |
1086 | } | |
2a96536e | 1087 | |
734c3c73 CK |
1088 | return 0; |
1089 | err_set_iommu: | |
1090 | platform_driver_unregister(&exynos_sysmmu_driver); | |
1091 | err_reg_driver: | |
1092 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1093 | return ret; |
1094 | } | |
1095 | subsys_initcall(exynos_iommu_init); |