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Merge branch 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvar...
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
134fac3f 39#include <linux/syscore_ops.h>
69575d38 40#include <linux/tboot.h>
adb2fe02 41#include <linux/dmi.h>
5cdede24 42#include <linux/pci-ats.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
5b6985ce
FY		 46#define ROOT_SIZE VTD_PAGE_SIZE
47#define CONTEXT_SIZE VTD_PAGE_SIZE
48
825507d6
MT		 49#define IS_BRIDGE_HOST_DEVICE(pdev) \
50 ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
ba395927
KA		 51#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
52#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 53#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 54
55#define IOAPIC_RANGE_START (0xfee00000)
56#define IOAPIC_RANGE_END (0xfeefffff)
57#define IOVA_START_ADDR (0x1000)
58
59#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
60
4ed0d3e6
FY		 61#define MAX_AGAW_WIDTH 64
62
2ebe3151
DW		 63#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
64#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
65
66/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
67 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
68#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
69 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
70#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 71
f27be03b 72#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 73#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 74#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 75
df08cdc7
AM		 76/* page table handling */
77#define LEVEL_STRIDE (9)
78#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
79
80static inline int agaw_to_level(int agaw)
81{
82 return agaw + 2;
83}
84
85static inline int agaw_to_width(int agaw)
86{
87 return 30 + agaw * LEVEL_STRIDE;
88}
89
90static inline int width_to_agaw(int width)
91{
92 return (width - 30) / LEVEL_STRIDE;
93}
94
95static inline unsigned int level_to_offset_bits(int level)
96{
97 return (level - 1) * LEVEL_STRIDE;
98}
99
100static inline int pfn_level_offset(unsigned long pfn, int level)
101{
102 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
103}
104
105static inline unsigned long level_mask(int level)
106{
107 return -1UL << level_to_offset_bits(level);
108}
109
110static inline unsigned long level_size(int level)
111{
112 return 1UL << level_to_offset_bits(level);
113}
114
115static inline unsigned long align_to_level(unsigned long pfn, int level)
116{
117 return (pfn + level_size(level) - 1) & level_mask(level);
118}
fd18de50 119
6dd9a7c7
YS		 120static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
121{
122 return 1 << ((lvl - 1) * LEVEL_STRIDE);
123}
124
dd4e8319
DW		 125/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
126 are never going to work. */
127static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
128{
129 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
130}
131
132static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
133{
134 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
135}
136static inline unsigned long page_to_dma_pfn(struct page *pg)
137{
138 return mm_to_dma_pfn(page_to_pfn(pg));
139}
140static inline unsigned long virt_to_dma_pfn(void *p)
141{
142 return page_to_dma_pfn(virt_to_page(p));
143}
144
d9630fe9
WH		 145/* global iommu list, set NULL for ignored DMAR units */
146static struct intel_iommu **g_iommus;
147
e0fc7e0b 148static void __init check_tylersburg_isoch(void);
9af88143
DW		 149static int rwbf_quirk;
150
b779260b
JC		 151/*
152 * set to 1 to panic kernel if can't successfully enable VT-d
153 * (used when kernel is launched w/ TXT)
154 */
155static int force_on = 0;
156
46b08e1a
MM		 157/*
158 * 0: Present
159 * 1-11: Reserved
160 * 12-63: Context Ptr (12 - (haw-1))
161 * 64-127: Reserved
162 */
163struct root_entry {
164 u64 val;
165 u64 rsvd1;
166};
167#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
168static inline bool root_present(struct root_entry *root)
169{
170 return (root->val & 1);
171}
172static inline void set_root_present(struct root_entry *root)
173{
174 root->val |= 1;
175}
176static inline void set_root_value(struct root_entry *root, unsigned long value)
177{
178 root->val |= value & VTD_PAGE_MASK;
179}
180
181static inline struct context_entry *
182get_context_addr_from_root(struct root_entry *root)
183{
184 return (struct context_entry *)
185 (root_present(root)?phys_to_virt(
186 root->val & VTD_PAGE_MASK) :
187 NULL);
188}
189
7a8fc25e
MM		 190/*
191 * low 64 bits:
192 * 0: present
193 * 1: fault processing disable
194 * 2-3: translation type
195 * 12-63: address space root
196 * high 64 bits:
197 * 0-2: address width
198 * 3-6: aval
199 * 8-23: domain id
200 */
201struct context_entry {
202 u64 lo;
203 u64 hi;
204};
c07e7d21
MM		 205
206static inline bool context_present(struct context_entry *context)
207{
208 return (context->lo & 1);
209}
210static inline void context_set_present(struct context_entry *context)
211{
212 context->lo |= 1;
213}
214
215static inline void context_set_fault_enable(struct context_entry *context)
216{
217 context->lo &= (((u64)-1) << 2) | 1;
218}
219
c07e7d21
MM		 220static inline void context_set_translation_type(struct context_entry *context,
221 unsigned long value)
222{
223 context->lo &= (((u64)-1) << 4) | 3;
224 context->lo |= (value & 3) << 2;
225}
226
227static inline void context_set_address_root(struct context_entry *context,
228 unsigned long value)
229{
230 context->lo |= value & VTD_PAGE_MASK;
231}
232
233static inline void context_set_address_width(struct context_entry *context,
234 unsigned long value)
235{
236 context->hi |= value & 7;
237}
238
239static inline void context_set_domain_id(struct context_entry *context,
240 unsigned long value)
241{
242 context->hi |= (value & ((1 << 16) - 1)) << 8;
243}
244
245static inline void context_clear_entry(struct context_entry *context)
246{
247 context->lo = 0;
248 context->hi = 0;
249}
7a8fc25e 250
622ba12a
MM		 251/*
252 * 0: readable
253 * 1: writable
254 * 2-6: reserved
255 * 7: super page
9cf06697
SY		 256 * 8-10: available
257 * 11: snoop behavior
622ba12a
MM		 258 * 12-63: Host physcial address
259 */
260struct dma_pte {
261 u64 val;
262};
622ba12a 263
19c239ce
MM		 264static inline void dma_clear_pte(struct dma_pte *pte)
265{
266 pte->val = 0;
267}
268
269static inline void dma_set_pte_readable(struct dma_pte *pte)
270{
271 pte->val |= DMA_PTE_READ;
272}
273
274static inline void dma_set_pte_writable(struct dma_pte *pte)
275{
276 pte->val |= DMA_PTE_WRITE;
277}
278
9cf06697
SY		 279static inline void dma_set_pte_snp(struct dma_pte *pte)
280{
281 pte->val |= DMA_PTE_SNP;
282}
283
19c239ce
MM		 284static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
285{
286 pte->val = (pte->val & ~3) | (prot & 3);
287}
288
289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
dd4e8319 299static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 300{
dd4e8319 301 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 302}
303
304static inline bool dma_pte_present(struct dma_pte *pte)
305{
306 return (pte->val & 3) != 0;
307}
622ba12a 308
4399c8bf
AK		 309static inline bool dma_pte_superpage(struct dma_pte *pte)
310{
311 return (pte->val & (1 << 7));
312}
313
75e6bf96
DW		 314static inline int first_pte_in_page(struct dma_pte *pte)
315{
316 return !((unsigned long)pte & ~VTD_PAGE_MASK);
317}
318
2c2e2c38
FY		 319/*
320 * This domain is a statically identity mapping domain.
321 * 1. This domain creats a static 1:1 mapping to all usable memory.
322 * 2. It maps to each iommu if successful.
323 * 3. Each iommu mapps to this domain if successful.
324 */
19943b0e
DW		 325static struct dmar_domain *si_domain;
326static int hw_pass_through = 1;
2c2e2c38 327
3b5410e7 328/* devices under the same p2p bridge are owned in one domain */
cdc7b837 329#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 330
1ce28feb
WH		 331/* domain represents a virtual machine, more than one devices
332 * across iommus may be owned in one domain, e.g. kvm guest.
333 */
334#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
335
2c2e2c38
FY		 336/* si_domain contains mulitple devices */
337#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
338
99126f7c
MM		 339struct dmar_domain {
340 int id; /* domain id */
4c923d47 341 int nid; /* node id */
8c11e798 342 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 343
344 struct list_head devices; /* all devices' list */
345 struct iova_domain iovad; /* iova's that belong to this domain */
346
347 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 348 int gaw; /* max guest address width */
349
350 /* adjusted guest address width, 0 is level 2 30-bit */
351 int agaw;
352
3b5410e7 353 int flags; /* flags to find out type of domain */
8e604097
WH		 354
355 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 356 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 357 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 358 int iommu_superpage;/* Level of superpages supported:
359 0 == 4KiB (no superpages), 1 == 2MiB,
360 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 361 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 362 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 363};
364
a647dacb
MM		 365/* PCI domain-device relationship */
366struct device_domain_info {
367 struct list_head link; /* link to domain siblings */
368 struct list_head global; /* link to global list */
276dbf99
DW		 369 int segment; /* PCI domain */
370 u8 bus; /* PCI bus number */
a647dacb 371 u8 devfn; /* PCI devfn number */
45e829ea 372 struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 373 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 374 struct dmar_domain *domain; /* pointer to domain */
375};
376
5e0d2a6f 377static void flush_unmaps_timeout(unsigned long data);
378
379DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
380
80b20dd8 381#define HIGH_WATER_MARK 250
382struct deferred_flush_tables {
383 int next;
384 struct iova *iova[HIGH_WATER_MARK];
385 struct dmar_domain *domain[HIGH_WATER_MARK];
386};
387
388static struct deferred_flush_tables *deferred_flush;
389
5e0d2a6f 390/* bitmap for indexing intel_iommus */
5e0d2a6f 391static int g_num_of_iommus;
392
393static DEFINE_SPINLOCK(async_umap_flush_lock);
394static LIST_HEAD(unmaps_to_do);
395
396static int timer_on;
397static long list_size;
5e0d2a6f 398
ba395927
KA		 399static void domain_remove_dev_info(struct dmar_domain *domain);
400
d3f13810 401#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 402int dmar_disabled = 0;
403#else
404int dmar_disabled = 1;
d3f13810 405#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 406
2d9e667e 407static int dmar_map_gfx = 1;
7d3b03ce 408static int dmar_forcedac;
5e0d2a6f 409static int intel_iommu_strict;
6dd9a7c7 410static int intel_iommu_superpage = 1;
ba395927 411
c0771df8
DW		 412int intel_iommu_gfx_mapped;
413EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
414
ba395927
KA		 415#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
416static DEFINE_SPINLOCK(device_domain_lock);
417static LIST_HEAD(device_domain_list);
418
a8bcbb0d
JR		 419static struct iommu_ops intel_iommu_ops;
420
ba395927
KA		 421static int __init intel_iommu_setup(char *str)
422{
423 if (!str)
424 return -EINVAL;
425 while (*str) {
0cd5c3c8
KM		 426 if (!strncmp(str, "on", 2)) {
427 dmar_disabled = 0;
428 printk(KERN_INFO "Intel-IOMMU: enabled\n");
429 } else if (!strncmp(str, "off", 3)) {
ba395927 430 dmar_disabled = 1;
0cd5c3c8 431 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 432 } else if (!strncmp(str, "igfx_off", 8)) {
433 dmar_map_gfx = 0;
434 printk(KERN_INFO
435 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 436 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 437 printk(KERN_INFO
7d3b03ce
KA		 438 "Intel-IOMMU: Forcing DAC for PCI devices\n");
439 dmar_forcedac = 1;
5e0d2a6f 440 } else if (!strncmp(str, "strict", 6)) {
441 printk(KERN_INFO
442 "Intel-IOMMU: disable batched IOTLB flush\n");
443 intel_iommu_strict = 1;
6dd9a7c7
YS		 444 } else if (!strncmp(str, "sp_off", 6)) {
445 printk(KERN_INFO
446 "Intel-IOMMU: disable supported super page\n");
447 intel_iommu_superpage = 0;
ba395927
KA		 448 }
449
450 str += strcspn(str, ",");
451 while (*str == ',')
452 str++;
453 }
454 return 0;
455}
456__setup("intel_iommu=", intel_iommu_setup);
457
458static struct kmem_cache *iommu_domain_cache;
459static struct kmem_cache *iommu_devinfo_cache;
460static struct kmem_cache *iommu_iova_cache;
461
4c923d47 462static inline void *alloc_pgtable_page(int node)
eb3fa7cb 463{
4c923d47
SS		 464 struct page *page;
465 void *vaddr = NULL;
eb3fa7cb 466
4c923d47
SS		 467 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
468 if (page)
469 vaddr = page_address(page);
eb3fa7cb 470 return vaddr;
ba395927
KA		 471}
472
473static inline void free_pgtable_page(void *vaddr)
474{
475 free_page((unsigned long)vaddr);
476}
477
478static inline void *alloc_domain_mem(void)
479{
354bb65e 480 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 481}
482
38717946 483static void free_domain_mem(void *vaddr)
ba395927
KA		 484{
485 kmem_cache_free(iommu_domain_cache, vaddr);
486}
487
488static inline void * alloc_devinfo_mem(void)
489{
354bb65e 490 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 491}
492
493static inline void free_devinfo_mem(void *vaddr)
494{
495 kmem_cache_free(iommu_devinfo_cache, vaddr);
496}
497
498struct iova *alloc_iova_mem(void)
499{
354bb65e 500 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 501}
502
503void free_iova_mem(struct iova *iova)
504{
505 kmem_cache_free(iommu_iova_cache, iova);
506}
507
1b573683 508
4ed0d3e6 509static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 510{
511 unsigned long sagaw;
512 int agaw = -1;
513
514 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 515 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 516 agaw >= 0; agaw--) {
517 if (test_bit(agaw, &sagaw))
518 break;
519 }
520
521 return agaw;
522}
523
4ed0d3e6
FY		 524/*
525 * Calculate max SAGAW for each iommu.
526 */
527int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
528{
529 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
530}
531
532/*
533 * calculate agaw for each iommu.
534 * "SAGAW" may be different across iommus, use a default agaw, and
535 * get a supported less agaw for iommus that don't support the default agaw.
536 */
537int iommu_calculate_agaw(struct intel_iommu *iommu)
538{
539 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
540}
541
2c2e2c38 542/* This functionin only returns single iommu in a domain */
8c11e798
WH		 543static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
544{
545 int iommu_id;
546
2c2e2c38 547 /* si_domain and vm domain should not get here. */
1ce28feb 548 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 549 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 550
8c11e798
WH		 551 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
552 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
553 return NULL;
554
555 return g_iommus[iommu_id];
556}
557
8e604097
WH		 558static void domain_update_iommu_coherency(struct dmar_domain *domain)
559{
560 int i;
561
562 domain->iommu_coherency = 1;
563
a45946ab 564 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
8e604097
WH		 565 if (!ecap_coherent(g_iommus[i]->ecap)) {
566 domain->iommu_coherency = 0;
567 break;
568 }
8e604097
WH		 569 }
570}
571
58c610bd
SY		 572static void domain_update_iommu_snooping(struct dmar_domain *domain)
573{
574 int i;
575
576 domain->iommu_snooping = 1;
577
a45946ab 578 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 579 if (!ecap_sc_support(g_iommus[i]->ecap)) {
580 domain->iommu_snooping = 0;
581 break;
582 }
58c610bd
SY		 583 }
584}
585
6dd9a7c7
YS		 586static void domain_update_iommu_superpage(struct dmar_domain *domain)
587{
8140a95d
AK		 588 struct dmar_drhd_unit *drhd;
589 struct intel_iommu *iommu = NULL;
590 int mask = 0xf;
6dd9a7c7
YS		 591
592 if (!intel_iommu_superpage) {
593 domain->iommu_superpage = 0;
594 return;
595 }
596
8140a95d
AK		 597 /* set iommu_superpage to the smallest common denominator */
598 for_each_active_iommu(iommu, drhd) {
599 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 600 if (!mask) {
601 break;
602 }
603 }
604 domain->iommu_superpage = fls(mask);
605}
606
58c610bd
SY		 607/* Some capabilities may be different across iommus */
608static void domain_update_iommu_cap(struct dmar_domain *domain)
609{
610 domain_update_iommu_coherency(domain);
611 domain_update_iommu_snooping(domain);
6dd9a7c7 612 domain_update_iommu_superpage(domain);
58c610bd
SY		 613}
614
276dbf99 615static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 616{
617 struct dmar_drhd_unit *drhd = NULL;
618 int i;
619
620 for_each_drhd_unit(drhd) {
621 if (drhd->ignored)
622 continue;
276dbf99
DW		 623 if (segment != drhd->segment)
624 continue;
c7151a8d 625
924b6231 626 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 627 if (drhd->devices[i] &&
628 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 629 drhd->devices[i]->devfn == devfn)
630 return drhd->iommu;
4958c5dc
DW		 631 if (drhd->devices[i] &&
632 drhd->devices[i]->subordinate &&
924b6231
DW		 633 drhd->devices[i]->subordinate->number <= bus &&
634 drhd->devices[i]->subordinate->subordinate >= bus)
635 return drhd->iommu;
636 }
c7151a8d
WH		 637
638 if (drhd->include_all)
639 return drhd->iommu;
640 }
641
642 return NULL;
643}
644
5331fe6f
WH		 645static void domain_flush_cache(struct dmar_domain *domain,
646 void *addr, int size)
647{
648 if (!domain->iommu_coherency)
649 clflush_cache_range(addr, size);
650}
651
ba395927
KA		 652/* Gets context entry for a given bus and devfn */
653static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
654 u8 bus, u8 devfn)
655{
656 struct root_entry *root;
657 struct context_entry *context;
658 unsigned long phy_addr;
659 unsigned long flags;
660
661 spin_lock_irqsave(&iommu->lock, flags);
662 root = &iommu->root_entry[bus];
663 context = get_context_addr_from_root(root);
664 if (!context) {
4c923d47
SS		 665 context = (struct context_entry *)
666 alloc_pgtable_page(iommu->node);
ba395927
KA		 667 if (!context) {
668 spin_unlock_irqrestore(&iommu->lock, flags);
669 return NULL;
670 }
5b6985ce 671 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 672 phy_addr = virt_to_phys((void *)context);
673 set_root_value(root, phy_addr);
674 set_root_present(root);
675 __iommu_flush_cache(iommu, root, sizeof(*root));
676 }
677 spin_unlock_irqrestore(&iommu->lock, flags);
678 return &context[devfn];
679}
680
681static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
682{
683 struct root_entry *root;
684 struct context_entry *context;
685 int ret;
686 unsigned long flags;
687
688 spin_lock_irqsave(&iommu->lock, flags);
689 root = &iommu->root_entry[bus];
690 context = get_context_addr_from_root(root);
691 if (!context) {
692 ret = 0;
693 goto out;
694 }
c07e7d21 695 ret = context_present(&context[devfn]);
ba395927
KA		 696out:
697 spin_unlock_irqrestore(&iommu->lock, flags);
698 return ret;
699}
700
701static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
702{
703 struct root_entry *root;
704 struct context_entry *context;
705 unsigned long flags;
706
707 spin_lock_irqsave(&iommu->lock, flags);
708 root = &iommu->root_entry[bus];
709 context = get_context_addr_from_root(root);
710 if (context) {
c07e7d21 711 context_clear_entry(&context[devfn]);
ba395927
KA		 712 __iommu_flush_cache(iommu, &context[devfn], \
713 sizeof(*context));
714 }
715 spin_unlock_irqrestore(&iommu->lock, flags);
716}
717
718static void free_context_table(struct intel_iommu *iommu)
719{
720 struct root_entry *root;
721 int i;
722 unsigned long flags;
723 struct context_entry *context;
724
725 spin_lock_irqsave(&iommu->lock, flags);
726 if (!iommu->root_entry) {
727 goto out;
728 }
729 for (i = 0; i < ROOT_ENTRY_NR; i++) {
730 root = &iommu->root_entry[i];
731 context = get_context_addr_from_root(root);
732 if (context)
733 free_pgtable_page(context);
734 }
735 free_pgtable_page(iommu->root_entry);
736 iommu->root_entry = NULL;
737out:
738 spin_unlock_irqrestore(&iommu->lock, flags);
739}
740
b026fd28 741static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
4399c8bf 742 unsigned long pfn, int target_level)
ba395927 743{
b026fd28 744 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 745 struct dma_pte *parent, *pte = NULL;
746 int level = agaw_to_level(domain->agaw);
4399c8bf 747 int offset;
ba395927
KA		 748
749 BUG_ON(!domain->pgd);
b026fd28 750 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 751 parent = domain->pgd;
752
ba395927
KA		 753 while (level > 0) {
754 void *tmp_page;
755
b026fd28 756 offset = pfn_level_offset(pfn, level);
ba395927 757 pte = &parent[offset];
4399c8bf 758 if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7
YS		 759 break;
760 if (level == target_level)
ba395927
KA		 761 break;
762
19c239ce 763 if (!dma_pte_present(pte)) {
c85994e4
DW		 764 uint64_t pteval;
765
4c923d47 766 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 767
206a73c1 768 if (!tmp_page)
ba395927 769 return NULL;
206a73c1 770
c85994e4 771 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 772 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 773 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
774 /* Someone else set it while we were thinking; use theirs. */
775 free_pgtable_page(tmp_page);
776 } else {
777 dma_pte_addr(pte);
778 domain_flush_cache(domain, pte, sizeof(*pte));
779 }
ba395927 780 }
19c239ce 781 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 782 level--;
783 }
784
ba395927
KA		 785 return pte;
786}
787
6dd9a7c7 788
ba395927 789/* return address's pte at specific level */
90dcfb5e
DW		 790static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
791 unsigned long pfn,
6dd9a7c7 792 int level, int *large_page)
ba395927
KA		 793{
794 struct dma_pte *parent, *pte = NULL;
795 int total = agaw_to_level(domain->agaw);
796 int offset;
797
798 parent = domain->pgd;
799 while (level <= total) {
90dcfb5e 800 offset = pfn_level_offset(pfn, total);
ba395927
KA		 801 pte = &parent[offset];
802 if (level == total)
803 return pte;
804
6dd9a7c7
YS		 805 if (!dma_pte_present(pte)) {
806 *large_page = total;
ba395927 807 break;
6dd9a7c7
YS		 808 }
809
810 if (pte->val & DMA_PTE_LARGE_PAGE) {
811 *large_page = total;
812 return pte;
813 }
814
19c239ce 815 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 816 total--;
817 }
818 return NULL;
819}
820
ba395927 821/* clear last level pte, a tlb flush should be followed */
292827cb 822static int dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 823 unsigned long start_pfn,
824 unsigned long last_pfn)
ba395927 825{
04b18e65 826 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 827 unsigned int large_page = 1;
310a5ab9 828 struct dma_pte *first_pte, *pte;
292827cb 829 int order;
66eae846 830
04b18e65 831 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 832 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 833 BUG_ON(start_pfn > last_pfn);
ba395927 834
04b18e65 835 /* we don't need lock here; nobody else touches the iova range */
59c36286 836 do {
6dd9a7c7
YS		 837 large_page = 1;
838 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 839 if (!pte) {
6dd9a7c7 840 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 841 continue;
842 }
6dd9a7c7 843 do {
310a5ab9 844 dma_clear_pte(pte);
6dd9a7c7 845 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 846 pte++;
75e6bf96
DW		 847 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
848
310a5ab9
DW		 849 domain_flush_cache(domain, first_pte,
850 (void *)pte - (void *)first_pte);
59c36286
DW		 851
852 } while (start_pfn && start_pfn <= last_pfn);
292827cb
AK		 853
854 order = (large_page - 1) * 9;
855 return order;
ba395927
KA		 856}
857
858/* free page table pages. last level pte should already be cleared */
859static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 860 unsigned long start_pfn,
861 unsigned long last_pfn)
ba395927 862{
6660c63a 863 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 864 struct dma_pte *first_pte, *pte;
ba395927
KA		 865 int total = agaw_to_level(domain->agaw);
866 int level;
6660c63a 867 unsigned long tmp;
6dd9a7c7 868 int large_page = 2;
ba395927 869
6660c63a
DW		 870 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
871 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 872 BUG_ON(start_pfn > last_pfn);
ba395927 873
f3a0a52f 874 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 875 level = 2;
876 while (level <= total) {
6660c63a
DW		 877 tmp = align_to_level(start_pfn, level);
878
f3a0a52f 879 /* If we can't even clear one PTE at this level, we're done */
6660c63a 880 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 881 return;
882
59c36286 883 do {
6dd9a7c7
YS		 884 large_page = level;
885 first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
886 if (large_page > level)
887 level = large_page + 1;
f3a0a52f
DW		 888 if (!pte) {
889 tmp = align_to_level(tmp + 1, level + 1);
890 continue;
891 }
75e6bf96 892 do {
6a43e574
DW		 893 if (dma_pte_present(pte)) {
894 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
895 dma_clear_pte(pte);
896 }
f3a0a52f
DW		 897 pte++;
898 tmp += level_size(level);
75e6bf96
DW		 899 } while (!first_pte_in_page(pte) &&
900 tmp + level_size(level) - 1 <= last_pfn);
901
f3a0a52f
DW		 902 domain_flush_cache(domain, first_pte,
903 (void *)pte - (void *)first_pte);
904
59c36286 905 } while (tmp && tmp + level_size(level) - 1 <= last_pfn);
ba395927
KA		 906 level++;
907 }
908 /* free pgd */
d794dc9b 909 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 910 free_pgtable_page(domain->pgd);
911 domain->pgd = NULL;
912 }
913}
914
915/* iommu handling */
916static int iommu_alloc_root_entry(struct intel_iommu *iommu)
917{
918 struct root_entry *root;
919 unsigned long flags;
920
4c923d47 921 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 922 if (!root)
923 return -ENOMEM;
924
5b6985ce 925 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 926
927 spin_lock_irqsave(&iommu->lock, flags);
928 iommu->root_entry = root;
929 spin_unlock_irqrestore(&iommu->lock, flags);
930
931 return 0;
932}
933
ba395927
KA		 934static void iommu_set_root_entry(struct intel_iommu *iommu)
935{
936 void *addr;
c416daa9 937 u32 sts;
ba395927
KA		 938 unsigned long flag;
939
940 addr = iommu->root_entry;
941
1f5b3c3f 942 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 943 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
944
c416daa9 945 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 946
947 /* Make sure hardware complete it */
948 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 949 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 950
1f5b3c3f 951 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 952}
953
954static void iommu_flush_write_buffer(struct intel_iommu *iommu)
955{
956 u32 val;
957 unsigned long flag;
958
9af88143 959 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 960 return;
ba395927 961
1f5b3c3f 962 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 963 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 964
965 /* Make sure hardware complete it */
966 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 967 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 968
1f5b3c3f 969 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 970}
971
972/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 973static void __iommu_flush_context(struct intel_iommu *iommu,
974 u16 did, u16 source_id, u8 function_mask,
975 u64 type)
ba395927
KA		 976{
977 u64 val = 0;
978 unsigned long flag;
979
ba395927
KA		 980 switch (type) {
981 case DMA_CCMD_GLOBAL_INVL:
982 val = DMA_CCMD_GLOBAL_INVL;
983 break;
984 case DMA_CCMD_DOMAIN_INVL:
985 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
986 break;
987 case DMA_CCMD_DEVICE_INVL:
988 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
989 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
990 break;
991 default:
992 BUG();
993 }
994 val |= DMA_CCMD_ICC;
995
1f5b3c3f 996 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 997 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
998
999 /* Make sure hardware complete it */
1000 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1001 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1002
1f5b3c3f 1003 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1004}
1005
ba395927 1006/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1007static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1008 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1009{
1010 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1011 u64 val = 0, val_iva = 0;
1012 unsigned long flag;
1013
ba395927
KA		 1014 switch (type) {
1015 case DMA_TLB_GLOBAL_FLUSH:
1016 /* global flush doesn't need set IVA_REG */
1017 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1018 break;
1019 case DMA_TLB_DSI_FLUSH:
1020 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1021 break;
1022 case DMA_TLB_PSI_FLUSH:
1023 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1024 /* Note: always flush non-leaf currently */
1025 val_iva = size_order | addr;
1026 break;
1027 default:
1028 BUG();
1029 }
1030 /* Note: set drain read/write */
1031#if 0
1032 /*
1033 * This is probably to be super secure.. Looks like we can
1034 * ignore it without any impact.
1035 */
1036 if (cap_read_drain(iommu->cap))
1037 val |= DMA_TLB_READ_DRAIN;
1038#endif
1039 if (cap_write_drain(iommu->cap))
1040 val |= DMA_TLB_WRITE_DRAIN;
1041
1f5b3c3f 1042 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1043 /* Note: Only uses first TLB reg currently */
1044 if (val_iva)
1045 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1046 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1047
1048 /* Make sure hardware complete it */
1049 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1050 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1051
1f5b3c3f 1052 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1053
1054 /* check IOTLB invalidation granularity */
1055 if (DMA_TLB_IAIG(val) == 0)
1056 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1057 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1058 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1059 (unsigned long long)DMA_TLB_IIRG(type),
1060 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1061}
1062
93a23a72
YZ		 1063static struct device_domain_info *iommu_support_dev_iotlb(
1064 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1065{
1066 int found = 0;
1067 unsigned long flags;
1068 struct device_domain_info *info;
1069 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1070
1071 if (!ecap_dev_iotlb_support(iommu->ecap))
1072 return NULL;
1073
1074 if (!iommu->qi)
1075 return NULL;
1076
1077 spin_lock_irqsave(&device_domain_lock, flags);
1078 list_for_each_entry(info, &domain->devices, link)
1079 if (info->bus == bus && info->devfn == devfn) {
1080 found = 1;
1081 break;
1082 }
1083 spin_unlock_irqrestore(&device_domain_lock, flags);
1084
1085 if (!found || !info->dev)
1086 return NULL;
1087
1088 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1089 return NULL;
1090
1091 if (!dmar_find_matched_atsr_unit(info->dev))
1092 return NULL;
1093
1094 info->iommu = iommu;
1095
1096 return info;
1097}
1098
1099static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1100{
93a23a72
YZ		 1101 if (!info)
1102 return;
1103
1104 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1105}
1106
1107static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1108{
1109 if (!info->dev || !pci_ats_enabled(info->dev))
1110 return;
1111
1112 pci_disable_ats(info->dev);
1113}
1114
1115static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1116 u64 addr, unsigned mask)
1117{
1118 u16 sid, qdep;
1119 unsigned long flags;
1120 struct device_domain_info *info;
1121
1122 spin_lock_irqsave(&device_domain_lock, flags);
1123 list_for_each_entry(info, &domain->devices, link) {
1124 if (!info->dev || !pci_ats_enabled(info->dev))
1125 continue;
1126
1127 sid = info->bus << 8 | info->devfn;
1128 qdep = pci_ats_queue_depth(info->dev);
1129 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1130 }
1131 spin_unlock_irqrestore(&device_domain_lock, flags);
1132}
1133
1f0ef2aa 1134static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
82653633 1135 unsigned long pfn, unsigned int pages, int map)
ba395927 1136{
9dd2fe89 1137 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1138 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1139
ba395927
KA		 1140 BUG_ON(pages == 0);
1141
ba395927 1142 /*
9dd2fe89
YZ		 1143 * Fallback to domain selective flush if no PSI support or the size is
1144 * too big.
ba395927
KA		 1145 * PSI requires page size to be 2 ^ x, and the base address is naturally
1146 * aligned to the size
1147 */
9dd2fe89
YZ		 1148 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1149 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1150 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1151 else
1152 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1153 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1154
1155 /*
82653633
NA		 1156 * In caching mode, changes of pages from non-present to present require
1157 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1158 */
82653633 1159 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1160 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1161}
1162
f8bab735 1163static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1164{
1165 u32 pmen;
1166 unsigned long flags;
1167
1f5b3c3f 1168 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1169 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1170 pmen &= ~DMA_PMEN_EPM;
1171 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1172
1173 /* wait for the protected region status bit to clear */
1174 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1175 readl, !(pmen & DMA_PMEN_PRS), pmen);
1176
1f5b3c3f 1177 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1178}
1179
ba395927
KA		 1180static int iommu_enable_translation(struct intel_iommu *iommu)
1181{
1182 u32 sts;
1183 unsigned long flags;
1184
1f5b3c3f 1185 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1186 iommu->gcmd |= DMA_GCMD_TE;
1187 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1188
1189 /* Make sure hardware complete it */
1190 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1191 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1192
1f5b3c3f 1193 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1194 return 0;
1195}
1196
1197static int iommu_disable_translation(struct intel_iommu *iommu)
1198{
1199 u32 sts;
1200 unsigned long flag;
1201
1f5b3c3f 1202 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1203 iommu->gcmd &= ~DMA_GCMD_TE;
1204 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1205
1206 /* Make sure hardware complete it */
1207 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1208 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1209
1f5b3c3f 1210 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1211 return 0;
1212}
1213
3460a6d9 1214
ba395927
KA		 1215static int iommu_init_domains(struct intel_iommu *iommu)
1216{
1217 unsigned long ndomains;
1218 unsigned long nlongs;
1219
1220 ndomains = cap_ndoms(iommu->cap);
680a7524
YL		 1221 pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
1222 ndomains);
ba395927
KA		 1223 nlongs = BITS_TO_LONGS(ndomains);
1224
94a91b50
DD		 1225 spin_lock_init(&iommu->lock);
1226
ba395927
KA		 1227 /* TBD: there might be 64K domains,
1228 * consider other allocation for future chip
1229 */
1230 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1231 if (!iommu->domain_ids) {
1232 printk(KERN_ERR "Allocating domain id array failed\n");
1233 return -ENOMEM;
1234 }
1235 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1236 GFP_KERNEL);
1237 if (!iommu->domains) {
1238 printk(KERN_ERR "Allocating domain array failed\n");
ba395927
KA		 1239 return -ENOMEM;
1240 }
1241
1242 /*
1243 * if Caching mode is set, then invalid translations are tagged
1244 * with domainid 0. Hence we need to pre-allocate it.
1245 */
1246 if (cap_caching_mode(iommu->cap))
1247 set_bit(0, iommu->domain_ids);
1248 return 0;
1249}
ba395927 1250
ba395927
KA		 1251
1252static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1253static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1254
1255void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1256{
1257 struct dmar_domain *domain;
1258 int i;
c7151a8d 1259 unsigned long flags;
ba395927 1260
94a91b50 1261 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1262 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
94a91b50
DD		 1263 domain = iommu->domains[i];
1264 clear_bit(i, iommu->domain_ids);
1265
1266 spin_lock_irqsave(&domain->iommu_lock, flags);
1267 if (--domain->iommu_count == 0) {
1268 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1269 vm_domain_exit(domain);
1270 else
1271 domain_exit(domain);
1272 }
1273 spin_unlock_irqrestore(&domain->iommu_lock, flags);
5e98c4b1 1274 }
ba395927
KA		 1275 }
1276
1277 if (iommu->gcmd & DMA_GCMD_TE)
1278 iommu_disable_translation(iommu);
1279
1280 if (iommu->irq) {
dced35ae 1281 irq_set_handler_data(iommu->irq, NULL);
ba395927
KA		 1282 /* This will mask the irq */
1283 free_irq(iommu->irq, iommu);
1284 destroy_irq(iommu->irq);
1285 }
1286
1287 kfree(iommu->domains);
1288 kfree(iommu->domain_ids);
1289
d9630fe9
WH		 1290 g_iommus[iommu->seq_id] = NULL;
1291
1292 /* if all iommus are freed, free g_iommus */
1293 for (i = 0; i < g_num_of_iommus; i++) {
1294 if (g_iommus[i])
1295 break;
1296 }
1297
1298 if (i == g_num_of_iommus)
1299 kfree(g_iommus);
1300
ba395927
KA		 1301 /* free context mapping */
1302 free_context_table(iommu);
ba395927
KA		 1303}
1304
2c2e2c38 1305static struct dmar_domain *alloc_domain(void)
ba395927 1306{
ba395927 1307 struct dmar_domain *domain;
ba395927
KA		 1308
1309 domain = alloc_domain_mem();
1310 if (!domain)
1311 return NULL;
1312
4c923d47 1313 domain->nid = -1;
2c2e2c38
FY		 1314 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1315 domain->flags = 0;
1316
1317 return domain;
1318}
1319
1320static int iommu_attach_domain(struct dmar_domain *domain,
1321 struct intel_iommu *iommu)
1322{
1323 int num;
1324 unsigned long ndomains;
1325 unsigned long flags;
1326
ba395927
KA		 1327 ndomains = cap_ndoms(iommu->cap);
1328
1329 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1330
ba395927
KA		 1331 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1332 if (num >= ndomains) {
1333 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1334 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1335 return -ENOMEM;
ba395927
KA		 1336 }
1337
ba395927 1338 domain->id = num;
2c2e2c38 1339 set_bit(num, iommu->domain_ids);
8c11e798 1340 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1341 iommu->domains[num] = domain;
1342 spin_unlock_irqrestore(&iommu->lock, flags);
1343
2c2e2c38 1344 return 0;
ba395927
KA		 1345}
1346
2c2e2c38
FY		 1347static void iommu_detach_domain(struct dmar_domain *domain,
1348 struct intel_iommu *iommu)
ba395927
KA		 1349{
1350 unsigned long flags;
2c2e2c38
FY		 1351 int num, ndomains;
1352 int found = 0;
ba395927 1353
8c11e798 1354 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1355 ndomains = cap_ndoms(iommu->cap);
a45946ab 1356 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38
FY		 1357 if (iommu->domains[num] == domain) {
1358 found = 1;
1359 break;
1360 }
2c2e2c38
FY		 1361 }
1362
1363 if (found) {
1364 clear_bit(num, iommu->domain_ids);
1365 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1366 iommu->domains[num] = NULL;
1367 }
8c11e798 1368 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1369}
1370
1371static struct iova_domain reserved_iova_list;
8a443df4 1372static struct lock_class_key reserved_rbtree_key;
ba395927 1373
51a63e67 1374static int dmar_init_reserved_ranges(void)
ba395927
KA		 1375{
1376 struct pci_dev *pdev = NULL;
1377 struct iova *iova;
1378 int i;
ba395927 1379
f661197e 1380 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1381
8a443df4
MG		 1382 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1383 &reserved_rbtree_key);
1384
ba395927
KA		 1385 /* IOAPIC ranges shouldn't be accessed by DMA */
1386 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1387 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1388 if (!iova) {
ba395927 1389 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1390 return -ENODEV;
1391 }
ba395927
KA		 1392
1393 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1394 for_each_pci_dev(pdev) {
1395 struct resource *r;
1396
1397 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1398 r = &pdev->resource[i];
1399 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1400 continue;
1a4a4551
DW		 1401 iova = reserve_iova(&reserved_iova_list,
1402 IOVA_PFN(r->start),
1403 IOVA_PFN(r->end));
51a63e67 1404 if (!iova) {
ba395927 1405 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1406 return -ENODEV;
1407 }
ba395927
KA		 1408 }
1409 }
51a63e67 1410 return 0;
ba395927
KA		 1411}
1412
1413static void domain_reserve_special_ranges(struct dmar_domain *domain)
1414{
1415 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1416}
1417
1418static inline int guestwidth_to_adjustwidth(int gaw)
1419{
1420 int agaw;
1421 int r = (gaw - 12) % 9;
1422
1423 if (r == 0)
1424 agaw = gaw;
1425 else
1426 agaw = gaw + 9 - r;
1427 if (agaw > 64)
1428 agaw = 64;
1429 return agaw;
1430}
1431
1432static int domain_init(struct dmar_domain *domain, int guest_width)
1433{
1434 struct intel_iommu *iommu;
1435 int adjust_width, agaw;
1436 unsigned long sagaw;
1437
f661197e 1438 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1439 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1440
1441 domain_reserve_special_ranges(domain);
1442
1443 /* calculate AGAW */
8c11e798 1444 iommu = domain_get_iommu(domain);
ba395927
KA		 1445 if (guest_width > cap_mgaw(iommu->cap))
1446 guest_width = cap_mgaw(iommu->cap);
1447 domain->gaw = guest_width;
1448 adjust_width = guestwidth_to_adjustwidth(guest_width);
1449 agaw = width_to_agaw(adjust_width);
1450 sagaw = cap_sagaw(iommu->cap);
1451 if (!test_bit(agaw, &sagaw)) {
1452 /* hardware doesn't support it, choose a bigger one */
1453 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1454 agaw = find_next_bit(&sagaw, 5, agaw);
1455 if (agaw >= 5)
1456 return -ENODEV;
1457 }
1458 domain->agaw = agaw;
1459 INIT_LIST_HEAD(&domain->devices);
1460
8e604097
WH		 1461 if (ecap_coherent(iommu->ecap))
1462 domain->iommu_coherency = 1;
1463 else
1464 domain->iommu_coherency = 0;
1465
58c610bd
SY		 1466 if (ecap_sc_support(iommu->ecap))
1467 domain->iommu_snooping = 1;
1468 else
1469 domain->iommu_snooping = 0;
1470
6dd9a7c7 1471 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
c7151a8d 1472 domain->iommu_count = 1;
4c923d47 1473 domain->nid = iommu->node;
c7151a8d 1474
ba395927 1475 /* always allocate the top pgd */
4c923d47 1476 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1477 if (!domain->pgd)
1478 return -ENOMEM;
5b6985ce 1479 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1480 return 0;
1481}
1482
1483static void domain_exit(struct dmar_domain *domain)
1484{
2c2e2c38
FY		 1485 struct dmar_drhd_unit *drhd;
1486 struct intel_iommu *iommu;
ba395927
KA		 1487
1488 /* Domain 0 is reserved, so dont process it */
1489 if (!domain)
1490 return;
1491
7b668357
AW		 1492 /* Flush any lazy unmaps that may reference this domain */
1493 if (!intel_iommu_strict)
1494 flush_unmaps_timeout(0);
1495
ba395927
KA		 1496 domain_remove_dev_info(domain);
1497 /* destroy iovas */
1498 put_iova_domain(&domain->iovad);
ba395927
KA		 1499
1500 /* clear ptes */
595badf5 1501 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1502
1503 /* free page tables */
d794dc9b 1504 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1505
2c2e2c38
FY		 1506 for_each_active_iommu(iommu, drhd)
1507 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1508 iommu_detach_domain(domain, iommu);
1509
ba395927
KA		 1510 free_domain_mem(domain);
1511}
1512
4ed0d3e6
FY		 1513static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1514 u8 bus, u8 devfn, int translation)
ba395927
KA		 1515{
1516 struct context_entry *context;
ba395927 1517 unsigned long flags;
5331fe6f 1518 struct intel_iommu *iommu;
ea6606b0
WH		 1519 struct dma_pte *pgd;
1520 unsigned long num;
1521 unsigned long ndomains;
1522 int id;
1523 int agaw;
93a23a72 1524 struct device_domain_info *info = NULL;
ba395927
KA		 1525
1526 pr_debug("Set context mapping for %02x:%02x.%d\n",
1527 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1528
ba395927 1529 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1530 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1531 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1532
276dbf99 1533 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1534 if (!iommu)
1535 return -ENODEV;
1536
ba395927
KA		 1537 context = device_to_context_entry(iommu, bus, devfn);
1538 if (!context)
1539 return -ENOMEM;
1540 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1541 if (context_present(context)) {
ba395927
KA		 1542 spin_unlock_irqrestore(&iommu->lock, flags);
1543 return 0;
1544 }
1545
ea6606b0
WH		 1546 id = domain->id;
1547 pgd = domain->pgd;
1548
2c2e2c38
FY		 1549 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1550 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1551 int found = 0;
1552
1553 /* find an available domain id for this device in iommu */
1554 ndomains = cap_ndoms(iommu->cap);
a45946ab 1555 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1556 if (iommu->domains[num] == domain) {
1557 id = num;
1558 found = 1;
1559 break;
1560 }
ea6606b0
WH		 1561 }
1562
1563 if (found == 0) {
1564 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1565 if (num >= ndomains) {
1566 spin_unlock_irqrestore(&iommu->lock, flags);
1567 printk(KERN_ERR "IOMMU: no free domain ids\n");
1568 return -EFAULT;
1569 }
1570
1571 set_bit(num, iommu->domain_ids);
1572 iommu->domains[num] = domain;
1573 id = num;
1574 }
1575
1576 /* Skip top levels of page tables for
1577 * iommu which has less agaw than default.
1672af11 1578 * Unnecessary for PT mode.
ea6606b0 1579 */
1672af11
CW		 1580 if (translation != CONTEXT_TT_PASS_THROUGH) {
1581 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1582 pgd = phys_to_virt(dma_pte_addr(pgd));
1583 if (!dma_pte_present(pgd)) {
1584 spin_unlock_irqrestore(&iommu->lock, flags);
1585 return -ENOMEM;
1586 }
ea6606b0
WH		 1587 }
1588 }
1589 }
1590
1591 context_set_domain_id(context, id);
4ed0d3e6 1592
93a23a72
YZ		 1593 if (translation != CONTEXT_TT_PASS_THROUGH) {
1594 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1595 translation = info ? CONTEXT_TT_DEV_IOTLB :
1596 CONTEXT_TT_MULTI_LEVEL;
1597 }
4ed0d3e6
FY		 1598 /*
1599 * In pass through mode, AW must be programmed to indicate the largest
1600 * AGAW value supported by hardware. And ASR is ignored by hardware.
1601 */
93a23a72 1602 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1603 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1604 else {
1605 context_set_address_root(context, virt_to_phys(pgd));
1606 context_set_address_width(context, iommu->agaw);
1607 }
4ed0d3e6
FY		 1608
1609 context_set_translation_type(context, translation);
c07e7d21
MM		 1610 context_set_fault_enable(context);
1611 context_set_present(context);
5331fe6f 1612 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1613
4c25a2c1
DW		 1614 /*
1615 * It's a non-present to present mapping. If hardware doesn't cache
1616 * non-present entry we only need to flush the write-buffer. If the
1617 * _does_ cache non-present entries, then it does so in the special
1618 * domain #0, which we have to flush:
1619 */
1620 if (cap_caching_mode(iommu->cap)) {
1621 iommu->flush.flush_context(iommu, 0,
1622 (((u16)bus) << 8) | devfn,
1623 DMA_CCMD_MASK_NOBIT,
1624 DMA_CCMD_DEVICE_INVL);
82653633 1625 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1626 } else {
ba395927 1627 iommu_flush_write_buffer(iommu);
4c25a2c1 1628 }
93a23a72 1629 iommu_enable_dev_iotlb(info);
ba395927 1630 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1631
1632 spin_lock_irqsave(&domain->iommu_lock, flags);
1633 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1634 domain->iommu_count++;
4c923d47
SS		 1635 if (domain->iommu_count == 1)
1636 domain->nid = iommu->node;
58c610bd 1637 domain_update_iommu_cap(domain);
c7151a8d
WH		 1638 }
1639 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1640 return 0;
1641}
1642
1643static int
4ed0d3e6
FY		 1644domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1645 int translation)
ba395927
KA		 1646{
1647 int ret;
1648 struct pci_dev *tmp, *parent;
1649
276dbf99 1650 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1651 pdev->bus->number, pdev->devfn,
1652 translation);
ba395927
KA		 1653 if (ret)
1654 return ret;
1655
1656 /* dependent device mapping */
1657 tmp = pci_find_upstream_pcie_bridge(pdev);
1658 if (!tmp)
1659 return 0;
1660 /* Secondary interface's bus number and devfn 0 */
1661 parent = pdev->bus->self;
1662 while (parent != tmp) {
276dbf99
DW		 1663 ret = domain_context_mapping_one(domain,
1664 pci_domain_nr(parent->bus),
1665 parent->bus->number,
4ed0d3e6 1666 parent->devfn, translation);
ba395927
KA		 1667 if (ret)
1668 return ret;
1669 parent = parent->bus->self;
1670 }
45e829ea 1671 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
ba395927 1672 return domain_context_mapping_one(domain,
276dbf99 1673 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1674 tmp->subordinate->number, 0,
1675 translation);
ba395927
KA		 1676 else /* this is a legacy PCI bridge */
1677 return domain_context_mapping_one(domain,
276dbf99
DW		 1678 pci_domain_nr(tmp->bus),
1679 tmp->bus->number,
4ed0d3e6
FY		 1680 tmp->devfn,
1681 translation);
ba395927
KA		 1682}
1683
5331fe6f 1684static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1685{
1686 int ret;
1687 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1688 struct intel_iommu *iommu;
1689
276dbf99
DW		 1690 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1691 pdev->devfn);
5331fe6f
WH		 1692 if (!iommu)
1693 return -ENODEV;
ba395927 1694
276dbf99 1695 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1696 if (!ret)
1697 return ret;
1698 /* dependent device mapping */
1699 tmp = pci_find_upstream_pcie_bridge(pdev);
1700 if (!tmp)
1701 return ret;
1702 /* Secondary interface's bus number and devfn 0 */
1703 parent = pdev->bus->self;
1704 while (parent != tmp) {
8c11e798 1705 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1706 parent->devfn);
ba395927
KA		 1707 if (!ret)
1708 return ret;
1709 parent = parent->bus->self;
1710 }
5f4d91a1 1711 if (pci_is_pcie(tmp))
276dbf99
DW		 1712 return device_context_mapped(iommu, tmp->subordinate->number,
1713 0);
ba395927 1714 else
276dbf99
DW		 1715 return device_context_mapped(iommu, tmp->bus->number,
1716 tmp->devfn);
ba395927
KA		 1717}
1718
f532959b
FY		 1719/* Returns a number of VTD pages, but aligned to MM page size */
1720static inline unsigned long aligned_nrpages(unsigned long host_addr,
1721 size_t size)
1722{
1723 host_addr &= ~PAGE_MASK;
1724 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1725}
1726
6dd9a7c7
YS		 1727/* Return largest possible superpage level for a given mapping */
1728static inline int hardware_largepage_caps(struct dmar_domain *domain,
1729 unsigned long iov_pfn,
1730 unsigned long phy_pfn,
1731 unsigned long pages)
1732{
1733 int support, level = 1;
1734 unsigned long pfnmerge;
1735
1736 support = domain->iommu_superpage;
1737
1738 /* To use a large page, the virtual *and* physical addresses
1739 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1740 of them will mean we have to use smaller pages. So just
1741 merge them and check both at once. */
1742 pfnmerge = iov_pfn | phy_pfn;
1743
1744 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1745 pages >>= VTD_STRIDE_SHIFT;
1746 if (!pages)
1747 break;
1748 pfnmerge >>= VTD_STRIDE_SHIFT;
1749 level++;
1750 support--;
1751 }
1752 return level;
1753}
1754
9051aa02
DW		 1755static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1756 struct scatterlist *sg, unsigned long phys_pfn,
1757 unsigned long nr_pages, int prot)
e1605495
DW		 1758{
1759 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1760 phys_addr_t uninitialized_var(pteval);
e1605495 1761 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1762 unsigned long sg_res;
6dd9a7c7
YS		 1763 unsigned int largepage_lvl = 0;
1764 unsigned long lvl_pages = 0;
e1605495
DW		 1765
1766 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1767
1768 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1769 return -EINVAL;
1770
1771 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1772
9051aa02
DW		 1773 if (sg)
1774 sg_res = 0;
1775 else {
1776 sg_res = nr_pages + 1;
1777 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1778 }
1779
6dd9a7c7 1780 while (nr_pages > 0) {
c85994e4
DW		 1781 uint64_t tmp;
1782
e1605495 1783 if (!sg_res) {
f532959b 1784 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1785 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1786 sg->dma_length = sg->length;
1787 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1788 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1789 }
6dd9a7c7 1790
e1605495 1791 if (!pte) {
6dd9a7c7
YS		 1792 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1793
1794 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
e1605495
DW		 1795 if (!pte)
1796 return -ENOMEM;
6dd9a7c7
YS		 1797 /* It is large page*/
1798 if (largepage_lvl > 1)
1799 pteval |= DMA_PTE_LARGE_PAGE;
1800 else
1801 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
1802
e1605495
DW		 1803 }
1804 /* We don't need lock here, nobody else
1805 * touches the iova range
1806 */
7766a3fb 1807 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1808 if (tmp) {
1bf20f0d 1809 static int dumps = 5;
c85994e4
DW		 1810 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1811 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1812 if (dumps) {
1813 dumps--;
1814 debug_dma_dump_mappings(NULL);
1815 }
1816 WARN_ON(1);
1817 }
6dd9a7c7
YS		 1818
1819 lvl_pages = lvl_to_nr_pages(largepage_lvl);
1820
1821 BUG_ON(nr_pages < lvl_pages);
1822 BUG_ON(sg_res < lvl_pages);
1823
1824 nr_pages -= lvl_pages;
1825 iov_pfn += lvl_pages;
1826 phys_pfn += lvl_pages;
1827 pteval += lvl_pages * VTD_PAGE_SIZE;
1828 sg_res -= lvl_pages;
1829
1830 /* If the next PTE would be the first in a new page, then we
1831 need to flush the cache on the entries we've just written.
1832 And then we'll need to recalculate 'pte', so clear it and
1833 let it get set again in the if (!pte) block above.
1834
1835 If we're done (!nr_pages) we need to flush the cache too.
1836
1837 Also if we've been setting superpages, we may need to
1838 recalculate 'pte' and switch back to smaller pages for the
1839 end of the mapping, if the trailing size is not enough to
1840 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 1841 pte++;
6dd9a7c7
YS		 1842 if (!nr_pages || first_pte_in_page(pte) ||
1843 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 1844 domain_flush_cache(domain, first_pte,
1845 (void *)pte - (void *)first_pte);
1846 pte = NULL;
1847 }
6dd9a7c7
YS		 1848
1849 if (!sg_res && nr_pages)
e1605495
DW		 1850 sg = sg_next(sg);
1851 }
1852 return 0;
1853}
1854
9051aa02
DW		 1855static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1856 struct scatterlist *sg, unsigned long nr_pages,
1857 int prot)
ba395927 1858{
9051aa02
DW		 1859 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1860}
6f6a00e4 1861
9051aa02
DW		 1862static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1863 unsigned long phys_pfn, unsigned long nr_pages,
1864 int prot)
1865{
1866 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1867}
1868
c7151a8d 1869static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1870{
c7151a8d
WH		 1871 if (!iommu)
1872 return;
8c11e798
WH		 1873
1874 clear_context_table(iommu, bus, devfn);
1875 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1876 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1877 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1878}
1879
1880static void domain_remove_dev_info(struct dmar_domain *domain)
1881{
1882 struct device_domain_info *info;
1883 unsigned long flags;
c7151a8d 1884 struct intel_iommu *iommu;
ba395927
KA		 1885
1886 spin_lock_irqsave(&device_domain_lock, flags);
1887 while (!list_empty(&domain->devices)) {
1888 info = list_entry(domain->devices.next,
1889 struct device_domain_info, link);
1890 list_del(&info->link);
1891 list_del(&info->global);
1892 if (info->dev)
358dd8ac 1893 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1894 spin_unlock_irqrestore(&device_domain_lock, flags);
1895
93a23a72 1896 iommu_disable_dev_iotlb(info);
276dbf99 1897 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1898 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1899 free_devinfo_mem(info);
1900
1901 spin_lock_irqsave(&device_domain_lock, flags);
1902 }
1903 spin_unlock_irqrestore(&device_domain_lock, flags);
1904}
1905
1906/*
1907 * find_domain
358dd8ac 1908 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1909 */
38717946 1910static struct dmar_domain *
ba395927
KA		 1911find_domain(struct pci_dev *pdev)
1912{
1913 struct device_domain_info *info;
1914
1915 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1916 info = pdev->dev.archdata.iommu;
ba395927
KA		 1917 if (info)
1918 return info->domain;
1919 return NULL;
1920}
1921
ba395927
KA		 1922/* domain is initialized */
1923static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1924{
1925 struct dmar_domain *domain, *found = NULL;
1926 struct intel_iommu *iommu;
1927 struct dmar_drhd_unit *drhd;
1928 struct device_domain_info *info, *tmp;
1929 struct pci_dev *dev_tmp;
1930 unsigned long flags;
1931 int bus = 0, devfn = 0;
276dbf99 1932 int segment;
2c2e2c38 1933 int ret;
ba395927
KA		 1934
1935 domain = find_domain(pdev);
1936 if (domain)
1937 return domain;
1938
276dbf99
DW		 1939 segment = pci_domain_nr(pdev->bus);
1940
ba395927
KA		 1941 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1942 if (dev_tmp) {
5f4d91a1 1943 if (pci_is_pcie(dev_tmp)) {
ba395927
KA		 1944 bus = dev_tmp->subordinate->number;
1945 devfn = 0;
1946 } else {
1947 bus = dev_tmp->bus->number;
1948 devfn = dev_tmp->devfn;
1949 }
1950 spin_lock_irqsave(&device_domain_lock, flags);
1951 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1952 if (info->segment == segment &&
1953 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1954 found = info->domain;
1955 break;
1956 }
1957 }
1958 spin_unlock_irqrestore(&device_domain_lock, flags);
1959 /* pcie-pci bridge already has a domain, uses it */
1960 if (found) {
1961 domain = found;
1962 goto found_domain;
1963 }
1964 }
1965
2c2e2c38
FY		 1966 domain = alloc_domain();
1967 if (!domain)
1968 goto error;
1969
ba395927
KA		 1970 /* Allocate new domain for the device */
1971 drhd = dmar_find_matched_drhd_unit(pdev);
1972 if (!drhd) {
1973 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1974 pci_name(pdev));
1975 return NULL;
1976 }
1977 iommu = drhd->iommu;
1978
2c2e2c38
FY		 1979 ret = iommu_attach_domain(domain, iommu);
1980 if (ret) {
2fe9723d 1981 free_domain_mem(domain);
ba395927 1982 goto error;
2c2e2c38 1983 }
ba395927
KA		 1984
1985 if (domain_init(domain, gaw)) {
1986 domain_exit(domain);
1987 goto error;
1988 }
1989
1990 /* register pcie-to-pci device */
1991 if (dev_tmp) {
1992 info = alloc_devinfo_mem();
1993 if (!info) {
1994 domain_exit(domain);
1995 goto error;
1996 }
276dbf99 1997 info->segment = segment;
ba395927
KA		 1998 info->bus = bus;
1999 info->devfn = devfn;
2000 info->dev = NULL;
2001 info->domain = domain;
2002 /* This domain is shared by devices under p2p bridge */
3b5410e7 2003 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 2004
2005 /* pcie-to-pci bridge already has a domain, uses it */
2006 found = NULL;
2007 spin_lock_irqsave(&device_domain_lock, flags);
2008 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 2009 if (tmp->segment == segment &&
2010 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 2011 found = tmp->domain;
2012 break;
2013 }
2014 }
2015 if (found) {
00dfff77 2016 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927
KA		 2017 free_devinfo_mem(info);
2018 domain_exit(domain);
2019 domain = found;
2020 } else {
2021 list_add(&info->link, &domain->devices);
2022 list_add(&info->global, &device_domain_list);
00dfff77 2023 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2024 }
ba395927
KA		 2025 }
2026
2027found_domain:
2028 info = alloc_devinfo_mem();
2029 if (!info)
2030 goto error;
276dbf99 2031 info->segment = segment;
ba395927
KA		 2032 info->bus = pdev->bus->number;
2033 info->devfn = pdev->devfn;
2034 info->dev = pdev;
2035 info->domain = domain;
2036 spin_lock_irqsave(&device_domain_lock, flags);
2037 /* somebody is fast */
2038 found = find_domain(pdev);
2039 if (found != NULL) {
2040 spin_unlock_irqrestore(&device_domain_lock, flags);
2041 if (found != domain) {
2042 domain_exit(domain);
2043 domain = found;
2044 }
2045 free_devinfo_mem(info);
2046 return domain;
2047 }
2048 list_add(&info->link, &domain->devices);
2049 list_add(&info->global, &device_domain_list);
358dd8ac 2050 pdev->dev.archdata.iommu = info;
ba395927
KA		 2051 spin_unlock_irqrestore(&device_domain_lock, flags);
2052 return domain;
2053error:
2054 /* recheck it here, maybe others set it */
2055 return find_domain(pdev);
2056}
2057
2c2e2c38 2058static int iommu_identity_mapping;
e0fc7e0b
DW		 2059#define IDENTMAP_ALL 1
2060#define IDENTMAP_GFX 2
2061#define IDENTMAP_AZALIA 4
2c2e2c38 2062
b213203e
DW		 2063static int iommu_domain_identity_map(struct dmar_domain *domain,
2064 unsigned long long start,
2065 unsigned long long end)
ba395927 2066{
c5395d5c
DW		 2067 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2068 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2069
2070 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2071 dma_to_mm_pfn(last_vpfn))) {
ba395927 2072 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2073 return -ENOMEM;
ba395927
KA		 2074 }
2075
c5395d5c
DW		 2076 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2077 start, end, domain->id);
ba395927
KA		 2078 /*
2079 * RMRR range might have overlap with physical memory range,
2080 * clear it first
2081 */
c5395d5c 2082 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2083
c5395d5c
DW		 2084 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2085 last_vpfn - first_vpfn + 1,
61df7443 2086 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2087}
2088
2089static int iommu_prepare_identity_map(struct pci_dev *pdev,
2090 unsigned long long start,
2091 unsigned long long end)
2092{
2093 struct dmar_domain *domain;
2094 int ret;
2095
c7ab48d2 2096 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2097 if (!domain)
2098 return -ENOMEM;
2099
19943b0e
DW		 2100 /* For _hardware_ passthrough, don't bother. But for software
2101 passthrough, we do it anyway -- it may indicate a memory
2102 range which is reserved in E820, so which didn't get set
2103 up to start with in si_domain */
2104 if (domain == si_domain && hw_pass_through) {
2105 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2106 pci_name(pdev), start, end);
2107 return 0;
2108 }
2109
2110 printk(KERN_INFO
2111 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2112 pci_name(pdev), start, end);
2ff729f5 2113
5595b528
DW		 2114 if (end < start) {
2115 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2116 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2117 dmi_get_system_info(DMI_BIOS_VENDOR),
2118 dmi_get_system_info(DMI_BIOS_VERSION),
2119 dmi_get_system_info(DMI_PRODUCT_VERSION));
2120 ret = -EIO;
2121 goto error;
2122 }
2123
2ff729f5
DW		 2124 if (end >> agaw_to_width(domain->agaw)) {
2125 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2126 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2127 agaw_to_width(domain->agaw),
2128 dmi_get_system_info(DMI_BIOS_VENDOR),
2129 dmi_get_system_info(DMI_BIOS_VERSION),
2130 dmi_get_system_info(DMI_PRODUCT_VERSION));
2131 ret = -EIO;
2132 goto error;
2133 }
19943b0e 2134
b213203e 2135 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2136 if (ret)
2137 goto error;
2138
2139 /* context entry init */
4ed0d3e6 2140 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2141 if (ret)
2142 goto error;
2143
2144 return 0;
2145
2146 error:
ba395927
KA		 2147 domain_exit(domain);
2148 return ret;
ba395927
KA		 2149}
2150
2151static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2152 struct pci_dev *pdev)
2153{
358dd8ac 2154 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2155 return 0;
2156 return iommu_prepare_identity_map(pdev, rmrr->base_address,
70e535d1 2157 rmrr->end_address);
ba395927
KA		 2158}
2159
d3f13810 2160#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2161static inline void iommu_prepare_isa(void)
2162{
2163 struct pci_dev *pdev;
2164 int ret;
2165
2166 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2167 if (!pdev)
2168 return;
2169
c7ab48d2 2170 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
70e535d1 2171 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2172
2173 if (ret)
c7ab48d2
DW		 2174 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2175 "floppy might not work\n");
49a0429e
KA		 2176
2177}
2178#else
2179static inline void iommu_prepare_isa(void)
2180{
2181 return;
2182}
d3f13810 2183#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2184
2c2e2c38 2185static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2186
2187static int __init si_domain_work_fn(unsigned long start_pfn,
2188 unsigned long end_pfn, void *datax)
2189{
2190 int *ret = datax;
2191
2192 *ret = iommu_domain_identity_map(si_domain,
2193 (uint64_t)start_pfn << PAGE_SHIFT,
2194 (uint64_t)end_pfn << PAGE_SHIFT);
2195 return *ret;
2196
2197}
2198
071e1374 2199static int __init si_domain_init(int hw)
2c2e2c38
FY		 2200{
2201 struct dmar_drhd_unit *drhd;
2202 struct intel_iommu *iommu;
c7ab48d2 2203 int nid, ret = 0;
2c2e2c38
FY		 2204
2205 si_domain = alloc_domain();
2206 if (!si_domain)
2207 return -EFAULT;
2208
c7ab48d2 2209 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2210
2211 for_each_active_iommu(iommu, drhd) {
2212 ret = iommu_attach_domain(si_domain, iommu);
2213 if (ret) {
2214 domain_exit(si_domain);
2215 return -EFAULT;
2216 }
2217 }
2218
2219 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2220 domain_exit(si_domain);
2221 return -EFAULT;
2222 }
2223
2224 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2225
19943b0e
DW		 2226 if (hw)
2227 return 0;
2228
c7ab48d2
DW		 2229 for_each_online_node(nid) {
2230 work_with_active_regions(nid, si_domain_work_fn, &ret);
2231 if (ret)
2232 return ret;
2233 }
2234
2c2e2c38
FY		 2235 return 0;
2236}
2237
2238static void domain_remove_one_dev_info(struct dmar_domain *domain,
2239 struct pci_dev *pdev);
2240static int identity_mapping(struct pci_dev *pdev)
2241{
2242 struct device_domain_info *info;
2243
2244 if (likely(!iommu_identity_mapping))
2245 return 0;
2246
cb452a40
MT		 2247 info = pdev->dev.archdata.iommu;
2248 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2249 return (info->domain == si_domain);
2c2e2c38 2250
2c2e2c38
FY		 2251 return 0;
2252}
2253
2254static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2255 struct pci_dev *pdev,
2256 int translation)
2c2e2c38
FY		 2257{
2258 struct device_domain_info *info;
2259 unsigned long flags;
5fe60f4e 2260 int ret;
2c2e2c38
FY		 2261
2262 info = alloc_devinfo_mem();
2263 if (!info)
2264 return -ENOMEM;
2265
5fe60f4e
DW		 2266 ret = domain_context_mapping(domain, pdev, translation);
2267 if (ret) {
2268 free_devinfo_mem(info);
2269 return ret;
2270 }
2271
2c2e2c38
FY		 2272 info->segment = pci_domain_nr(pdev->bus);
2273 info->bus = pdev->bus->number;
2274 info->devfn = pdev->devfn;
2275 info->dev = pdev;
2276 info->domain = domain;
2277
2278 spin_lock_irqsave(&device_domain_lock, flags);
2279 list_add(&info->link, &domain->devices);
2280 list_add(&info->global, &device_domain_list);
2281 pdev->dev.archdata.iommu = info;
2282 spin_unlock_irqrestore(&device_domain_lock, flags);
2283
2284 return 0;
2285}
2286
6941af28
DW		 2287static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2288{
e0fc7e0b
DW		 2289 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2290 return 1;
2291
2292 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2293 return 1;
2294
2295 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2296 return 0;
6941af28 2297
3dfc813d
DW		 2298 /*
2299 * We want to start off with all devices in the 1:1 domain, and
2300 * take them out later if we find they can't access all of memory.
2301 *
2302 * However, we can't do this for PCI devices behind bridges,
2303 * because all PCI devices behind the same bridge will end up
2304 * with the same source-id on their transactions.
2305 *
2306 * Practically speaking, we can't change things around for these
2307 * devices at run-time, because we can't be sure there'll be no
2308 * DMA transactions in flight for any of their siblings.
2309 *
2310 * So PCI devices (unless they're on the root bus) as well as
2311 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2312 * the 1:1 domain, just in _case_ one of their siblings turns out
2313 * not to be able to map all of memory.
2314 */
5f4d91a1 2315 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2316 if (!pci_is_root_bus(pdev->bus))
2317 return 0;
2318 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2319 return 0;
2320 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2321 return 0;
2322
2323 /*
2324 * At boot time, we don't yet know if devices will be 64-bit capable.
2325 * Assume that they will -- if they turn out not to be, then we can
2326 * take them out of the 1:1 domain later.
2327 */
8fcc5372
CW		 2328 if (!startup) {
2329 /*
2330 * If the device's dma_mask is less than the system's memory
2331 * size then this is not a candidate for identity mapping.
2332 */
2333 u64 dma_mask = pdev->dma_mask;
2334
2335 if (pdev->dev.coherent_dma_mask &&
2336 pdev->dev.coherent_dma_mask < dma_mask)
2337 dma_mask = pdev->dev.coherent_dma_mask;
2338
2339 return dma_mask >= dma_get_required_mask(&pdev->dev);
2340 }
6941af28
DW		 2341
2342 return 1;
2343}
2344
071e1374 2345static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2346{
2c2e2c38
FY		 2347 struct pci_dev *pdev = NULL;
2348 int ret;
2349
19943b0e 2350 ret = si_domain_init(hw);
2c2e2c38
FY		 2351 if (ret)
2352 return -EFAULT;
2353
2c2e2c38 2354 for_each_pci_dev(pdev) {
825507d6
MT		 2355 /* Skip Host/PCI Bridge devices */
2356 if (IS_BRIDGE_HOST_DEVICE(pdev))
2357 continue;
6941af28 2358 if (iommu_should_identity_map(pdev, 1)) {
19943b0e
DW		 2359 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2360 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2361
5fe60f4e 2362 ret = domain_add_dev_info(si_domain, pdev,
19943b0e 2363 hw ? CONTEXT_TT_PASS_THROUGH :
62edf5dc
DW		 2364 CONTEXT_TT_MULTI_LEVEL);
2365 if (ret)
2366 return ret;
62edf5dc 2367 }
2c2e2c38
FY		 2368 }
2369
2370 return 0;
2371}
2372
b779260b 2373static int __init init_dmars(void)
ba395927
KA		 2374{
2375 struct dmar_drhd_unit *drhd;
2376 struct dmar_rmrr_unit *rmrr;
2377 struct pci_dev *pdev;
2378 struct intel_iommu *iommu;
9d783ba0 2379 int i, ret;
2c2e2c38 2380
ba395927
KA		 2381 /*
2382 * for each drhd
2383 * allocate root
2384 * initialize and program root entry to not present
2385 * endfor
2386 */
2387 for_each_drhd_unit(drhd) {
5e0d2a6f 2388 g_num_of_iommus++;
2389 /*
2390 * lock not needed as this is only incremented in the single
2391 * threaded kernel __init code path all other access are read
2392 * only
2393 */
2394 }
2395
d9630fe9
WH		 2396 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2397 GFP_KERNEL);
2398 if (!g_iommus) {
2399 printk(KERN_ERR "Allocating global iommu array failed\n");
2400 ret = -ENOMEM;
2401 goto error;
2402 }
2403
80b20dd8 2404 deferred_flush = kzalloc(g_num_of_iommus *
2405 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2406 if (!deferred_flush) {
5e0d2a6f 2407 ret = -ENOMEM;
2408 goto error;
2409 }
2410
5e0d2a6f 2411 for_each_drhd_unit(drhd) {
2412 if (drhd->ignored)
2413 continue;
1886e8a9
SS		 2414
2415 iommu = drhd->iommu;
d9630fe9 2416 g_iommus[iommu->seq_id] = iommu;
ba395927 2417
e61d98d8
SS		 2418 ret = iommu_init_domains(iommu);
2419 if (ret)
2420 goto error;
2421
ba395927
KA		 2422 /*
2423 * TBD:
2424 * we could share the same root & context tables
25985edc 2425 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2426 */
2427 ret = iommu_alloc_root_entry(iommu);
2428 if (ret) {
2429 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2430 goto error;
2431 }
4ed0d3e6 2432 if (!ecap_pass_through(iommu->ecap))
19943b0e 2433 hw_pass_through = 0;
ba395927
KA		 2434 }
2435
1531a6a6
SS		 2436 /*
2437 * Start from the sane iommu hardware state.
2438 */
a77b67d4
YS		 2439 for_each_drhd_unit(drhd) {
2440 if (drhd->ignored)
2441 continue;
2442
2443 iommu = drhd->iommu;
1531a6a6
SS		 2444
2445 /*
2446 * If the queued invalidation is already initialized by us
2447 * (for example, while enabling interrupt-remapping) then
2448 * we got the things already rolling from a sane state.
2449 */
2450 if (iommu->qi)
2451 continue;
2452
2453 /*
2454 * Clear any previous faults.
2455 */
2456 dmar_fault(-1, iommu);
2457 /*
2458 * Disable queued invalidation if supported and already enabled
2459 * before OS handover.
2460 */
2461 dmar_disable_qi(iommu);
2462 }
2463
2464 for_each_drhd_unit(drhd) {
2465 if (drhd->ignored)
2466 continue;
2467
2468 iommu = drhd->iommu;
2469
a77b67d4
YS		 2470 if (dmar_enable_qi(iommu)) {
2471 /*
2472 * Queued Invalidate not enabled, use Register Based
2473 * Invalidate
2474 */
2475 iommu->flush.flush_context = __iommu_flush_context;
2476 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2477 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2478 "invalidation\n",
680a7524 2479 iommu->seq_id,
b4e0f9eb 2480 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2481 } else {
2482 iommu->flush.flush_context = qi_flush_context;
2483 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2484 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2485 "invalidation\n",
680a7524 2486 iommu->seq_id,
b4e0f9eb 2487 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2488 }
2489 }
2490
19943b0e 2491 if (iommu_pass_through)
e0fc7e0b
DW		 2492 iommu_identity_mapping |= IDENTMAP_ALL;
2493
d3f13810 2494#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2495 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2496#endif
e0fc7e0b
DW		 2497
2498 check_tylersburg_isoch();
2499
ba395927 2500 /*
19943b0e
DW		 2501 * If pass through is not set or not enabled, setup context entries for
2502 * identity mappings for rmrr, gfx, and isa and may fall back to static
2503 * identity mapping if iommu_identity_mapping is set.
ba395927 2504 */
19943b0e
DW		 2505 if (iommu_identity_mapping) {
2506 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2507 if (ret) {
19943b0e
DW		 2508 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2509 goto error;
ba395927
KA		 2510 }
2511 }
ba395927 2512 /*
19943b0e
DW		 2513 * For each rmrr
2514 * for each dev attached to rmrr
2515 * do
2516 * locate drhd for dev, alloc domain for dev
2517 * allocate free domain
2518 * allocate page table entries for rmrr
2519 * if context not allocated for bus
2520 * allocate and init context
2521 * set present in root table for this bus
2522 * init context with domain, translation etc
2523 * endfor
2524 * endfor
ba395927 2525 */
19943b0e
DW		 2526 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2527 for_each_rmrr_units(rmrr) {
2528 for (i = 0; i < rmrr->devices_cnt; i++) {
2529 pdev = rmrr->devices[i];
2530 /*
2531 * some BIOS lists non-exist devices in DMAR
2532 * table.
2533 */
2534 if (!pdev)
2535 continue;
2536 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2537 if (ret)
2538 printk(KERN_ERR
2539 "IOMMU: mapping reserved region failed\n");
ba395927 2540 }
4ed0d3e6 2541 }
49a0429e 2542
19943b0e
DW		 2543 iommu_prepare_isa();
2544
ba395927
KA		 2545 /*
2546 * for each drhd
2547 * enable fault log
2548 * global invalidate context cache
2549 * global invalidate iotlb
2550 * enable translation
2551 */
2552 for_each_drhd_unit(drhd) {
51a63e67
JC		 2553 if (drhd->ignored) {
2554 /*
2555 * we always have to disable PMRs or DMA may fail on
2556 * this device
2557 */
2558 if (force_on)
2559 iommu_disable_protect_mem_regions(drhd->iommu);
ba395927 2560 continue;
51a63e67 2561 }
ba395927 2562 iommu = drhd->iommu;
ba395927
KA		 2563
2564 iommu_flush_write_buffer(iommu);
2565
3460a6d9
KA		 2566 ret = dmar_set_interrupt(iommu);
2567 if (ret)
2568 goto error;
2569
ba395927
KA		 2570 iommu_set_root_entry(iommu);
2571
4c25a2c1 2572 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2573 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2574
ba395927
KA		 2575 ret = iommu_enable_translation(iommu);
2576 if (ret)
2577 goto error;
b94996c9
DW		 2578
2579 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2580 }
2581
2582 return 0;
2583error:
2584 for_each_drhd_unit(drhd) {
2585 if (drhd->ignored)
2586 continue;
2587 iommu = drhd->iommu;
2588 free_iommu(iommu);
2589 }
d9630fe9 2590 kfree(g_iommus);
ba395927
KA		 2591 return ret;
2592}
2593
5a5e02a6 2594/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2595static struct iova *intel_alloc_iova(struct device *dev,
2596 struct dmar_domain *domain,
2597 unsigned long nrpages, uint64_t dma_mask)
ba395927 2598{
ba395927 2599 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2600 struct iova *iova = NULL;
ba395927 2601
875764de
DW		 2602 /* Restrict dma_mask to the width that the iommu can handle */
2603 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2604
2605 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2606 /*
2607 * First try to allocate an io virtual address in
284901a9 2608 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2609 * from higher range
ba395927 2610 */
875764de
DW		 2611 iova = alloc_iova(&domain->iovad, nrpages,
2612 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2613 if (iova)
2614 return iova;
2615 }
2616 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2617 if (unlikely(!iova)) {
2618 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2619 nrpages, pci_name(pdev));
f76aec76
KA		 2620 return NULL;
2621 }
2622
2623 return iova;
2624}
2625
147202aa 2626static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2627{
2628 struct dmar_domain *domain;
2629 int ret;
2630
2631 domain = get_domain_for_dev(pdev,
2632 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2633 if (!domain) {
2634 printk(KERN_ERR
2635 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2636 return NULL;
ba395927
KA		 2637 }
2638
2639 /* make sure context mapping is ok */
5331fe6f 2640 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2641 ret = domain_context_mapping(domain, pdev,
2642 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2643 if (ret) {
2644 printk(KERN_ERR
2645 "Domain context map for %s failed",
2646 pci_name(pdev));
4fe05bbc 2647 return NULL;
f76aec76 2648 }
ba395927
KA		 2649 }
2650
f76aec76
KA		 2651 return domain;
2652}
2653
147202aa
DW		 2654static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2655{
2656 struct device_domain_info *info;
2657
2658 /* No lock here, assumes no domain exit in normal case */
2659 info = dev->dev.archdata.iommu;
2660 if (likely(info))
2661 return info->domain;
2662
2663 return __get_valid_domain_for_dev(dev);
2664}
2665
2c2e2c38
FY		 2666static int iommu_dummy(struct pci_dev *pdev)
2667{
2668 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2669}
2670
2671/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2672static int iommu_no_mapping(struct device *dev)
2c2e2c38 2673{
73676832 2674 struct pci_dev *pdev;
2c2e2c38
FY		 2675 int found;
2676
73676832
DW		 2677 if (unlikely(dev->bus != &pci_bus_type))
2678 return 1;
2679
2680 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2681 if (iommu_dummy(pdev))
2682 return 1;
2683
2c2e2c38 2684 if (!iommu_identity_mapping)
1e4c64c4 2685 return 0;
2c2e2c38
FY		 2686
2687 found = identity_mapping(pdev);
2688 if (found) {
6941af28 2689 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2690 return 1;
2691 else {
2692 /*
2693 * 32 bit DMA is removed from si_domain and fall back
2694 * to non-identity mapping.
2695 */
2696 domain_remove_one_dev_info(si_domain, pdev);
2697 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2698 pci_name(pdev));
2699 return 0;
2700 }
2701 } else {
2702 /*
2703 * In case of a detached 64 bit DMA device from vm, the device
2704 * is put into si_domain for identity mapping.
2705 */
6941af28 2706 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2707 int ret;
5fe60f4e
DW		 2708 ret = domain_add_dev_info(si_domain, pdev,
2709 hw_pass_through ?
2710 CONTEXT_TT_PASS_THROUGH :
2711 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2712 if (!ret) {
2713 printk(KERN_INFO "64bit %s uses identity mapping\n",
2714 pci_name(pdev));
2715 return 1;
2716 }
2717 }
2718 }
2719
1e4c64c4 2720 return 0;
2c2e2c38
FY		 2721}
2722
bb9e6d65
FT		 2723static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2724 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2725{
2726 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2727 struct dmar_domain *domain;
5b6985ce 2728 phys_addr_t start_paddr;
f76aec76
KA		 2729 struct iova *iova;
2730 int prot = 0;
6865f0d1 2731 int ret;
8c11e798 2732 struct intel_iommu *iommu;
33041ec0 2733 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2734
2735 BUG_ON(dir == DMA_NONE);
2c2e2c38 2736
73676832 2737 if (iommu_no_mapping(hwdev))
6865f0d1 2738 return paddr;
f76aec76
KA		 2739
2740 domain = get_valid_domain_for_dev(pdev);
2741 if (!domain)
2742 return 0;
2743
8c11e798 2744 iommu = domain_get_iommu(domain);
88cb6a74 2745 size = aligned_nrpages(paddr, size);
f76aec76 2746
c681d0ba 2747 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2748 if (!iova)
2749 goto error;
2750
ba395927
KA		 2751 /*
2752 * Check if DMAR supports zero-length reads on write only
2753 * mappings..
2754 */
2755 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2756 !cap_zlr(iommu->cap))
ba395927
KA		 2757 prot |= DMA_PTE_READ;
2758 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2759 prot |= DMA_PTE_WRITE;
2760 /*
6865f0d1 2761 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2762 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2763 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2764 * is not a big problem
2765 */
0ab36de2 2766 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2767 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2768 if (ret)
2769 goto error;
2770
1f0ef2aa
DW		 2771 /* it's a non-present to present mapping. Only flush if caching mode */
2772 if (cap_caching_mode(iommu->cap))
82653633 2773 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
1f0ef2aa 2774 else
8c11e798 2775 iommu_flush_write_buffer(iommu);
f76aec76 2776
03d6a246
DW		 2777 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2778 start_paddr += paddr & ~PAGE_MASK;
2779 return start_paddr;
ba395927 2780
ba395927 2781error:
f76aec76
KA		 2782 if (iova)
2783 __free_iova(&domain->iovad, iova);
4cf2e75d 2784 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2785 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2786 return 0;
2787}
2788
ffbbef5c
FT		 2789static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2790 unsigned long offset, size_t size,
2791 enum dma_data_direction dir,
2792 struct dma_attrs *attrs)
bb9e6d65 2793{
ffbbef5c
FT		 2794 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2795 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2796}
2797
5e0d2a6f 2798static void flush_unmaps(void)
2799{
80b20dd8 2800 int i, j;
5e0d2a6f 2801
5e0d2a6f 2802 timer_on = 0;
2803
2804 /* just flush them all */
2805 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2806 struct intel_iommu *iommu = g_iommus[i];
2807 if (!iommu)
2808 continue;
c42d9f32 2809
9dd2fe89
YZ		 2810 if (!deferred_flush[i].next)
2811 continue;
2812
78d5f0f5
NA		 2813 /* In caching mode, global flushes turn emulation expensive */
2814 if (!cap_caching_mode(iommu->cap))
2815 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2816 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2817 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2818 unsigned long mask;
2819 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 2820 struct dmar_domain *domain = deferred_flush[i].domain[j];
2821
2822 /* On real hardware multiple invalidations are expensive */
2823 if (cap_caching_mode(iommu->cap))
2824 iommu_flush_iotlb_psi(iommu, domain->id,
2825 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
2826 else {
2827 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
2828 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2829 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
2830 }
93a23a72 2831 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2832 }
9dd2fe89 2833 deferred_flush[i].next = 0;
5e0d2a6f 2834 }
2835
5e0d2a6f 2836 list_size = 0;
5e0d2a6f 2837}
2838
2839static void flush_unmaps_timeout(unsigned long data)
2840{
80b20dd8 2841 unsigned long flags;
2842
2843 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2844 flush_unmaps();
80b20dd8 2845 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2846}
2847
2848static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2849{
2850 unsigned long flags;
80b20dd8 2851 int next, iommu_id;
8c11e798 2852 struct intel_iommu *iommu;
5e0d2a6f 2853
2854 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2855 if (list_size == HIGH_WATER_MARK)
2856 flush_unmaps();
2857
8c11e798
WH		 2858 iommu = domain_get_iommu(dom);
2859 iommu_id = iommu->seq_id;
c42d9f32 2860
80b20dd8 2861 next = deferred_flush[iommu_id].next;
2862 deferred_flush[iommu_id].domain[next] = dom;
2863 deferred_flush[iommu_id].iova[next] = iova;
2864 deferred_flush[iommu_id].next++;
5e0d2a6f 2865
2866 if (!timer_on) {
2867 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2868 timer_on = 1;
2869 }
2870 list_size++;
2871 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2872}
2873
ffbbef5c
FT		 2874static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2875 size_t size, enum dma_data_direction dir,
2876 struct dma_attrs *attrs)
ba395927 2877{
ba395927 2878 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2879 struct dmar_domain *domain;
d794dc9b 2880 unsigned long start_pfn, last_pfn;
ba395927 2881 struct iova *iova;
8c11e798 2882 struct intel_iommu *iommu;
ba395927 2883
73676832 2884 if (iommu_no_mapping(dev))
f76aec76 2885 return;
2c2e2c38 2886
ba395927
KA		 2887 domain = find_domain(pdev);
2888 BUG_ON(!domain);
2889
8c11e798
WH		 2890 iommu = domain_get_iommu(domain);
2891
ba395927 2892 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2893 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2894 (unsigned long long)dev_addr))
ba395927 2895 return;
ba395927 2896
d794dc9b
DW		 2897 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2898 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2899
d794dc9b
DW		 2900 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2901 pci_name(pdev), start_pfn, last_pfn);
ba395927 2902
f76aec76 2903 /* clear the whole page */
d794dc9b
DW		 2904 dma_pte_clear_range(domain, start_pfn, last_pfn);
2905
f76aec76 2906 /* free page tables */
d794dc9b
DW		 2907 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2908
5e0d2a6f 2909 if (intel_iommu_strict) {
03d6a246 2910 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 2911 last_pfn - start_pfn + 1, 0);
5e0d2a6f 2912 /* free iova */
2913 __free_iova(&domain->iovad, iova);
2914 } else {
2915 add_unmap(domain, iova);
2916 /*
2917 * queue up the release of the unmap to save the 1/6th of the
2918 * cpu used up by the iotlb flush operation...
2919 */
5e0d2a6f 2920 }
ba395927
KA		 2921}
2922
d7ab5c46
FT		 2923static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2924 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2925{
2926 void *vaddr;
2927 int order;
2928
5b6985ce 2929 size = PAGE_ALIGN(size);
ba395927 2930 order = get_order(size);
e8bb910d
AW		 2931
2932 if (!iommu_no_mapping(hwdev))
2933 flags &= ~(GFP_DMA | GFP_DMA32);
2934 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
2935 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
2936 flags |= GFP_DMA;
2937 else
2938 flags |= GFP_DMA32;
2939 }
ba395927
KA		 2940
2941 vaddr = (void *)__get_free_pages(flags, order);
2942 if (!vaddr)
2943 return NULL;
2944 memset(vaddr, 0, size);
2945
bb9e6d65
FT		 2946 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2947 DMA_BIDIRECTIONAL,
2948 hwdev->coherent_dma_mask);
ba395927
KA		 2949 if (*dma_handle)
2950 return vaddr;
2951 free_pages((unsigned long)vaddr, order);
2952 return NULL;
2953}
2954
d7ab5c46
FT		 2955static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2956 dma_addr_t dma_handle)
ba395927
KA		 2957{
2958 int order;
2959
5b6985ce 2960 size = PAGE_ALIGN(size);
ba395927
KA		 2961 order = get_order(size);
2962
0db9b7ae 2963 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 2964 free_pages((unsigned long)vaddr, order);
2965}
2966
d7ab5c46
FT		 2967static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2968 int nelems, enum dma_data_direction dir,
2969 struct dma_attrs *attrs)
ba395927 2970{
ba395927
KA		 2971 struct pci_dev *pdev = to_pci_dev(hwdev);
2972 struct dmar_domain *domain;
d794dc9b 2973 unsigned long start_pfn, last_pfn;
f76aec76 2974 struct iova *iova;
8c11e798 2975 struct intel_iommu *iommu;
ba395927 2976
73676832 2977 if (iommu_no_mapping(hwdev))
ba395927
KA		 2978 return;
2979
2980 domain = find_domain(pdev);
8c11e798
WH		 2981 BUG_ON(!domain);
2982
2983 iommu = domain_get_iommu(domain);
ba395927 2984
c03ab37c 2985 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2986 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2987 (unsigned long long)sglist[0].dma_address))
f76aec76 2988 return;
f76aec76 2989
d794dc9b
DW		 2990 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2991 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2992
2993 /* clear the whole page */
d794dc9b
DW		 2994 dma_pte_clear_range(domain, start_pfn, last_pfn);
2995
f76aec76 2996 /* free page tables */
d794dc9b 2997 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2998
acea0018
DW		 2999 if (intel_iommu_strict) {
3000 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 3001 last_pfn - start_pfn + 1, 0);
acea0018
DW		 3002 /* free iova */
3003 __free_iova(&domain->iovad, iova);
3004 } else {
3005 add_unmap(domain, iova);
3006 /*
3007 * queue up the release of the unmap to save the 1/6th of the
3008 * cpu used up by the iotlb flush operation...
3009 */
3010 }
ba395927
KA		 3011}
3012
ba395927 3013static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3014 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3015{
3016 int i;
c03ab37c 3017 struct scatterlist *sg;
ba395927 3018
c03ab37c 3019 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3020 BUG_ON(!sg_page(sg));
4cf2e75d 3021 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3022 sg->dma_length = sg->length;
ba395927
KA		 3023 }
3024 return nelems;
3025}
3026
d7ab5c46
FT		 3027static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3028 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3029{
ba395927 3030 int i;
ba395927
KA		 3031 struct pci_dev *pdev = to_pci_dev(hwdev);
3032 struct dmar_domain *domain;
f76aec76
KA		 3033 size_t size = 0;
3034 int prot = 0;
f76aec76
KA		 3035 struct iova *iova = NULL;
3036 int ret;
c03ab37c 3037 struct scatterlist *sg;
b536d24d 3038 unsigned long start_vpfn;
8c11e798 3039 struct intel_iommu *iommu;
ba395927
KA		 3040
3041 BUG_ON(dir == DMA_NONE);
73676832 3042 if (iommu_no_mapping(hwdev))
c03ab37c 3043 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3044
f76aec76
KA		 3045 domain = get_valid_domain_for_dev(pdev);
3046 if (!domain)
3047 return 0;
3048
8c11e798
WH		 3049 iommu = domain_get_iommu(domain);
3050
b536d24d 3051 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3052 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3053
5a5e02a6
DW		 3054 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3055 pdev->dma_mask);
f76aec76 3056 if (!iova) {
c03ab37c 3057 sglist->dma_length = 0;
f76aec76
KA		 3058 return 0;
3059 }
3060
3061 /*
3062 * Check if DMAR supports zero-length reads on write only
3063 * mappings..
3064 */
3065 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3066 !cap_zlr(iommu->cap))
f76aec76
KA		 3067 prot |= DMA_PTE_READ;
3068 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3069 prot |= DMA_PTE_WRITE;
3070
b536d24d 3071 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3072
f532959b 3073 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3074 if (unlikely(ret)) {
3075 /* clear the page */
3076 dma_pte_clear_range(domain, start_vpfn,
3077 start_vpfn + size - 1);
3078 /* free page tables */
3079 dma_pte_free_pagetable(domain, start_vpfn,
3080 start_vpfn + size - 1);
3081 /* free iova */
3082 __free_iova(&domain->iovad, iova);
3083 return 0;
ba395927
KA		 3084 }
3085
1f0ef2aa
DW		 3086 /* it's a non-present to present mapping. Only flush if caching mode */
3087 if (cap_caching_mode(iommu->cap))
82653633 3088 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
1f0ef2aa 3089 else
8c11e798 3090 iommu_flush_write_buffer(iommu);
1f0ef2aa 3091
ba395927
KA		 3092 return nelems;
3093}
3094
dfb805e8
FT		 3095static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3096{
3097 return !dma_addr;
3098}
3099
160c1d8e 3100struct dma_map_ops intel_dma_ops = {
ba395927
KA		 3101 .alloc_coherent = intel_alloc_coherent,
3102 .free_coherent = intel_free_coherent,
ba395927
KA		 3103 .map_sg = intel_map_sg,
3104 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3105 .map_page = intel_map_page,
3106 .unmap_page = intel_unmap_page,
dfb805e8 3107 .mapping_error = intel_mapping_error,
ba395927
KA		 3108};
3109
3110static inline int iommu_domain_cache_init(void)
3111{
3112 int ret = 0;
3113
3114 iommu_domain_cache = kmem_cache_create("iommu_domain",
3115 sizeof(struct dmar_domain),
3116 0,
3117 SLAB_HWCACHE_ALIGN,
3118
3119 NULL);
3120 if (!iommu_domain_cache) {
3121 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3122 ret = -ENOMEM;
3123 }
3124
3125 return ret;
3126}
3127
3128static inline int iommu_devinfo_cache_init(void)
3129{
3130 int ret = 0;
3131
3132 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3133 sizeof(struct device_domain_info),
3134 0,
3135 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3136 NULL);
3137 if (!iommu_devinfo_cache) {
3138 printk(KERN_ERR "Couldn't create devinfo cache\n");
3139 ret = -ENOMEM;
3140 }
3141
3142 return ret;
3143}
3144
3145static inline int iommu_iova_cache_init(void)
3146{
3147 int ret = 0;
3148
3149 iommu_iova_cache = kmem_cache_create("iommu_iova",
3150 sizeof(struct iova),
3151 0,
3152 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3153 NULL);
3154 if (!iommu_iova_cache) {
3155 printk(KERN_ERR "Couldn't create iova cache\n");
3156 ret = -ENOMEM;
3157 }
3158
3159 return ret;
3160}
3161
3162static int __init iommu_init_mempool(void)
3163{
3164 int ret;
3165 ret = iommu_iova_cache_init();
3166 if (ret)
3167 return ret;
3168
3169 ret = iommu_domain_cache_init();
3170 if (ret)
3171 goto domain_error;
3172
3173 ret = iommu_devinfo_cache_init();
3174 if (!ret)
3175 return ret;
3176
3177 kmem_cache_destroy(iommu_domain_cache);
3178domain_error:
3179 kmem_cache_destroy(iommu_iova_cache);
3180
3181 return -ENOMEM;
3182}
3183
3184static void __init iommu_exit_mempool(void)
3185{
3186 kmem_cache_destroy(iommu_devinfo_cache);
3187 kmem_cache_destroy(iommu_domain_cache);
3188 kmem_cache_destroy(iommu_iova_cache);
3189
3190}
3191
556ab45f
DW		 3192static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3193{
3194 struct dmar_drhd_unit *drhd;
3195 u32 vtbar;
3196 int rc;
3197
3198 /* We know that this device on this chipset has its own IOMMU.
3199 * If we find it under a different IOMMU, then the BIOS is lying
3200 * to us. Hope that the IOMMU for this device is actually
3201 * disabled, and it needs no translation...
3202 */
3203 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3204 if (rc) {
3205 /* "can't" happen */
3206 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3207 return;
3208 }
3209 vtbar &= 0xffff0000;
3210
3211 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3212 drhd = dmar_find_matched_drhd_unit(pdev);
3213 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3214 TAINT_FIRMWARE_WORKAROUND,
3215 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3216 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3217}
3218DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3219
ba395927
KA		 3220static void __init init_no_remapping_devices(void)
3221{
3222 struct dmar_drhd_unit *drhd;
3223
3224 for_each_drhd_unit(drhd) {
3225 if (!drhd->include_all) {
3226 int i;
3227 for (i = 0; i < drhd->devices_cnt; i++)
3228 if (drhd->devices[i] != NULL)
3229 break;
3230 /* ignore DMAR unit if no pci devices exist */
3231 if (i == drhd->devices_cnt)
3232 drhd->ignored = 1;
3233 }
3234 }
3235
ba395927
KA		 3236 for_each_drhd_unit(drhd) {
3237 int i;
3238 if (drhd->ignored || drhd->include_all)
3239 continue;
3240
3241 for (i = 0; i < drhd->devices_cnt; i++)
3242 if (drhd->devices[i] &&
c0771df8 3243 !IS_GFX_DEVICE(drhd->devices[i]))
ba395927
KA		 3244 break;
3245
3246 if (i < drhd->devices_cnt)
3247 continue;
3248
c0771df8
DW		 3249 /* This IOMMU has *only* gfx devices. Either bypass it or
3250 set the gfx_mapped flag, as appropriate */
3251 if (dmar_map_gfx) {
3252 intel_iommu_gfx_mapped = 1;
3253 } else {
3254 drhd->ignored = 1;
3255 for (i = 0; i < drhd->devices_cnt; i++) {
3256 if (!drhd->devices[i])
3257 continue;
3258 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3259 }
ba395927
KA		 3260 }
3261 }
3262}
3263
f59c7b69
FY		 3264#ifdef CONFIG_SUSPEND
3265static int init_iommu_hw(void)
3266{
3267 struct dmar_drhd_unit *drhd;
3268 struct intel_iommu *iommu = NULL;
3269
3270 for_each_active_iommu(iommu, drhd)
3271 if (iommu->qi)
3272 dmar_reenable_qi(iommu);
3273
b779260b
JC		 3274 for_each_iommu(iommu, drhd) {
3275 if (drhd->ignored) {
3276 /*
3277 * we always have to disable PMRs or DMA may fail on
3278 * this device
3279 */
3280 if (force_on)
3281 iommu_disable_protect_mem_regions(iommu);
3282 continue;
3283 }
3284
f59c7b69
FY		 3285 iommu_flush_write_buffer(iommu);
3286
3287 iommu_set_root_entry(iommu);
3288
3289 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3290 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3291 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3292 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3293 if (iommu_enable_translation(iommu))
3294 return 1;
b94996c9 3295 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3296 }
3297
3298 return 0;
3299}
3300
3301static void iommu_flush_all(void)
3302{
3303 struct dmar_drhd_unit *drhd;
3304 struct intel_iommu *iommu;
3305
3306 for_each_active_iommu(iommu, drhd) {
3307 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3308 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3309 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3310 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3311 }
3312}
3313
134fac3f 3314static int iommu_suspend(void)
f59c7b69
FY		 3315{
3316 struct dmar_drhd_unit *drhd;
3317 struct intel_iommu *iommu = NULL;
3318 unsigned long flag;
3319
3320 for_each_active_iommu(iommu, drhd) {
3321 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3322 GFP_ATOMIC);
3323 if (!iommu->iommu_state)
3324 goto nomem;
3325 }
3326
3327 iommu_flush_all();
3328
3329 for_each_active_iommu(iommu, drhd) {
3330 iommu_disable_translation(iommu);
3331
1f5b3c3f 3332 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3333
3334 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3335 readl(iommu->reg + DMAR_FECTL_REG);
3336 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3337 readl(iommu->reg + DMAR_FEDATA_REG);
3338 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3339 readl(iommu->reg + DMAR_FEADDR_REG);
3340 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3341 readl(iommu->reg + DMAR_FEUADDR_REG);
3342
1f5b3c3f 3343 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3344 }
3345 return 0;
3346
3347nomem:
3348 for_each_active_iommu(iommu, drhd)
3349 kfree(iommu->iommu_state);
3350
3351 return -ENOMEM;
3352}
3353
134fac3f 3354static void iommu_resume(void)
f59c7b69
FY		 3355{
3356 struct dmar_drhd_unit *drhd;
3357 struct intel_iommu *iommu = NULL;
3358 unsigned long flag;
3359
3360 if (init_iommu_hw()) {
b779260b
JC		 3361 if (force_on)
3362 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3363 else
3364 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3365 return;
f59c7b69
FY		 3366 }
3367
3368 for_each_active_iommu(iommu, drhd) {
3369
1f5b3c3f 3370 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3371
3372 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3373 iommu->reg + DMAR_FECTL_REG);
3374 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3375 iommu->reg + DMAR_FEDATA_REG);
3376 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3377 iommu->reg + DMAR_FEADDR_REG);
3378 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3379 iommu->reg + DMAR_FEUADDR_REG);
3380
1f5b3c3f 3381 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3382 }
3383
3384 for_each_active_iommu(iommu, drhd)
3385 kfree(iommu->iommu_state);
f59c7b69
FY		 3386}
3387
134fac3f 3388static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3389 .resume = iommu_resume,
3390 .suspend = iommu_suspend,
3391};
3392
134fac3f 3393static void __init init_iommu_pm_ops(void)
f59c7b69 3394{
134fac3f 3395 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3396}
3397
3398#else
99592ba4 3399static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3400#endif /* CONFIG_PM */
3401
318fe7df
SS		 3402LIST_HEAD(dmar_rmrr_units);
3403
3404static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
3405{
3406 list_add(&rmrr->list, &dmar_rmrr_units);
3407}
3408
3409
3410int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3411{
3412 struct acpi_dmar_reserved_memory *rmrr;
3413 struct dmar_rmrr_unit *rmrru;
3414
3415 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3416 if (!rmrru)
3417 return -ENOMEM;
3418
3419 rmrru->hdr = header;
3420 rmrr = (struct acpi_dmar_reserved_memory *)header;
3421 rmrru->base_address = rmrr->base_address;
3422 rmrru->end_address = rmrr->end_address;
3423
3424 dmar_register_rmrr_unit(rmrru);
3425 return 0;
3426}
3427
3428static int __init
3429rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
3430{
3431 struct acpi_dmar_reserved_memory *rmrr;
3432 int ret;
3433
3434 rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
3435 ret = dmar_parse_dev_scope((void *)(rmrr + 1),
3436 ((void *)rmrr) + rmrr->header.length,
3437 &rmrru->devices_cnt, &rmrru->devices, rmrr->segment);
3438
3439 if (ret || (rmrru->devices_cnt == 0)) {
3440 list_del(&rmrru->list);
3441 kfree(rmrru);
3442 }
3443 return ret;
3444}
3445
3446static LIST_HEAD(dmar_atsr_units);
3447
3448int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3449{
3450 struct acpi_dmar_atsr *atsr;
3451 struct dmar_atsr_unit *atsru;
3452
3453 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3454 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3455 if (!atsru)
3456 return -ENOMEM;
3457
3458 atsru->hdr = hdr;
3459 atsru->include_all = atsr->flags & 0x1;
3460
3461 list_add(&atsru->list, &dmar_atsr_units);
3462
3463 return 0;
3464}
3465
3466static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
3467{
3468 int rc;
3469 struct acpi_dmar_atsr *atsr;
3470
3471 if (atsru->include_all)
3472 return 0;
3473
3474 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3475 rc = dmar_parse_dev_scope((void *)(atsr + 1),
3476 (void *)atsr + atsr->header.length,
3477 &atsru->devices_cnt, &atsru->devices,
3478 atsr->segment);
3479 if (rc || !atsru->devices_cnt) {
3480 list_del(&atsru->list);
3481 kfree(atsru);
3482 }
3483
3484 return rc;
3485}
3486
3487int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3488{
3489 int i;
3490 struct pci_bus *bus;
3491 struct acpi_dmar_atsr *atsr;
3492 struct dmar_atsr_unit *atsru;
3493
3494 dev = pci_physfn(dev);
3495
3496 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3497 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3498 if (atsr->segment == pci_domain_nr(dev->bus))
3499 goto found;
3500 }
3501
3502 return 0;
3503
3504found:
3505 for (bus = dev->bus; bus; bus = bus->parent) {
3506 struct pci_dev *bridge = bus->self;
3507
3508 if (!bridge || !pci_is_pcie(bridge) ||
3509 bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
3510 return 0;
3511
3512 if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
3513 for (i = 0; i < atsru->devices_cnt; i++)
3514 if (atsru->devices[i] == bridge)
3515 return 1;
3516 break;
3517 }
3518 }
3519
3520 if (atsru->include_all)
3521 return 1;
3522
3523 return 0;
3524}
3525
3526int dmar_parse_rmrr_atsr_dev(void)
3527{
3528 struct dmar_rmrr_unit *rmrr, *rmrr_n;
3529 struct dmar_atsr_unit *atsr, *atsr_n;
3530 int ret = 0;
3531
3532 list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
3533 ret = rmrr_parse_dev(rmrr);
3534 if (ret)
3535 return ret;
3536 }
3537
3538 list_for_each_entry_safe(atsr, atsr_n, &dmar_atsr_units, list) {
3539 ret = atsr_parse_dev(atsr);
3540 if (ret)
3541 return ret;
3542 }
3543
3544 return ret;
3545}
3546
99dcaded
FY		 3547/*
3548 * Here we only respond to action of unbound device from driver.
3549 *
3550 * Added device is not attached to its DMAR domain here yet. That will happen
3551 * when mapping the device to iova.
3552 */
3553static int device_notifier(struct notifier_block *nb,
3554 unsigned long action, void *data)
3555{
3556 struct device *dev = data;
3557 struct pci_dev *pdev = to_pci_dev(dev);
3558 struct dmar_domain *domain;
3559
44cd613c
DW		 3560 if (iommu_no_mapping(dev))
3561 return 0;
3562
99dcaded
FY		 3563 domain = find_domain(pdev);
3564 if (!domain)
3565 return 0;
3566
a97590e5 3567 if (action == BUS_NOTIFY_UNBOUND_DRIVER && !iommu_pass_through) {
99dcaded
FY		 3568 domain_remove_one_dev_info(domain, pdev);
3569
a97590e5
AW		 3570 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3571 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3572 list_empty(&domain->devices))
3573 domain_exit(domain);
3574 }
3575
99dcaded
FY		 3576 return 0;
3577}
3578
3579static struct notifier_block device_nb = {
3580 .notifier_call = device_notifier,
3581};
3582
ba395927
KA		 3583int __init intel_iommu_init(void)
3584{
3585 int ret = 0;
3586
a59b50e9
JC		 3587 /* VT-d is required for a TXT/tboot launch, so enforce that */
3588 force_on = tboot_force_iommu();
3589
3590 if (dmar_table_init()) {
3591 if (force_on)
3592 panic("tboot: Failed to initialize DMAR table\n");
ba395927 3593 return -ENODEV;
a59b50e9 3594 }
ba395927 3595
c2c7286a 3596 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3597 if (force_on)
3598 panic("tboot: Failed to initialize DMAR device scope\n");
1886e8a9 3599 return -ENODEV;
a59b50e9 3600 }
1886e8a9 3601
75f1cdf1 3602 if (no_iommu || dmar_disabled)
2ae21010
SS		 3603 return -ENODEV;
3604
51a63e67
JC		 3605 if (iommu_init_mempool()) {
3606 if (force_on)
3607 panic("tboot: Failed to initialize iommu memory\n");
3608 return -ENODEV;
3609 }
3610
318fe7df
SS		 3611 if (list_empty(&dmar_rmrr_units))
3612 printk(KERN_INFO "DMAR: No RMRR found\n");
3613
3614 if (list_empty(&dmar_atsr_units))
3615 printk(KERN_INFO "DMAR: No ATSR found\n");
3616
51a63e67
JC		 3617 if (dmar_init_reserved_ranges()) {
3618 if (force_on)
3619 panic("tboot: Failed to reserve iommu ranges\n");
3620 return -ENODEV;
3621 }
ba395927
KA		 3622
3623 init_no_remapping_devices();
3624
b779260b 3625 ret = init_dmars();
ba395927 3626 if (ret) {
a59b50e9
JC		 3627 if (force_on)
3628 panic("tboot: Failed to initialize DMARs\n");
ba395927
KA		 3629 printk(KERN_ERR "IOMMU: dmar init failed\n");
3630 put_iova_domain(&reserved_iova_list);
3631 iommu_exit_mempool();
3632 return ret;
3633 }
3634 printk(KERN_INFO
3635 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3636
5e0d2a6f 3637 init_timer(&unmap_timer);
75f1cdf1
FT		 3638#ifdef CONFIG_SWIOTLB
3639 swiotlb = 0;
3640#endif
19943b0e 3641 dma_ops = &intel_dma_ops;
4ed0d3e6 3642
134fac3f 3643 init_iommu_pm_ops();
a8bcbb0d 3644
4236d97d 3645 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
a8bcbb0d 3646
99dcaded
FY		 3647 bus_register_notifier(&pci_bus_type, &device_nb);
3648
ba395927
KA		 3649 return 0;
3650}
e820482c 3651
3199aa6b
HW		 3652static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3653 struct pci_dev *pdev)
3654{
3655 struct pci_dev *tmp, *parent;
3656
3657 if (!iommu || !pdev)
3658 return;
3659
3660 /* dependent device detach */
3661 tmp = pci_find_upstream_pcie_bridge(pdev);
3662 /* Secondary interface's bus number and devfn 0 */
3663 if (tmp) {
3664 parent = pdev->bus->self;
3665 while (parent != tmp) {
3666 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3667 parent->devfn);
3199aa6b
HW		 3668 parent = parent->bus->self;
3669 }
45e829ea 3670 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 3671 iommu_detach_dev(iommu,
3672 tmp->subordinate->number, 0);
3673 else /* this is a legacy PCI bridge */
276dbf99
DW		 3674 iommu_detach_dev(iommu, tmp->bus->number,
3675 tmp->devfn);
3199aa6b
HW		 3676 }
3677}
3678
2c2e2c38 3679static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3680 struct pci_dev *pdev)
3681{
3682 struct device_domain_info *info;
3683 struct intel_iommu *iommu;
3684 unsigned long flags;
3685 int found = 0;
3686 struct list_head *entry, *tmp;
3687
276dbf99
DW		 3688 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3689 pdev->devfn);
c7151a8d
WH		 3690 if (!iommu)
3691 return;
3692
3693 spin_lock_irqsave(&device_domain_lock, flags);
3694 list_for_each_safe(entry, tmp, &domain->devices) {
3695 info = list_entry(entry, struct device_domain_info, link);
8519dc44
MH		 3696 if (info->segment == pci_domain_nr(pdev->bus) &&
3697 info->bus == pdev->bus->number &&
c7151a8d
WH		 3698 info->devfn == pdev->devfn) {
3699 list_del(&info->link);
3700 list_del(&info->global);
3701 if (info->dev)
3702 info->dev->dev.archdata.iommu = NULL;
3703 spin_unlock_irqrestore(&device_domain_lock, flags);
3704
93a23a72 3705 iommu_disable_dev_iotlb(info);
c7151a8d 3706 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3707 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3708 free_devinfo_mem(info);
3709
3710 spin_lock_irqsave(&device_domain_lock, flags);
3711
3712 if (found)
3713 break;
3714 else
3715 continue;
3716 }
3717
3718 /* if there is no other devices under the same iommu
3719 * owned by this domain, clear this iommu in iommu_bmp
3720 * update iommu count and coherency
3721 */
276dbf99
DW		 3722 if (iommu == device_to_iommu(info->segment, info->bus,
3723 info->devfn))
c7151a8d
WH		 3724 found = 1;
3725 }
3726
3e7abe25
RD		 3727 spin_unlock_irqrestore(&device_domain_lock, flags);
3728
c7151a8d
WH		 3729 if (found == 0) {
3730 unsigned long tmp_flags;
3731 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3732 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3733 domain->iommu_count--;
58c610bd 3734 domain_update_iommu_cap(domain);
c7151a8d 3735 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 3736
9b4554b2
AW		 3737 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3738 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
3739 spin_lock_irqsave(&iommu->lock, tmp_flags);
3740 clear_bit(domain->id, iommu->domain_ids);
3741 iommu->domains[domain->id] = NULL;
3742 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
3743 }
c7151a8d 3744 }
c7151a8d
WH		 3745}
3746
3747static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3748{
3749 struct device_domain_info *info;
3750 struct intel_iommu *iommu;
3751 unsigned long flags1, flags2;
3752
3753 spin_lock_irqsave(&device_domain_lock, flags1);
3754 while (!list_empty(&domain->devices)) {
3755 info = list_entry(domain->devices.next,
3756 struct device_domain_info, link);
3757 list_del(&info->link);
3758 list_del(&info->global);
3759 if (info->dev)
3760 info->dev->dev.archdata.iommu = NULL;
3761
3762 spin_unlock_irqrestore(&device_domain_lock, flags1);
3763
93a23a72 3764 iommu_disable_dev_iotlb(info);
276dbf99 3765 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3766 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3767 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3768
3769 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3770 * and capabilities
c7151a8d
WH		 3771 */
3772 spin_lock_irqsave(&domain->iommu_lock, flags2);
3773 if (test_and_clear_bit(iommu->seq_id,
3774 &domain->iommu_bmp)) {
3775 domain->iommu_count--;
58c610bd 3776 domain_update_iommu_cap(domain);
c7151a8d
WH		 3777 }
3778 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3779
3780 free_devinfo_mem(info);
3781 spin_lock_irqsave(&device_domain_lock, flags1);
3782 }
3783 spin_unlock_irqrestore(&device_domain_lock, flags1);
3784}
3785
5e98c4b1
WH		 3786/* domain id for virtual machine, it won't be set in context */
3787static unsigned long vm_domid;
3788
3789static struct dmar_domain *iommu_alloc_vm_domain(void)
3790{
3791 struct dmar_domain *domain;
3792
3793 domain = alloc_domain_mem();
3794 if (!domain)
3795 return NULL;
3796
3797 domain->id = vm_domid++;
4c923d47 3798 domain->nid = -1;
5e98c4b1
WH		 3799 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3800 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3801
3802 return domain;
3803}
3804
2c2e2c38 3805static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3806{
3807 int adjust_width;
3808
3809 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3810 spin_lock_init(&domain->iommu_lock);
3811
3812 domain_reserve_special_ranges(domain);
3813
3814 /* calculate AGAW */
3815 domain->gaw = guest_width;
3816 adjust_width = guestwidth_to_adjustwidth(guest_width);
3817 domain->agaw = width_to_agaw(adjust_width);
3818
3819 INIT_LIST_HEAD(&domain->devices);
3820
3821 domain->iommu_count = 0;
3822 domain->iommu_coherency = 0;
c5b15255 3823 domain->iommu_snooping = 0;
6dd9a7c7 3824 domain->iommu_superpage = 0;
fe40f1e0 3825 domain->max_addr = 0;
4c923d47 3826 domain->nid = -1;
5e98c4b1
WH		 3827
3828 /* always allocate the top pgd */
4c923d47 3829 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 3830 if (!domain->pgd)
3831 return -ENOMEM;
3832 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3833 return 0;
3834}
3835
3836static void iommu_free_vm_domain(struct dmar_domain *domain)
3837{
3838 unsigned long flags;
3839 struct dmar_drhd_unit *drhd;
3840 struct intel_iommu *iommu;
3841 unsigned long i;
3842 unsigned long ndomains;
3843
3844 for_each_drhd_unit(drhd) {
3845 if (drhd->ignored)
3846 continue;
3847 iommu = drhd->iommu;
3848
3849 ndomains = cap_ndoms(iommu->cap);
a45946ab 3850 for_each_set_bit(i, iommu->domain_ids, ndomains) {
5e98c4b1
WH		 3851 if (iommu->domains[i] == domain) {
3852 spin_lock_irqsave(&iommu->lock, flags);
3853 clear_bit(i, iommu->domain_ids);
3854 iommu->domains[i] = NULL;
3855 spin_unlock_irqrestore(&iommu->lock, flags);
3856 break;
3857 }
5e98c4b1
WH		 3858 }
3859 }
3860}
3861
3862static void vm_domain_exit(struct dmar_domain *domain)
3863{
5e98c4b1
WH		 3864 /* Domain 0 is reserved, so dont process it */
3865 if (!domain)
3866 return;
3867
3868 vm_domain_remove_all_dev_info(domain);
3869 /* destroy iovas */
3870 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3871
3872 /* clear ptes */
595badf5 3873 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3874
3875 /* free page tables */
d794dc9b 3876 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3877
3878 iommu_free_vm_domain(domain);
3879 free_domain_mem(domain);
3880}
3881
5d450806 3882static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3883{
5d450806 3884 struct dmar_domain *dmar_domain;
38717946 3885
5d450806
JR		 3886 dmar_domain = iommu_alloc_vm_domain();
3887 if (!dmar_domain) {
38717946 3888 printk(KERN_ERR
5d450806
JR		 3889 "intel_iommu_domain_init: dmar_domain == NULL\n");
3890 return -ENOMEM;
38717946 3891 }
2c2e2c38 3892 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3893 printk(KERN_ERR
5d450806
JR		 3894 "intel_iommu_domain_init() failed\n");
3895 vm_domain_exit(dmar_domain);
3896 return -ENOMEM;
38717946 3897 }
8140a95d 3898 domain_update_iommu_cap(dmar_domain);
5d450806 3899 domain->priv = dmar_domain;
faa3d6f5 3900
5d450806 3901 return 0;
38717946 3902}
38717946 3903
5d450806 3904static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3905{
5d450806
JR		 3906 struct dmar_domain *dmar_domain = domain->priv;
3907
3908 domain->priv = NULL;
3909 vm_domain_exit(dmar_domain);
38717946 3910}
38717946 3911
4c5478c9
JR		 3912static int intel_iommu_attach_device(struct iommu_domain *domain,
3913 struct device *dev)
38717946 3914{
4c5478c9
JR		 3915 struct dmar_domain *dmar_domain = domain->priv;
3916 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3917 struct intel_iommu *iommu;
3918 int addr_width;
faa3d6f5
WH		 3919
3920 /* normally pdev is not mapped */
3921 if (unlikely(domain_context_mapped(pdev))) {
3922 struct dmar_domain *old_domain;
3923
3924 old_domain = find_domain(pdev);
3925 if (old_domain) {
2c2e2c38
FY		 3926 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3927 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3928 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3929 else
3930 domain_remove_dev_info(old_domain);
3931 }
3932 }
3933
276dbf99
DW		 3934 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3935 pdev->devfn);
fe40f1e0
WH		 3936 if (!iommu)
3937 return -ENODEV;
3938
3939 /* check if this iommu agaw is sufficient for max mapped address */
3940 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 3941 if (addr_width > cap_mgaw(iommu->cap))
3942 addr_width = cap_mgaw(iommu->cap);
3943
3944 if (dmar_domain->max_addr > (1LL << addr_width)) {
3945 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 3946 "sufficient for the mapped address (%llx)\n",
a99c47a2 3947 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 3948 return -EFAULT;
3949 }
a99c47a2
TL		 3950 dmar_domain->gaw = addr_width;
3951
3952 /*
3953 * Knock out extra levels of page tables if necessary
3954 */
3955 while (iommu->agaw < dmar_domain->agaw) {
3956 struct dma_pte *pte;
3957
3958 pte = dmar_domain->pgd;
3959 if (dma_pte_present(pte)) {
25cbff16
SY		 3960 dmar_domain->pgd = (struct dma_pte *)
3961 phys_to_virt(dma_pte_addr(pte));
7a661013 3962 free_pgtable_page(pte);
a99c47a2
TL		 3963 }
3964 dmar_domain->agaw--;
3965 }
fe40f1e0 3966
5fe60f4e 3967 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 3968}
38717946 3969
4c5478c9
JR		 3970static void intel_iommu_detach_device(struct iommu_domain *domain,
3971 struct device *dev)
38717946 3972{
4c5478c9
JR		 3973 struct dmar_domain *dmar_domain = domain->priv;
3974 struct pci_dev *pdev = to_pci_dev(dev);
3975
2c2e2c38 3976 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3977}
c7151a8d 3978
b146a1c9
JR		 3979static int intel_iommu_map(struct iommu_domain *domain,
3980 unsigned long iova, phys_addr_t hpa,
3981 int gfp_order, int iommu_prot)
faa3d6f5 3982{
dde57a21 3983 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 3984 u64 max_addr;
dde57a21 3985 int prot = 0;
b146a1c9 3986 size_t size;
faa3d6f5 3987 int ret;
fe40f1e0 3988
dde57a21
JR		 3989 if (iommu_prot & IOMMU_READ)
3990 prot |= DMA_PTE_READ;
3991 if (iommu_prot & IOMMU_WRITE)
3992 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3993 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3994 prot |= DMA_PTE_SNP;
dde57a21 3995
b146a1c9 3996 size = PAGE_SIZE << gfp_order;
163cc52c 3997 max_addr = iova + size;
dde57a21 3998 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3999 u64 end;
4000
4001 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4002 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4003 if (end < max_addr) {
8954da1f 4004 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4005 "sufficient for the mapped address (%llx)\n",
8954da1f 4006 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4007 return -EFAULT;
4008 }
dde57a21 4009 dmar_domain->max_addr = max_addr;
fe40f1e0 4010 }
ad051221
DW		 4011 /* Round up size to next multiple of PAGE_SIZE, if it and
4012 the low bits of hpa would take us onto the next page */
88cb6a74 4013 size = aligned_nrpages(hpa, size);
ad051221
DW		 4014 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4015 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4016 return ret;
38717946 4017}
38717946 4018
b146a1c9
JR		 4019static int intel_iommu_unmap(struct iommu_domain *domain,
4020 unsigned long iova, int gfp_order)
38717946 4021{
dde57a21 4022 struct dmar_domain *dmar_domain = domain->priv;
b146a1c9 4023 size_t size = PAGE_SIZE << gfp_order;
292827cb 4024 int order;
4b99d352 4025
292827cb 4026 order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
163cc52c 4027 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 4028
163cc52c
DW		 4029 if (dmar_domain->max_addr == iova + size)
4030 dmar_domain->max_addr = iova;
b146a1c9 4031
292827cb 4032 return order;
38717946 4033}
38717946 4034
d14d6577
JR		 4035static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4036 unsigned long iova)
38717946 4037{
d14d6577 4038 struct dmar_domain *dmar_domain = domain->priv;
38717946 4039 struct dma_pte *pte;
faa3d6f5 4040 u64 phys = 0;
38717946 4041
6dd9a7c7 4042 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
38717946 4043 if (pte)
faa3d6f5 4044 phys = dma_pte_addr(pte);
38717946 4045
faa3d6f5 4046 return phys;
38717946 4047}
a8bcbb0d 4048
dbb9fd86
SY		 4049static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4050 unsigned long cap)
4051{
4052 struct dmar_domain *dmar_domain = domain->priv;
4053
4054 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4055 return dmar_domain->iommu_snooping;
323f99cb
TL		 4056 if (cap == IOMMU_CAP_INTR_REMAP)
4057 return intr_remapping_enabled;
dbb9fd86
SY		 4058
4059 return 0;
4060}
4061
a8bcbb0d
JR		 4062static struct iommu_ops intel_iommu_ops = {
4063 .domain_init = intel_iommu_domain_init,
4064 .domain_destroy = intel_iommu_domain_destroy,
4065 .attach_dev = intel_iommu_attach_device,
4066 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4067 .map = intel_iommu_map,
4068 .unmap = intel_iommu_unmap,
a8bcbb0d 4069 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4070 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 4071};
9af88143
DW		 4072
4073static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
4074{
4075 /*
4076 * Mobile 4 Series Chipset neglects to set RWBF capability,
4077 * but needs it:
4078 */
4079 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4080 rwbf_quirk = 1;
2d9e667e
DW		 4081
4082 /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
4083 if (dev->revision == 0x07) {
4084 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4085 dmar_map_gfx = 0;
4086 }
9af88143
DW		 4087}
4088
4089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
e0fc7e0b 4090
eecfd57f
AJ		 4091#define GGC 0x52
4092#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4093#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4094#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4095#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4096#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4097#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4098#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4099#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4100
9eecabcb
DW		 4101static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4102{
4103 unsigned short ggc;
4104
eecfd57f 4105 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4106 return;
4107
eecfd57f 4108 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4109 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4110 dmar_map_gfx = 0;
6fbcfb3e
DW		 4111 } else if (dmar_map_gfx) {
4112 /* we have to ensure the gfx device is idle before we flush */
4113 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4114 intel_iommu_strict = 1;
4115 }
9eecabcb
DW		 4116}
4117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4121
e0fc7e0b
DW		 4122/* On Tylersburg chipsets, some BIOSes have been known to enable the
4123 ISOCH DMAR unit for the Azalia sound device, but not give it any
4124 TLB entries, which causes it to deadlock. Check for that. We do
4125 this in a function called from init_dmars(), instead of in a PCI
4126 quirk, because we don't want to print the obnoxious "BIOS broken"
4127 message if VT-d is actually disabled.
4128*/
4129static void __init check_tylersburg_isoch(void)
4130{
4131 struct pci_dev *pdev;
4132 uint32_t vtisochctrl;
4133
4134 /* If there's no Azalia in the system anyway, forget it. */
4135 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4136 if (!pdev)
4137 return;
4138 pci_dev_put(pdev);
4139
4140 /* System Management Registers. Might be hidden, in which case
4141 we can't do the sanity check. But that's OK, because the
4142 known-broken BIOSes _don't_ actually hide it, so far. */
4143 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4144 if (!pdev)
4145 return;
4146
4147 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4148 pci_dev_put(pdev);
4149 return;
4150 }
4151
4152 pci_dev_put(pdev);
4153
4154 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4155 if (vtisochctrl & 1)
4156 return;
4157
4158 /* Drop all bits other than the number of TLB entries */
4159 vtisochctrl &= 0x1c;
4160
4161 /* If we have the recommended number of TLB entries (16), fine. */
4162 if (vtisochctrl == 0x10)
4163 return;
4164
4165 /* Zero TLB entries? You get to ride the short bus to school. */
4166 if (!vtisochctrl) {
4167 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4168 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4169 dmi_get_system_info(DMI_BIOS_VENDOR),
4170 dmi_get_system_info(DMI_BIOS_VERSION),
4171 dmi_get_system_info(DMI_PRODUCT_VERSION));
4172 iommu_identity_mapping |= IDENTMAP_AZALIA;
4173 return;
4174 }
4175
4176 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4177 vtisochctrl);
4178}
Linux kernel - Deliverables
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