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iommu/vt-d: Detect pre enabled translation
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
9f10e5bf 18 * Joerg Roedel <jroedel@suse.de>
ba395927
KA		 19 */
20
9f10e5bf
JR		 21#define pr_fmt(fmt) "DMAR: " fmt
22
ba395927
KA		 23#include <linux/init.h>
24#include <linux/bitmap.h>
5e0d2a6f 25#include <linux/debugfs.h>
54485c30 26#include <linux/export.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
75f05569 35#include <linux/memory.h>
5e0d2a6f 36#include <linux/timer.h>
38717946 37#include <linux/iova.h>
5d450806 38#include <linux/iommu.h>
38717946 39#include <linux/intel-iommu.h>
134fac3f 40#include <linux/syscore_ops.h>
69575d38 41#include <linux/tboot.h>
adb2fe02 42#include <linux/dmi.h>
5cdede24 43#include <linux/pci-ats.h>
0ee332c1 44#include <linux/memblock.h>
36746436 45#include <linux/dma-contiguous.h>
8a8f422d 46#include <asm/irq_remapping.h>
ba395927 47#include <asm/cacheflush.h>
46a7fa27 48#include <asm/iommu.h>
ba395927 49
078e1ee2
JR		 50#include "irq_remapping.h"
51
5b6985ce
FY		 52#define ROOT_SIZE VTD_PAGE_SIZE
53#define CONTEXT_SIZE VTD_PAGE_SIZE
54
ba395927 55#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
18436afd 56#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
ba395927 57#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 58#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 59
60#define IOAPIC_RANGE_START (0xfee00000)
61#define IOAPIC_RANGE_END (0xfeefffff)
62#define IOVA_START_ADDR (0x1000)
63
64#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
65
4ed0d3e6 66#define MAX_AGAW_WIDTH 64
5c645b35 67#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 68
2ebe3151
DW		 69#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
70#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
71
72/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
73 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
74#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
75 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
76#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 77
1b722500
RM		 78/* IO virtual address start page frame number */
79#define IOVA_START_PFN (1)
80
f27be03b 81#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 82#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 83#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 84
df08cdc7
AM		 85/* page table handling */
86#define LEVEL_STRIDE (9)
87#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
88
6d1c56a9
OBC		 89/*
90 * This bitmap is used to advertise the page sizes our hardware support
91 * to the IOMMU core, which will then use this information to split
92 * physically contiguous memory regions it is mapping into page sizes
93 * that we support.
94 *
95 * Traditionally the IOMMU core just handed us the mappings directly,
96 * after making sure the size is an order of a 4KiB page and that the
97 * mapping has natural alignment.
98 *
99 * To retain this behavior, we currently advertise that we support
100 * all page sizes that are an order of 4KiB.
101 *
102 * If at some point we'd like to utilize the IOMMU core's new behavior,
103 * we could change this to advertise the real page sizes we support.
104 */
105#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
106
df08cdc7
AM		 107static inline int agaw_to_level(int agaw)
108{
109 return agaw + 2;
110}
111
112static inline int agaw_to_width(int agaw)
113{
5c645b35 114 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 115}
116
117static inline int width_to_agaw(int width)
118{
5c645b35 119 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 120}
121
122static inline unsigned int level_to_offset_bits(int level)
123{
124 return (level - 1) * LEVEL_STRIDE;
125}
126
127static inline int pfn_level_offset(unsigned long pfn, int level)
128{
129 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
130}
131
132static inline unsigned long level_mask(int level)
133{
134 return -1UL << level_to_offset_bits(level);
135}
136
137static inline unsigned long level_size(int level)
138{
139 return 1UL << level_to_offset_bits(level);
140}
141
142static inline unsigned long align_to_level(unsigned long pfn, int level)
143{
144 return (pfn + level_size(level) - 1) & level_mask(level);
145}
fd18de50 146
6dd9a7c7
YS		 147static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
148{
5c645b35 149 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 150}
151
dd4e8319
DW		 152/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
153 are never going to work. */
154static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
155{
156 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
157}
158
159static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
160{
161 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
162}
163static inline unsigned long page_to_dma_pfn(struct page *pg)
164{
165 return mm_to_dma_pfn(page_to_pfn(pg));
166}
167static inline unsigned long virt_to_dma_pfn(void *p)
168{
169 return page_to_dma_pfn(virt_to_page(p));
170}
171
d9630fe9
WH		 172/* global iommu list, set NULL for ignored DMAR units */
173static struct intel_iommu **g_iommus;
174
e0fc7e0b 175static void __init check_tylersburg_isoch(void);
9af88143
DW		 176static int rwbf_quirk;
177
b779260b
JC		 178/*
179 * set to 1 to panic kernel if can't successfully enable VT-d
180 * (used when kernel is launched w/ TXT)
181 */
182static int force_on = 0;
183
46b08e1a
MM		 184/*
185 * 0: Present
186 * 1-11: Reserved
187 * 12-63: Context Ptr (12 - (haw-1))
188 * 64-127: Reserved
189 */
190struct root_entry {
03ecc32c
DW		 191 u64 lo;
192 u64 hi;
46b08e1a
MM		 193};
194#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
46b08e1a 195
46b08e1a 196
7a8fc25e
MM		 197/*
198 * low 64 bits:
199 * 0: present
200 * 1: fault processing disable
201 * 2-3: translation type
202 * 12-63: address space root
203 * high 64 bits:
204 * 0-2: address width
205 * 3-6: aval
206 * 8-23: domain id
207 */
208struct context_entry {
209 u64 lo;
210 u64 hi;
211};
c07e7d21
MM		 212
213static inline bool context_present(struct context_entry *context)
214{
215 return (context->lo & 1);
216}
217static inline void context_set_present(struct context_entry *context)
218{
219 context->lo |= 1;
220}
221
222static inline void context_set_fault_enable(struct context_entry *context)
223{
224 context->lo &= (((u64)-1) << 2) | 1;
225}
226
c07e7d21
MM		 227static inline void context_set_translation_type(struct context_entry *context,
228 unsigned long value)
229{
230 context->lo &= (((u64)-1) << 4) | 3;
231 context->lo |= (value & 3) << 2;
232}
233
234static inline void context_set_address_root(struct context_entry *context,
235 unsigned long value)
236{
1a2262f9 237 context->lo &= ~VTD_PAGE_MASK;
c07e7d21
MM		 238 context->lo |= value & VTD_PAGE_MASK;
239}
240
241static inline void context_set_address_width(struct context_entry *context,
242 unsigned long value)
243{
244 context->hi |= value & 7;
245}
246
247static inline void context_set_domain_id(struct context_entry *context,
248 unsigned long value)
249{
250 context->hi |= (value & ((1 << 16) - 1)) << 8;
251}
252
253static inline void context_clear_entry(struct context_entry *context)
254{
255 context->lo = 0;
256 context->hi = 0;
257}
7a8fc25e 258
622ba12a
MM		 259/*
260 * 0: readable
261 * 1: writable
262 * 2-6: reserved
263 * 7: super page
9cf06697
SY		 264 * 8-10: available
265 * 11: snoop behavior
622ba12a
MM		 266 * 12-63: Host physcial address
267 */
268struct dma_pte {
269 u64 val;
270};
622ba12a 271
19c239ce
MM		 272static inline void dma_clear_pte(struct dma_pte *pte)
273{
274 pte->val = 0;
275}
276
19c239ce
MM		 277static inline u64 dma_pte_addr(struct dma_pte *pte)
278{
c85994e4
DW		 279#ifdef CONFIG_64BIT
280 return pte->val & VTD_PAGE_MASK;
281#else
282 /* Must have a full atomic 64-bit read */
1a8bd481 283 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 284#endif
19c239ce
MM		 285}
286
19c239ce
MM		 287static inline bool dma_pte_present(struct dma_pte *pte)
288{
289 return (pte->val & 3) != 0;
290}
622ba12a 291
4399c8bf
AK		 292static inline bool dma_pte_superpage(struct dma_pte *pte)
293{
c3c75eb7 294 return (pte->val & DMA_PTE_LARGE_PAGE);
4399c8bf
AK		 295}
296
75e6bf96
DW		 297static inline int first_pte_in_page(struct dma_pte *pte)
298{
299 return !((unsigned long)pte & ~VTD_PAGE_MASK);
300}
301
2c2e2c38
FY		 302/*
303 * This domain is a statically identity mapping domain.
304 * 1. This domain creats a static 1:1 mapping to all usable memory.
305 * 2. It maps to each iommu if successful.
306 * 3. Each iommu mapps to this domain if successful.
307 */
19943b0e
DW		 308static struct dmar_domain *si_domain;
309static int hw_pass_through = 1;
2c2e2c38 310
1ce28feb
WH		 311/* domain represents a virtual machine, more than one devices
312 * across iommus may be owned in one domain, e.g. kvm guest.
313 */
ab8dfe25 314#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0)
1ce28feb 315
2c2e2c38 316/* si_domain contains mulitple devices */
ab8dfe25 317#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1)
2c2e2c38 318
99126f7c
MM		 319struct dmar_domain {
320 int id; /* domain id */
4c923d47 321 int nid; /* node id */
78d8e704 322 DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
1b198bb0 323 /* bitmap of iommus this domain uses*/
99126f7c 324
00a77deb 325 struct list_head devices; /* all devices' list */
99126f7c
MM		 326 struct iova_domain iovad; /* iova's that belong to this domain */
327
328 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 329 int gaw; /* max guest address width */
330
331 /* adjusted guest address width, 0 is level 2 30-bit */
332 int agaw;
333
3b5410e7 334 int flags; /* flags to find out type of domain */
8e604097
WH		 335
336 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 337 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 338 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 339 int iommu_superpage;/* Level of superpages supported:
340 0 == 4KiB (no superpages), 1 == 2MiB,
341 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 342 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 343 u64 max_addr; /* maximum mapped address */
00a77deb
JR		 344
345 struct iommu_domain domain; /* generic domain data structure for
346 iommu core */
99126f7c
MM		 347};
348
a647dacb
MM		 349/* PCI domain-device relationship */
350struct device_domain_info {
351 struct list_head link; /* link to domain siblings */
352 struct list_head global; /* link to global list */
276dbf99 353 u8 bus; /* PCI bus number */
a647dacb 354 u8 devfn; /* PCI devfn number */
0bcb3e28 355 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 356 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 357 struct dmar_domain *domain; /* pointer to domain */
358};
359
b94e4117
JL		 360struct dmar_rmrr_unit {
361 struct list_head list; /* list of rmrr units */
362 struct acpi_dmar_header *hdr; /* ACPI header */
363 u64 base_address; /* reserved base address*/
364 u64 end_address; /* reserved end address */
832bd858 365 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 366 int devices_cnt; /* target device count */
367};
368
369struct dmar_atsr_unit {
370 struct list_head list; /* list of ATSR units */
371 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 372 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 373 int devices_cnt; /* target device count */
374 u8 include_all:1; /* include all ports */
375};
376
377static LIST_HEAD(dmar_atsr_units);
378static LIST_HEAD(dmar_rmrr_units);
379
380#define for_each_rmrr_units(rmrr) \
381 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
382
5e0d2a6f 383static void flush_unmaps_timeout(unsigned long data);
384
b707cb02 385static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 386
80b20dd8 387#define HIGH_WATER_MARK 250
388struct deferred_flush_tables {
389 int next;
390 struct iova *iova[HIGH_WATER_MARK];
391 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 392 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 393};
394
395static struct deferred_flush_tables *deferred_flush;
396
5e0d2a6f 397/* bitmap for indexing intel_iommus */
5e0d2a6f 398static int g_num_of_iommus;
399
400static DEFINE_SPINLOCK(async_umap_flush_lock);
401static LIST_HEAD(unmaps_to_do);
402
403static int timer_on;
404static long list_size;
5e0d2a6f 405
92d03cc8 406static void domain_exit(struct dmar_domain *domain);
ba395927 407static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117 408static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 409 struct device *dev);
92d03cc8 410static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 411 struct device *dev);
2a46ddf7
JL		 412static int domain_detach_iommu(struct dmar_domain *domain,
413 struct intel_iommu *iommu);
ba395927 414
d3f13810 415#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 416int dmar_disabled = 0;
417#else
418int dmar_disabled = 1;
d3f13810 419#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 420
8bc1f85c
ED		 421int intel_iommu_enabled = 0;
422EXPORT_SYMBOL_GPL(intel_iommu_enabled);
423
2d9e667e 424static int dmar_map_gfx = 1;
7d3b03ce 425static int dmar_forcedac;
5e0d2a6f 426static int intel_iommu_strict;
6dd9a7c7 427static int intel_iommu_superpage = 1;
c83b2f20
DW		 428static int intel_iommu_ecs = 1;
429
430/* We only actually use ECS when PASID support (on the new bit 40)
431 * is also advertised. Some early implementations — the ones with
432 * PASID support on bit 28 — have issues even when we *only* use
433 * extended root/context tables. */
434#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
435 ecap_pasid(iommu->ecap))
ba395927 436
c0771df8
DW		 437int intel_iommu_gfx_mapped;
438EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
439
ba395927
KA		 440#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
441static DEFINE_SPINLOCK(device_domain_lock);
442static LIST_HEAD(device_domain_list);
443
b22f6434 444static const struct iommu_ops intel_iommu_ops;
a8bcbb0d 445
4158c2ec
JR		 446static bool translation_pre_enabled(struct intel_iommu *iommu)
447{
448 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
449}
450
451static void init_translation_status(struct intel_iommu *iommu)
452{
453 u32 gsts;
454
455 gsts = readl(iommu->reg + DMAR_GSTS_REG);
456 if (gsts & DMA_GSTS_TES)
457 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
458}
459
00a77deb
JR		 460/* Convert generic 'struct iommu_domain to private struct dmar_domain */
461static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
462{
463 return container_of(dom, struct dmar_domain, domain);
464}
465
ba395927
KA		 466static int __init intel_iommu_setup(char *str)
467{
468 if (!str)
469 return -EINVAL;
470 while (*str) {
0cd5c3c8
KM		 471 if (!strncmp(str, "on", 2)) {
472 dmar_disabled = 0;
9f10e5bf 473 pr_info("IOMMU enabled\n");
0cd5c3c8 474 } else if (!strncmp(str, "off", 3)) {
ba395927 475 dmar_disabled = 1;
9f10e5bf 476 pr_info("IOMMU disabled\n");
ba395927
KA		 477 } else if (!strncmp(str, "igfx_off", 8)) {
478 dmar_map_gfx = 0;
9f10e5bf 479 pr_info("Disable GFX device mapping\n");
7d3b03ce 480 } else if (!strncmp(str, "forcedac", 8)) {
9f10e5bf 481 pr_info("Forcing DAC for PCI devices\n");
7d3b03ce 482 dmar_forcedac = 1;
5e0d2a6f 483 } else if (!strncmp(str, "strict", 6)) {
9f10e5bf 484 pr_info("Disable batched IOTLB flush\n");
5e0d2a6f 485 intel_iommu_strict = 1;
6dd9a7c7 486 } else if (!strncmp(str, "sp_off", 6)) {
9f10e5bf 487 pr_info("Disable supported super page\n");
6dd9a7c7 488 intel_iommu_superpage = 0;
c83b2f20
DW		 489 } else if (!strncmp(str, "ecs_off", 7)) {
490 printk(KERN_INFO
491 "Intel-IOMMU: disable extended context table support\n");
492 intel_iommu_ecs = 0;
ba395927
KA		 493 }
494
495 str += strcspn(str, ",");
496 while (*str == ',')
497 str++;
498 }
499 return 0;
500}
501__setup("intel_iommu=", intel_iommu_setup);
502
503static struct kmem_cache *iommu_domain_cache;
504static struct kmem_cache *iommu_devinfo_cache;
ba395927 505
4c923d47 506static inline void *alloc_pgtable_page(int node)
eb3fa7cb 507{
4c923d47
SS		 508 struct page *page;
509 void *vaddr = NULL;
eb3fa7cb 510
4c923d47
SS		 511 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
512 if (page)
513 vaddr = page_address(page);
eb3fa7cb 514 return vaddr;
ba395927
KA		 515}
516
517static inline void free_pgtable_page(void *vaddr)
518{
519 free_page((unsigned long)vaddr);
520}
521
522static inline void *alloc_domain_mem(void)
523{
354bb65e 524 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 525}
526
38717946 527static void free_domain_mem(void *vaddr)
ba395927
KA		 528{
529 kmem_cache_free(iommu_domain_cache, vaddr);
530}
531
532static inline void * alloc_devinfo_mem(void)
533{
354bb65e 534 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 535}
536
537static inline void free_devinfo_mem(void *vaddr)
538{
539 kmem_cache_free(iommu_devinfo_cache, vaddr);
540}
541
ab8dfe25
JL		 542static inline int domain_type_is_vm(struct dmar_domain *domain)
543{
544 return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
545}
546
547static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
548{
549 return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
550 DOMAIN_FLAG_STATIC_IDENTITY);
551}
1b573683 552
162d1b10
JL		 553static inline int domain_pfn_supported(struct dmar_domain *domain,
554 unsigned long pfn)
555{
556 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
557
558 return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
559}
560
4ed0d3e6 561static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 562{
563 unsigned long sagaw;
564 int agaw = -1;
565
566 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 567 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 568 agaw >= 0; agaw--) {
569 if (test_bit(agaw, &sagaw))
570 break;
571 }
572
573 return agaw;
574}
575
4ed0d3e6
FY		 576/*
577 * Calculate max SAGAW for each iommu.
578 */
579int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
580{
581 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
582}
583
584/*
585 * calculate agaw for each iommu.
586 * "SAGAW" may be different across iommus, use a default agaw, and
587 * get a supported less agaw for iommus that don't support the default agaw.
588 */
589int iommu_calculate_agaw(struct intel_iommu *iommu)
590{
591 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
592}
593
2c2e2c38 594/* This functionin only returns single iommu in a domain */
8c11e798
WH		 595static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
596{
597 int iommu_id;
598
2c2e2c38 599 /* si_domain and vm domain should not get here. */
ab8dfe25 600 BUG_ON(domain_type_is_vm_or_si(domain));
1b198bb0 601 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 602 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
603 return NULL;
604
605 return g_iommus[iommu_id];
606}
607
8e604097
WH		 608static void domain_update_iommu_coherency(struct dmar_domain *domain)
609{
d0501960
DW		 610 struct dmar_drhd_unit *drhd;
611 struct intel_iommu *iommu;
2f119c78
QL		 612 bool found = false;
613 int i;
2e12bc29 614
d0501960 615 domain->iommu_coherency = 1;
8e604097 616
1b198bb0 617 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
2f119c78 618 found = true;
8e604097
WH		 619 if (!ecap_coherent(g_iommus[i]->ecap)) {
620 domain->iommu_coherency = 0;
621 break;
622 }
8e604097 623 }
d0501960
DW		 624 if (found)
625 return;
626
627 /* No hardware attached; use lowest common denominator */
628 rcu_read_lock();
629 for_each_active_iommu(iommu, drhd) {
630 if (!ecap_coherent(iommu->ecap)) {
631 domain->iommu_coherency = 0;
632 break;
633 }
634 }
635 rcu_read_unlock();
8e604097
WH		 636}
637
161f6934 638static int domain_update_iommu_snooping(struct intel_iommu *skip)
58c610bd 639{
161f6934
JL		 640 struct dmar_drhd_unit *drhd;
641 struct intel_iommu *iommu;
642 int ret = 1;
58c610bd 643
161f6934
JL		 644 rcu_read_lock();
645 for_each_active_iommu(iommu, drhd) {
646 if (iommu != skip) {
647 if (!ecap_sc_support(iommu->ecap)) {
648 ret = 0;
649 break;
650 }
58c610bd 651 }
58c610bd 652 }
161f6934
JL		 653 rcu_read_unlock();
654
655 return ret;
58c610bd
SY		 656}
657
161f6934 658static int domain_update_iommu_superpage(struct intel_iommu *skip)
6dd9a7c7 659{
8140a95d 660 struct dmar_drhd_unit *drhd;
161f6934 661 struct intel_iommu *iommu;
8140a95d 662 int mask = 0xf;
6dd9a7c7
YS		 663
664 if (!intel_iommu_superpage) {
161f6934 665 return 0;
6dd9a7c7
YS		 666 }
667
8140a95d 668 /* set iommu_superpage to the smallest common denominator */
0e242612 669 rcu_read_lock();
8140a95d 670 for_each_active_iommu(iommu, drhd) {
161f6934
JL		 671 if (iommu != skip) {
672 mask &= cap_super_page_val(iommu->cap);
673 if (!mask)
674 break;
6dd9a7c7
YS		 675 }
676 }
0e242612
JL		 677 rcu_read_unlock();
678
161f6934 679 return fls(mask);
6dd9a7c7
YS		 680}
681
58c610bd
SY		 682/* Some capabilities may be different across iommus */
683static void domain_update_iommu_cap(struct dmar_domain *domain)
684{
685 domain_update_iommu_coherency(domain);
161f6934
JL		 686 domain->iommu_snooping = domain_update_iommu_snooping(NULL);
687 domain->iommu_superpage = domain_update_iommu_superpage(NULL);
58c610bd
SY		 688}
689
03ecc32c
DW		 690static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
691 u8 bus, u8 devfn, int alloc)
692{
693 struct root_entry *root = &iommu->root_entry[bus];
694 struct context_entry *context;
695 u64 *entry;
696
c83b2f20 697 if (ecs_enabled(iommu)) {
03ecc32c
DW		 698 if (devfn >= 0x80) {
699 devfn -= 0x80;
700 entry = &root->hi;
701 }
702 devfn *= 2;
703 }
704 entry = &root->lo;
705 if (*entry & 1)
706 context = phys_to_virt(*entry & VTD_PAGE_MASK);
707 else {
708 unsigned long phy_addr;
709 if (!alloc)
710 return NULL;
711
712 context = alloc_pgtable_page(iommu->node);
713 if (!context)
714 return NULL;
715
716 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
717 phy_addr = virt_to_phys((void *)context);
718 *entry = phy_addr | 1;
719 __iommu_flush_cache(iommu, entry, sizeof(*entry));
720 }
721 return &context[devfn];
722}
723
4ed6a540
DW		 724static int iommu_dummy(struct device *dev)
725{
726 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
727}
728
156baca8 729static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
c7151a8d
WH		 730{
731 struct dmar_drhd_unit *drhd = NULL;
b683b230 732 struct intel_iommu *iommu;
156baca8
DW		 733 struct device *tmp;
734 struct pci_dev *ptmp, *pdev = NULL;
aa4d066a 735 u16 segment = 0;
c7151a8d
WH		 736 int i;
737
4ed6a540
DW		 738 if (iommu_dummy(dev))
739 return NULL;
740
156baca8
DW		 741 if (dev_is_pci(dev)) {
742 pdev = to_pci_dev(dev);
743 segment = pci_domain_nr(pdev->bus);
ca5b74d2 744 } else if (has_acpi_companion(dev))
156baca8
DW		 745 dev = &ACPI_COMPANION(dev)->dev;
746
0e242612 747 rcu_read_lock();
b683b230 748 for_each_active_iommu(iommu, drhd) {
156baca8 749 if (pdev && segment != drhd->segment)
276dbf99 750 continue;
c7151a8d 751
b683b230 752 for_each_active_dev_scope(drhd->devices,
156baca8
DW		 753 drhd->devices_cnt, i, tmp) {
754 if (tmp == dev) {
755 *bus = drhd->devices[i].bus;
756 *devfn = drhd->devices[i].devfn;
b683b230 757 goto out;
156baca8
DW		 758 }
759
760 if (!pdev || !dev_is_pci(tmp))
761 continue;
762
763 ptmp = to_pci_dev(tmp);
764 if (ptmp->subordinate &&
765 ptmp->subordinate->number <= pdev->bus->number &&
766 ptmp->subordinate->busn_res.end >= pdev->bus->number)
767 goto got_pdev;
924b6231 768 }
c7151a8d 769
156baca8
DW		 770 if (pdev && drhd->include_all) {
771 got_pdev:
772 *bus = pdev->bus->number;
773 *devfn = pdev->devfn;
b683b230 774 goto out;
156baca8 775 }
c7151a8d 776 }
b683b230 777 iommu = NULL;
156baca8 778 out:
0e242612 779 rcu_read_unlock();
c7151a8d 780
b683b230 781 return iommu;
c7151a8d
WH		 782}
783
5331fe6f
WH		 784static void domain_flush_cache(struct dmar_domain *domain,
785 void *addr, int size)
786{
787 if (!domain->iommu_coherency)
788 clflush_cache_range(addr, size);
789}
790
ba395927
KA		 791static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
792{
ba395927 793 struct context_entry *context;
03ecc32c 794 int ret = 0;
ba395927
KA		 795 unsigned long flags;
796
797 spin_lock_irqsave(&iommu->lock, flags);
03ecc32c
DW		 798 context = iommu_context_addr(iommu, bus, devfn, 0);
799 if (context)
800 ret = context_present(context);
ba395927
KA		 801 spin_unlock_irqrestore(&iommu->lock, flags);
802 return ret;
803}
804
805static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
806{
ba395927
KA		 807 struct context_entry *context;
808 unsigned long flags;
809
810 spin_lock_irqsave(&iommu->lock, flags);
03ecc32c 811 context = iommu_context_addr(iommu, bus, devfn, 0);
ba395927 812 if (context) {
03ecc32c
DW		 813 context_clear_entry(context);
814 __iommu_flush_cache(iommu, context, sizeof(*context));
ba395927
KA		 815 }
816 spin_unlock_irqrestore(&iommu->lock, flags);
817}
818
819static void free_context_table(struct intel_iommu *iommu)
820{
ba395927
KA		 821 int i;
822 unsigned long flags;
823 struct context_entry *context;
824
825 spin_lock_irqsave(&iommu->lock, flags);
826 if (!iommu->root_entry) {
827 goto out;
828 }
829 for (i = 0; i < ROOT_ENTRY_NR; i++) {
03ecc32c 830 context = iommu_context_addr(iommu, i, 0, 0);
ba395927
KA		 831 if (context)
832 free_pgtable_page(context);
03ecc32c 833
c83b2f20 834 if (!ecs_enabled(iommu))
03ecc32c
DW		 835 continue;
836
837 context = iommu_context_addr(iommu, i, 0x80, 0);
838 if (context)
839 free_pgtable_page(context);
840
ba395927
KA		 841 }
842 free_pgtable_page(iommu->root_entry);
843 iommu->root_entry = NULL;
844out:
845 spin_unlock_irqrestore(&iommu->lock, flags);
846}
847
b026fd28 848static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 849 unsigned long pfn, int *target_level)
ba395927 850{
ba395927
KA		 851 struct dma_pte *parent, *pte = NULL;
852 int level = agaw_to_level(domain->agaw);
4399c8bf 853 int offset;
ba395927
KA		 854
855 BUG_ON(!domain->pgd);
f9423606 856
162d1b10 857 if (!domain_pfn_supported(domain, pfn))
f9423606
JS		 858 /* Address beyond IOMMU's addressing capabilities. */
859 return NULL;
860
ba395927
KA		 861 parent = domain->pgd;
862
5cf0a76f 863 while (1) {
ba395927
KA		 864 void *tmp_page;
865
b026fd28 866 offset = pfn_level_offset(pfn, level);
ba395927 867 pte = &parent[offset];
5cf0a76f 868 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 869 break;
5cf0a76f 870 if (level == *target_level)
ba395927
KA		 871 break;
872
19c239ce 873 if (!dma_pte_present(pte)) {
c85994e4
DW		 874 uint64_t pteval;
875
4c923d47 876 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 877
206a73c1 878 if (!tmp_page)
ba395927 879 return NULL;
206a73c1 880
c85994e4 881 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 882 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
effad4b5 883 if (cmpxchg64(&pte->val, 0ULL, pteval))
c85994e4
DW		 884 /* Someone else set it while we were thinking; use theirs. */
885 free_pgtable_page(tmp_page);
effad4b5 886 else
c85994e4 887 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927 888 }
5cf0a76f
DW		 889 if (level == 1)
890 break;
891
19c239ce 892 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 893 level--;
894 }
895
5cf0a76f
DW		 896 if (!*target_level)
897 *target_level = level;
898
ba395927
KA		 899 return pte;
900}
901
6dd9a7c7 902
ba395927 903/* return address's pte at specific level */
90dcfb5e
DW		 904static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
905 unsigned long pfn,
6dd9a7c7 906 int level, int *large_page)
ba395927
KA		 907{
908 struct dma_pte *parent, *pte = NULL;
909 int total = agaw_to_level(domain->agaw);
910 int offset;
911
912 parent = domain->pgd;
913 while (level <= total) {
90dcfb5e 914 offset = pfn_level_offset(pfn, total);
ba395927
KA		 915 pte = &parent[offset];
916 if (level == total)
917 return pte;
918
6dd9a7c7
YS		 919 if (!dma_pte_present(pte)) {
920 *large_page = total;
ba395927 921 break;
6dd9a7c7
YS		 922 }
923
e16922af 924 if (dma_pte_superpage(pte)) {
6dd9a7c7
YS		 925 *large_page = total;
926 return pte;
927 }
928
19c239ce 929 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 930 total--;
931 }
932 return NULL;
933}
934
ba395927 935/* clear last level pte, a tlb flush should be followed */
5cf0a76f 936static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 937 unsigned long start_pfn,
938 unsigned long last_pfn)
ba395927 939{
6dd9a7c7 940 unsigned int large_page = 1;
310a5ab9 941 struct dma_pte *first_pte, *pte;
66eae846 942
162d1b10
JL		 943 BUG_ON(!domain_pfn_supported(domain, start_pfn));
944 BUG_ON(!domain_pfn_supported(domain, last_pfn));
59c36286 945 BUG_ON(start_pfn > last_pfn);
ba395927 946
04b18e65 947 /* we don't need lock here; nobody else touches the iova range */
59c36286 948 do {
6dd9a7c7
YS		 949 large_page = 1;
950 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 951 if (!pte) {
6dd9a7c7 952 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 953 continue;
954 }
6dd9a7c7 955 do {
310a5ab9 956 dma_clear_pte(pte);
6dd9a7c7 957 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 958 pte++;
75e6bf96
DW		 959 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
960
310a5ab9
DW		 961 domain_flush_cache(domain, first_pte,
962 (void *)pte - (void *)first_pte);
59c36286
DW		 963
964 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 965}
966
3269ee0b
AW		 967static void dma_pte_free_level(struct dmar_domain *domain, int level,
968 struct dma_pte *pte, unsigned long pfn,
969 unsigned long start_pfn, unsigned long last_pfn)
970{
971 pfn = max(start_pfn, pfn);
972 pte = &pte[pfn_level_offset(pfn, level)];
973
974 do {
975 unsigned long level_pfn;
976 struct dma_pte *level_pte;
977
978 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
979 goto next;
980
981 level_pfn = pfn & level_mask(level - 1);
982 level_pte = phys_to_virt(dma_pte_addr(pte));
983
984 if (level > 2)
985 dma_pte_free_level(domain, level - 1, level_pte,
986 level_pfn, start_pfn, last_pfn);
987
988 /* If range covers entire pagetable, free it */
989 if (!(start_pfn > level_pfn ||
08336fd2 990 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 991 dma_clear_pte(pte);
992 domain_flush_cache(domain, pte, sizeof(*pte));
993 free_pgtable_page(level_pte);
994 }
995next:
996 pfn += level_size(level);
997 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
998}
999
ba395927
KA		 1000/* free page table pages. last level pte should already be cleared */
1001static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 1002 unsigned long start_pfn,
1003 unsigned long last_pfn)
ba395927 1004{
162d1b10
JL		 1005 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1006 BUG_ON(!domain_pfn_supported(domain, last_pfn));
59c36286 1007 BUG_ON(start_pfn > last_pfn);
ba395927 1008
d41a4adb
JL		 1009 dma_pte_clear_range(domain, start_pfn, last_pfn);
1010
f3a0a52f 1011 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 1012 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
1013 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 1014
ba395927 1015 /* free pgd */
d794dc9b 1016 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 1017 free_pgtable_page(domain->pgd);
1018 domain->pgd = NULL;
1019 }
1020}
1021
ea8ea460
DW		 1022/* When a page at a given level is being unlinked from its parent, we don't
1023 need to *modify* it at all. All we need to do is make a list of all the
1024 pages which can be freed just as soon as we've flushed the IOTLB and we
1025 know the hardware page-walk will no longer touch them.
1026 The 'pte' argument is the *parent* PTE, pointing to the page that is to
1027 be freed. */
1028static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1029 int level, struct dma_pte *pte,
1030 struct page *freelist)
1031{
1032 struct page *pg;
1033
1034 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1035 pg->freelist = freelist;
1036 freelist = pg;
1037
1038 if (level == 1)
1039 return freelist;
1040
adeb2590
JL		 1041 pte = page_address(pg);
1042 do {
ea8ea460
DW		 1043 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1044 freelist = dma_pte_list_pagetables(domain, level - 1,
1045 pte, freelist);
adeb2590
JL		 1046 pte++;
1047 } while (!first_pte_in_page(pte));
ea8ea460
DW		 1048
1049 return freelist;
1050}
1051
1052static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1053 struct dma_pte *pte, unsigned long pfn,
1054 unsigned long start_pfn,
1055 unsigned long last_pfn,
1056 struct page *freelist)
1057{
1058 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1059
1060 pfn = max(start_pfn, pfn);
1061 pte = &pte[pfn_level_offset(pfn, level)];
1062
1063 do {
1064 unsigned long level_pfn;
1065
1066 if (!dma_pte_present(pte))
1067 goto next;
1068
1069 level_pfn = pfn & level_mask(level);
1070
1071 /* If range covers entire pagetable, free it */
1072 if (start_pfn <= level_pfn &&
1073 last_pfn >= level_pfn + level_size(level) - 1) {
1074 /* These suborbinate page tables are going away entirely. Don't
1075 bother to clear them; we're just going to *free* them. */
1076 if (level > 1 && !dma_pte_superpage(pte))
1077 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1078
1079 dma_clear_pte(pte);
1080 if (!first_pte)
1081 first_pte = pte;
1082 last_pte = pte;
1083 } else if (level > 1) {
1084 /* Recurse down into a level that isn't *entirely* obsolete */
1085 freelist = dma_pte_clear_level(domain, level - 1,
1086 phys_to_virt(dma_pte_addr(pte)),
1087 level_pfn, start_pfn, last_pfn,
1088 freelist);
1089 }
1090next:
1091 pfn += level_size(level);
1092 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1093
1094 if (first_pte)
1095 domain_flush_cache(domain, first_pte,
1096 (void *)++last_pte - (void *)first_pte);
1097
1098 return freelist;
1099}
1100
1101/* We can't just free the pages because the IOMMU may still be walking
1102 the page tables, and may have cached the intermediate levels. The
1103 pages can only be freed after the IOTLB flush has been done. */
1104struct page *domain_unmap(struct dmar_domain *domain,
1105 unsigned long start_pfn,
1106 unsigned long last_pfn)
1107{
ea8ea460
DW		 1108 struct page *freelist = NULL;
1109
162d1b10
JL		 1110 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1111 BUG_ON(!domain_pfn_supported(domain, last_pfn));
ea8ea460
DW		 1112 BUG_ON(start_pfn > last_pfn);
1113
1114 /* we don't need lock here; nobody else touches the iova range */
1115 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1116 domain->pgd, 0, start_pfn, last_pfn, NULL);
1117
1118 /* free pgd */
1119 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1120 struct page *pgd_page = virt_to_page(domain->pgd);
1121 pgd_page->freelist = freelist;
1122 freelist = pgd_page;
1123
1124 domain->pgd = NULL;
1125 }
1126
1127 return freelist;
1128}
1129
1130void dma_free_pagelist(struct page *freelist)
1131{
1132 struct page *pg;
1133
1134 while ((pg = freelist)) {
1135 freelist = pg->freelist;
1136 free_pgtable_page(page_address(pg));
1137 }
1138}
1139
ba395927
KA		 1140/* iommu handling */
1141static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1142{
1143 struct root_entry *root;
1144 unsigned long flags;
1145
4c923d47 1146 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ffebeb46 1147 if (!root) {
9f10e5bf 1148 pr_err("Allocating root entry for %s failed\n",
ffebeb46 1149 iommu->name);
ba395927 1150 return -ENOMEM;
ffebeb46 1151 }
ba395927 1152
5b6985ce 1153 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1154
1155 spin_lock_irqsave(&iommu->lock, flags);
1156 iommu->root_entry = root;
1157 spin_unlock_irqrestore(&iommu->lock, flags);
1158
1159 return 0;
1160}
1161
ba395927
KA		 1162static void iommu_set_root_entry(struct intel_iommu *iommu)
1163{
03ecc32c 1164 u64 addr;
c416daa9 1165 u32 sts;
ba395927
KA		 1166 unsigned long flag;
1167
03ecc32c 1168 addr = virt_to_phys(iommu->root_entry);
c83b2f20 1169 if (ecs_enabled(iommu))
03ecc32c 1170 addr |= DMA_RTADDR_RTT;
ba395927 1171
1f5b3c3f 1172 raw_spin_lock_irqsave(&iommu->register_lock, flag);
03ecc32c 1173 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
ba395927 1174
c416daa9 1175 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1176
1177 /* Make sure hardware complete it */
1178 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1179 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1180
1f5b3c3f 1181 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1182}
1183
1184static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1185{
1186 u32 val;
1187 unsigned long flag;
1188
9af88143 1189 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1190 return;
ba395927 1191
1f5b3c3f 1192 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1193 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1194
1195 /* Make sure hardware complete it */
1196 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1197 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1198
1f5b3c3f 1199 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1200}
1201
1202/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1203static void __iommu_flush_context(struct intel_iommu *iommu,
1204 u16 did, u16 source_id, u8 function_mask,
1205 u64 type)
ba395927
KA		 1206{
1207 u64 val = 0;
1208 unsigned long flag;
1209
ba395927
KA		 1210 switch (type) {
1211 case DMA_CCMD_GLOBAL_INVL:
1212 val = DMA_CCMD_GLOBAL_INVL;
1213 break;
1214 case DMA_CCMD_DOMAIN_INVL:
1215 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1216 break;
1217 case DMA_CCMD_DEVICE_INVL:
1218 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1219 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1220 break;
1221 default:
1222 BUG();
1223 }
1224 val |= DMA_CCMD_ICC;
1225
1f5b3c3f 1226 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1227 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1228
1229 /* Make sure hardware complete it */
1230 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1231 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1232
1f5b3c3f 1233 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1234}
1235
ba395927 1236/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1237static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1238 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1239{
1240 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1241 u64 val = 0, val_iva = 0;
1242 unsigned long flag;
1243
ba395927
KA		 1244 switch (type) {
1245 case DMA_TLB_GLOBAL_FLUSH:
1246 /* global flush doesn't need set IVA_REG */
1247 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1248 break;
1249 case DMA_TLB_DSI_FLUSH:
1250 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1251 break;
1252 case DMA_TLB_PSI_FLUSH:
1253 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1254 /* IH bit is passed in as part of address */
ba395927
KA		 1255 val_iva = size_order | addr;
1256 break;
1257 default:
1258 BUG();
1259 }
1260 /* Note: set drain read/write */
1261#if 0
1262 /*
1263 * This is probably to be super secure.. Looks like we can
1264 * ignore it without any impact.
1265 */
1266 if (cap_read_drain(iommu->cap))
1267 val |= DMA_TLB_READ_DRAIN;
1268#endif
1269 if (cap_write_drain(iommu->cap))
1270 val |= DMA_TLB_WRITE_DRAIN;
1271
1f5b3c3f 1272 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1273 /* Note: Only uses first TLB reg currently */
1274 if (val_iva)
1275 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1276 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1277
1278 /* Make sure hardware complete it */
1279 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1280 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1281
1f5b3c3f 1282 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1283
1284 /* check IOTLB invalidation granularity */
1285 if (DMA_TLB_IAIG(val) == 0)
9f10e5bf 1286 pr_err("Flush IOTLB failed\n");
ba395927 1287 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
9f10e5bf 1288 pr_debug("TLB flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1289 (unsigned long long)DMA_TLB_IIRG(type),
1290 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1291}
1292
64ae892b
DW		 1293static struct device_domain_info *
1294iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1295 u8 bus, u8 devfn)
93a23a72 1296{
2f119c78 1297 bool found = false;
93a23a72
YZ		 1298 unsigned long flags;
1299 struct device_domain_info *info;
0bcb3e28 1300 struct pci_dev *pdev;
93a23a72
YZ		 1301
1302 if (!ecap_dev_iotlb_support(iommu->ecap))
1303 return NULL;
1304
1305 if (!iommu->qi)
1306 return NULL;
1307
1308 spin_lock_irqsave(&device_domain_lock, flags);
1309 list_for_each_entry(info, &domain->devices, link)
c3b497c6
JL		 1310 if (info->iommu == iommu && info->bus == bus &&
1311 info->devfn == devfn) {
2f119c78 1312 found = true;
93a23a72
YZ		 1313 break;
1314 }
1315 spin_unlock_irqrestore(&device_domain_lock, flags);
1316
0bcb3e28 1317 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1318 return NULL;
1319
0bcb3e28
DW		 1320 pdev = to_pci_dev(info->dev);
1321
1322 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1323 return NULL;
1324
0bcb3e28 1325 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1326 return NULL;
1327
93a23a72
YZ		 1328 return info;
1329}
1330
1331static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1332{
0bcb3e28 1333 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1334 return;
1335
0bcb3e28 1336 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1337}
1338
1339static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1340{
0bcb3e28
DW		 1341 if (!info->dev || !dev_is_pci(info->dev) ||
1342 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1343 return;
1344
0bcb3e28 1345 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1346}
1347
1348static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1349 u64 addr, unsigned mask)
1350{
1351 u16 sid, qdep;
1352 unsigned long flags;
1353 struct device_domain_info *info;
1354
1355 spin_lock_irqsave(&device_domain_lock, flags);
1356 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1357 struct pci_dev *pdev;
1358 if (!info->dev || !dev_is_pci(info->dev))
1359 continue;
1360
1361 pdev = to_pci_dev(info->dev);
1362 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1363 continue;
1364
1365 sid = info->bus << 8 | info->devfn;
0bcb3e28 1366 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1367 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1368 }
1369 spin_unlock_irqrestore(&device_domain_lock, flags);
1370}
1371
1f0ef2aa 1372static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1373 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1374{
9dd2fe89 1375 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1376 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1377
ba395927
KA		 1378 BUG_ON(pages == 0);
1379
ea8ea460
DW		 1380 if (ih)
1381 ih = 1 << 6;
ba395927 1382 /*
9dd2fe89
YZ		 1383 * Fallback to domain selective flush if no PSI support or the size is
1384 * too big.
ba395927
KA		 1385 * PSI requires page size to be 2 ^ x, and the base address is naturally
1386 * aligned to the size
1387 */
9dd2fe89
YZ		 1388 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1389 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1390 DMA_TLB_DSI_FLUSH);
9dd2fe89 1391 else
ea8ea460 1392 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1393 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1394
1395 /*
82653633
NA		 1396 * In caching mode, changes of pages from non-present to present require
1397 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1398 */
82653633 1399 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1400 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1401}
1402
f8bab735 1403static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1404{
1405 u32 pmen;
1406 unsigned long flags;
1407
1f5b3c3f 1408 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1409 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1410 pmen &= ~DMA_PMEN_EPM;
1411 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1412
1413 /* wait for the protected region status bit to clear */
1414 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1415 readl, !(pmen & DMA_PMEN_PRS), pmen);
1416
1f5b3c3f 1417 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1418}
1419
2a41ccee 1420static void iommu_enable_translation(struct intel_iommu *iommu)
ba395927
KA		 1421{
1422 u32 sts;
1423 unsigned long flags;
1424
1f5b3c3f 1425 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1426 iommu->gcmd |= DMA_GCMD_TE;
1427 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1428
1429 /* Make sure hardware complete it */
1430 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1431 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1432
1f5b3c3f 1433 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1434}
1435
2a41ccee 1436static void iommu_disable_translation(struct intel_iommu *iommu)
ba395927
KA		 1437{
1438 u32 sts;
1439 unsigned long flag;
1440
1f5b3c3f 1441 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1442 iommu->gcmd &= ~DMA_GCMD_TE;
1443 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1444
1445 /* Make sure hardware complete it */
1446 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1447 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1448
1f5b3c3f 1449 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1450}
1451
3460a6d9 1452
ba395927
KA		 1453static int iommu_init_domains(struct intel_iommu *iommu)
1454{
1455 unsigned long ndomains;
1456 unsigned long nlongs;
1457
1458 ndomains = cap_ndoms(iommu->cap);
9f10e5bf
JR		 1459 pr_debug("%s: Number of Domains supported <%ld>\n",
1460 iommu->name, ndomains);
ba395927
KA		 1461 nlongs = BITS_TO_LONGS(ndomains);
1462
94a91b50
DD		 1463 spin_lock_init(&iommu->lock);
1464
ba395927
KA		 1465 /* TBD: there might be 64K domains,
1466 * consider other allocation for future chip
1467 */
1468 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1469 if (!iommu->domain_ids) {
9f10e5bf
JR		 1470 pr_err("%s: Allocating domain id array failed\n",
1471 iommu->name);
ba395927
KA		 1472 return -ENOMEM;
1473 }
1474 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1475 GFP_KERNEL);
1476 if (!iommu->domains) {
9f10e5bf
JR		 1477 pr_err("%s: Allocating domain array failed\n",
1478 iommu->name);
852bdb04
JL		 1479 kfree(iommu->domain_ids);
1480 iommu->domain_ids = NULL;
ba395927
KA		 1481 return -ENOMEM;
1482 }
1483
1484 /*
1485 * if Caching mode is set, then invalid translations are tagged
1486 * with domainid 0. Hence we need to pre-allocate it.
1487 */
1488 if (cap_caching_mode(iommu->cap))
1489 set_bit(0, iommu->domain_ids);
1490 return 0;
1491}
ba395927 1492
ffebeb46 1493static void disable_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1494{
1495 struct dmar_domain *domain;
2a46ddf7 1496 int i;
ba395927 1497
94a91b50 1498 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1499 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1500 /*
1501 * Domain id 0 is reserved for invalid translation
1502 * if hardware supports caching mode.
1503 */
1504 if (cap_caching_mode(iommu->cap) && i == 0)
1505 continue;
1506
94a91b50
DD		 1507 domain = iommu->domains[i];
1508 clear_bit(i, iommu->domain_ids);
129ad281
JL		 1509 if (domain_detach_iommu(domain, iommu) == 0 &&
1510 !domain_type_is_vm(domain))
92d03cc8 1511 domain_exit(domain);
5e98c4b1 1512 }
ba395927
KA		 1513 }
1514
1515 if (iommu->gcmd & DMA_GCMD_TE)
1516 iommu_disable_translation(iommu);
ffebeb46 1517}
ba395927 1518
ffebeb46
JL		 1519static void free_dmar_iommu(struct intel_iommu *iommu)
1520{
1521 if ((iommu->domains) && (iommu->domain_ids)) {
1522 kfree(iommu->domains);
1523 kfree(iommu->domain_ids);
1524 iommu->domains = NULL;
1525 iommu->domain_ids = NULL;
1526 }
ba395927 1527
d9630fe9
WH		 1528 g_iommus[iommu->seq_id] = NULL;
1529
ba395927
KA		 1530 /* free context mapping */
1531 free_context_table(iommu);
ba395927
KA		 1532}
1533
ab8dfe25 1534static struct dmar_domain *alloc_domain(int flags)
ba395927 1535{
92d03cc8
JL		 1536 /* domain id for virtual machine, it won't be set in context */
1537 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1538 struct dmar_domain *domain;
ba395927
KA		 1539
1540 domain = alloc_domain_mem();
1541 if (!domain)
1542 return NULL;
1543
ab8dfe25 1544 memset(domain, 0, sizeof(*domain));
4c923d47 1545 domain->nid = -1;
ab8dfe25 1546 domain->flags = flags;
92d03cc8
JL		 1547 spin_lock_init(&domain->iommu_lock);
1548 INIT_LIST_HEAD(&domain->devices);
ab8dfe25 1549 if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
92d03cc8 1550 domain->id = atomic_inc_return(&vm_domid);
2c2e2c38
FY		 1551
1552 return domain;
1553}
1554
fb170fb4
JL		 1555static int __iommu_attach_domain(struct dmar_domain *domain,
1556 struct intel_iommu *iommu)
2c2e2c38
FY		 1557{
1558 int num;
1559 unsigned long ndomains;
2c2e2c38 1560
ba395927 1561 ndomains = cap_ndoms(iommu->cap);
ba395927 1562 num = find_first_zero_bit(iommu->domain_ids, ndomains);
fb170fb4
JL		 1563 if (num < ndomains) {
1564 set_bit(num, iommu->domain_ids);
1565 iommu->domains[num] = domain;
1566 } else {
1567 num = -ENOSPC;
ba395927
KA		 1568 }
1569
fb170fb4
JL		 1570 return num;
1571}
1572
1573static int iommu_attach_domain(struct dmar_domain *domain,
1574 struct intel_iommu *iommu)
1575{
1576 int num;
1577 unsigned long flags;
1578
1579 spin_lock_irqsave(&iommu->lock, flags);
1580 num = __iommu_attach_domain(domain, iommu);
44bde614 1581 spin_unlock_irqrestore(&iommu->lock, flags);
fb170fb4 1582 if (num < 0)
9f10e5bf 1583 pr_err("%s: No free domain ids\n", iommu->name);
ba395927 1584
fb170fb4 1585 return num;
ba395927
KA		 1586}
1587
44bde614
JL		 1588static int iommu_attach_vm_domain(struct dmar_domain *domain,
1589 struct intel_iommu *iommu)
1590{
1591 int num;
1592 unsigned long ndomains;
1593
1594 ndomains = cap_ndoms(iommu->cap);
1595 for_each_set_bit(num, iommu->domain_ids, ndomains)
1596 if (iommu->domains[num] == domain)
1597 return num;
1598
1599 return __iommu_attach_domain(domain, iommu);
1600}
1601
2c2e2c38
FY		 1602static void iommu_detach_domain(struct dmar_domain *domain,
1603 struct intel_iommu *iommu)
ba395927
KA		 1604{
1605 unsigned long flags;
2c2e2c38 1606 int num, ndomains;
ba395927 1607
8c11e798 1608 spin_lock_irqsave(&iommu->lock, flags);
fb170fb4
JL		 1609 if (domain_type_is_vm_or_si(domain)) {
1610 ndomains = cap_ndoms(iommu->cap);
1611 for_each_set_bit(num, iommu->domain_ids, ndomains) {
1612 if (iommu->domains[num] == domain) {
1613 clear_bit(num, iommu->domain_ids);
1614 iommu->domains[num] = NULL;
1615 break;
1616 }
2c2e2c38 1617 }
fb170fb4
JL		 1618 } else {
1619 clear_bit(domain->id, iommu->domain_ids);
1620 iommu->domains[domain->id] = NULL;
2c2e2c38 1621 }
8c11e798 1622 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1623}
1624
fb170fb4
JL		 1625static void domain_attach_iommu(struct dmar_domain *domain,
1626 struct intel_iommu *iommu)
1627{
1628 unsigned long flags;
1629
1630 spin_lock_irqsave(&domain->iommu_lock, flags);
1631 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1632 domain->iommu_count++;
1633 if (domain->iommu_count == 1)
1634 domain->nid = iommu->node;
1635 domain_update_iommu_cap(domain);
1636 }
1637 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1638}
1639
1640static int domain_detach_iommu(struct dmar_domain *domain,
1641 struct intel_iommu *iommu)
1642{
1643 unsigned long flags;
1644 int count = INT_MAX;
1645
1646 spin_lock_irqsave(&domain->iommu_lock, flags);
1647 if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
1648 count = --domain->iommu_count;
1649 domain_update_iommu_cap(domain);
1650 }
1651 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1652
1653 return count;
1654}
1655
ba395927 1656static struct iova_domain reserved_iova_list;
8a443df4 1657static struct lock_class_key reserved_rbtree_key;
ba395927 1658
51a63e67 1659static int dmar_init_reserved_ranges(void)
ba395927
KA		 1660{
1661 struct pci_dev *pdev = NULL;
1662 struct iova *iova;
1663 int i;
ba395927 1664
0fb5fe87
RM		 1665 init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
1666 DMA_32BIT_PFN);
ba395927 1667
8a443df4
MG		 1668 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1669 &reserved_rbtree_key);
1670
ba395927
KA		 1671 /* IOAPIC ranges shouldn't be accessed by DMA */
1672 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1673 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1674 if (!iova) {
9f10e5bf 1675 pr_err("Reserve IOAPIC range failed\n");
51a63e67
JC		 1676 return -ENODEV;
1677 }
ba395927
KA		 1678
1679 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1680 for_each_pci_dev(pdev) {
1681 struct resource *r;
1682
1683 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1684 r = &pdev->resource[i];
1685 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1686 continue;
1a4a4551
DW		 1687 iova = reserve_iova(&reserved_iova_list,
1688 IOVA_PFN(r->start),
1689 IOVA_PFN(r->end));
51a63e67 1690 if (!iova) {
9f10e5bf 1691 pr_err("Reserve iova failed\n");
51a63e67
JC		 1692 return -ENODEV;
1693 }
ba395927
KA		 1694 }
1695 }
51a63e67 1696 return 0;
ba395927
KA		 1697}
1698
1699static void domain_reserve_special_ranges(struct dmar_domain *domain)
1700{
1701 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1702}
1703
1704static inline int guestwidth_to_adjustwidth(int gaw)
1705{
1706 int agaw;
1707 int r = (gaw - 12) % 9;
1708
1709 if (r == 0)
1710 agaw = gaw;
1711 else
1712 agaw = gaw + 9 - r;
1713 if (agaw > 64)
1714 agaw = 64;
1715 return agaw;
1716}
1717
1718static int domain_init(struct dmar_domain *domain, int guest_width)
1719{
1720 struct intel_iommu *iommu;
1721 int adjust_width, agaw;
1722 unsigned long sagaw;
1723
0fb5fe87
RM		 1724 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
1725 DMA_32BIT_PFN);
ba395927
KA		 1726 domain_reserve_special_ranges(domain);
1727
1728 /* calculate AGAW */
8c11e798 1729 iommu = domain_get_iommu(domain);
ba395927
KA		 1730 if (guest_width > cap_mgaw(iommu->cap))
1731 guest_width = cap_mgaw(iommu->cap);
1732 domain->gaw = guest_width;
1733 adjust_width = guestwidth_to_adjustwidth(guest_width);
1734 agaw = width_to_agaw(adjust_width);
1735 sagaw = cap_sagaw(iommu->cap);
1736 if (!test_bit(agaw, &sagaw)) {
1737 /* hardware doesn't support it, choose a bigger one */
9f10e5bf 1738 pr_debug("Hardware doesn't support agaw %d\n", agaw);
ba395927
KA		 1739 agaw = find_next_bit(&sagaw, 5, agaw);
1740 if (agaw >= 5)
1741 return -ENODEV;
1742 }
1743 domain->agaw = agaw;
ba395927 1744
8e604097
WH		 1745 if (ecap_coherent(iommu->ecap))
1746 domain->iommu_coherency = 1;
1747 else
1748 domain->iommu_coherency = 0;
1749
58c610bd
SY		 1750 if (ecap_sc_support(iommu->ecap))
1751 domain->iommu_snooping = 1;
1752 else
1753 domain->iommu_snooping = 0;
1754
214e39aa
DW		 1755 if (intel_iommu_superpage)
1756 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1757 else
1758 domain->iommu_superpage = 0;
1759
4c923d47 1760 domain->nid = iommu->node;
c7151a8d 1761
ba395927 1762 /* always allocate the top pgd */
4c923d47 1763 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1764 if (!domain->pgd)
1765 return -ENOMEM;
5b6985ce 1766 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1767 return 0;
1768}
1769
1770static void domain_exit(struct dmar_domain *domain)
1771{
ea8ea460 1772 struct page *freelist = NULL;
71684406 1773 int i;
ba395927
KA		 1774
1775 /* Domain 0 is reserved, so dont process it */
1776 if (!domain)
1777 return;
1778
7b668357
AW		 1779 /* Flush any lazy unmaps that may reference this domain */
1780 if (!intel_iommu_strict)
1781 flush_unmaps_timeout(0);
1782
92d03cc8 1783 /* remove associated devices */
ba395927 1784 domain_remove_dev_info(domain);
92d03cc8 1785
ba395927
KA		 1786 /* destroy iovas */
1787 put_iova_domain(&domain->iovad);
ba395927 1788
ea8ea460 1789 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1790
92d03cc8 1791 /* clear attached or cached domains */
0e242612 1792 rcu_read_lock();
71684406
AW		 1793 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus)
1794 iommu_detach_domain(domain, g_iommus[i]);
0e242612 1795 rcu_read_unlock();
2c2e2c38 1796
ea8ea460
DW		 1797 dma_free_pagelist(freelist);
1798
ba395927
KA		 1799 free_domain_mem(domain);
1800}
1801
64ae892b
DW		 1802static int domain_context_mapping_one(struct dmar_domain *domain,
1803 struct intel_iommu *iommu,
1804 u8 bus, u8 devfn, int translation)
ba395927
KA		 1805{
1806 struct context_entry *context;
ba395927 1807 unsigned long flags;
ea6606b0 1808 struct dma_pte *pgd;
ea6606b0
WH		 1809 int id;
1810 int agaw;
93a23a72 1811 struct device_domain_info *info = NULL;
ba395927
KA		 1812
1813 pr_debug("Set context mapping for %02x:%02x.%d\n",
1814 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1815
ba395927 1816 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1817 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1818 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1819
03ecc32c
DW		 1820 spin_lock_irqsave(&iommu->lock, flags);
1821 context = iommu_context_addr(iommu, bus, devfn, 1);
1822 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1823 if (!context)
1824 return -ENOMEM;
1825 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1826 if (context_present(context)) {
ba395927
KA		 1827 spin_unlock_irqrestore(&iommu->lock, flags);
1828 return 0;
1829 }
1830
ea6606b0
WH		 1831 id = domain->id;
1832 pgd = domain->pgd;
1833
ab8dfe25 1834 if (domain_type_is_vm_or_si(domain)) {
44bde614
JL		 1835 if (domain_type_is_vm(domain)) {
1836 id = iommu_attach_vm_domain(domain, iommu);
fb170fb4 1837 if (id < 0) {
ea6606b0 1838 spin_unlock_irqrestore(&iommu->lock, flags);
9f10e5bf 1839 pr_err("%s: No free domain ids\n", iommu->name);
ea6606b0
WH		 1840 return -EFAULT;
1841 }
ea6606b0
WH		 1842 }
1843
1844 /* Skip top levels of page tables for
1845 * iommu which has less agaw than default.
1672af11 1846 * Unnecessary for PT mode.
ea6606b0 1847 */
1672af11
CW		 1848 if (translation != CONTEXT_TT_PASS_THROUGH) {
1849 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1850 pgd = phys_to_virt(dma_pte_addr(pgd));
1851 if (!dma_pte_present(pgd)) {
1852 spin_unlock_irqrestore(&iommu->lock, flags);
1853 return -ENOMEM;
1854 }
ea6606b0
WH		 1855 }
1856 }
1857 }
1858
1859 context_set_domain_id(context, id);
4ed0d3e6 1860
93a23a72 1861 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1862 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1863 translation = info ? CONTEXT_TT_DEV_IOTLB :
1864 CONTEXT_TT_MULTI_LEVEL;
1865 }
4ed0d3e6
FY		 1866 /*
1867 * In pass through mode, AW must be programmed to indicate the largest
1868 * AGAW value supported by hardware. And ASR is ignored by hardware.
1869 */
93a23a72 1870 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1871 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1872 else {
1873 context_set_address_root(context, virt_to_phys(pgd));
1874 context_set_address_width(context, iommu->agaw);
1875 }
4ed0d3e6
FY		 1876
1877 context_set_translation_type(context, translation);
c07e7d21
MM		 1878 context_set_fault_enable(context);
1879 context_set_present(context);
5331fe6f 1880 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1881
4c25a2c1
DW		 1882 /*
1883 * It's a non-present to present mapping. If hardware doesn't cache
1884 * non-present entry we only need to flush the write-buffer. If the
1885 * _does_ cache non-present entries, then it does so in the special
1886 * domain #0, which we have to flush:
1887 */
1888 if (cap_caching_mode(iommu->cap)) {
1889 iommu->flush.flush_context(iommu, 0,
1890 (((u16)bus) << 8) | devfn,
1891 DMA_CCMD_MASK_NOBIT,
1892 DMA_CCMD_DEVICE_INVL);
18fd779a 1893 iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1894 } else {
ba395927 1895 iommu_flush_write_buffer(iommu);
4c25a2c1 1896 }
93a23a72 1897 iommu_enable_dev_iotlb(info);
ba395927 1898 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d 1899
fb170fb4
JL		 1900 domain_attach_iommu(domain, iommu);
1901
ba395927
KA		 1902 return 0;
1903}
1904
579305f7
AW		 1905struct domain_context_mapping_data {
1906 struct dmar_domain *domain;
1907 struct intel_iommu *iommu;
1908 int translation;
1909};
1910
1911static int domain_context_mapping_cb(struct pci_dev *pdev,
1912 u16 alias, void *opaque)
1913{
1914 struct domain_context_mapping_data *data = opaque;
1915
1916 return domain_context_mapping_one(data->domain, data->iommu,
1917 PCI_BUS_NUM(alias), alias & 0xff,
1918 data->translation);
1919}
1920
ba395927 1921static int
e1f167f3
DW		 1922domain_context_mapping(struct dmar_domain *domain, struct device *dev,
1923 int translation)
ba395927 1924{
64ae892b 1925 struct intel_iommu *iommu;
156baca8 1926 u8 bus, devfn;
579305f7 1927 struct domain_context_mapping_data data;
64ae892b 1928
e1f167f3 1929 iommu = device_to_iommu(dev, &bus, &devfn);
64ae892b
DW		 1930 if (!iommu)
1931 return -ENODEV;
ba395927 1932
579305f7
AW		 1933 if (!dev_is_pci(dev))
1934 return domain_context_mapping_one(domain, iommu, bus, devfn,
4ed0d3e6 1935 translation);
579305f7
AW		 1936
1937 data.domain = domain;
1938 data.iommu = iommu;
1939 data.translation = translation;
1940
1941 return pci_for_each_dma_alias(to_pci_dev(dev),
1942 &domain_context_mapping_cb, &data);
1943}
1944
1945static int domain_context_mapped_cb(struct pci_dev *pdev,
1946 u16 alias, void *opaque)
1947{
1948 struct intel_iommu *iommu = opaque;
1949
1950 return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
ba395927
KA		 1951}
1952
e1f167f3 1953static int domain_context_mapped(struct device *dev)
ba395927 1954{
5331fe6f 1955 struct intel_iommu *iommu;
156baca8 1956 u8 bus, devfn;
5331fe6f 1957
e1f167f3 1958 iommu = device_to_iommu(dev, &bus, &devfn);
5331fe6f
WH		 1959 if (!iommu)
1960 return -ENODEV;
ba395927 1961
579305f7
AW		 1962 if (!dev_is_pci(dev))
1963 return device_context_mapped(iommu, bus, devfn);
e1f167f3 1964
579305f7
AW		 1965 return !pci_for_each_dma_alias(to_pci_dev(dev),
1966 domain_context_mapped_cb, iommu);
ba395927
KA		 1967}
1968
f532959b
FY		 1969/* Returns a number of VTD pages, but aligned to MM page size */
1970static inline unsigned long aligned_nrpages(unsigned long host_addr,
1971 size_t size)
1972{
1973 host_addr &= ~PAGE_MASK;
1974 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1975}
1976
6dd9a7c7
YS		 1977/* Return largest possible superpage level for a given mapping */
1978static inline int hardware_largepage_caps(struct dmar_domain *domain,
1979 unsigned long iov_pfn,
1980 unsigned long phy_pfn,
1981 unsigned long pages)
1982{
1983 int support, level = 1;
1984 unsigned long pfnmerge;
1985
1986 support = domain->iommu_superpage;
1987
1988 /* To use a large page, the virtual *and* physical addresses
1989 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1990 of them will mean we have to use smaller pages. So just
1991 merge them and check both at once. */
1992 pfnmerge = iov_pfn | phy_pfn;
1993
1994 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1995 pages >>= VTD_STRIDE_SHIFT;
1996 if (!pages)
1997 break;
1998 pfnmerge >>= VTD_STRIDE_SHIFT;
1999 level++;
2000 support--;
2001 }
2002 return level;
2003}
2004
9051aa02
DW		 2005static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2006 struct scatterlist *sg, unsigned long phys_pfn,
2007 unsigned long nr_pages, int prot)
e1605495
DW		 2008{
2009 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 2010 phys_addr_t uninitialized_var(pteval);
cc4f14aa 2011 unsigned long sg_res = 0;
6dd9a7c7
YS		 2012 unsigned int largepage_lvl = 0;
2013 unsigned long lvl_pages = 0;
e1605495 2014
162d1b10 2015 BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
e1605495
DW		 2016
2017 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
2018 return -EINVAL;
2019
2020 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
2021
cc4f14aa
JL		 2022 if (!sg) {
2023 sg_res = nr_pages;
9051aa02
DW		 2024 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
2025 }
2026
6dd9a7c7 2027 while (nr_pages > 0) {
c85994e4
DW		 2028 uint64_t tmp;
2029
e1605495 2030 if (!sg_res) {
f532959b 2031 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 2032 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
2033 sg->dma_length = sg->length;
2034 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 2035 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 2036 }
6dd9a7c7 2037
e1605495 2038 if (!pte) {
6dd9a7c7
YS		 2039 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
2040
5cf0a76f 2041 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 2042 if (!pte)
2043 return -ENOMEM;
6dd9a7c7 2044 /* It is large page*/
6491d4d0 2045 if (largepage_lvl > 1) {
6dd9a7c7 2046 pteval |= DMA_PTE_LARGE_PAGE;
d41a4adb
JL		 2047 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2048 /*
2049 * Ensure that old small page tables are
2050 * removed to make room for superpage,
2051 * if they exist.
2052 */
6491d4d0 2053 dma_pte_free_pagetable(domain, iov_pfn,
d41a4adb 2054 iov_pfn + lvl_pages - 1);
6491d4d0 2055 } else {
6dd9a7c7 2056 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 2057 }
6dd9a7c7 2058
e1605495
DW		 2059 }
2060 /* We don't need lock here, nobody else
2061 * touches the iova range
2062 */
7766a3fb 2063 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2064 if (tmp) {
1bf20f0d 2065 static int dumps = 5;
9f10e5bf
JR		 2066 pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2067 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2068 if (dumps) {
2069 dumps--;
2070 debug_dma_dump_mappings(NULL);
2071 }
2072 WARN_ON(1);
2073 }
6dd9a7c7
YS		 2074
2075 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2076
2077 BUG_ON(nr_pages < lvl_pages);
2078 BUG_ON(sg_res < lvl_pages);
2079
2080 nr_pages -= lvl_pages;
2081 iov_pfn += lvl_pages;
2082 phys_pfn += lvl_pages;
2083 pteval += lvl_pages * VTD_PAGE_SIZE;
2084 sg_res -= lvl_pages;
2085
2086 /* If the next PTE would be the first in a new page, then we
2087 need to flush the cache on the entries we've just written.
2088 And then we'll need to recalculate 'pte', so clear it and
2089 let it get set again in the if (!pte) block above.
2090
2091 If we're done (!nr_pages) we need to flush the cache too.
2092
2093 Also if we've been setting superpages, we may need to
2094 recalculate 'pte' and switch back to smaller pages for the
2095 end of the mapping, if the trailing size is not enough to
2096 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2097 pte++;
6dd9a7c7
YS		 2098 if (!nr_pages || first_pte_in_page(pte) ||
2099 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2100 domain_flush_cache(domain, first_pte,
2101 (void *)pte - (void *)first_pte);
2102 pte = NULL;
2103 }
6dd9a7c7
YS		 2104
2105 if (!sg_res && nr_pages)
e1605495
DW		 2106 sg = sg_next(sg);
2107 }
2108 return 0;
2109}
2110
9051aa02
DW		 2111static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2112 struct scatterlist *sg, unsigned long nr_pages,
2113 int prot)
ba395927 2114{
9051aa02
DW		 2115 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2116}
6f6a00e4 2117
9051aa02
DW		 2118static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2119 unsigned long phys_pfn, unsigned long nr_pages,
2120 int prot)
2121{
2122 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2123}
2124
c7151a8d 2125static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2126{
c7151a8d
WH		 2127 if (!iommu)
2128 return;
8c11e798
WH		 2129
2130 clear_context_table(iommu, bus, devfn);
2131 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2132 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2133 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2134}
2135
109b9b04
DW		 2136static inline void unlink_domain_info(struct device_domain_info *info)
2137{
2138 assert_spin_locked(&device_domain_lock);
2139 list_del(&info->link);
2140 list_del(&info->global);
2141 if (info->dev)
0bcb3e28 2142 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2143}
2144
ba395927
KA		 2145static void domain_remove_dev_info(struct dmar_domain *domain)
2146{
3a74ca01 2147 struct device_domain_info *info, *tmp;
fb170fb4 2148 unsigned long flags;
ba395927
KA		 2149
2150 spin_lock_irqsave(&device_domain_lock, flags);
3a74ca01 2151 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
109b9b04 2152 unlink_domain_info(info);
ba395927
KA		 2153 spin_unlock_irqrestore(&device_domain_lock, flags);
2154
93a23a72 2155 iommu_disable_dev_iotlb(info);
7c7faa11 2156 iommu_detach_dev(info->iommu, info->bus, info->devfn);
ba395927 2157
ab8dfe25 2158 if (domain_type_is_vm(domain)) {
7c7faa11 2159 iommu_detach_dependent_devices(info->iommu, info->dev);
fb170fb4 2160 domain_detach_iommu(domain, info->iommu);
92d03cc8
JL		 2161 }
2162
2163 free_devinfo_mem(info);
ba395927
KA		 2164 spin_lock_irqsave(&device_domain_lock, flags);
2165 }
2166 spin_unlock_irqrestore(&device_domain_lock, flags);
2167}
2168
2169/*
2170 * find_domain
1525a29a 2171 * Note: we use struct device->archdata.iommu stores the info
ba395927 2172 */
1525a29a 2173static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2174{
2175 struct device_domain_info *info;
2176
2177 /* No lock here, assumes no domain exit in normal case */
1525a29a 2178 info = dev->archdata.iommu;
ba395927
KA		 2179 if (info)
2180 return info->domain;
2181 return NULL;
2182}
2183
5a8f40e8 2184static inline struct device_domain_info *
745f2586
JL		 2185dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2186{
2187 struct device_domain_info *info;
2188
2189 list_for_each_entry(info, &device_domain_list, global)
41e80dca 2190 if (info->iommu->segment == segment && info->bus == bus &&
745f2586 2191 info->devfn == devfn)
5a8f40e8 2192 return info;
745f2586
JL		 2193
2194 return NULL;
2195}
2196
5a8f40e8 2197static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
41e80dca 2198 int bus, int devfn,
b718cd3d
DW		 2199 struct device *dev,
2200 struct dmar_domain *domain)
745f2586 2201{
5a8f40e8 2202 struct dmar_domain *found = NULL;
745f2586
JL		 2203 struct device_domain_info *info;
2204 unsigned long flags;
2205
2206 info = alloc_devinfo_mem();
2207 if (!info)
b718cd3d 2208 return NULL;
745f2586 2209
745f2586
JL		 2210 info->bus = bus;
2211 info->devfn = devfn;
2212 info->dev = dev;
2213 info->domain = domain;
5a8f40e8 2214 info->iommu = iommu;
745f2586
JL		 2215
2216 spin_lock_irqsave(&device_domain_lock, flags);
2217 if (dev)
0bcb3e28 2218 found = find_domain(dev);
5a8f40e8
DW		 2219 else {
2220 struct device_domain_info *info2;
41e80dca 2221 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
5a8f40e8
DW		 2222 if (info2)
2223 found = info2->domain;
2224 }
745f2586
JL		 2225 if (found) {
2226 spin_unlock_irqrestore(&device_domain_lock, flags);
2227 free_devinfo_mem(info);
b718cd3d
DW		 2228 /* Caller must free the original domain */
2229 return found;
745f2586
JL		 2230 }
2231
b718cd3d
DW		 2232 list_add(&info->link, &domain->devices);
2233 list_add(&info->global, &device_domain_list);
2234 if (dev)
2235 dev->archdata.iommu = info;
2236 spin_unlock_irqrestore(&device_domain_lock, flags);
2237
2238 return domain;
745f2586
JL		 2239}
2240
579305f7
AW		 2241static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
2242{
2243 *(u16 *)opaque = alias;
2244 return 0;
2245}
2246
ba395927 2247/* domain is initialized */
146922ec 2248static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
ba395927 2249{
579305f7
AW		 2250 struct dmar_domain *domain, *tmp;
2251 struct intel_iommu *iommu;
5a8f40e8 2252 struct device_domain_info *info;
579305f7 2253 u16 dma_alias;
ba395927 2254 unsigned long flags;
aa4d066a 2255 u8 bus, devfn;
ba395927 2256
146922ec 2257 domain = find_domain(dev);
ba395927
KA		 2258 if (domain)
2259 return domain;
2260
579305f7
AW		 2261 iommu = device_to_iommu(dev, &bus, &devfn);
2262 if (!iommu)
2263 return NULL;
2264
146922ec
DW		 2265 if (dev_is_pci(dev)) {
2266 struct pci_dev *pdev = to_pci_dev(dev);
276dbf99 2267
579305f7
AW		 2268 pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
2269
2270 spin_lock_irqsave(&device_domain_lock, flags);
2271 info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
2272 PCI_BUS_NUM(dma_alias),
2273 dma_alias & 0xff);
2274 if (info) {
2275 iommu = info->iommu;
2276 domain = info->domain;
5a8f40e8 2277 }
579305f7 2278 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2279
579305f7
AW		 2280 /* DMA alias already has a domain, uses it */
2281 if (info)
2282 goto found_domain;
2283 }
ba395927 2284
146922ec 2285 /* Allocate and initialize new domain for the device */
ab8dfe25 2286 domain = alloc_domain(0);
745f2586 2287 if (!domain)
579305f7 2288 return NULL;
44bde614
JL		 2289 domain->id = iommu_attach_domain(domain, iommu);
2290 if (domain->id < 0) {
2fe9723d 2291 free_domain_mem(domain);
579305f7 2292 return NULL;
2c2e2c38 2293 }
fb170fb4 2294 domain_attach_iommu(domain, iommu);
579305f7
AW		 2295 if (domain_init(domain, gaw)) {
2296 domain_exit(domain);
2297 return NULL;
2c2e2c38 2298 }
ba395927 2299
579305f7
AW		 2300 /* register PCI DMA alias device */
2301 if (dev_is_pci(dev)) {
2302 tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias),
2303 dma_alias & 0xff, NULL, domain);
2304
2305 if (!tmp || tmp != domain) {
2306 domain_exit(domain);
2307 domain = tmp;
2308 }
2309
b718cd3d 2310 if (!domain)
579305f7 2311 return NULL;
ba395927
KA		 2312 }
2313
2314found_domain:
579305f7
AW		 2315 tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
2316
2317 if (!tmp || tmp != domain) {
2318 domain_exit(domain);
2319 domain = tmp;
2320 }
b718cd3d
DW		 2321
2322 return domain;
ba395927
KA		 2323}
2324
2c2e2c38 2325static int iommu_identity_mapping;
e0fc7e0b
DW		 2326#define IDENTMAP_ALL 1
2327#define IDENTMAP_GFX 2
2328#define IDENTMAP_AZALIA 4
2c2e2c38 2329
b213203e
DW		 2330static int iommu_domain_identity_map(struct dmar_domain *domain,
2331 unsigned long long start,
2332 unsigned long long end)
ba395927 2333{
c5395d5c
DW		 2334 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2335 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2336
2337 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2338 dma_to_mm_pfn(last_vpfn))) {
9f10e5bf 2339 pr_err("Reserving iova failed\n");
b213203e 2340 return -ENOMEM;
ba395927
KA		 2341 }
2342
c5395d5c
DW		 2343 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2344 start, end, domain->id);
ba395927
KA		 2345 /*
2346 * RMRR range might have overlap with physical memory range,
2347 * clear it first
2348 */
c5395d5c 2349 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2350
c5395d5c
DW		 2351 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2352 last_vpfn - first_vpfn + 1,
61df7443 2353 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2354}
2355
0b9d9753 2356static int iommu_prepare_identity_map(struct device *dev,
b213203e
DW		 2357 unsigned long long start,
2358 unsigned long long end)
2359{
2360 struct dmar_domain *domain;
2361 int ret;
2362
0b9d9753 2363 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2364 if (!domain)
2365 return -ENOMEM;
2366
19943b0e
DW		 2367 /* For _hardware_ passthrough, don't bother. But for software
2368 passthrough, we do it anyway -- it may indicate a memory
2369 range which is reserved in E820, so which didn't get set
2370 up to start with in si_domain */
2371 if (domain == si_domain && hw_pass_through) {
9f10e5bf
JR		 2372 pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2373 dev_name(dev), start, end);
19943b0e
DW		 2374 return 0;
2375 }
2376
9f10e5bf
JR		 2377 pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2378 dev_name(dev), start, end);
2379
5595b528
DW		 2380 if (end < start) {
2381 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2382 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2383 dmi_get_system_info(DMI_BIOS_VENDOR),
2384 dmi_get_system_info(DMI_BIOS_VERSION),
2385 dmi_get_system_info(DMI_PRODUCT_VERSION));
2386 ret = -EIO;
2387 goto error;
2388 }
2389
2ff729f5
DW		 2390 if (end >> agaw_to_width(domain->agaw)) {
2391 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2392 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2393 agaw_to_width(domain->agaw),
2394 dmi_get_system_info(DMI_BIOS_VENDOR),
2395 dmi_get_system_info(DMI_BIOS_VERSION),
2396 dmi_get_system_info(DMI_PRODUCT_VERSION));
2397 ret = -EIO;
2398 goto error;
2399 }
19943b0e 2400
b213203e 2401 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2402 if (ret)
2403 goto error;
2404
2405 /* context entry init */
0b9d9753 2406 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2407 if (ret)
2408 goto error;
2409
2410 return 0;
2411
2412 error:
ba395927
KA		 2413 domain_exit(domain);
2414 return ret;
ba395927
KA		 2415}
2416
2417static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
0b9d9753 2418 struct device *dev)
ba395927 2419{
0b9d9753 2420 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927 2421 return 0;
0b9d9753
DW		 2422 return iommu_prepare_identity_map(dev, rmrr->base_address,
2423 rmrr->end_address);
ba395927
KA		 2424}
2425
d3f13810 2426#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2427static inline void iommu_prepare_isa(void)
2428{
2429 struct pci_dev *pdev;
2430 int ret;
2431
2432 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2433 if (!pdev)
2434 return;
2435
9f10e5bf 2436 pr_info("Prepare 0-16MiB unity mapping for LPC\n");
0b9d9753 2437 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2438
2439 if (ret)
9f10e5bf 2440 pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
49a0429e 2441
9b27e82d 2442 pci_dev_put(pdev);
49a0429e
KA		 2443}
2444#else
2445static inline void iommu_prepare_isa(void)
2446{
2447 return;
2448}
d3f13810 2449#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2450
2c2e2c38 2451static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2452
071e1374 2453static int __init si_domain_init(int hw)
2c2e2c38
FY		 2454{
2455 struct dmar_drhd_unit *drhd;
2456 struct intel_iommu *iommu;
c7ab48d2 2457 int nid, ret = 0;
44bde614 2458 bool first = true;
2c2e2c38 2459
ab8dfe25 2460 si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2c2e2c38
FY		 2461 if (!si_domain)
2462 return -EFAULT;
2463
2c2e2c38
FY		 2464 for_each_active_iommu(iommu, drhd) {
2465 ret = iommu_attach_domain(si_domain, iommu);
fb170fb4 2466 if (ret < 0) {
2c2e2c38
FY		 2467 domain_exit(si_domain);
2468 return -EFAULT;
44bde614
JL		 2469 } else if (first) {
2470 si_domain->id = ret;
2471 first = false;
2472 } else if (si_domain->id != ret) {
2473 domain_exit(si_domain);
2474 return -EFAULT;
2c2e2c38 2475 }
fb170fb4 2476 domain_attach_iommu(si_domain, iommu);
2c2e2c38
FY		 2477 }
2478
2479 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2480 domain_exit(si_domain);
2481 return -EFAULT;
2482 }
2483
9f10e5bf 2484 pr_debug("Identity mapping domain is domain %d\n",
9544c003 2485 si_domain->id);
2c2e2c38 2486
19943b0e
DW		 2487 if (hw)
2488 return 0;
2489
c7ab48d2 2490 for_each_online_node(nid) {
5dfe8660
TH		 2491 unsigned long start_pfn, end_pfn;
2492 int i;
2493
2494 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2495 ret = iommu_domain_identity_map(si_domain,
2496 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2497 if (ret)
2498 return ret;
2499 }
c7ab48d2
DW		 2500 }
2501
2c2e2c38
FY		 2502 return 0;
2503}
2504
9b226624 2505static int identity_mapping(struct device *dev)
2c2e2c38
FY		 2506{
2507 struct device_domain_info *info;
2508
2509 if (likely(!iommu_identity_mapping))
2510 return 0;
2511
9b226624 2512 info = dev->archdata.iommu;
cb452a40
MT		 2513 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2514 return (info->domain == si_domain);
2c2e2c38 2515
2c2e2c38
FY		 2516 return 0;
2517}
2518
2519static int domain_add_dev_info(struct dmar_domain *domain,
5913c9bf 2520 struct device *dev, int translation)
2c2e2c38 2521{
0ac72664 2522 struct dmar_domain *ndomain;
5a8f40e8 2523 struct intel_iommu *iommu;
156baca8 2524 u8 bus, devfn;
5fe60f4e 2525 int ret;
2c2e2c38 2526
5913c9bf 2527 iommu = device_to_iommu(dev, &bus, &devfn);
5a8f40e8
DW		 2528 if (!iommu)
2529 return -ENODEV;
2530
5913c9bf 2531 ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
0ac72664
DW		 2532 if (ndomain != domain)
2533 return -EBUSY;
2c2e2c38 2534
5913c9bf 2535 ret = domain_context_mapping(domain, dev, translation);
e2ad23d0 2536 if (ret) {
5913c9bf 2537 domain_remove_one_dev_info(domain, dev);
e2ad23d0
DW		 2538 return ret;
2539 }
2540
2c2e2c38
FY		 2541 return 0;
2542}
2543
0b9d9753 2544static bool device_has_rmrr(struct device *dev)
ea2447f7
TM		 2545{
2546 struct dmar_rmrr_unit *rmrr;
832bd858 2547 struct device *tmp;
ea2447f7
TM		 2548 int i;
2549
0e242612 2550 rcu_read_lock();
ea2447f7 2551 for_each_rmrr_units(rmrr) {
b683b230
JL		 2552 /*
2553 * Return TRUE if this RMRR contains the device that
2554 * is passed in.
2555 */
2556 for_each_active_dev_scope(rmrr->devices,
2557 rmrr->devices_cnt, i, tmp)
0b9d9753 2558 if (tmp == dev) {
0e242612 2559 rcu_read_unlock();
ea2447f7 2560 return true;
b683b230 2561 }
ea2447f7 2562 }
0e242612 2563 rcu_read_unlock();
ea2447f7
TM		 2564 return false;
2565}
2566
c875d2c1
AW		 2567/*
2568 * There are a couple cases where we need to restrict the functionality of
2569 * devices associated with RMRRs. The first is when evaluating a device for
2570 * identity mapping because problems exist when devices are moved in and out
2571 * of domains and their respective RMRR information is lost. This means that
2572 * a device with associated RMRRs will never be in a "passthrough" domain.
2573 * The second is use of the device through the IOMMU API. This interface
2574 * expects to have full control of the IOVA space for the device. We cannot
2575 * satisfy both the requirement that RMRR access is maintained and have an
2576 * unencumbered IOVA space. We also have no ability to quiesce the device's
2577 * use of the RMRR space or even inform the IOMMU API user of the restriction.
2578 * We therefore prevent devices associated with an RMRR from participating in
2579 * the IOMMU API, which eliminates them from device assignment.
2580 *
2581 * In both cases we assume that PCI USB devices with RMRRs have them largely
2582 * for historical reasons and that the RMRR space is not actively used post
2583 * boot. This exclusion may change if vendors begin to abuse it.
18436afd
DW		 2584 *
2585 * The same exception is made for graphics devices, with the requirement that
2586 * any use of the RMRR regions will be torn down before assigning the device
2587 * to a guest.
c875d2c1
AW		 2588 */
2589static bool device_is_rmrr_locked(struct device *dev)
2590{
2591 if (!device_has_rmrr(dev))
2592 return false;
2593
2594 if (dev_is_pci(dev)) {
2595 struct pci_dev *pdev = to_pci_dev(dev);
2596
18436afd 2597 if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
c875d2c1
AW		 2598 return false;
2599 }
2600
2601 return true;
2602}
2603
3bdb2591 2604static int iommu_should_identity_map(struct device *dev, int startup)
6941af28 2605{
ea2447f7 2606
3bdb2591
DW		 2607 if (dev_is_pci(dev)) {
2608 struct pci_dev *pdev = to_pci_dev(dev);
ea2447f7 2609
c875d2c1 2610 if (device_is_rmrr_locked(dev))
3bdb2591 2611 return 0;
e0fc7e0b 2612
3bdb2591
DW		 2613 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2614 return 1;
e0fc7e0b 2615
3bdb2591
DW		 2616 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2617 return 1;
6941af28 2618
3bdb2591 2619 if (!(iommu_identity_mapping & IDENTMAP_ALL))
3dfc813d 2620 return 0;
3bdb2591
DW		 2621
2622 /*
2623 * We want to start off with all devices in the 1:1 domain, and
2624 * take them out later if we find they can't access all of memory.
2625 *
2626 * However, we can't do this for PCI devices behind bridges,
2627 * because all PCI devices behind the same bridge will end up
2628 * with the same source-id on their transactions.
2629 *
2630 * Practically speaking, we can't change things around for these
2631 * devices at run-time, because we can't be sure there'll be no
2632 * DMA transactions in flight for any of their siblings.
2633 *
2634 * So PCI devices (unless they're on the root bus) as well as
2635 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2636 * the 1:1 domain, just in _case_ one of their siblings turns out
2637 * not to be able to map all of memory.
2638 */
2639 if (!pci_is_pcie(pdev)) {
2640 if (!pci_is_root_bus(pdev->bus))
2641 return 0;
2642 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2643 return 0;
2644 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d 2645 return 0;
3bdb2591
DW		 2646 } else {
2647 if (device_has_rmrr(dev))
2648 return 0;
2649 }
3dfc813d 2650
3bdb2591 2651 /*
3dfc813d 2652 * At boot time, we don't yet know if devices will be 64-bit capable.
3bdb2591 2653 * Assume that they will — if they turn out not to be, then we can
3dfc813d
DW		 2654 * take them out of the 1:1 domain later.
2655 */
8fcc5372
CW		 2656 if (!startup) {
2657 /*
2658 * If the device's dma_mask is less than the system's memory
2659 * size then this is not a candidate for identity mapping.
2660 */
3bdb2591 2661 u64 dma_mask = *dev->dma_mask;
8fcc5372 2662
3bdb2591
DW		 2663 if (dev->coherent_dma_mask &&
2664 dev->coherent_dma_mask < dma_mask)
2665 dma_mask = dev->coherent_dma_mask;
8fcc5372 2666
3bdb2591 2667 return dma_mask >= dma_get_required_mask(dev);
8fcc5372 2668 }
6941af28
DW		 2669
2670 return 1;
2671}
2672
cf04eee8
DW		 2673static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
2674{
2675 int ret;
2676
2677 if (!iommu_should_identity_map(dev, 1))
2678 return 0;
2679
2680 ret = domain_add_dev_info(si_domain, dev,
2681 hw ? CONTEXT_TT_PASS_THROUGH :
2682 CONTEXT_TT_MULTI_LEVEL);
2683 if (!ret)
9f10e5bf
JR		 2684 pr_info("%s identity mapping for device %s\n",
2685 hw ? "Hardware" : "Software", dev_name(dev));
cf04eee8
DW		 2686 else if (ret == -ENODEV)
2687 /* device not associated with an iommu */
2688 ret = 0;
2689
2690 return ret;
2691}
2692
2693
071e1374 2694static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2695{
2c2e2c38 2696 struct pci_dev *pdev = NULL;
cf04eee8
DW		 2697 struct dmar_drhd_unit *drhd;
2698 struct intel_iommu *iommu;
2699 struct device *dev;
2700 int i;
2701 int ret = 0;
2c2e2c38 2702
19943b0e 2703 ret = si_domain_init(hw);
2c2e2c38
FY		 2704 if (ret)
2705 return -EFAULT;
2706
2c2e2c38 2707 for_each_pci_dev(pdev) {
cf04eee8
DW		 2708 ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
2709 if (ret)
2710 return ret;
2711 }
2712
2713 for_each_active_iommu(iommu, drhd)
2714 for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
2715 struct acpi_device_physical_node *pn;
2716 struct acpi_device *adev;
2717
2718 if (dev->bus != &acpi_bus_type)
2719 continue;
2720
2721 adev= to_acpi_device(dev);
2722 mutex_lock(&adev->physical_node_lock);
2723 list_for_each_entry(pn, &adev->physical_node_list, node) {
2724 ret = dev_prepare_static_identity_mapping(pn->dev, hw);
2725 if (ret)
2726 break;
eae460b6 2727 }
cf04eee8
DW		 2728 mutex_unlock(&adev->physical_node_lock);
2729 if (ret)
2730 return ret;
62edf5dc 2731 }
2c2e2c38
FY		 2732
2733 return 0;
2734}
2735
ffebeb46
JL		 2736static void intel_iommu_init_qi(struct intel_iommu *iommu)
2737{
2738 /*
2739 * Start from the sane iommu hardware state.
2740 * If the queued invalidation is already initialized by us
2741 * (for example, while enabling interrupt-remapping) then
2742 * we got the things already rolling from a sane state.
2743 */
2744 if (!iommu->qi) {
2745 /*
2746 * Clear any previous faults.
2747 */
2748 dmar_fault(-1, iommu);
2749 /*
2750 * Disable queued invalidation if supported and already enabled
2751 * before OS handover.
2752 */
2753 dmar_disable_qi(iommu);
2754 }
2755
2756 if (dmar_enable_qi(iommu)) {
2757 /*
2758 * Queued Invalidate not enabled, use Register Based Invalidate
2759 */
2760 iommu->flush.flush_context = __iommu_flush_context;
2761 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
9f10e5bf 2762 pr_info("%s: Using Register based invalidation\n",
ffebeb46
JL		 2763 iommu->name);
2764 } else {
2765 iommu->flush.flush_context = qi_flush_context;
2766 iommu->flush.flush_iotlb = qi_flush_iotlb;
9f10e5bf 2767 pr_info("%s: Using Queued invalidation\n", iommu->name);
ffebeb46
JL		 2768 }
2769}
2770
b779260b 2771static int __init init_dmars(void)
ba395927
KA		 2772{
2773 struct dmar_drhd_unit *drhd;
2774 struct dmar_rmrr_unit *rmrr;
832bd858 2775 struct device *dev;
ba395927 2776 struct intel_iommu *iommu;
9d783ba0 2777 int i, ret;
2c2e2c38 2778
ba395927
KA		 2779 /*
2780 * for each drhd
2781 * allocate root
2782 * initialize and program root entry to not present
2783 * endfor
2784 */
2785 for_each_drhd_unit(drhd) {
5e0d2a6f 2786 /*
2787 * lock not needed as this is only incremented in the single
2788 * threaded kernel __init code path all other access are read
2789 * only
2790 */
78d8e704 2791 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
1b198bb0
MT		 2792 g_num_of_iommus++;
2793 continue;
2794 }
9f10e5bf 2795 pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
5e0d2a6f 2796 }
2797
ffebeb46
JL		 2798 /* Preallocate enough resources for IOMMU hot-addition */
2799 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
2800 g_num_of_iommus = DMAR_UNITS_SUPPORTED;
2801
d9630fe9
WH		 2802 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2803 GFP_KERNEL);
2804 if (!g_iommus) {
9f10e5bf 2805 pr_err("Allocating global iommu array failed\n");
d9630fe9
WH		 2806 ret = -ENOMEM;
2807 goto error;
2808 }
2809
80b20dd8 2810 deferred_flush = kzalloc(g_num_of_iommus *
2811 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2812 if (!deferred_flush) {
5e0d2a6f 2813 ret = -ENOMEM;
989d51fc 2814 goto free_g_iommus;
5e0d2a6f 2815 }
2816
7c919779 2817 for_each_active_iommu(iommu, drhd) {
d9630fe9 2818 g_iommus[iommu->seq_id] = iommu;
ba395927 2819
b63d80d1
JR		 2820 intel_iommu_init_qi(iommu);
2821
e61d98d8
SS		 2822 ret = iommu_init_domains(iommu);
2823 if (ret)
989d51fc 2824 goto free_iommu;
e61d98d8 2825
4158c2ec
JR		 2826 init_translation_status(iommu);
2827
2828 if (translation_pre_enabled(iommu))
2829 pr_info("Translation already enabled - trying to copy translation structures\n");
2830
ba395927
KA		 2831 /*
2832 * TBD:
2833 * we could share the same root & context tables
25985edc 2834 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2835 */
2836 ret = iommu_alloc_root_entry(iommu);
ffebeb46 2837 if (ret)
989d51fc 2838 goto free_iommu;
5f0a7f76
JR		 2839
2840 iommu_flush_write_buffer(iommu);
2841 iommu_set_root_entry(iommu);
2842 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2843 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2844
4ed0d3e6 2845 if (!ecap_pass_through(iommu->ecap))
19943b0e 2846 hw_pass_through = 0;
ba395927
KA		 2847 }
2848
19943b0e 2849 if (iommu_pass_through)
e0fc7e0b
DW		 2850 iommu_identity_mapping |= IDENTMAP_ALL;
2851
d3f13810 2852#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2853 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2854#endif
e0fc7e0b
DW		 2855
2856 check_tylersburg_isoch();
2857
ba395927 2858 /*
19943b0e
DW		 2859 * If pass through is not set or not enabled, setup context entries for
2860 * identity mappings for rmrr, gfx, and isa and may fall back to static
2861 * identity mapping if iommu_identity_mapping is set.
ba395927 2862 */
19943b0e
DW		 2863 if (iommu_identity_mapping) {
2864 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2865 if (ret) {
9f10e5bf 2866 pr_crit("Failed to setup IOMMU pass-through\n");
989d51fc 2867 goto free_iommu;
ba395927
KA		 2868 }
2869 }
ba395927 2870 /*
19943b0e
DW		 2871 * For each rmrr
2872 * for each dev attached to rmrr
2873 * do
2874 * locate drhd for dev, alloc domain for dev
2875 * allocate free domain
2876 * allocate page table entries for rmrr
2877 * if context not allocated for bus
2878 * allocate and init context
2879 * set present in root table for this bus
2880 * init context with domain, translation etc
2881 * endfor
2882 * endfor
ba395927 2883 */
9f10e5bf 2884 pr_info("Setting RMRR:\n");
19943b0e 2885 for_each_rmrr_units(rmrr) {
b683b230
JL		 2886 /* some BIOS lists non-exist devices in DMAR table. */
2887 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858 2888 i, dev) {
0b9d9753 2889 ret = iommu_prepare_rmrr_dev(rmrr, dev);
19943b0e 2890 if (ret)
9f10e5bf 2891 pr_err("Mapping reserved region failed\n");
ba395927 2892 }
4ed0d3e6 2893 }
49a0429e 2894
19943b0e
DW		 2895 iommu_prepare_isa();
2896
ba395927
KA		 2897 /*
2898 * for each drhd
2899 * enable fault log
2900 * global invalidate context cache
2901 * global invalidate iotlb
2902 * enable translation
2903 */
7c919779 2904 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2905 if (drhd->ignored) {
2906 /*
2907 * we always have to disable PMRs or DMA may fail on
2908 * this device
2909 */
2910 if (force_on)
7c919779 2911 iommu_disable_protect_mem_regions(iommu);
ba395927 2912 continue;
51a63e67 2913 }
ba395927
KA		 2914
2915 iommu_flush_write_buffer(iommu);
2916
3460a6d9
KA		 2917 ret = dmar_set_interrupt(iommu);
2918 if (ret)
989d51fc 2919 goto free_iommu;
3460a6d9 2920
2a41ccee 2921 iommu_enable_translation(iommu);
b94996c9 2922 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2923 }
2924
2925 return 0;
989d51fc
JL		 2926
2927free_iommu:
ffebeb46
JL		 2928 for_each_active_iommu(iommu, drhd) {
2929 disable_dmar_iommu(iommu);
a868e6b7 2930 free_dmar_iommu(iommu);
ffebeb46 2931 }
9bdc531e 2932 kfree(deferred_flush);
989d51fc 2933free_g_iommus:
d9630fe9 2934 kfree(g_iommus);
989d51fc 2935error:
ba395927
KA		 2936 return ret;
2937}
2938
5a5e02a6 2939/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2940static struct iova *intel_alloc_iova(struct device *dev,
2941 struct dmar_domain *domain,
2942 unsigned long nrpages, uint64_t dma_mask)
ba395927 2943{
ba395927 2944 struct iova *iova = NULL;
ba395927 2945
875764de
DW		 2946 /* Restrict dma_mask to the width that the iommu can handle */
2947 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2948
2949 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2950 /*
2951 * First try to allocate an io virtual address in
284901a9 2952 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2953 * from higher range
ba395927 2954 */
875764de
DW		 2955 iova = alloc_iova(&domain->iovad, nrpages,
2956 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2957 if (iova)
2958 return iova;
2959 }
2960 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2961 if (unlikely(!iova)) {
9f10e5bf 2962 pr_err("Allocating %ld-page iova for %s failed",
207e3592 2963 nrpages, dev_name(dev));
f76aec76
KA		 2964 return NULL;
2965 }
2966
2967 return iova;
2968}
2969
d4b709f4 2970static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
f76aec76
KA		 2971{
2972 struct dmar_domain *domain;
2973 int ret;
2974
d4b709f4 2975 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
f76aec76 2976 if (!domain) {
9f10e5bf 2977 pr_err("Allocating domain for %s failed\n",
d4b709f4 2978 dev_name(dev));
4fe05bbc 2979 return NULL;
ba395927
KA		 2980 }
2981
2982 /* make sure context mapping is ok */
d4b709f4
DW		 2983 if (unlikely(!domain_context_mapped(dev))) {
2984 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
f76aec76 2985 if (ret) {
9f10e5bf 2986 pr_err("Domain context map for %s failed\n",
d4b709f4 2987 dev_name(dev));
4fe05bbc 2988 return NULL;
f76aec76 2989 }
ba395927
KA		 2990 }
2991
f76aec76
KA		 2992 return domain;
2993}
2994
d4b709f4 2995static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
147202aa
DW		 2996{
2997 struct device_domain_info *info;
2998
2999 /* No lock here, assumes no domain exit in normal case */
d4b709f4 3000 info = dev->archdata.iommu;
147202aa
DW		 3001 if (likely(info))
3002 return info->domain;
3003
3004 return __get_valid_domain_for_dev(dev);
3005}
3006
ecb509ec 3007/* Check if the dev needs to go through non-identity map and unmap process.*/
73676832 3008static int iommu_no_mapping(struct device *dev)
2c2e2c38
FY		 3009{
3010 int found;
3011
3d89194a 3012 if (iommu_dummy(dev))
1e4c64c4
DW		 3013 return 1;
3014
2c2e2c38 3015 if (!iommu_identity_mapping)
1e4c64c4 3016 return 0;
2c2e2c38 3017
9b226624 3018 found = identity_mapping(dev);
2c2e2c38 3019 if (found) {
ecb509ec 3020 if (iommu_should_identity_map(dev, 0))
2c2e2c38
FY		 3021 return 1;
3022 else {
3023 /*
3024 * 32 bit DMA is removed from si_domain and fall back
3025 * to non-identity mapping.
3026 */
bf9c9eda 3027 domain_remove_one_dev_info(si_domain, dev);
9f10e5bf
JR		 3028 pr_info("32bit %s uses non-identity mapping\n",
3029 dev_name(dev));
2c2e2c38
FY		 3030 return 0;
3031 }
3032 } else {
3033 /*
3034 * In case of a detached 64 bit DMA device from vm, the device
3035 * is put into si_domain for identity mapping.
3036 */
ecb509ec 3037 if (iommu_should_identity_map(dev, 0)) {
2c2e2c38 3038 int ret;
5913c9bf 3039 ret = domain_add_dev_info(si_domain, dev,
5fe60f4e
DW		 3040 hw_pass_through ?
3041 CONTEXT_TT_PASS_THROUGH :
3042 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38 3043 if (!ret) {
9f10e5bf
JR		 3044 pr_info("64bit %s uses identity mapping\n",
3045 dev_name(dev));
2c2e2c38
FY		 3046 return 1;
3047 }
3048 }
3049 }
3050
1e4c64c4 3051 return 0;
2c2e2c38
FY		 3052}
3053
5040a918 3054static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
bb9e6d65 3055 size_t size, int dir, u64 dma_mask)
f76aec76 3056{
f76aec76 3057 struct dmar_domain *domain;
5b6985ce 3058 phys_addr_t start_paddr;
f76aec76
KA		 3059 struct iova *iova;
3060 int prot = 0;
6865f0d1 3061 int ret;
8c11e798 3062 struct intel_iommu *iommu;
33041ec0 3063 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 3064
3065 BUG_ON(dir == DMA_NONE);
2c2e2c38 3066
5040a918 3067 if (iommu_no_mapping(dev))
6865f0d1 3068 return paddr;
f76aec76 3069
5040a918 3070 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3071 if (!domain)
3072 return 0;
3073
8c11e798 3074 iommu = domain_get_iommu(domain);
88cb6a74 3075 size = aligned_nrpages(paddr, size);
f76aec76 3076
5040a918 3077 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 3078 if (!iova)
3079 goto error;
3080
ba395927
KA		 3081 /*
3082 * Check if DMAR supports zero-length reads on write only
3083 * mappings..
3084 */
3085 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3086 !cap_zlr(iommu->cap))
ba395927
KA		 3087 prot |= DMA_PTE_READ;
3088 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3089 prot |= DMA_PTE_WRITE;
3090 /*
6865f0d1 3091 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 3092 * page. Note: if two part of one page are separately mapped, we
6865f0d1 3093 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 3094 * is not a big problem
3095 */
0ab36de2 3096 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 3097 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 3098 if (ret)
3099 goto error;
3100
1f0ef2aa
DW		 3101 /* it's a non-present to present mapping. Only flush if caching mode */
3102 if (cap_caching_mode(iommu->cap))
ea8ea460 3103 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 3104 else
8c11e798 3105 iommu_flush_write_buffer(iommu);
f76aec76 3106
03d6a246
DW		 3107 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3108 start_paddr += paddr & ~PAGE_MASK;
3109 return start_paddr;
ba395927 3110
ba395927 3111error:
f76aec76
KA		 3112 if (iova)
3113 __free_iova(&domain->iovad, iova);
9f10e5bf 3114 pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
5040a918 3115 dev_name(dev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3116 return 0;
3117}
3118
ffbbef5c
FT		 3119static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3120 unsigned long offset, size_t size,
3121 enum dma_data_direction dir,
3122 struct dma_attrs *attrs)
bb9e6d65 3123{
ffbbef5c 3124 return __intel_map_single(dev, page_to_phys(page) + offset, size,
46333e37 3125 dir, *dev->dma_mask);
bb9e6d65
FT		 3126}
3127
5e0d2a6f 3128static void flush_unmaps(void)
3129{
80b20dd8 3130 int i, j;
5e0d2a6f 3131
5e0d2a6f 3132 timer_on = 0;
3133
3134 /* just flush them all */
3135 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3136 struct intel_iommu *iommu = g_iommus[i];
3137 if (!iommu)
3138 continue;
c42d9f32 3139
9dd2fe89
YZ		 3140 if (!deferred_flush[i].next)
3141 continue;
3142
78d5f0f5
NA		 3143 /* In caching mode, global flushes turn emulation expensive */
3144 if (!cap_caching_mode(iommu->cap))
3145 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3146 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3147 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3148 unsigned long mask;
3149 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3150 struct dmar_domain *domain = deferred_flush[i].domain[j];
3151
3152 /* On real hardware multiple invalidations are expensive */
3153 if (cap_caching_mode(iommu->cap))
3154 iommu_flush_iotlb_psi(iommu, domain->id,
a156ef99 3155 iova->pfn_lo, iova_size(iova),
ea8ea460 3156 !deferred_flush[i].freelist[j], 0);
78d5f0f5 3157 else {
a156ef99 3158 mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
78d5f0f5
NA		 3159 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3160 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3161 }
93a23a72 3162 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3163 if (deferred_flush[i].freelist[j])
3164 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3165 }
9dd2fe89 3166 deferred_flush[i].next = 0;
5e0d2a6f 3167 }
3168
5e0d2a6f 3169 list_size = 0;
5e0d2a6f 3170}
3171
3172static void flush_unmaps_timeout(unsigned long data)
3173{
80b20dd8 3174 unsigned long flags;
3175
3176 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3177 flush_unmaps();
80b20dd8 3178 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3179}
3180
ea8ea460 3181static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3182{
3183 unsigned long flags;
80b20dd8 3184 int next, iommu_id;
8c11e798 3185 struct intel_iommu *iommu;
5e0d2a6f 3186
3187 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3188 if (list_size == HIGH_WATER_MARK)
3189 flush_unmaps();
3190
8c11e798
WH		 3191 iommu = domain_get_iommu(dom);
3192 iommu_id = iommu->seq_id;
c42d9f32 3193
80b20dd8 3194 next = deferred_flush[iommu_id].next;
3195 deferred_flush[iommu_id].domain[next] = dom;
3196 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3197 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3198 deferred_flush[iommu_id].next++;
5e0d2a6f 3199
3200 if (!timer_on) {
3201 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3202 timer_on = 1;
3203 }
3204 list_size++;
3205 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3206}
3207
d41a4adb 3208static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
ba395927 3209{
f76aec76 3210 struct dmar_domain *domain;
d794dc9b 3211 unsigned long start_pfn, last_pfn;
ba395927 3212 struct iova *iova;
8c11e798 3213 struct intel_iommu *iommu;
ea8ea460 3214 struct page *freelist;
ba395927 3215
73676832 3216 if (iommu_no_mapping(dev))
f76aec76 3217 return;
2c2e2c38 3218
1525a29a 3219 domain = find_domain(dev);
ba395927
KA		 3220 BUG_ON(!domain);
3221
8c11e798
WH		 3222 iommu = domain_get_iommu(domain);
3223
ba395927 3224 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3225 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3226 (unsigned long long)dev_addr))
ba395927 3227 return;
ba395927 3228
d794dc9b
DW		 3229 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3230 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3231
d794dc9b 3232 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
207e3592 3233 dev_name(dev), start_pfn, last_pfn);
ba395927 3234
ea8ea460 3235 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3236
5e0d2a6f 3237 if (intel_iommu_strict) {
03d6a246 3238 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3239 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3240 /* free iova */
3241 __free_iova(&domain->iovad, iova);
ea8ea460 3242 dma_free_pagelist(freelist);
5e0d2a6f 3243 } else {
ea8ea460 3244 add_unmap(domain, iova, freelist);
5e0d2a6f 3245 /*
3246 * queue up the release of the unmap to save the 1/6th of the
3247 * cpu used up by the iotlb flush operation...
3248 */
5e0d2a6f 3249 }
ba395927
KA		 3250}
3251
d41a4adb
JL		 3252static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3253 size_t size, enum dma_data_direction dir,
3254 struct dma_attrs *attrs)
3255{
3256 intel_unmap(dev, dev_addr);
3257}
3258
5040a918 3259static void *intel_alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 3260 dma_addr_t *dma_handle, gfp_t flags,
3261 struct dma_attrs *attrs)
ba395927 3262{
36746436 3263 struct page *page = NULL;
ba395927
KA		 3264 int order;
3265
5b6985ce 3266 size = PAGE_ALIGN(size);
ba395927 3267 order = get_order(size);
e8bb910d 3268
5040a918 3269 if (!iommu_no_mapping(dev))
e8bb910d 3270 flags &= ~(GFP_DMA | GFP_DMA32);
5040a918
DW		 3271 else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3272 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
e8bb910d
AW		 3273 flags |= GFP_DMA;
3274 else
3275 flags |= GFP_DMA32;
3276 }
ba395927 3277
36746436
AM		 3278 if (flags & __GFP_WAIT) {
3279 unsigned int count = size >> PAGE_SHIFT;
3280
3281 page = dma_alloc_from_contiguous(dev, count, order);
3282 if (page && iommu_no_mapping(dev) &&
3283 page_to_phys(page) + size > dev->coherent_dma_mask) {
3284 dma_release_from_contiguous(dev, page, count);
3285 page = NULL;
3286 }
3287 }
3288
3289 if (!page)
3290 page = alloc_pages(flags, order);
3291 if (!page)
ba395927 3292 return NULL;
36746436 3293 memset(page_address(page), 0, size);
ba395927 3294
36746436 3295 *dma_handle = __intel_map_single(dev, page_to_phys(page), size,
bb9e6d65 3296 DMA_BIDIRECTIONAL,
5040a918 3297 dev->coherent_dma_mask);
ba395927 3298 if (*dma_handle)
36746436
AM		 3299 return page_address(page);
3300 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3301 __free_pages(page, order);
3302
ba395927
KA		 3303 return NULL;
3304}
3305
5040a918 3306static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
baa676fc 3307 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3308{
3309 int order;
36746436 3310 struct page *page = virt_to_page(vaddr);
ba395927 3311
5b6985ce 3312 size = PAGE_ALIGN(size);
ba395927
KA		 3313 order = get_order(size);
3314
d41a4adb 3315 intel_unmap(dev, dma_handle);
36746436
AM		 3316 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3317 __free_pages(page, order);
ba395927
KA		 3318}
3319
5040a918 3320static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
d7ab5c46
FT		 3321 int nelems, enum dma_data_direction dir,
3322 struct dma_attrs *attrs)
ba395927 3323{
d41a4adb 3324 intel_unmap(dev, sglist[0].dma_address);
ba395927
KA		 3325}
3326
ba395927 3327static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3328 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3329{
3330 int i;
c03ab37c 3331 struct scatterlist *sg;
ba395927 3332
c03ab37c 3333 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3334 BUG_ON(!sg_page(sg));
4cf2e75d 3335 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3336 sg->dma_length = sg->length;
ba395927
KA		 3337 }
3338 return nelems;
3339}
3340
5040a918 3341static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
d7ab5c46 3342 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3343{
ba395927 3344 int i;
ba395927 3345 struct dmar_domain *domain;
f76aec76
KA		 3346 size_t size = 0;
3347 int prot = 0;
f76aec76
KA		 3348 struct iova *iova = NULL;
3349 int ret;
c03ab37c 3350 struct scatterlist *sg;
b536d24d 3351 unsigned long start_vpfn;
8c11e798 3352 struct intel_iommu *iommu;
ba395927
KA		 3353
3354 BUG_ON(dir == DMA_NONE);
5040a918
DW		 3355 if (iommu_no_mapping(dev))
3356 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
ba395927 3357
5040a918 3358 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3359 if (!domain)
3360 return 0;
3361
8c11e798
WH		 3362 iommu = domain_get_iommu(domain);
3363
b536d24d 3364 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3365 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3366
5040a918
DW		 3367 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3368 *dev->dma_mask);
f76aec76 3369 if (!iova) {
c03ab37c 3370 sglist->dma_length = 0;
f76aec76
KA		 3371 return 0;
3372 }
3373
3374 /*
3375 * Check if DMAR supports zero-length reads on write only
3376 * mappings..
3377 */
3378 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3379 !cap_zlr(iommu->cap))
f76aec76
KA		 3380 prot |= DMA_PTE_READ;
3381 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3382 prot |= DMA_PTE_WRITE;
3383
b536d24d 3384 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3385
f532959b 3386 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495 3387 if (unlikely(ret)) {
e1605495
DW		 3388 dma_pte_free_pagetable(domain, start_vpfn,
3389 start_vpfn + size - 1);
e1605495
DW		 3390 __free_iova(&domain->iovad, iova);
3391 return 0;
ba395927
KA		 3392 }
3393
1f0ef2aa
DW		 3394 /* it's a non-present to present mapping. Only flush if caching mode */
3395 if (cap_caching_mode(iommu->cap))
ea8ea460 3396 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3397 else
8c11e798 3398 iommu_flush_write_buffer(iommu);
1f0ef2aa 3399
ba395927
KA		 3400 return nelems;
3401}
3402
dfb805e8
FT		 3403static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3404{
3405 return !dma_addr;
3406}
3407
160c1d8e 3408struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3409 .alloc = intel_alloc_coherent,
3410 .free = intel_free_coherent,
ba395927
KA		 3411 .map_sg = intel_map_sg,
3412 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3413 .map_page = intel_map_page,
3414 .unmap_page = intel_unmap_page,
dfb805e8 3415 .mapping_error = intel_mapping_error,
ba395927
KA		 3416};
3417
3418static inline int iommu_domain_cache_init(void)
3419{
3420 int ret = 0;
3421
3422 iommu_domain_cache = kmem_cache_create("iommu_domain",
3423 sizeof(struct dmar_domain),
3424 0,
3425 SLAB_HWCACHE_ALIGN,
3426
3427 NULL);
3428 if (!iommu_domain_cache) {
9f10e5bf 3429 pr_err("Couldn't create iommu_domain cache\n");
ba395927
KA		 3430 ret = -ENOMEM;
3431 }
3432
3433 return ret;
3434}
3435
3436static inline int iommu_devinfo_cache_init(void)
3437{
3438 int ret = 0;
3439
3440 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3441 sizeof(struct device_domain_info),
3442 0,
3443 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3444 NULL);
3445 if (!iommu_devinfo_cache) {
9f10e5bf 3446 pr_err("Couldn't create devinfo cache\n");
ba395927
KA		 3447 ret = -ENOMEM;
3448 }
3449
3450 return ret;
3451}
3452
ba395927
KA		 3453static int __init iommu_init_mempool(void)
3454{
3455 int ret;
3456 ret = iommu_iova_cache_init();
3457 if (ret)
3458 return ret;
3459
3460 ret = iommu_domain_cache_init();
3461 if (ret)
3462 goto domain_error;
3463
3464 ret = iommu_devinfo_cache_init();
3465 if (!ret)
3466 return ret;
3467
3468 kmem_cache_destroy(iommu_domain_cache);
3469domain_error:
85b45456 3470 iommu_iova_cache_destroy();
ba395927
KA		 3471
3472 return -ENOMEM;
3473}
3474
3475static void __init iommu_exit_mempool(void)
3476{
3477 kmem_cache_destroy(iommu_devinfo_cache);
3478 kmem_cache_destroy(iommu_domain_cache);
85b45456 3479 iommu_iova_cache_destroy();
ba395927
KA		 3480}
3481
556ab45f
DW		 3482static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3483{
3484 struct dmar_drhd_unit *drhd;
3485 u32 vtbar;
3486 int rc;
3487
3488 /* We know that this device on this chipset has its own IOMMU.
3489 * If we find it under a different IOMMU, then the BIOS is lying
3490 * to us. Hope that the IOMMU for this device is actually
3491 * disabled, and it needs no translation...
3492 */
3493 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3494 if (rc) {
3495 /* "can't" happen */
3496 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3497 return;
3498 }
3499 vtbar &= 0xffff0000;
3500
3501 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3502 drhd = dmar_find_matched_drhd_unit(pdev);
3503 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3504 TAINT_FIRMWARE_WORKAROUND,
3505 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3506 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3507}
3508DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3509
ba395927
KA		 3510static void __init init_no_remapping_devices(void)
3511{
3512 struct dmar_drhd_unit *drhd;
832bd858 3513 struct device *dev;
b683b230 3514 int i;
ba395927
KA		 3515
3516 for_each_drhd_unit(drhd) {
3517 if (!drhd->include_all) {
b683b230
JL		 3518 for_each_active_dev_scope(drhd->devices,
3519 drhd->devices_cnt, i, dev)
3520 break;
832bd858 3521 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3522 if (i == drhd->devices_cnt)
3523 drhd->ignored = 1;
3524 }
3525 }
3526
7c919779 3527 for_each_active_drhd_unit(drhd) {
7c919779 3528 if (drhd->include_all)
ba395927
KA		 3529 continue;
3530
b683b230
JL		 3531 for_each_active_dev_scope(drhd->devices,
3532 drhd->devices_cnt, i, dev)
832bd858 3533 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3534 break;
ba395927
KA		 3535 if (i < drhd->devices_cnt)
3536 continue;
3537
c0771df8
DW		 3538 /* This IOMMU has *only* gfx devices. Either bypass it or
3539 set the gfx_mapped flag, as appropriate */
3540 if (dmar_map_gfx) {
3541 intel_iommu_gfx_mapped = 1;
3542 } else {
3543 drhd->ignored = 1;
b683b230
JL		 3544 for_each_active_dev_scope(drhd->devices,
3545 drhd->devices_cnt, i, dev)
832bd858 3546 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3547 }
3548 }
3549}
3550
f59c7b69
FY		 3551#ifdef CONFIG_SUSPEND
3552static int init_iommu_hw(void)
3553{
3554 struct dmar_drhd_unit *drhd;
3555 struct intel_iommu *iommu = NULL;
3556
3557 for_each_active_iommu(iommu, drhd)
3558 if (iommu->qi)
3559 dmar_reenable_qi(iommu);
3560
b779260b
JC		 3561 for_each_iommu(iommu, drhd) {
3562 if (drhd->ignored) {
3563 /*
3564 * we always have to disable PMRs or DMA may fail on
3565 * this device
3566 */
3567 if (force_on)
3568 iommu_disable_protect_mem_regions(iommu);
3569 continue;
3570 }
3571
f59c7b69
FY		 3572 iommu_flush_write_buffer(iommu);
3573
3574 iommu_set_root_entry(iommu);
3575
3576 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3577 DMA_CCMD_GLOBAL_INVL);
2a41ccee
JL		 3578 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3579 iommu_enable_translation(iommu);
b94996c9 3580 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3581 }
3582
3583 return 0;
3584}
3585
3586static void iommu_flush_all(void)
3587{
3588 struct dmar_drhd_unit *drhd;
3589 struct intel_iommu *iommu;
3590
3591 for_each_active_iommu(iommu, drhd) {
3592 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3593 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3594 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3595 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3596 }
3597}
3598
134fac3f 3599static int iommu_suspend(void)
f59c7b69
FY		 3600{
3601 struct dmar_drhd_unit *drhd;
3602 struct intel_iommu *iommu = NULL;
3603 unsigned long flag;
3604
3605 for_each_active_iommu(iommu, drhd) {
3606 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3607 GFP_ATOMIC);
3608 if (!iommu->iommu_state)
3609 goto nomem;
3610 }
3611
3612 iommu_flush_all();
3613
3614 for_each_active_iommu(iommu, drhd) {
3615 iommu_disable_translation(iommu);
3616
1f5b3c3f 3617 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3618
3619 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3620 readl(iommu->reg + DMAR_FECTL_REG);
3621 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3622 readl(iommu->reg + DMAR_FEDATA_REG);
3623 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3624 readl(iommu->reg + DMAR_FEADDR_REG);
3625 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3626 readl(iommu->reg + DMAR_FEUADDR_REG);
3627
1f5b3c3f 3628 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3629 }
3630 return 0;
3631
3632nomem:
3633 for_each_active_iommu(iommu, drhd)
3634 kfree(iommu->iommu_state);
3635
3636 return -ENOMEM;
3637}
3638
134fac3f 3639static void iommu_resume(void)
f59c7b69
FY		 3640{
3641 struct dmar_drhd_unit *drhd;
3642 struct intel_iommu *iommu = NULL;
3643 unsigned long flag;
3644
3645 if (init_iommu_hw()) {
b779260b
JC		 3646 if (force_on)
3647 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3648 else
3649 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3650 return;
f59c7b69
FY		 3651 }
3652
3653 for_each_active_iommu(iommu, drhd) {
3654
1f5b3c3f 3655 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3656
3657 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3658 iommu->reg + DMAR_FECTL_REG);
3659 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3660 iommu->reg + DMAR_FEDATA_REG);
3661 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3662 iommu->reg + DMAR_FEADDR_REG);
3663 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3664 iommu->reg + DMAR_FEUADDR_REG);
3665
1f5b3c3f 3666 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3667 }
3668
3669 for_each_active_iommu(iommu, drhd)
3670 kfree(iommu->iommu_state);
f59c7b69
FY		 3671}
3672
134fac3f 3673static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3674 .resume = iommu_resume,
3675 .suspend = iommu_suspend,
3676};
3677
134fac3f 3678static void __init init_iommu_pm_ops(void)
f59c7b69 3679{
134fac3f 3680 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3681}
3682
3683#else
99592ba4 3684static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3685#endif /* CONFIG_PM */
3686
318fe7df 3687
c2a0b538 3688int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
318fe7df
SS		 3689{
3690 struct acpi_dmar_reserved_memory *rmrr;
3691 struct dmar_rmrr_unit *rmrru;
3692
3693 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3694 if (!rmrru)
3695 return -ENOMEM;
3696
3697 rmrru->hdr = header;
3698 rmrr = (struct acpi_dmar_reserved_memory *)header;
3699 rmrru->base_address = rmrr->base_address;
3700 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3701 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3702 ((void *)rmrr) + rmrr->header.length,
3703 &rmrru->devices_cnt);
3704 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3705 kfree(rmrru);
3706 return -ENOMEM;
3707 }
318fe7df 3708
2e455289 3709 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3710
2e455289 3711 return 0;
318fe7df
SS		 3712}
3713
6b197249
JL		 3714static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
3715{
3716 struct dmar_atsr_unit *atsru;
3717 struct acpi_dmar_atsr *tmp;
3718
3719 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3720 tmp = (struct acpi_dmar_atsr *)atsru->hdr;
3721 if (atsr->segment != tmp->segment)
3722 continue;
3723 if (atsr->header.length != tmp->header.length)
3724 continue;
3725 if (memcmp(atsr, tmp, atsr->header.length) == 0)
3726 return atsru;
3727 }
3728
3729 return NULL;
3730}
3731
3732int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
318fe7df
SS		 3733{
3734 struct acpi_dmar_atsr *atsr;
3735 struct dmar_atsr_unit *atsru;
3736
6b197249
JL		 3737 if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
3738 return 0;
3739
318fe7df 3740 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
6b197249
JL		 3741 atsru = dmar_find_atsr(atsr);
3742 if (atsru)
3743 return 0;
3744
3745 atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
318fe7df
SS		 3746 if (!atsru)
3747 return -ENOMEM;
3748
6b197249
JL		 3749 /*
3750 * If memory is allocated from slab by ACPI _DSM method, we need to
3751 * copy the memory content because the memory buffer will be freed
3752 * on return.
3753 */
3754 atsru->hdr = (void *)(atsru + 1);
3755 memcpy(atsru->hdr, hdr, hdr->length);
318fe7df 3756 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3757 if (!atsru->include_all) {
3758 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3759 (void *)atsr + atsr->header.length,
3760 &atsru->devices_cnt);
3761 if (atsru->devices_cnt && atsru->devices == NULL) {
3762 kfree(atsru);
3763 return -ENOMEM;
3764 }
3765 }
318fe7df 3766
0e242612 3767 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3768
3769 return 0;
3770}
3771
9bdc531e
JL		 3772static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3773{
3774 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3775 kfree(atsru);
3776}
3777
6b197249
JL		 3778int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
3779{
3780 struct acpi_dmar_atsr *atsr;
3781 struct dmar_atsr_unit *atsru;
3782
3783 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3784 atsru = dmar_find_atsr(atsr);
3785 if (atsru) {
3786 list_del_rcu(&atsru->list);
3787 synchronize_rcu();
3788 intel_iommu_free_atsr(atsru);
3789 }
3790
3791 return 0;
3792}
3793
3794int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
3795{
3796 int i;
3797 struct device *dev;
3798 struct acpi_dmar_atsr *atsr;
3799 struct dmar_atsr_unit *atsru;
3800
3801 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3802 atsru = dmar_find_atsr(atsr);
3803 if (!atsru)
3804 return 0;
3805
3806 if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
3807 for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
3808 i, dev)
3809 return -EBUSY;
3810
3811 return 0;
3812}
3813
ffebeb46
JL		 3814static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
3815{
3816 int sp, ret = 0;
3817 struct intel_iommu *iommu = dmaru->iommu;
3818
3819 if (g_iommus[iommu->seq_id])
3820 return 0;
3821
3822 if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
9f10e5bf 3823 pr_warn("%s: Doesn't support hardware pass through.\n",
ffebeb46
JL		 3824 iommu->name);
3825 return -ENXIO;
3826 }
3827 if (!ecap_sc_support(iommu->ecap) &&
3828 domain_update_iommu_snooping(iommu)) {
9f10e5bf 3829 pr_warn("%s: Doesn't support snooping.\n",
ffebeb46
JL		 3830 iommu->name);
3831 return -ENXIO;
3832 }
3833 sp = domain_update_iommu_superpage(iommu) - 1;
3834 if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
9f10e5bf 3835 pr_warn("%s: Doesn't support large page.\n",
ffebeb46
JL		 3836 iommu->name);
3837 return -ENXIO;
3838 }
3839
3840 /*
3841 * Disable translation if already enabled prior to OS handover.
3842 */
3843 if (iommu->gcmd & DMA_GCMD_TE)
3844 iommu_disable_translation(iommu);
3845
3846 g_iommus[iommu->seq_id] = iommu;
3847 ret = iommu_init_domains(iommu);
3848 if (ret == 0)
3849 ret = iommu_alloc_root_entry(iommu);
3850 if (ret)
3851 goto out;
3852
3853 if (dmaru->ignored) {
3854 /*
3855 * we always have to disable PMRs or DMA may fail on this device
3856 */
3857 if (force_on)
3858 iommu_disable_protect_mem_regions(iommu);
3859 return 0;
3860 }
3861
3862 intel_iommu_init_qi(iommu);
3863 iommu_flush_write_buffer(iommu);
3864 ret = dmar_set_interrupt(iommu);
3865 if (ret)
3866 goto disable_iommu;
3867
3868 iommu_set_root_entry(iommu);
3869 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3870 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3871 iommu_enable_translation(iommu);
3872
3873 if (si_domain) {
3874 ret = iommu_attach_domain(si_domain, iommu);
3875 if (ret < 0 || si_domain->id != ret)
3876 goto disable_iommu;
3877 domain_attach_iommu(si_domain, iommu);
3878 }
3879
3880 iommu_disable_protect_mem_regions(iommu);
3881 return 0;
3882
3883disable_iommu:
3884 disable_dmar_iommu(iommu);
3885out:
3886 free_dmar_iommu(iommu);
3887 return ret;
3888}
3889
6b197249
JL		 3890int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
3891{
ffebeb46
JL		 3892 int ret = 0;
3893 struct intel_iommu *iommu = dmaru->iommu;
3894
3895 if (!intel_iommu_enabled)
3896 return 0;
3897 if (iommu == NULL)
3898 return -EINVAL;
3899
3900 if (insert) {
3901 ret = intel_iommu_add(dmaru);
3902 } else {
3903 disable_dmar_iommu(iommu);
3904 free_dmar_iommu(iommu);
3905 }
3906
3907 return ret;
6b197249
JL		 3908}
3909
9bdc531e
JL		 3910static void intel_iommu_free_dmars(void)
3911{
3912 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3913 struct dmar_atsr_unit *atsru, *atsr_n;
3914
3915 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3916 list_del(&rmrru->list);
3917 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3918 kfree(rmrru);
318fe7df
SS		 3919 }
3920
9bdc531e
JL		 3921 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3922 list_del(&atsru->list);
3923 intel_iommu_free_atsr(atsru);
3924 }
318fe7df
SS		 3925}
3926
3927int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3928{
b683b230 3929 int i, ret = 1;
318fe7df 3930 struct pci_bus *bus;
832bd858
DW		 3931 struct pci_dev *bridge = NULL;
3932 struct device *tmp;
318fe7df
SS		 3933 struct acpi_dmar_atsr *atsr;
3934 struct dmar_atsr_unit *atsru;
3935
3936 dev = pci_physfn(dev);
318fe7df 3937 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3938 bridge = bus->self;
318fe7df 3939 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3940 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3941 return 0;
b5f82ddf 3942 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3943 break;
318fe7df 3944 }
b5f82ddf
JL		 3945 if (!bridge)
3946 return 0;
318fe7df 3947
0e242612 3948 rcu_read_lock();
b5f82ddf
JL		 3949 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3950 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3951 if (atsr->segment != pci_domain_nr(dev->bus))
3952 continue;
3953
b683b230 3954 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 3955 if (tmp == &bridge->dev)
b683b230 3956 goto out;
b5f82ddf
JL		 3957
3958 if (atsru->include_all)
b683b230 3959 goto out;
b5f82ddf 3960 }
b683b230
JL		 3961 ret = 0;
3962out:
0e242612 3963 rcu_read_unlock();
318fe7df 3964
b683b230 3965 return ret;
318fe7df
SS		 3966}
3967
59ce0515
JL		 3968int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3969{
3970 int ret = 0;
3971 struct dmar_rmrr_unit *rmrru;
3972 struct dmar_atsr_unit *atsru;
3973 struct acpi_dmar_atsr *atsr;
3974 struct acpi_dmar_reserved_memory *rmrr;
3975
3976 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3977 return 0;
3978
3979 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3980 rmrr = container_of(rmrru->hdr,
3981 struct acpi_dmar_reserved_memory, header);
3982 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3983 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3984 ((void *)rmrr) + rmrr->header.length,
3985 rmrr->segment, rmrru->devices,
3986 rmrru->devices_cnt);
27e24950 3987 if(ret < 0)
59ce0515
JL		 3988 return ret;
3989 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
27e24950
JL		 3990 dmar_remove_dev_scope(info, rmrr->segment,
3991 rmrru->devices, rmrru->devices_cnt);
59ce0515
JL		 3992 }
3993 }
3994
3995 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3996 if (atsru->include_all)
3997 continue;
3998
3999 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4000 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4001 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
4002 (void *)atsr + atsr->header.length,
4003 atsr->segment, atsru->devices,
4004 atsru->devices_cnt);
4005 if (ret > 0)
4006 break;
4007 else if(ret < 0)
4008 return ret;
4009 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4010 if (dmar_remove_dev_scope(info, atsr->segment,
4011 atsru->devices, atsru->devices_cnt))
4012 break;
4013 }
4014 }
4015
4016 return 0;
4017}
4018
99dcaded
FY		 4019/*
4020 * Here we only respond to action of unbound device from driver.
4021 *
4022 * Added device is not attached to its DMAR domain here yet. That will happen
4023 * when mapping the device to iova.
4024 */
4025static int device_notifier(struct notifier_block *nb,
4026 unsigned long action, void *data)
4027{
4028 struct device *dev = data;
99dcaded
FY		 4029 struct dmar_domain *domain;
4030
3d89194a 4031 if (iommu_dummy(dev))
44cd613c
DW		 4032 return 0;
4033
1196c2fb 4034 if (action != BUS_NOTIFY_REMOVED_DEVICE)
7e7dfab7
JL		 4035 return 0;
4036
1525a29a 4037 domain = find_domain(dev);
99dcaded
FY		 4038 if (!domain)
4039 return 0;
4040
3a5670e8 4041 down_read(&dmar_global_lock);
bf9c9eda 4042 domain_remove_one_dev_info(domain, dev);
ab8dfe25 4043 if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
7e7dfab7 4044 domain_exit(domain);
3a5670e8 4045 up_read(&dmar_global_lock);
a97590e5 4046
99dcaded
FY		 4047 return 0;
4048}
4049
4050static struct notifier_block device_nb = {
4051 .notifier_call = device_notifier,
4052};
4053
75f05569
JL		 4054static int intel_iommu_memory_notifier(struct notifier_block *nb,
4055 unsigned long val, void *v)
4056{
4057 struct memory_notify *mhp = v;
4058 unsigned long long start, end;
4059 unsigned long start_vpfn, last_vpfn;
4060
4061 switch (val) {
4062 case MEM_GOING_ONLINE:
4063 start = mhp->start_pfn << PAGE_SHIFT;
4064 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
4065 if (iommu_domain_identity_map(si_domain, start, end)) {
9f10e5bf 4066 pr_warn("Failed to build identity map for [%llx-%llx]\n",
75f05569
JL		 4067 start, end);
4068 return NOTIFY_BAD;
4069 }
4070 break;
4071
4072 case MEM_OFFLINE:
4073 case MEM_CANCEL_ONLINE:
4074 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
4075 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
4076 while (start_vpfn <= last_vpfn) {
4077 struct iova *iova;
4078 struct dmar_drhd_unit *drhd;
4079 struct intel_iommu *iommu;
ea8ea460 4080 struct page *freelist;
75f05569
JL		 4081
4082 iova = find_iova(&si_domain->iovad, start_vpfn);
4083 if (iova == NULL) {
9f10e5bf 4084 pr_debug("Failed get IOVA for PFN %lx\n",
75f05569
JL		 4085 start_vpfn);
4086 break;
4087 }
4088
4089 iova = split_and_remove_iova(&si_domain->iovad, iova,
4090 start_vpfn, last_vpfn);
4091 if (iova == NULL) {
9f10e5bf 4092 pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
75f05569
JL		 4093 start_vpfn, last_vpfn);
4094 return NOTIFY_BAD;
4095 }
4096
ea8ea460
DW		 4097 freelist = domain_unmap(si_domain, iova->pfn_lo,
4098 iova->pfn_hi);
4099
75f05569
JL		 4100 rcu_read_lock();
4101 for_each_active_iommu(iommu, drhd)
4102 iommu_flush_iotlb_psi(iommu, si_domain->id,
a156ef99 4103 iova->pfn_lo, iova_size(iova),
ea8ea460 4104 !freelist, 0);
75f05569 4105 rcu_read_unlock();
ea8ea460 4106 dma_free_pagelist(freelist);
75f05569
JL		 4107
4108 start_vpfn = iova->pfn_hi + 1;
4109 free_iova_mem(iova);
4110 }
4111 break;
4112 }
4113
4114 return NOTIFY_OK;
4115}
4116
4117static struct notifier_block intel_iommu_memory_nb = {
4118 .notifier_call = intel_iommu_memory_notifier,
4119 .priority = 0
4120};
4121
a5459cfe
AW		 4122
4123static ssize_t intel_iommu_show_version(struct device *dev,
4124 struct device_attribute *attr,
4125 char *buf)
4126{
4127 struct intel_iommu *iommu = dev_get_drvdata(dev);
4128 u32 ver = readl(iommu->reg + DMAR_VER_REG);
4129 return sprintf(buf, "%d:%d\n",
4130 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
4131}
4132static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
4133
4134static ssize_t intel_iommu_show_address(struct device *dev,
4135 struct device_attribute *attr,
4136 char *buf)
4137{
4138 struct intel_iommu *iommu = dev_get_drvdata(dev);
4139 return sprintf(buf, "%llx\n", iommu->reg_phys);
4140}
4141static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
4142
4143static ssize_t intel_iommu_show_cap(struct device *dev,
4144 struct device_attribute *attr,
4145 char *buf)
4146{
4147 struct intel_iommu *iommu = dev_get_drvdata(dev);
4148 return sprintf(buf, "%llx\n", iommu->cap);
4149}
4150static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
4151
4152static ssize_t intel_iommu_show_ecap(struct device *dev,
4153 struct device_attribute *attr,
4154 char *buf)
4155{
4156 struct intel_iommu *iommu = dev_get_drvdata(dev);
4157 return sprintf(buf, "%llx\n", iommu->ecap);
4158}
4159static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
4160
4161static struct attribute *intel_iommu_attrs[] = {
4162 &dev_attr_version.attr,
4163 &dev_attr_address.attr,
4164 &dev_attr_cap.attr,
4165 &dev_attr_ecap.attr,
4166 NULL,
4167};
4168
4169static struct attribute_group intel_iommu_group = {
4170 .name = "intel-iommu",
4171 .attrs = intel_iommu_attrs,
4172};
4173
4174const struct attribute_group *intel_iommu_groups[] = {
4175 &intel_iommu_group,
4176 NULL,
4177};
4178
ba395927
KA		 4179int __init intel_iommu_init(void)
4180{
9bdc531e 4181 int ret = -ENODEV;
3a93c841 4182 struct dmar_drhd_unit *drhd;
7c919779 4183 struct intel_iommu *iommu;
ba395927 4184
a59b50e9
JC		 4185 /* VT-d is required for a TXT/tboot launch, so enforce that */
4186 force_on = tboot_force_iommu();
4187
3a5670e8
JL		 4188 if (iommu_init_mempool()) {
4189 if (force_on)
4190 panic("tboot: Failed to initialize iommu memory\n");
4191 return -ENOMEM;
4192 }
4193
4194 down_write(&dmar_global_lock);
a59b50e9
JC		 4195 if (dmar_table_init()) {
4196 if (force_on)
4197 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 4198 goto out_free_dmar;
a59b50e9 4199 }
ba395927 4200
3a93c841
TI		 4201 /*
4202 * Disable translation if already enabled prior to OS handover.
4203 */
7c919779 4204 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 4205 if (iommu->gcmd & DMA_GCMD_TE)
4206 iommu_disable_translation(iommu);
3a93c841 4207
c2c7286a 4208 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 4209 if (force_on)
4210 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 4211 goto out_free_dmar;
a59b50e9 4212 }
1886e8a9 4213
75f1cdf1 4214 if (no_iommu || dmar_disabled)
9bdc531e 4215 goto out_free_dmar;
2ae21010 4216
318fe7df 4217 if (list_empty(&dmar_rmrr_units))
9f10e5bf 4218 pr_info("No RMRR found\n");
318fe7df
SS		 4219
4220 if (list_empty(&dmar_atsr_units))
9f10e5bf 4221 pr_info("No ATSR found\n");
318fe7df 4222
51a63e67
JC		 4223 if (dmar_init_reserved_ranges()) {
4224 if (force_on)
4225 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 4226 goto out_free_reserved_range;
51a63e67 4227 }
ba395927
KA		 4228
4229 init_no_remapping_devices();
4230
b779260b 4231 ret = init_dmars();
ba395927 4232 if (ret) {
a59b50e9
JC		 4233 if (force_on)
4234 panic("tboot: Failed to initialize DMARs\n");
9f10e5bf 4235 pr_err("Initialization failed\n");
9bdc531e 4236 goto out_free_reserved_range;
ba395927 4237 }
3a5670e8 4238 up_write(&dmar_global_lock);
9f10e5bf 4239 pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
ba395927 4240
5e0d2a6f 4241 init_timer(&unmap_timer);
75f1cdf1
FT		 4242#ifdef CONFIG_SWIOTLB
4243 swiotlb = 0;
4244#endif
19943b0e 4245 dma_ops = &intel_dma_ops;
4ed0d3e6 4246
134fac3f 4247 init_iommu_pm_ops();
a8bcbb0d 4248
a5459cfe
AW		 4249 for_each_active_iommu(iommu, drhd)
4250 iommu->iommu_dev = iommu_device_create(NULL, iommu,
4251 intel_iommu_groups,
4252 iommu->name);
4253
4236d97d 4254 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 4255 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 4256 if (si_domain && !hw_pass_through)
4257 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 4258
8bc1f85c
ED		 4259 intel_iommu_enabled = 1;
4260
ba395927 4261 return 0;
9bdc531e
JL		 4262
4263out_free_reserved_range:
4264 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 4265out_free_dmar:
4266 intel_iommu_free_dmars();
3a5670e8
JL		 4267 up_write(&dmar_global_lock);
4268 iommu_exit_mempool();
9bdc531e 4269 return ret;
ba395927 4270}
e820482c 4271
579305f7
AW		 4272static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4273{
4274 struct intel_iommu *iommu = opaque;
4275
4276 iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4277 return 0;
4278}
4279
4280/*
4281 * NB - intel-iommu lacks any sort of reference counting for the users of
4282 * dependent devices. If multiple endpoints have intersecting dependent
4283 * devices, unbinding the driver from any one of them will possibly leave
4284 * the others unable to operate.
4285 */
3199aa6b 4286static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 4287 struct device *dev)
3199aa6b 4288{
0bcb3e28 4289 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 4290 return;
4291
579305f7 4292 pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu);
3199aa6b
HW		 4293}
4294
2c2e2c38 4295static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 4296 struct device *dev)
c7151a8d 4297{
bca2b916 4298 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4299 struct intel_iommu *iommu;
4300 unsigned long flags;
2f119c78 4301 bool found = false;
156baca8 4302 u8 bus, devfn;
c7151a8d 4303
bf9c9eda 4304 iommu = device_to_iommu(dev, &bus, &devfn);
c7151a8d
WH		 4305 if (!iommu)
4306 return;
4307
4308 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4309 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
bf9c9eda
DW		 4310 if (info->iommu == iommu && info->bus == bus &&
4311 info->devfn == devfn) {
109b9b04 4312 unlink_domain_info(info);
c7151a8d
WH		 4313 spin_unlock_irqrestore(&device_domain_lock, flags);
4314
93a23a72 4315 iommu_disable_dev_iotlb(info);
c7151a8d 4316 iommu_detach_dev(iommu, info->bus, info->devfn);
bf9c9eda 4317 iommu_detach_dependent_devices(iommu, dev);
c7151a8d
WH		 4318 free_devinfo_mem(info);
4319
4320 spin_lock_irqsave(&device_domain_lock, flags);
4321
4322 if (found)
4323 break;
4324 else
4325 continue;
4326 }
4327
4328 /* if there is no other devices under the same iommu
4329 * owned by this domain, clear this iommu in iommu_bmp
4330 * update iommu count and coherency
4331 */
8bbc4410 4332 if (info->iommu == iommu)
2f119c78 4333 found = true;
c7151a8d
WH		 4334 }
4335
3e7abe25
RD		 4336 spin_unlock_irqrestore(&device_domain_lock, flags);
4337
c7151a8d 4338 if (found == 0) {
fb170fb4
JL		 4339 domain_detach_iommu(domain, iommu);
4340 if (!domain_type_is_vm_or_si(domain))
4341 iommu_detach_domain(domain, iommu);
c7151a8d 4342 }
c7151a8d
WH		 4343}
4344
2c2e2c38 4345static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4346{
4347 int adjust_width;
4348
0fb5fe87
RM		 4349 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
4350 DMA_32BIT_PFN);
5e98c4b1
WH		 4351 domain_reserve_special_ranges(domain);
4352
4353 /* calculate AGAW */
4354 domain->gaw = guest_width;
4355 adjust_width = guestwidth_to_adjustwidth(guest_width);
4356 domain->agaw = width_to_agaw(adjust_width);
4357
5e98c4b1 4358 domain->iommu_coherency = 0;
c5b15255 4359 domain->iommu_snooping = 0;
6dd9a7c7 4360 domain->iommu_superpage = 0;
fe40f1e0 4361 domain->max_addr = 0;
5e98c4b1
WH		 4362
4363 /* always allocate the top pgd */
4c923d47 4364 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4365 if (!domain->pgd)
4366 return -ENOMEM;
4367 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4368 return 0;
4369}
4370
00a77deb 4371static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
38717946 4372{
5d450806 4373 struct dmar_domain *dmar_domain;
00a77deb
JR		 4374 struct iommu_domain *domain;
4375
4376 if (type != IOMMU_DOMAIN_UNMANAGED)
4377 return NULL;
38717946 4378
ab8dfe25 4379 dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
5d450806 4380 if (!dmar_domain) {
9f10e5bf 4381 pr_err("Can't allocate dmar_domain\n");
00a77deb 4382 return NULL;
38717946 4383 }
2c2e2c38 4384 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
9f10e5bf 4385 pr_err("Domain initialization failed\n");
92d03cc8 4386 domain_exit(dmar_domain);
00a77deb 4387 return NULL;
38717946 4388 }
8140a95d 4389 domain_update_iommu_cap(dmar_domain);
faa3d6f5 4390
00a77deb 4391 domain = &dmar_domain->domain;
8a0e715b
JR		 4392 domain->geometry.aperture_start = 0;
4393 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4394 domain->geometry.force_aperture = true;
4395
00a77deb 4396 return domain;
38717946 4397}
38717946 4398
00a77deb 4399static void intel_iommu_domain_free(struct iommu_domain *domain)
38717946 4400{
00a77deb 4401 domain_exit(to_dmar_domain(domain));
38717946 4402}
38717946 4403
4c5478c9
JR		 4404static int intel_iommu_attach_device(struct iommu_domain *domain,
4405 struct device *dev)
38717946 4406{
00a77deb 4407 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
fe40f1e0
WH		 4408 struct intel_iommu *iommu;
4409 int addr_width;
156baca8 4410 u8 bus, devfn;
faa3d6f5 4411
c875d2c1
AW		 4412 if (device_is_rmrr_locked(dev)) {
4413 dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n");
4414 return -EPERM;
4415 }
4416
7207d8f9
DW		 4417 /* normally dev is not mapped */
4418 if (unlikely(domain_context_mapped(dev))) {
faa3d6f5
WH		 4419 struct dmar_domain *old_domain;
4420
1525a29a 4421 old_domain = find_domain(dev);
faa3d6f5 4422 if (old_domain) {
ab8dfe25 4423 if (domain_type_is_vm_or_si(dmar_domain))
bf9c9eda 4424 domain_remove_one_dev_info(old_domain, dev);
faa3d6f5
WH		 4425 else
4426 domain_remove_dev_info(old_domain);
62c22167
JR		 4427
4428 if (!domain_type_is_vm_or_si(old_domain) &&
4429 list_empty(&old_domain->devices))
4430 domain_exit(old_domain);
faa3d6f5
WH		 4431 }
4432 }
4433
156baca8 4434 iommu = device_to_iommu(dev, &bus, &devfn);
fe40f1e0
WH		 4435 if (!iommu)
4436 return -ENODEV;
4437
4438 /* check if this iommu agaw is sufficient for max mapped address */
4439 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4440 if (addr_width > cap_mgaw(iommu->cap))
4441 addr_width = cap_mgaw(iommu->cap);
4442
4443 if (dmar_domain->max_addr > (1LL << addr_width)) {
9f10e5bf 4444 pr_err("%s: iommu width (%d) is not "
fe40f1e0 4445 "sufficient for the mapped address (%llx)\n",
a99c47a2 4446 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4447 return -EFAULT;
4448 }
a99c47a2
TL		 4449 dmar_domain->gaw = addr_width;
4450
4451 /*
4452 * Knock out extra levels of page tables if necessary
4453 */
4454 while (iommu->agaw < dmar_domain->agaw) {
4455 struct dma_pte *pte;
4456
4457 pte = dmar_domain->pgd;
4458 if (dma_pte_present(pte)) {
25cbff16
SY		 4459 dmar_domain->pgd = (struct dma_pte *)
4460 phys_to_virt(dma_pte_addr(pte));
7a661013 4461 free_pgtable_page(pte);
a99c47a2
TL		 4462 }
4463 dmar_domain->agaw--;
4464 }
fe40f1e0 4465
5913c9bf 4466 return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
38717946 4467}
38717946 4468
4c5478c9
JR		 4469static void intel_iommu_detach_device(struct iommu_domain *domain,
4470 struct device *dev)
38717946 4471{
00a77deb 4472 domain_remove_one_dev_info(to_dmar_domain(domain), dev);
faa3d6f5 4473}
c7151a8d 4474
b146a1c9
JR		 4475static int intel_iommu_map(struct iommu_domain *domain,
4476 unsigned long iova, phys_addr_t hpa,
5009065d 4477 size_t size, int iommu_prot)
faa3d6f5 4478{
00a77deb 4479 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
fe40f1e0 4480 u64 max_addr;
dde57a21 4481 int prot = 0;
faa3d6f5 4482 int ret;
fe40f1e0 4483
dde57a21
JR		 4484 if (iommu_prot & IOMMU_READ)
4485 prot |= DMA_PTE_READ;
4486 if (iommu_prot & IOMMU_WRITE)
4487 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4488 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4489 prot |= DMA_PTE_SNP;
dde57a21 4490
163cc52c 4491 max_addr = iova + size;
dde57a21 4492 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4493 u64 end;
4494
4495 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4496 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4497 if (end < max_addr) {
9f10e5bf 4498 pr_err("%s: iommu width (%d) is not "
fe40f1e0 4499 "sufficient for the mapped address (%llx)\n",
8954da1f 4500 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4501 return -EFAULT;
4502 }
dde57a21 4503 dmar_domain->max_addr = max_addr;
fe40f1e0 4504 }
ad051221
DW		 4505 /* Round up size to next multiple of PAGE_SIZE, if it and
4506 the low bits of hpa would take us onto the next page */
88cb6a74 4507 size = aligned_nrpages(hpa, size);
ad051221
DW		 4508 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4509 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4510 return ret;
38717946 4511}
38717946 4512
5009065d 4513static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4514 unsigned long iova, size_t size)
38717946 4515{
00a77deb 4516 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
ea8ea460
DW		 4517 struct page *freelist = NULL;
4518 struct intel_iommu *iommu;
4519 unsigned long start_pfn, last_pfn;
4520 unsigned int npages;
4521 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4522
4523 /* Cope with horrid API which requires us to unmap more than the
4524 size argument if it happens to be a large-page mapping. */
4525 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4526 BUG();
4527
4528 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4529 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4530
ea8ea460
DW		 4531 start_pfn = iova >> VTD_PAGE_SHIFT;
4532 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4533
4534 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4535
4536 npages = last_pfn - start_pfn + 1;
4537
4538 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4539 iommu = g_iommus[iommu_id];
4540
4541 /*
4542 * find bit position of dmar_domain
4543 */
4544 ndomains = cap_ndoms(iommu->cap);
4545 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4546 if (iommu->domains[num] == dmar_domain)
4547 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4548 npages, !freelist, 0);
4549 }
4550
4551 }
4552
4553 dma_free_pagelist(freelist);
fe40f1e0 4554
163cc52c
DW		 4555 if (dmar_domain->max_addr == iova + size)
4556 dmar_domain->max_addr = iova;
b146a1c9 4557
5cf0a76f 4558 return size;
38717946 4559}
38717946 4560
d14d6577 4561static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4562 dma_addr_t iova)
38717946 4563{
00a77deb 4564 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
38717946 4565 struct dma_pte *pte;
5cf0a76f 4566 int level = 0;
faa3d6f5 4567 u64 phys = 0;
38717946 4568
5cf0a76f 4569 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4570 if (pte)
faa3d6f5 4571 phys = dma_pte_addr(pte);
38717946 4572
faa3d6f5 4573 return phys;
38717946 4574}
a8bcbb0d 4575
5d587b8d 4576static bool intel_iommu_capable(enum iommu_cap cap)
dbb9fd86 4577{
dbb9fd86 4578 if (cap == IOMMU_CAP_CACHE_COHERENCY)
5d587b8d 4579 return domain_update_iommu_snooping(NULL) == 1;
323f99cb 4580 if (cap == IOMMU_CAP_INTR_REMAP)
5d587b8d 4581 return irq_remapping_enabled == 1;
dbb9fd86 4582
5d587b8d 4583 return false;
dbb9fd86
SY		 4584}
4585
abdfdde2
AW		 4586static int intel_iommu_add_device(struct device *dev)
4587{
a5459cfe 4588 struct intel_iommu *iommu;
abdfdde2 4589 struct iommu_group *group;
156baca8 4590 u8 bus, devfn;
70ae6f0d 4591
a5459cfe
AW		 4592 iommu = device_to_iommu(dev, &bus, &devfn);
4593 if (!iommu)
70ae6f0d
AW		 4594 return -ENODEV;
4595
a5459cfe 4596 iommu_device_link(iommu->iommu_dev, dev);
a4ff1fc2 4597
e17f9ff4 4598 group = iommu_group_get_for_dev(dev);
783f157b 4599
e17f9ff4
AW		 4600 if (IS_ERR(group))
4601 return PTR_ERR(group);
bcb71abe 4602
abdfdde2 4603 iommu_group_put(group);
e17f9ff4 4604 return 0;
abdfdde2 4605}
70ae6f0d 4606
abdfdde2
AW		 4607static void intel_iommu_remove_device(struct device *dev)
4608{
a5459cfe
AW		 4609 struct intel_iommu *iommu;
4610 u8 bus, devfn;
4611
4612 iommu = device_to_iommu(dev, &bus, &devfn);
4613 if (!iommu)
4614 return;
4615
abdfdde2 4616 iommu_group_remove_device(dev);
a5459cfe
AW		 4617
4618 iommu_device_unlink(iommu->iommu_dev, dev);
70ae6f0d
AW		 4619}
4620
b22f6434 4621static const struct iommu_ops intel_iommu_ops = {
5d587b8d 4622 .capable = intel_iommu_capable,
00a77deb
JR		 4623 .domain_alloc = intel_iommu_domain_alloc,
4624 .domain_free = intel_iommu_domain_free,
a8bcbb0d
JR		 4625 .attach_dev = intel_iommu_attach_device,
4626 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4627 .map = intel_iommu_map,
4628 .unmap = intel_iommu_unmap,
315786eb 4629 .map_sg = default_iommu_map_sg,
a8bcbb0d 4630 .iova_to_phys = intel_iommu_iova_to_phys,
abdfdde2
AW		 4631 .add_device = intel_iommu_add_device,
4632 .remove_device = intel_iommu_remove_device,
6d1c56a9 4633 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4634};
9af88143 4635
9452618e
DV		 4636static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4637{
4638 /* G4x/GM45 integrated gfx dmar support is totally busted. */
9f10e5bf 4639 pr_info("Disabling IOMMU for graphics on this chipset\n");
9452618e
DV		 4640 dmar_map_gfx = 0;
4641}
4642
4643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4650
d34d6517 4651static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4652{
4653 /*
4654 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4655 * but needs it. Same seems to hold for the desktop versions.
9af88143 4656 */
9f10e5bf 4657 pr_info("Forcing write-buffer flush capability\n");
9af88143
DW		 4658 rwbf_quirk = 1;
4659}
4660
4661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4668
eecfd57f
AJ		 4669#define GGC 0x52
4670#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4671#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4672#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4673#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4674#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4675#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4676#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4677#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4678
d34d6517 4679static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4680{
4681 unsigned short ggc;
4682
eecfd57f 4683 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4684 return;
4685
eecfd57f 4686 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9f10e5bf 4687 pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
9eecabcb 4688 dmar_map_gfx = 0;
6fbcfb3e
DW		 4689 } else if (dmar_map_gfx) {
4690 /* we have to ensure the gfx device is idle before we flush */
9f10e5bf 4691 pr_info("Disabling batched IOTLB flush on Ironlake\n");
6fbcfb3e
DW		 4692 intel_iommu_strict = 1;
4693 }
9eecabcb
DW		 4694}
4695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4699
e0fc7e0b
DW		 4700/* On Tylersburg chipsets, some BIOSes have been known to enable the
4701 ISOCH DMAR unit for the Azalia sound device, but not give it any
4702 TLB entries, which causes it to deadlock. Check for that. We do
4703 this in a function called from init_dmars(), instead of in a PCI
4704 quirk, because we don't want to print the obnoxious "BIOS broken"
4705 message if VT-d is actually disabled.
4706*/
4707static void __init check_tylersburg_isoch(void)
4708{
4709 struct pci_dev *pdev;
4710 uint32_t vtisochctrl;
4711
4712 /* If there's no Azalia in the system anyway, forget it. */
4713 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4714 if (!pdev)
4715 return;
4716 pci_dev_put(pdev);
4717
4718 /* System Management Registers. Might be hidden, in which case
4719 we can't do the sanity check. But that's OK, because the
4720 known-broken BIOSes _don't_ actually hide it, so far. */
4721 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4722 if (!pdev)
4723 return;
4724
4725 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4726 pci_dev_put(pdev);
4727 return;
4728 }
4729
4730 pci_dev_put(pdev);
4731
4732 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4733 if (vtisochctrl & 1)
4734 return;
4735
4736 /* Drop all bits other than the number of TLB entries */
4737 vtisochctrl &= 0x1c;
4738
4739 /* If we have the recommended number of TLB entries (16), fine. */
4740 if (vtisochctrl == 0x10)
4741 return;
4742
4743 /* Zero TLB entries? You get to ride the short bus to school. */
4744 if (!vtisochctrl) {
4745 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4746 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4747 dmi_get_system_info(DMI_BIOS_VENDOR),
4748 dmi_get_system_info(DMI_BIOS_VERSION),
4749 dmi_get_system_info(DMI_PRODUCT_VERSION));
4750 iommu_identity_mapping |= IDENTMAP_AZALIA;
4751 return;
4752 }
9f10e5bf
JR		 4753
4754 pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
e0fc7e0b
DW		 4755 vtisochctrl);
4756}
Linux kernel - Deliverables
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