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iommu/vt-d: Finally enable translation for non-PCI devices
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 18 */
19
20#include <linux/init.h>
21#include <linux/bitmap.h>
5e0d2a6f 22#include <linux/debugfs.h>
54485c30 23#include <linux/export.h>
ba395927
KA		 24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
ba395927
KA		 27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/dmar.h>
30#include <linux/dma-mapping.h>
31#include <linux/mempool.h>
75f05569 32#include <linux/memory.h>
5e0d2a6f 33#include <linux/timer.h>
38717946 34#include <linux/iova.h>
5d450806 35#include <linux/iommu.h>
38717946 36#include <linux/intel-iommu.h>
134fac3f 37#include <linux/syscore_ops.h>
69575d38 38#include <linux/tboot.h>
adb2fe02 39#include <linux/dmi.h>
5cdede24 40#include <linux/pci-ats.h>
0ee332c1 41#include <linux/memblock.h>
8a8f422d 42#include <asm/irq_remapping.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
078e1ee2 46#include "irq_remapping.h"
61e015ac 47#include "pci.h"
078e1ee2 48
5b6985ce
FY		 49#define ROOT_SIZE VTD_PAGE_SIZE
50#define CONTEXT_SIZE VTD_PAGE_SIZE
51
ba395927
KA		 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 55
56#define IOAPIC_RANGE_START (0xfee00000)
57#define IOAPIC_RANGE_END (0xfeefffff)
58#define IOVA_START_ADDR (0x1000)
59
60#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
4ed0d3e6 62#define MAX_AGAW_WIDTH 64
5c645b35 63#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 64
2ebe3151
DW		 65#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 73
f27be03b 74#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 75#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 76#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 77
df08cdc7
AM		 78/* page table handling */
79#define LEVEL_STRIDE (9)
80#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
6d1c56a9
OBC		 82/*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
df08cdc7
AM		 100static inline int agaw_to_level(int agaw)
101{
102 return agaw + 2;
103}
104
105static inline int agaw_to_width(int agaw)
106{
5c645b35 107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 108}
109
110static inline int width_to_agaw(int width)
111{
5c645b35 112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 113}
114
115static inline unsigned int level_to_offset_bits(int level)
116{
117 return (level - 1) * LEVEL_STRIDE;
118}
119
120static inline int pfn_level_offset(unsigned long pfn, int level)
121{
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123}
124
125static inline unsigned long level_mask(int level)
126{
127 return -1UL << level_to_offset_bits(level);
128}
129
130static inline unsigned long level_size(int level)
131{
132 return 1UL << level_to_offset_bits(level);
133}
134
135static inline unsigned long align_to_level(unsigned long pfn, int level)
136{
137 return (pfn + level_size(level) - 1) & level_mask(level);
138}
fd18de50 139
6dd9a7c7
YS		 140static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141{
5c645b35 142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 143}
144
dd4e8319
DW		 145/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148{
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150}
151
152static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153{
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155}
156static inline unsigned long page_to_dma_pfn(struct page *pg)
157{
158 return mm_to_dma_pfn(page_to_pfn(pg));
159}
160static inline unsigned long virt_to_dma_pfn(void *p)
161{
162 return page_to_dma_pfn(virt_to_page(p));
163}
164
d9630fe9
WH		 165/* global iommu list, set NULL for ignored DMAR units */
166static struct intel_iommu **g_iommus;
167
e0fc7e0b 168static void __init check_tylersburg_isoch(void);
9af88143
DW		 169static int rwbf_quirk;
170
b779260b
JC		 171/*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175static int force_on = 0;
176
46b08e1a
MM		 177/*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183struct root_entry {
184 u64 val;
185 u64 rsvd1;
186};
187#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188static inline bool root_present(struct root_entry *root)
189{
190 return (root->val & 1);
191}
192static inline void set_root_present(struct root_entry *root)
193{
194 root->val |= 1;
195}
196static inline void set_root_value(struct root_entry *root, unsigned long value)
197{
198 root->val |= value & VTD_PAGE_MASK;
199}
200
201static inline struct context_entry *
202get_context_addr_from_root(struct root_entry *root)
203{
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208}
209
7a8fc25e
MM		 210/*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221struct context_entry {
222 u64 lo;
223 u64 hi;
224};
c07e7d21
MM		 225
226static inline bool context_present(struct context_entry *context)
227{
228 return (context->lo & 1);
229}
230static inline void context_set_present(struct context_entry *context)
231{
232 context->lo |= 1;
233}
234
235static inline void context_set_fault_enable(struct context_entry *context)
236{
237 context->lo &= (((u64)-1) << 2) | 1;
238}
239
c07e7d21
MM		 240static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242{
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245}
246
247static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249{
250 context->lo |= value & VTD_PAGE_MASK;
251}
252
253static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255{
256 context->hi |= value & 7;
257}
258
259static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261{
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263}
264
265static inline void context_clear_entry(struct context_entry *context)
266{
267 context->lo = 0;
268 context->hi = 0;
269}
7a8fc25e 270
622ba12a
MM		 271/*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
9cf06697
SY		 276 * 8-10: available
277 * 11: snoop behavior
622ba12a
MM		 278 * 12-63: Host physcial address
279 */
280struct dma_pte {
281 u64 val;
282};
622ba12a 283
19c239ce
MM		 284static inline void dma_clear_pte(struct dma_pte *pte)
285{
286 pte->val = 0;
287}
288
19c239ce
MM		 289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
19c239ce
MM		 299static inline bool dma_pte_present(struct dma_pte *pte)
300{
301 return (pte->val & 3) != 0;
302}
622ba12a 303
4399c8bf
AK		 304static inline bool dma_pte_superpage(struct dma_pte *pte)
305{
306 return (pte->val & (1 << 7));
307}
308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
3b5410e7 323/* devices under the same p2p bridge are owned in one domain */
cdc7b837 324#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 325
1ce28feb
WH		 326/* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
2c2e2c38
FY		 331/* si_domain contains mulitple devices */
332#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
1b198bb0
MT		 334/* define the limit of IOMMUs supported in each domain */
335#ifdef CONFIG_X86
336# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
337#else
338# define IOMMU_UNITS_SUPPORTED 64
339#endif
340
99126f7c
MM		 341struct dmar_domain {
342 int id; /* domain id */
4c923d47 343 int nid; /* node id */
1b198bb0
MT		 344 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
345 /* bitmap of iommus this domain uses*/
99126f7c
MM		 346
347 struct list_head devices; /* all devices' list */
348 struct iova_domain iovad; /* iova's that belong to this domain */
349
350 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 351 int gaw; /* max guest address width */
352
353 /* adjusted guest address width, 0 is level 2 30-bit */
354 int agaw;
355
3b5410e7 356 int flags; /* flags to find out type of domain */
8e604097
WH		 357
358 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 359 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 360 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 361 int iommu_superpage;/* Level of superpages supported:
362 0 == 4KiB (no superpages), 1 == 2MiB,
363 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 364 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 365 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 366};
367
a647dacb
MM		 368/* PCI domain-device relationship */
369struct device_domain_info {
370 struct list_head link; /* link to domain siblings */
371 struct list_head global; /* link to global list */
276dbf99 372 u8 bus; /* PCI bus number */
a647dacb 373 u8 devfn; /* PCI devfn number */
0bcb3e28 374 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 375 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 376 struct dmar_domain *domain; /* pointer to domain */
377};
378
b94e4117
JL		 379struct dmar_rmrr_unit {
380 struct list_head list; /* list of rmrr units */
381 struct acpi_dmar_header *hdr; /* ACPI header */
382 u64 base_address; /* reserved base address*/
383 u64 end_address; /* reserved end address */
832bd858 384 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 385 int devices_cnt; /* target device count */
386};
387
388struct dmar_atsr_unit {
389 struct list_head list; /* list of ATSR units */
390 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 391 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 392 int devices_cnt; /* target device count */
393 u8 include_all:1; /* include all ports */
394};
395
396static LIST_HEAD(dmar_atsr_units);
397static LIST_HEAD(dmar_rmrr_units);
398
399#define for_each_rmrr_units(rmrr) \
400 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
401
5e0d2a6f 402static void flush_unmaps_timeout(unsigned long data);
403
b707cb02 404static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 405
80b20dd8 406#define HIGH_WATER_MARK 250
407struct deferred_flush_tables {
408 int next;
409 struct iova *iova[HIGH_WATER_MARK];
410 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 411 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 412};
413
414static struct deferred_flush_tables *deferred_flush;
415
5e0d2a6f 416/* bitmap for indexing intel_iommus */
5e0d2a6f 417static int g_num_of_iommus;
418
419static DEFINE_SPINLOCK(async_umap_flush_lock);
420static LIST_HEAD(unmaps_to_do);
421
422static int timer_on;
423static long list_size;
5e0d2a6f 424
92d03cc8 425static void domain_exit(struct dmar_domain *domain);
ba395927 426static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117 427static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 428 struct device *dev);
92d03cc8 429static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 430 struct device *dev);
ba395927 431
d3f13810 432#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 433int dmar_disabled = 0;
434#else
435int dmar_disabled = 1;
d3f13810 436#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 437
8bc1f85c
ED		 438int intel_iommu_enabled = 0;
439EXPORT_SYMBOL_GPL(intel_iommu_enabled);
440
2d9e667e 441static int dmar_map_gfx = 1;
7d3b03ce 442static int dmar_forcedac;
5e0d2a6f 443static int intel_iommu_strict;
6dd9a7c7 444static int intel_iommu_superpage = 1;
ba395927 445
c0771df8
DW		 446int intel_iommu_gfx_mapped;
447EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
448
ba395927
KA		 449#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
450static DEFINE_SPINLOCK(device_domain_lock);
451static LIST_HEAD(device_domain_list);
452
a8bcbb0d
JR		 453static struct iommu_ops intel_iommu_ops;
454
ba395927
KA		 455static int __init intel_iommu_setup(char *str)
456{
457 if (!str)
458 return -EINVAL;
459 while (*str) {
0cd5c3c8
KM		 460 if (!strncmp(str, "on", 2)) {
461 dmar_disabled = 0;
462 printk(KERN_INFO "Intel-IOMMU: enabled\n");
463 } else if (!strncmp(str, "off", 3)) {
ba395927 464 dmar_disabled = 1;
0cd5c3c8 465 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 466 } else if (!strncmp(str, "igfx_off", 8)) {
467 dmar_map_gfx = 0;
468 printk(KERN_INFO
469 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 470 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 471 printk(KERN_INFO
7d3b03ce
KA		 472 "Intel-IOMMU: Forcing DAC for PCI devices\n");
473 dmar_forcedac = 1;
5e0d2a6f 474 } else if (!strncmp(str, "strict", 6)) {
475 printk(KERN_INFO
476 "Intel-IOMMU: disable batched IOTLB flush\n");
477 intel_iommu_strict = 1;
6dd9a7c7
YS		 478 } else if (!strncmp(str, "sp_off", 6)) {
479 printk(KERN_INFO
480 "Intel-IOMMU: disable supported super page\n");
481 intel_iommu_superpage = 0;
ba395927
KA		 482 }
483
484 str += strcspn(str, ",");
485 while (*str == ',')
486 str++;
487 }
488 return 0;
489}
490__setup("intel_iommu=", intel_iommu_setup);
491
492static struct kmem_cache *iommu_domain_cache;
493static struct kmem_cache *iommu_devinfo_cache;
494static struct kmem_cache *iommu_iova_cache;
495
4c923d47 496static inline void *alloc_pgtable_page(int node)
eb3fa7cb 497{
4c923d47
SS		 498 struct page *page;
499 void *vaddr = NULL;
eb3fa7cb 500
4c923d47
SS		 501 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
502 if (page)
503 vaddr = page_address(page);
eb3fa7cb 504 return vaddr;
ba395927
KA		 505}
506
507static inline void free_pgtable_page(void *vaddr)
508{
509 free_page((unsigned long)vaddr);
510}
511
512static inline void *alloc_domain_mem(void)
513{
354bb65e 514 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 515}
516
38717946 517static void free_domain_mem(void *vaddr)
ba395927
KA		 518{
519 kmem_cache_free(iommu_domain_cache, vaddr);
520}
521
522static inline void * alloc_devinfo_mem(void)
523{
354bb65e 524 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 525}
526
527static inline void free_devinfo_mem(void *vaddr)
528{
529 kmem_cache_free(iommu_devinfo_cache, vaddr);
530}
531
532struct iova *alloc_iova_mem(void)
533{
354bb65e 534 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 535}
536
537void free_iova_mem(struct iova *iova)
538{
539 kmem_cache_free(iommu_iova_cache, iova);
540}
541
1b573683 542
4ed0d3e6 543static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 544{
545 unsigned long sagaw;
546 int agaw = -1;
547
548 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 549 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 550 agaw >= 0; agaw--) {
551 if (test_bit(agaw, &sagaw))
552 break;
553 }
554
555 return agaw;
556}
557
4ed0d3e6
FY		 558/*
559 * Calculate max SAGAW for each iommu.
560 */
561int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
562{
563 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
564}
565
566/*
567 * calculate agaw for each iommu.
568 * "SAGAW" may be different across iommus, use a default agaw, and
569 * get a supported less agaw for iommus that don't support the default agaw.
570 */
571int iommu_calculate_agaw(struct intel_iommu *iommu)
572{
573 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
574}
575
2c2e2c38 576/* This functionin only returns single iommu in a domain */
8c11e798
WH		 577static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
578{
579 int iommu_id;
580
2c2e2c38 581 /* si_domain and vm domain should not get here. */
1ce28feb 582 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 583 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 584
1b198bb0 585 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 586 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
587 return NULL;
588
589 return g_iommus[iommu_id];
590}
591
8e604097
WH		 592static void domain_update_iommu_coherency(struct dmar_domain *domain)
593{
d0501960
DW		 594 struct dmar_drhd_unit *drhd;
595 struct intel_iommu *iommu;
596 int i, found = 0;
2e12bc29 597
d0501960 598 domain->iommu_coherency = 1;
8e604097 599
1b198bb0 600 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
d0501960 601 found = 1;
8e604097
WH		 602 if (!ecap_coherent(g_iommus[i]->ecap)) {
603 domain->iommu_coherency = 0;
604 break;
605 }
8e604097 606 }
d0501960
DW		 607 if (found)
608 return;
609
610 /* No hardware attached; use lowest common denominator */
611 rcu_read_lock();
612 for_each_active_iommu(iommu, drhd) {
613 if (!ecap_coherent(iommu->ecap)) {
614 domain->iommu_coherency = 0;
615 break;
616 }
617 }
618 rcu_read_unlock();
8e604097
WH		 619}
620
58c610bd
SY		 621static void domain_update_iommu_snooping(struct dmar_domain *domain)
622{
623 int i;
624
625 domain->iommu_snooping = 1;
626
1b198bb0 627 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 628 if (!ecap_sc_support(g_iommus[i]->ecap)) {
629 domain->iommu_snooping = 0;
630 break;
631 }
58c610bd
SY		 632 }
633}
634
6dd9a7c7
YS		 635static void domain_update_iommu_superpage(struct dmar_domain *domain)
636{
8140a95d
AK		 637 struct dmar_drhd_unit *drhd;
638 struct intel_iommu *iommu = NULL;
639 int mask = 0xf;
6dd9a7c7
YS		 640
641 if (!intel_iommu_superpage) {
642 domain->iommu_superpage = 0;
643 return;
644 }
645
8140a95d 646 /* set iommu_superpage to the smallest common denominator */
0e242612 647 rcu_read_lock();
8140a95d
AK		 648 for_each_active_iommu(iommu, drhd) {
649 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 650 if (!mask) {
651 break;
652 }
653 }
0e242612
JL		 654 rcu_read_unlock();
655
6dd9a7c7
YS		 656 domain->iommu_superpage = fls(mask);
657}
658
58c610bd
SY		 659/* Some capabilities may be different across iommus */
660static void domain_update_iommu_cap(struct dmar_domain *domain)
661{
662 domain_update_iommu_coherency(domain);
663 domain_update_iommu_snooping(domain);
6dd9a7c7 664 domain_update_iommu_superpage(domain);
58c610bd
SY		 665}
666
156baca8 667static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
c7151a8d
WH		 668{
669 struct dmar_drhd_unit *drhd = NULL;
b683b230 670 struct intel_iommu *iommu;
156baca8
DW		 671 struct device *tmp;
672 struct pci_dev *ptmp, *pdev = NULL;
673 u16 segment;
c7151a8d
WH		 674 int i;
675
156baca8
DW		 676 if (dev_is_pci(dev)) {
677 pdev = to_pci_dev(dev);
678 segment = pci_domain_nr(pdev->bus);
679 } else if (ACPI_COMPANION(dev))
680 dev = &ACPI_COMPANION(dev)->dev;
681
0e242612 682 rcu_read_lock();
b683b230 683 for_each_active_iommu(iommu, drhd) {
156baca8 684 if (pdev && segment != drhd->segment)
276dbf99 685 continue;
c7151a8d 686
b683b230 687 for_each_active_dev_scope(drhd->devices,
156baca8
DW		 688 drhd->devices_cnt, i, tmp) {
689 if (tmp == dev) {
690 *bus = drhd->devices[i].bus;
691 *devfn = drhd->devices[i].devfn;
b683b230 692 goto out;
156baca8
DW		 693 }
694
695 if (!pdev || !dev_is_pci(tmp))
696 continue;
697
698 ptmp = to_pci_dev(tmp);
699 if (ptmp->subordinate &&
700 ptmp->subordinate->number <= pdev->bus->number &&
701 ptmp->subordinate->busn_res.end >= pdev->bus->number)
702 goto got_pdev;
924b6231 703 }
c7151a8d 704
156baca8
DW		 705 if (pdev && drhd->include_all) {
706 got_pdev:
707 *bus = pdev->bus->number;
708 *devfn = pdev->devfn;
b683b230 709 goto out;
156baca8 710 }
c7151a8d 711 }
b683b230 712 iommu = NULL;
156baca8 713 out:
0e242612 714 rcu_read_unlock();
c7151a8d 715
b683b230 716 return iommu;
c7151a8d
WH		 717}
718
5331fe6f
WH		 719static void domain_flush_cache(struct dmar_domain *domain,
720 void *addr, int size)
721{
722 if (!domain->iommu_coherency)
723 clflush_cache_range(addr, size);
724}
725
ba395927
KA		 726/* Gets context entry for a given bus and devfn */
727static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
728 u8 bus, u8 devfn)
729{
730 struct root_entry *root;
731 struct context_entry *context;
732 unsigned long phy_addr;
733 unsigned long flags;
734
735 spin_lock_irqsave(&iommu->lock, flags);
736 root = &iommu->root_entry[bus];
737 context = get_context_addr_from_root(root);
738 if (!context) {
4c923d47
SS		 739 context = (struct context_entry *)
740 alloc_pgtable_page(iommu->node);
ba395927
KA		 741 if (!context) {
742 spin_unlock_irqrestore(&iommu->lock, flags);
743 return NULL;
744 }
5b6985ce 745 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 746 phy_addr = virt_to_phys((void *)context);
747 set_root_value(root, phy_addr);
748 set_root_present(root);
749 __iommu_flush_cache(iommu, root, sizeof(*root));
750 }
751 spin_unlock_irqrestore(&iommu->lock, flags);
752 return &context[devfn];
753}
754
755static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
756{
757 struct root_entry *root;
758 struct context_entry *context;
759 int ret;
760 unsigned long flags;
761
762 spin_lock_irqsave(&iommu->lock, flags);
763 root = &iommu->root_entry[bus];
764 context = get_context_addr_from_root(root);
765 if (!context) {
766 ret = 0;
767 goto out;
768 }
c07e7d21 769 ret = context_present(&context[devfn]);
ba395927
KA		 770out:
771 spin_unlock_irqrestore(&iommu->lock, flags);
772 return ret;
773}
774
775static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
776{
777 struct root_entry *root;
778 struct context_entry *context;
779 unsigned long flags;
780
781 spin_lock_irqsave(&iommu->lock, flags);
782 root = &iommu->root_entry[bus];
783 context = get_context_addr_from_root(root);
784 if (context) {
c07e7d21 785 context_clear_entry(&context[devfn]);
ba395927
KA		 786 __iommu_flush_cache(iommu, &context[devfn], \
787 sizeof(*context));
788 }
789 spin_unlock_irqrestore(&iommu->lock, flags);
790}
791
792static void free_context_table(struct intel_iommu *iommu)
793{
794 struct root_entry *root;
795 int i;
796 unsigned long flags;
797 struct context_entry *context;
798
799 spin_lock_irqsave(&iommu->lock, flags);
800 if (!iommu->root_entry) {
801 goto out;
802 }
803 for (i = 0; i < ROOT_ENTRY_NR; i++) {
804 root = &iommu->root_entry[i];
805 context = get_context_addr_from_root(root);
806 if (context)
807 free_pgtable_page(context);
808 }
809 free_pgtable_page(iommu->root_entry);
810 iommu->root_entry = NULL;
811out:
812 spin_unlock_irqrestore(&iommu->lock, flags);
813}
814
b026fd28 815static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 816 unsigned long pfn, int *target_level)
ba395927 817{
b026fd28 818 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 819 struct dma_pte *parent, *pte = NULL;
820 int level = agaw_to_level(domain->agaw);
4399c8bf 821 int offset;
ba395927
KA		 822
823 BUG_ON(!domain->pgd);
f9423606
JS		 824
825 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
826 /* Address beyond IOMMU's addressing capabilities. */
827 return NULL;
828
ba395927
KA		 829 parent = domain->pgd;
830
5cf0a76f 831 while (1) {
ba395927
KA		 832 void *tmp_page;
833
b026fd28 834 offset = pfn_level_offset(pfn, level);
ba395927 835 pte = &parent[offset];
5cf0a76f 836 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 837 break;
5cf0a76f 838 if (level == *target_level)
ba395927
KA		 839 break;
840
19c239ce 841 if (!dma_pte_present(pte)) {
c85994e4
DW		 842 uint64_t pteval;
843
4c923d47 844 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 845
206a73c1 846 if (!tmp_page)
ba395927 847 return NULL;
206a73c1 848
c85994e4 849 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 850 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 851 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
852 /* Someone else set it while we were thinking; use theirs. */
853 free_pgtable_page(tmp_page);
854 } else {
855 dma_pte_addr(pte);
856 domain_flush_cache(domain, pte, sizeof(*pte));
857 }
ba395927 858 }
5cf0a76f
DW		 859 if (level == 1)
860 break;
861
19c239ce 862 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 863 level--;
864 }
865
5cf0a76f
DW		 866 if (!*target_level)
867 *target_level = level;
868
ba395927
KA		 869 return pte;
870}
871
6dd9a7c7 872
ba395927 873/* return address's pte at specific level */
90dcfb5e
DW		 874static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
875 unsigned long pfn,
6dd9a7c7 876 int level, int *large_page)
ba395927
KA		 877{
878 struct dma_pte *parent, *pte = NULL;
879 int total = agaw_to_level(domain->agaw);
880 int offset;
881
882 parent = domain->pgd;
883 while (level <= total) {
90dcfb5e 884 offset = pfn_level_offset(pfn, total);
ba395927
KA		 885 pte = &parent[offset];
886 if (level == total)
887 return pte;
888
6dd9a7c7
YS		 889 if (!dma_pte_present(pte)) {
890 *large_page = total;
ba395927 891 break;
6dd9a7c7
YS		 892 }
893
894 if (pte->val & DMA_PTE_LARGE_PAGE) {
895 *large_page = total;
896 return pte;
897 }
898
19c239ce 899 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 900 total--;
901 }
902 return NULL;
903}
904
ba395927 905/* clear last level pte, a tlb flush should be followed */
5cf0a76f 906static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 907 unsigned long start_pfn,
908 unsigned long last_pfn)
ba395927 909{
04b18e65 910 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 911 unsigned int large_page = 1;
310a5ab9 912 struct dma_pte *first_pte, *pte;
66eae846 913
04b18e65 914 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 915 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 916 BUG_ON(start_pfn > last_pfn);
ba395927 917
04b18e65 918 /* we don't need lock here; nobody else touches the iova range */
59c36286 919 do {
6dd9a7c7
YS		 920 large_page = 1;
921 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 922 if (!pte) {
6dd9a7c7 923 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 924 continue;
925 }
6dd9a7c7 926 do {
310a5ab9 927 dma_clear_pte(pte);
6dd9a7c7 928 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 929 pte++;
75e6bf96
DW		 930 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
931
310a5ab9
DW		 932 domain_flush_cache(domain, first_pte,
933 (void *)pte - (void *)first_pte);
59c36286
DW		 934
935 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 936}
937
3269ee0b
AW		 938static void dma_pte_free_level(struct dmar_domain *domain, int level,
939 struct dma_pte *pte, unsigned long pfn,
940 unsigned long start_pfn, unsigned long last_pfn)
941{
942 pfn = max(start_pfn, pfn);
943 pte = &pte[pfn_level_offset(pfn, level)];
944
945 do {
946 unsigned long level_pfn;
947 struct dma_pte *level_pte;
948
949 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
950 goto next;
951
952 level_pfn = pfn & level_mask(level - 1);
953 level_pte = phys_to_virt(dma_pte_addr(pte));
954
955 if (level > 2)
956 dma_pte_free_level(domain, level - 1, level_pte,
957 level_pfn, start_pfn, last_pfn);
958
959 /* If range covers entire pagetable, free it */
960 if (!(start_pfn > level_pfn ||
08336fd2 961 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 962 dma_clear_pte(pte);
963 domain_flush_cache(domain, pte, sizeof(*pte));
964 free_pgtable_page(level_pte);
965 }
966next:
967 pfn += level_size(level);
968 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
969}
970
ba395927
KA		 971/* free page table pages. last level pte should already be cleared */
972static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 973 unsigned long start_pfn,
974 unsigned long last_pfn)
ba395927 975{
6660c63a 976 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 977
6660c63a
DW		 978 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
979 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 980 BUG_ON(start_pfn > last_pfn);
ba395927 981
f3a0a52f 982 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 983 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
984 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 985
ba395927 986 /* free pgd */
d794dc9b 987 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 988 free_pgtable_page(domain->pgd);
989 domain->pgd = NULL;
990 }
991}
992
ea8ea460
DW		 993/* When a page at a given level is being unlinked from its parent, we don't
994 need to *modify* it at all. All we need to do is make a list of all the
995 pages which can be freed just as soon as we've flushed the IOTLB and we
996 know the hardware page-walk will no longer touch them.
997 The 'pte' argument is the *parent* PTE, pointing to the page that is to
998 be freed. */
999static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1000 int level, struct dma_pte *pte,
1001 struct page *freelist)
1002{
1003 struct page *pg;
1004
1005 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1006 pg->freelist = freelist;
1007 freelist = pg;
1008
1009 if (level == 1)
1010 return freelist;
1011
1012 for (pte = page_address(pg); !first_pte_in_page(pte); pte++) {
1013 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1014 freelist = dma_pte_list_pagetables(domain, level - 1,
1015 pte, freelist);
1016 }
1017
1018 return freelist;
1019}
1020
1021static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1022 struct dma_pte *pte, unsigned long pfn,
1023 unsigned long start_pfn,
1024 unsigned long last_pfn,
1025 struct page *freelist)
1026{
1027 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1028
1029 pfn = max(start_pfn, pfn);
1030 pte = &pte[pfn_level_offset(pfn, level)];
1031
1032 do {
1033 unsigned long level_pfn;
1034
1035 if (!dma_pte_present(pte))
1036 goto next;
1037
1038 level_pfn = pfn & level_mask(level);
1039
1040 /* If range covers entire pagetable, free it */
1041 if (start_pfn <= level_pfn &&
1042 last_pfn >= level_pfn + level_size(level) - 1) {
1043 /* These suborbinate page tables are going away entirely. Don't
1044 bother to clear them; we're just going to *free* them. */
1045 if (level > 1 && !dma_pte_superpage(pte))
1046 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1047
1048 dma_clear_pte(pte);
1049 if (!first_pte)
1050 first_pte = pte;
1051 last_pte = pte;
1052 } else if (level > 1) {
1053 /* Recurse down into a level that isn't *entirely* obsolete */
1054 freelist = dma_pte_clear_level(domain, level - 1,
1055 phys_to_virt(dma_pte_addr(pte)),
1056 level_pfn, start_pfn, last_pfn,
1057 freelist);
1058 }
1059next:
1060 pfn += level_size(level);
1061 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1062
1063 if (first_pte)
1064 domain_flush_cache(domain, first_pte,
1065 (void *)++last_pte - (void *)first_pte);
1066
1067 return freelist;
1068}
1069
1070/* We can't just free the pages because the IOMMU may still be walking
1071 the page tables, and may have cached the intermediate levels. The
1072 pages can only be freed after the IOTLB flush has been done. */
1073struct page *domain_unmap(struct dmar_domain *domain,
1074 unsigned long start_pfn,
1075 unsigned long last_pfn)
1076{
1077 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1078 struct page *freelist = NULL;
1079
1080 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1081 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1082 BUG_ON(start_pfn > last_pfn);
1083
1084 /* we don't need lock here; nobody else touches the iova range */
1085 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1086 domain->pgd, 0, start_pfn, last_pfn, NULL);
1087
1088 /* free pgd */
1089 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1090 struct page *pgd_page = virt_to_page(domain->pgd);
1091 pgd_page->freelist = freelist;
1092 freelist = pgd_page;
1093
1094 domain->pgd = NULL;
1095 }
1096
1097 return freelist;
1098}
1099
1100void dma_free_pagelist(struct page *freelist)
1101{
1102 struct page *pg;
1103
1104 while ((pg = freelist)) {
1105 freelist = pg->freelist;
1106 free_pgtable_page(page_address(pg));
1107 }
1108}
1109
ba395927
KA		 1110/* iommu handling */
1111static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1112{
1113 struct root_entry *root;
1114 unsigned long flags;
1115
4c923d47 1116 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 1117 if (!root)
1118 return -ENOMEM;
1119
5b6985ce 1120 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1121
1122 spin_lock_irqsave(&iommu->lock, flags);
1123 iommu->root_entry = root;
1124 spin_unlock_irqrestore(&iommu->lock, flags);
1125
1126 return 0;
1127}
1128
ba395927
KA		 1129static void iommu_set_root_entry(struct intel_iommu *iommu)
1130{
1131 void *addr;
c416daa9 1132 u32 sts;
ba395927
KA		 1133 unsigned long flag;
1134
1135 addr = iommu->root_entry;
1136
1f5b3c3f 1137 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1138 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1139
c416daa9 1140 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1141
1142 /* Make sure hardware complete it */
1143 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1144 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1145
1f5b3c3f 1146 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1147}
1148
1149static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1150{
1151 u32 val;
1152 unsigned long flag;
1153
9af88143 1154 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1155 return;
ba395927 1156
1f5b3c3f 1157 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1158 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1159
1160 /* Make sure hardware complete it */
1161 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1162 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1163
1f5b3c3f 1164 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1165}
1166
1167/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1168static void __iommu_flush_context(struct intel_iommu *iommu,
1169 u16 did, u16 source_id, u8 function_mask,
1170 u64 type)
ba395927
KA		 1171{
1172 u64 val = 0;
1173 unsigned long flag;
1174
ba395927
KA		 1175 switch (type) {
1176 case DMA_CCMD_GLOBAL_INVL:
1177 val = DMA_CCMD_GLOBAL_INVL;
1178 break;
1179 case DMA_CCMD_DOMAIN_INVL:
1180 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1181 break;
1182 case DMA_CCMD_DEVICE_INVL:
1183 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1184 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1185 break;
1186 default:
1187 BUG();
1188 }
1189 val |= DMA_CCMD_ICC;
1190
1f5b3c3f 1191 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1192 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1193
1194 /* Make sure hardware complete it */
1195 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1196 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1197
1f5b3c3f 1198 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1199}
1200
ba395927 1201/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1202static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1203 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1204{
1205 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1206 u64 val = 0, val_iva = 0;
1207 unsigned long flag;
1208
ba395927
KA		 1209 switch (type) {
1210 case DMA_TLB_GLOBAL_FLUSH:
1211 /* global flush doesn't need set IVA_REG */
1212 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1213 break;
1214 case DMA_TLB_DSI_FLUSH:
1215 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1216 break;
1217 case DMA_TLB_PSI_FLUSH:
1218 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1219 /* IH bit is passed in as part of address */
ba395927
KA		 1220 val_iva = size_order | addr;
1221 break;
1222 default:
1223 BUG();
1224 }
1225 /* Note: set drain read/write */
1226#if 0
1227 /*
1228 * This is probably to be super secure.. Looks like we can
1229 * ignore it without any impact.
1230 */
1231 if (cap_read_drain(iommu->cap))
1232 val |= DMA_TLB_READ_DRAIN;
1233#endif
1234 if (cap_write_drain(iommu->cap))
1235 val |= DMA_TLB_WRITE_DRAIN;
1236
1f5b3c3f 1237 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1238 /* Note: Only uses first TLB reg currently */
1239 if (val_iva)
1240 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1241 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1242
1243 /* Make sure hardware complete it */
1244 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1245 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1246
1f5b3c3f 1247 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1248
1249 /* check IOTLB invalidation granularity */
1250 if (DMA_TLB_IAIG(val) == 0)
1251 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1252 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1253 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1254 (unsigned long long)DMA_TLB_IIRG(type),
1255 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1256}
1257
64ae892b
DW		 1258static struct device_domain_info *
1259iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1260 u8 bus, u8 devfn)
93a23a72
YZ		 1261{
1262 int found = 0;
1263 unsigned long flags;
1264 struct device_domain_info *info;
0bcb3e28 1265 struct pci_dev *pdev;
93a23a72
YZ		 1266
1267 if (!ecap_dev_iotlb_support(iommu->ecap))
1268 return NULL;
1269
1270 if (!iommu->qi)
1271 return NULL;
1272
1273 spin_lock_irqsave(&device_domain_lock, flags);
1274 list_for_each_entry(info, &domain->devices, link)
1275 if (info->bus == bus && info->devfn == devfn) {
1276 found = 1;
1277 break;
1278 }
1279 spin_unlock_irqrestore(&device_domain_lock, flags);
1280
0bcb3e28 1281 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1282 return NULL;
1283
0bcb3e28
DW		 1284 pdev = to_pci_dev(info->dev);
1285
1286 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1287 return NULL;
1288
0bcb3e28 1289 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1290 return NULL;
1291
93a23a72
YZ		 1292 return info;
1293}
1294
1295static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1296{
0bcb3e28 1297 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1298 return;
1299
0bcb3e28 1300 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1301}
1302
1303static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1304{
0bcb3e28
DW		 1305 if (!info->dev || !dev_is_pci(info->dev) ||
1306 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1307 return;
1308
0bcb3e28 1309 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1310}
1311
1312static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1313 u64 addr, unsigned mask)
1314{
1315 u16 sid, qdep;
1316 unsigned long flags;
1317 struct device_domain_info *info;
1318
1319 spin_lock_irqsave(&device_domain_lock, flags);
1320 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1321 struct pci_dev *pdev;
1322 if (!info->dev || !dev_is_pci(info->dev))
1323 continue;
1324
1325 pdev = to_pci_dev(info->dev);
1326 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1327 continue;
1328
1329 sid = info->bus << 8 | info->devfn;
0bcb3e28 1330 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1331 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1332 }
1333 spin_unlock_irqrestore(&device_domain_lock, flags);
1334}
1335
1f0ef2aa 1336static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1337 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1338{
9dd2fe89 1339 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1340 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1341
ba395927
KA		 1342 BUG_ON(pages == 0);
1343
ea8ea460
DW		 1344 if (ih)
1345 ih = 1 << 6;
ba395927 1346 /*
9dd2fe89
YZ		 1347 * Fallback to domain selective flush if no PSI support or the size is
1348 * too big.
ba395927
KA		 1349 * PSI requires page size to be 2 ^ x, and the base address is naturally
1350 * aligned to the size
1351 */
9dd2fe89
YZ		 1352 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1353 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1354 DMA_TLB_DSI_FLUSH);
9dd2fe89 1355 else
ea8ea460 1356 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1357 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1358
1359 /*
82653633
NA		 1360 * In caching mode, changes of pages from non-present to present require
1361 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1362 */
82653633 1363 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1364 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1365}
1366
f8bab735 1367static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1368{
1369 u32 pmen;
1370 unsigned long flags;
1371
1f5b3c3f 1372 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1373 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1374 pmen &= ~DMA_PMEN_EPM;
1375 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1376
1377 /* wait for the protected region status bit to clear */
1378 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1379 readl, !(pmen & DMA_PMEN_PRS), pmen);
1380
1f5b3c3f 1381 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1382}
1383
ba395927
KA		 1384static int iommu_enable_translation(struct intel_iommu *iommu)
1385{
1386 u32 sts;
1387 unsigned long flags;
1388
1f5b3c3f 1389 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1390 iommu->gcmd |= DMA_GCMD_TE;
1391 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1392
1393 /* Make sure hardware complete it */
1394 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1395 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1396
1f5b3c3f 1397 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1398 return 0;
1399}
1400
1401static int iommu_disable_translation(struct intel_iommu *iommu)
1402{
1403 u32 sts;
1404 unsigned long flag;
1405
1f5b3c3f 1406 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1407 iommu->gcmd &= ~DMA_GCMD_TE;
1408 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1409
1410 /* Make sure hardware complete it */
1411 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1412 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1413
1f5b3c3f 1414 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1415 return 0;
1416}
1417
3460a6d9 1418
ba395927
KA		 1419static int iommu_init_domains(struct intel_iommu *iommu)
1420{
1421 unsigned long ndomains;
1422 unsigned long nlongs;
1423
1424 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1425 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1426 iommu->seq_id, ndomains);
ba395927
KA		 1427 nlongs = BITS_TO_LONGS(ndomains);
1428
94a91b50
DD		 1429 spin_lock_init(&iommu->lock);
1430
ba395927
KA		 1431 /* TBD: there might be 64K domains,
1432 * consider other allocation for future chip
1433 */
1434 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1435 if (!iommu->domain_ids) {
852bdb04
JL		 1436 pr_err("IOMMU%d: allocating domain id array failed\n",
1437 iommu->seq_id);
ba395927
KA		 1438 return -ENOMEM;
1439 }
1440 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1441 GFP_KERNEL);
1442 if (!iommu->domains) {
852bdb04
JL		 1443 pr_err("IOMMU%d: allocating domain array failed\n",
1444 iommu->seq_id);
1445 kfree(iommu->domain_ids);
1446 iommu->domain_ids = NULL;
ba395927
KA		 1447 return -ENOMEM;
1448 }
1449
1450 /*
1451 * if Caching mode is set, then invalid translations are tagged
1452 * with domainid 0. Hence we need to pre-allocate it.
1453 */
1454 if (cap_caching_mode(iommu->cap))
1455 set_bit(0, iommu->domain_ids);
1456 return 0;
1457}
ba395927 1458
a868e6b7 1459static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1460{
1461 struct dmar_domain *domain;
5ced12af 1462 int i, count;
c7151a8d 1463 unsigned long flags;
ba395927 1464
94a91b50 1465 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1466 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1467 /*
1468 * Domain id 0 is reserved for invalid translation
1469 * if hardware supports caching mode.
1470 */
1471 if (cap_caching_mode(iommu->cap) && i == 0)
1472 continue;
1473
94a91b50
DD		 1474 domain = iommu->domains[i];
1475 clear_bit(i, iommu->domain_ids);
1476
1477 spin_lock_irqsave(&domain->iommu_lock, flags);
5ced12af
JL		 1478 count = --domain->iommu_count;
1479 spin_unlock_irqrestore(&domain->iommu_lock, flags);
92d03cc8
JL		 1480 if (count == 0)
1481 domain_exit(domain);
5e98c4b1 1482 }
ba395927
KA		 1483 }
1484
1485 if (iommu->gcmd & DMA_GCMD_TE)
1486 iommu_disable_translation(iommu);
1487
ba395927
KA		 1488 kfree(iommu->domains);
1489 kfree(iommu->domain_ids);
a868e6b7
JL		 1490 iommu->domains = NULL;
1491 iommu->domain_ids = NULL;
ba395927 1492
d9630fe9
WH		 1493 g_iommus[iommu->seq_id] = NULL;
1494
ba395927
KA		 1495 /* free context mapping */
1496 free_context_table(iommu);
ba395927
KA		 1497}
1498
92d03cc8 1499static struct dmar_domain *alloc_domain(bool vm)
ba395927 1500{
92d03cc8
JL		 1501 /* domain id for virtual machine, it won't be set in context */
1502 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1503 struct dmar_domain *domain;
ba395927
KA		 1504
1505 domain = alloc_domain_mem();
1506 if (!domain)
1507 return NULL;
1508
4c923d47 1509 domain->nid = -1;
92d03cc8 1510 domain->iommu_count = 0;
1b198bb0 1511 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
2c2e2c38 1512 domain->flags = 0;
92d03cc8
JL		 1513 spin_lock_init(&domain->iommu_lock);
1514 INIT_LIST_HEAD(&domain->devices);
1515 if (vm) {
1516 domain->id = atomic_inc_return(&vm_domid);
1517 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
1518 }
2c2e2c38
FY		 1519
1520 return domain;
1521}
1522
1523static int iommu_attach_domain(struct dmar_domain *domain,
1524 struct intel_iommu *iommu)
1525{
1526 int num;
1527 unsigned long ndomains;
1528 unsigned long flags;
1529
ba395927
KA		 1530 ndomains = cap_ndoms(iommu->cap);
1531
1532 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1533
ba395927
KA		 1534 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1535 if (num >= ndomains) {
1536 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1537 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1538 return -ENOMEM;
ba395927
KA		 1539 }
1540
ba395927 1541 domain->id = num;
9ebd682e 1542 domain->iommu_count++;
2c2e2c38 1543 set_bit(num, iommu->domain_ids);
1b198bb0 1544 set_bit(iommu->seq_id, domain->iommu_bmp);
ba395927
KA		 1545 iommu->domains[num] = domain;
1546 spin_unlock_irqrestore(&iommu->lock, flags);
1547
2c2e2c38 1548 return 0;
ba395927
KA		 1549}
1550
2c2e2c38
FY		 1551static void iommu_detach_domain(struct dmar_domain *domain,
1552 struct intel_iommu *iommu)
ba395927
KA		 1553{
1554 unsigned long flags;
2c2e2c38 1555 int num, ndomains;
ba395927 1556
8c11e798 1557 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1558 ndomains = cap_ndoms(iommu->cap);
a45946ab 1559 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38 1560 if (iommu->domains[num] == domain) {
92d03cc8
JL		 1561 clear_bit(num, iommu->domain_ids);
1562 iommu->domains[num] = NULL;
2c2e2c38
FY		 1563 break;
1564 }
2c2e2c38 1565 }
8c11e798 1566 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1567}
1568
1569static struct iova_domain reserved_iova_list;
8a443df4 1570static struct lock_class_key reserved_rbtree_key;
ba395927 1571
51a63e67 1572static int dmar_init_reserved_ranges(void)
ba395927
KA		 1573{
1574 struct pci_dev *pdev = NULL;
1575 struct iova *iova;
1576 int i;
ba395927 1577
f661197e 1578 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1579
8a443df4
MG		 1580 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1581 &reserved_rbtree_key);
1582
ba395927
KA		 1583 /* IOAPIC ranges shouldn't be accessed by DMA */
1584 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1585 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1586 if (!iova) {
ba395927 1587 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1588 return -ENODEV;
1589 }
ba395927
KA		 1590
1591 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1592 for_each_pci_dev(pdev) {
1593 struct resource *r;
1594
1595 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1596 r = &pdev->resource[i];
1597 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1598 continue;
1a4a4551
DW		 1599 iova = reserve_iova(&reserved_iova_list,
1600 IOVA_PFN(r->start),
1601 IOVA_PFN(r->end));
51a63e67 1602 if (!iova) {
ba395927 1603 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1604 return -ENODEV;
1605 }
ba395927
KA		 1606 }
1607 }
51a63e67 1608 return 0;
ba395927
KA		 1609}
1610
1611static void domain_reserve_special_ranges(struct dmar_domain *domain)
1612{
1613 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1614}
1615
1616static inline int guestwidth_to_adjustwidth(int gaw)
1617{
1618 int agaw;
1619 int r = (gaw - 12) % 9;
1620
1621 if (r == 0)
1622 agaw = gaw;
1623 else
1624 agaw = gaw + 9 - r;
1625 if (agaw > 64)
1626 agaw = 64;
1627 return agaw;
1628}
1629
1630static int domain_init(struct dmar_domain *domain, int guest_width)
1631{
1632 struct intel_iommu *iommu;
1633 int adjust_width, agaw;
1634 unsigned long sagaw;
1635
f661197e 1636 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927
KA		 1637 domain_reserve_special_ranges(domain);
1638
1639 /* calculate AGAW */
8c11e798 1640 iommu = domain_get_iommu(domain);
ba395927
KA		 1641 if (guest_width > cap_mgaw(iommu->cap))
1642 guest_width = cap_mgaw(iommu->cap);
1643 domain->gaw = guest_width;
1644 adjust_width = guestwidth_to_adjustwidth(guest_width);
1645 agaw = width_to_agaw(adjust_width);
1646 sagaw = cap_sagaw(iommu->cap);
1647 if (!test_bit(agaw, &sagaw)) {
1648 /* hardware doesn't support it, choose a bigger one */
1649 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1650 agaw = find_next_bit(&sagaw, 5, agaw);
1651 if (agaw >= 5)
1652 return -ENODEV;
1653 }
1654 domain->agaw = agaw;
ba395927 1655
8e604097
WH		 1656 if (ecap_coherent(iommu->ecap))
1657 domain->iommu_coherency = 1;
1658 else
1659 domain->iommu_coherency = 0;
1660
58c610bd
SY		 1661 if (ecap_sc_support(iommu->ecap))
1662 domain->iommu_snooping = 1;
1663 else
1664 domain->iommu_snooping = 0;
1665
214e39aa
DW		 1666 if (intel_iommu_superpage)
1667 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1668 else
1669 domain->iommu_superpage = 0;
1670
4c923d47 1671 domain->nid = iommu->node;
c7151a8d 1672
ba395927 1673 /* always allocate the top pgd */
4c923d47 1674 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1675 if (!domain->pgd)
1676 return -ENOMEM;
5b6985ce 1677 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1678 return 0;
1679}
1680
1681static void domain_exit(struct dmar_domain *domain)
1682{
2c2e2c38
FY		 1683 struct dmar_drhd_unit *drhd;
1684 struct intel_iommu *iommu;
ea8ea460 1685 struct page *freelist = NULL;
ba395927
KA		 1686
1687 /* Domain 0 is reserved, so dont process it */
1688 if (!domain)
1689 return;
1690
7b668357
AW		 1691 /* Flush any lazy unmaps that may reference this domain */
1692 if (!intel_iommu_strict)
1693 flush_unmaps_timeout(0);
1694
92d03cc8 1695 /* remove associated devices */
ba395927 1696 domain_remove_dev_info(domain);
92d03cc8 1697
ba395927
KA		 1698 /* destroy iovas */
1699 put_iova_domain(&domain->iovad);
ba395927 1700
ea8ea460 1701 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1702
92d03cc8 1703 /* clear attached or cached domains */
0e242612 1704 rcu_read_lock();
2c2e2c38 1705 for_each_active_iommu(iommu, drhd)
92d03cc8
JL		 1706 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1707 test_bit(iommu->seq_id, domain->iommu_bmp))
2c2e2c38 1708 iommu_detach_domain(domain, iommu);
0e242612 1709 rcu_read_unlock();
2c2e2c38 1710
ea8ea460
DW		 1711 dma_free_pagelist(freelist);
1712
ba395927
KA		 1713 free_domain_mem(domain);
1714}
1715
64ae892b
DW		 1716static int domain_context_mapping_one(struct dmar_domain *domain,
1717 struct intel_iommu *iommu,
1718 u8 bus, u8 devfn, int translation)
ba395927
KA		 1719{
1720 struct context_entry *context;
ba395927 1721 unsigned long flags;
ea6606b0
WH		 1722 struct dma_pte *pgd;
1723 unsigned long num;
1724 unsigned long ndomains;
1725 int id;
1726 int agaw;
93a23a72 1727 struct device_domain_info *info = NULL;
ba395927
KA		 1728
1729 pr_debug("Set context mapping for %02x:%02x.%d\n",
1730 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1731
ba395927 1732 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1733 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1734 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1735
ba395927
KA		 1736 context = device_to_context_entry(iommu, bus, devfn);
1737 if (!context)
1738 return -ENOMEM;
1739 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1740 if (context_present(context)) {
ba395927
KA		 1741 spin_unlock_irqrestore(&iommu->lock, flags);
1742 return 0;
1743 }
1744
ea6606b0
WH		 1745 id = domain->id;
1746 pgd = domain->pgd;
1747
2c2e2c38
FY		 1748 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1749 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1750 int found = 0;
1751
1752 /* find an available domain id for this device in iommu */
1753 ndomains = cap_ndoms(iommu->cap);
a45946ab 1754 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1755 if (iommu->domains[num] == domain) {
1756 id = num;
1757 found = 1;
1758 break;
1759 }
ea6606b0
WH		 1760 }
1761
1762 if (found == 0) {
1763 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1764 if (num >= ndomains) {
1765 spin_unlock_irqrestore(&iommu->lock, flags);
1766 printk(KERN_ERR "IOMMU: no free domain ids\n");
1767 return -EFAULT;
1768 }
1769
1770 set_bit(num, iommu->domain_ids);
1771 iommu->domains[num] = domain;
1772 id = num;
1773 }
1774
1775 /* Skip top levels of page tables for
1776 * iommu which has less agaw than default.
1672af11 1777 * Unnecessary for PT mode.
ea6606b0 1778 */
1672af11
CW		 1779 if (translation != CONTEXT_TT_PASS_THROUGH) {
1780 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1781 pgd = phys_to_virt(dma_pte_addr(pgd));
1782 if (!dma_pte_present(pgd)) {
1783 spin_unlock_irqrestore(&iommu->lock, flags);
1784 return -ENOMEM;
1785 }
ea6606b0
WH		 1786 }
1787 }
1788 }
1789
1790 context_set_domain_id(context, id);
4ed0d3e6 1791
93a23a72 1792 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1793 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1794 translation = info ? CONTEXT_TT_DEV_IOTLB :
1795 CONTEXT_TT_MULTI_LEVEL;
1796 }
4ed0d3e6
FY		 1797 /*
1798 * In pass through mode, AW must be programmed to indicate the largest
1799 * AGAW value supported by hardware. And ASR is ignored by hardware.
1800 */
93a23a72 1801 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1802 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1803 else {
1804 context_set_address_root(context, virt_to_phys(pgd));
1805 context_set_address_width(context, iommu->agaw);
1806 }
4ed0d3e6
FY		 1807
1808 context_set_translation_type(context, translation);
c07e7d21
MM		 1809 context_set_fault_enable(context);
1810 context_set_present(context);
5331fe6f 1811 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1812
4c25a2c1
DW		 1813 /*
1814 * It's a non-present to present mapping. If hardware doesn't cache
1815 * non-present entry we only need to flush the write-buffer. If the
1816 * _does_ cache non-present entries, then it does so in the special
1817 * domain #0, which we have to flush:
1818 */
1819 if (cap_caching_mode(iommu->cap)) {
1820 iommu->flush.flush_context(iommu, 0,
1821 (((u16)bus) << 8) | devfn,
1822 DMA_CCMD_MASK_NOBIT,
1823 DMA_CCMD_DEVICE_INVL);
82653633 1824 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1825 } else {
ba395927 1826 iommu_flush_write_buffer(iommu);
4c25a2c1 1827 }
93a23a72 1828 iommu_enable_dev_iotlb(info);
ba395927 1829 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1830
1831 spin_lock_irqsave(&domain->iommu_lock, flags);
1b198bb0 1832 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
c7151a8d 1833 domain->iommu_count++;
4c923d47
SS		 1834 if (domain->iommu_count == 1)
1835 domain->nid = iommu->node;
58c610bd 1836 domain_update_iommu_cap(domain);
c7151a8d
WH		 1837 }
1838 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1839 return 0;
1840}
1841
1842static int
e1f167f3
DW		 1843domain_context_mapping(struct dmar_domain *domain, struct device *dev,
1844 int translation)
ba395927
KA		 1845{
1846 int ret;
e1f167f3 1847 struct pci_dev *pdev, *tmp, *parent;
64ae892b 1848 struct intel_iommu *iommu;
156baca8 1849 u8 bus, devfn;
64ae892b 1850
e1f167f3 1851 iommu = device_to_iommu(dev, &bus, &devfn);
64ae892b
DW		 1852 if (!iommu)
1853 return -ENODEV;
ba395927 1854
156baca8 1855 ret = domain_context_mapping_one(domain, iommu, bus, devfn,
4ed0d3e6 1856 translation);
e1f167f3 1857 if (ret || !dev_is_pci(dev))
ba395927
KA		 1858 return ret;
1859
1860 /* dependent device mapping */
e1f167f3 1861 pdev = to_pci_dev(dev);
ba395927
KA		 1862 tmp = pci_find_upstream_pcie_bridge(pdev);
1863 if (!tmp)
1864 return 0;
1865 /* Secondary interface's bus number and devfn 0 */
1866 parent = pdev->bus->self;
1867 while (parent != tmp) {
64ae892b 1868 ret = domain_context_mapping_one(domain, iommu,
276dbf99 1869 parent->bus->number,
4ed0d3e6 1870 parent->devfn, translation);
ba395927
KA		 1871 if (ret)
1872 return ret;
1873 parent = parent->bus->self;
1874 }
45e829ea 1875 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
64ae892b 1876 return domain_context_mapping_one(domain, iommu,
4ed0d3e6
FY		 1877 tmp->subordinate->number, 0,
1878 translation);
ba395927 1879 else /* this is a legacy PCI bridge */
64ae892b 1880 return domain_context_mapping_one(domain, iommu,
276dbf99 1881 tmp->bus->number,
4ed0d3e6
FY		 1882 tmp->devfn,
1883 translation);
ba395927
KA		 1884}
1885
e1f167f3 1886static int domain_context_mapped(struct device *dev)
ba395927
KA		 1887{
1888 int ret;
e1f167f3 1889 struct pci_dev *pdev, *tmp, *parent;
5331fe6f 1890 struct intel_iommu *iommu;
156baca8 1891 u8 bus, devfn;
5331fe6f 1892
e1f167f3 1893 iommu = device_to_iommu(dev, &bus, &devfn);
5331fe6f
WH		 1894 if (!iommu)
1895 return -ENODEV;
ba395927 1896
156baca8 1897 ret = device_context_mapped(iommu, bus, devfn);
e1f167f3 1898 if (!ret || !dev_is_pci(dev))
ba395927 1899 return ret;
e1f167f3 1900
ba395927 1901 /* dependent device mapping */
e1f167f3 1902 pdev = to_pci_dev(dev);
ba395927
KA		 1903 tmp = pci_find_upstream_pcie_bridge(pdev);
1904 if (!tmp)
1905 return ret;
1906 /* Secondary interface's bus number and devfn 0 */
1907 parent = pdev->bus->self;
1908 while (parent != tmp) {
8c11e798 1909 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1910 parent->devfn);
ba395927
KA		 1911 if (!ret)
1912 return ret;
1913 parent = parent->bus->self;
1914 }
5f4d91a1 1915 if (pci_is_pcie(tmp))
276dbf99
DW		 1916 return device_context_mapped(iommu, tmp->subordinate->number,
1917 0);
ba395927 1918 else
276dbf99
DW		 1919 return device_context_mapped(iommu, tmp->bus->number,
1920 tmp->devfn);
ba395927
KA		 1921}
1922
f532959b
FY		 1923/* Returns a number of VTD pages, but aligned to MM page size */
1924static inline unsigned long aligned_nrpages(unsigned long host_addr,
1925 size_t size)
1926{
1927 host_addr &= ~PAGE_MASK;
1928 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1929}
1930
6dd9a7c7
YS		 1931/* Return largest possible superpage level for a given mapping */
1932static inline int hardware_largepage_caps(struct dmar_domain *domain,
1933 unsigned long iov_pfn,
1934 unsigned long phy_pfn,
1935 unsigned long pages)
1936{
1937 int support, level = 1;
1938 unsigned long pfnmerge;
1939
1940 support = domain->iommu_superpage;
1941
1942 /* To use a large page, the virtual *and* physical addresses
1943 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1944 of them will mean we have to use smaller pages. So just
1945 merge them and check both at once. */
1946 pfnmerge = iov_pfn | phy_pfn;
1947
1948 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1949 pages >>= VTD_STRIDE_SHIFT;
1950 if (!pages)
1951 break;
1952 pfnmerge >>= VTD_STRIDE_SHIFT;
1953 level++;
1954 support--;
1955 }
1956 return level;
1957}
1958
9051aa02
DW		 1959static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1960 struct scatterlist *sg, unsigned long phys_pfn,
1961 unsigned long nr_pages, int prot)
e1605495
DW		 1962{
1963 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1964 phys_addr_t uninitialized_var(pteval);
e1605495 1965 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1966 unsigned long sg_res;
6dd9a7c7
YS		 1967 unsigned int largepage_lvl = 0;
1968 unsigned long lvl_pages = 0;
e1605495
DW		 1969
1970 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1971
1972 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1973 return -EINVAL;
1974
1975 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1976
9051aa02
DW		 1977 if (sg)
1978 sg_res = 0;
1979 else {
1980 sg_res = nr_pages + 1;
1981 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1982 }
1983
6dd9a7c7 1984 while (nr_pages > 0) {
c85994e4
DW		 1985 uint64_t tmp;
1986
e1605495 1987 if (!sg_res) {
f532959b 1988 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1989 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1990 sg->dma_length = sg->length;
1991 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1992 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1993 }
6dd9a7c7 1994
e1605495 1995 if (!pte) {
6dd9a7c7
YS		 1996 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1997
5cf0a76f 1998 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 1999 if (!pte)
2000 return -ENOMEM;
6dd9a7c7 2001 /* It is large page*/
6491d4d0 2002 if (largepage_lvl > 1) {
6dd9a7c7 2003 pteval |= DMA_PTE_LARGE_PAGE;
6491d4d0
WD		 2004 /* Ensure that old small page tables are removed to make room
2005 for superpage, if they exist. */
2006 dma_pte_clear_range(domain, iov_pfn,
2007 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
2008 dma_pte_free_pagetable(domain, iov_pfn,
2009 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
2010 } else {
6dd9a7c7 2011 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 2012 }
6dd9a7c7 2013
e1605495
DW		 2014 }
2015 /* We don't need lock here, nobody else
2016 * touches the iova range
2017 */
7766a3fb 2018 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2019 if (tmp) {
1bf20f0d 2020 static int dumps = 5;
c85994e4
DW		 2021 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2022 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2023 if (dumps) {
2024 dumps--;
2025 debug_dma_dump_mappings(NULL);
2026 }
2027 WARN_ON(1);
2028 }
6dd9a7c7
YS		 2029
2030 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2031
2032 BUG_ON(nr_pages < lvl_pages);
2033 BUG_ON(sg_res < lvl_pages);
2034
2035 nr_pages -= lvl_pages;
2036 iov_pfn += lvl_pages;
2037 phys_pfn += lvl_pages;
2038 pteval += lvl_pages * VTD_PAGE_SIZE;
2039 sg_res -= lvl_pages;
2040
2041 /* If the next PTE would be the first in a new page, then we
2042 need to flush the cache on the entries we've just written.
2043 And then we'll need to recalculate 'pte', so clear it and
2044 let it get set again in the if (!pte) block above.
2045
2046 If we're done (!nr_pages) we need to flush the cache too.
2047
2048 Also if we've been setting superpages, we may need to
2049 recalculate 'pte' and switch back to smaller pages for the
2050 end of the mapping, if the trailing size is not enough to
2051 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2052 pte++;
6dd9a7c7
YS		 2053 if (!nr_pages || first_pte_in_page(pte) ||
2054 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2055 domain_flush_cache(domain, first_pte,
2056 (void *)pte - (void *)first_pte);
2057 pte = NULL;
2058 }
6dd9a7c7
YS		 2059
2060 if (!sg_res && nr_pages)
e1605495
DW		 2061 sg = sg_next(sg);
2062 }
2063 return 0;
2064}
2065
9051aa02
DW		 2066static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2067 struct scatterlist *sg, unsigned long nr_pages,
2068 int prot)
ba395927 2069{
9051aa02
DW		 2070 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2071}
6f6a00e4 2072
9051aa02
DW		 2073static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2074 unsigned long phys_pfn, unsigned long nr_pages,
2075 int prot)
2076{
2077 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2078}
2079
c7151a8d 2080static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2081{
c7151a8d
WH		 2082 if (!iommu)
2083 return;
8c11e798
WH		 2084
2085 clear_context_table(iommu, bus, devfn);
2086 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2087 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2088 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2089}
2090
109b9b04
DW		 2091static inline void unlink_domain_info(struct device_domain_info *info)
2092{
2093 assert_spin_locked(&device_domain_lock);
2094 list_del(&info->link);
2095 list_del(&info->global);
2096 if (info->dev)
0bcb3e28 2097 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2098}
2099
ba395927
KA		 2100static void domain_remove_dev_info(struct dmar_domain *domain)
2101{
2102 struct device_domain_info *info;
92d03cc8 2103 unsigned long flags, flags2;
ba395927
KA		 2104
2105 spin_lock_irqsave(&device_domain_lock, flags);
2106 while (!list_empty(&domain->devices)) {
2107 info = list_entry(domain->devices.next,
2108 struct device_domain_info, link);
109b9b04 2109 unlink_domain_info(info);
ba395927
KA		 2110 spin_unlock_irqrestore(&device_domain_lock, flags);
2111
93a23a72 2112 iommu_disable_dev_iotlb(info);
7c7faa11 2113 iommu_detach_dev(info->iommu, info->bus, info->devfn);
ba395927 2114
92d03cc8 2115 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
7c7faa11 2116 iommu_detach_dependent_devices(info->iommu, info->dev);
92d03cc8
JL		 2117 /* clear this iommu in iommu_bmp, update iommu count
2118 * and capabilities
2119 */
2120 spin_lock_irqsave(&domain->iommu_lock, flags2);
7c7faa11 2121 if (test_and_clear_bit(info->iommu->seq_id,
92d03cc8
JL		 2122 domain->iommu_bmp)) {
2123 domain->iommu_count--;
2124 domain_update_iommu_cap(domain);
2125 }
2126 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2127 }
2128
2129 free_devinfo_mem(info);
ba395927
KA		 2130 spin_lock_irqsave(&device_domain_lock, flags);
2131 }
2132 spin_unlock_irqrestore(&device_domain_lock, flags);
2133}
2134
2135/*
2136 * find_domain
1525a29a 2137 * Note: we use struct device->archdata.iommu stores the info
ba395927 2138 */
1525a29a 2139static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2140{
2141 struct device_domain_info *info;
2142
2143 /* No lock here, assumes no domain exit in normal case */
1525a29a 2144 info = dev->archdata.iommu;
ba395927
KA		 2145 if (info)
2146 return info->domain;
2147 return NULL;
2148}
2149
5a8f40e8 2150static inline struct device_domain_info *
745f2586
JL		 2151dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2152{
2153 struct device_domain_info *info;
2154
2155 list_for_each_entry(info, &device_domain_list, global)
41e80dca 2156 if (info->iommu->segment == segment && info->bus == bus &&
745f2586 2157 info->devfn == devfn)
5a8f40e8 2158 return info;
745f2586
JL		 2159
2160 return NULL;
2161}
2162
5a8f40e8 2163static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
41e80dca 2164 int bus, int devfn,
b718cd3d
DW		 2165 struct device *dev,
2166 struct dmar_domain *domain)
745f2586 2167{
5a8f40e8 2168 struct dmar_domain *found = NULL;
745f2586
JL		 2169 struct device_domain_info *info;
2170 unsigned long flags;
2171
2172 info = alloc_devinfo_mem();
2173 if (!info)
b718cd3d 2174 return NULL;
745f2586 2175
745f2586
JL		 2176 info->bus = bus;
2177 info->devfn = devfn;
2178 info->dev = dev;
2179 info->domain = domain;
5a8f40e8 2180 info->iommu = iommu;
745f2586
JL		 2181 if (!dev)
2182 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2183
2184 spin_lock_irqsave(&device_domain_lock, flags);
2185 if (dev)
0bcb3e28 2186 found = find_domain(dev);
5a8f40e8
DW		 2187 else {
2188 struct device_domain_info *info2;
41e80dca 2189 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
5a8f40e8
DW		 2190 if (info2)
2191 found = info2->domain;
2192 }
745f2586
JL		 2193 if (found) {
2194 spin_unlock_irqrestore(&device_domain_lock, flags);
2195 free_devinfo_mem(info);
b718cd3d
DW		 2196 /* Caller must free the original domain */
2197 return found;
745f2586
JL		 2198 }
2199
b718cd3d
DW		 2200 list_add(&info->link, &domain->devices);
2201 list_add(&info->global, &device_domain_list);
2202 if (dev)
2203 dev->archdata.iommu = info;
2204 spin_unlock_irqrestore(&device_domain_lock, flags);
2205
2206 return domain;
745f2586
JL		 2207}
2208
ba395927 2209/* domain is initialized */
146922ec 2210static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
ba395927 2211{
e85bb5d4 2212 struct dmar_domain *domain, *free = NULL;
5a8f40e8
DW		 2213 struct intel_iommu *iommu = NULL;
2214 struct device_domain_info *info;
146922ec 2215 struct pci_dev *dev_tmp = NULL;
ba395927 2216 unsigned long flags;
146922ec 2217 u8 bus, devfn, bridge_bus, bridge_devfn;
ba395927 2218
146922ec 2219 domain = find_domain(dev);
ba395927
KA		 2220 if (domain)
2221 return domain;
2222
146922ec
DW		 2223 if (dev_is_pci(dev)) {
2224 struct pci_dev *pdev = to_pci_dev(dev);
2225 u16 segment;
276dbf99 2226
146922ec
DW		 2227 segment = pci_domain_nr(pdev->bus);
2228 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
2229 if (dev_tmp) {
2230 if (pci_is_pcie(dev_tmp)) {
2231 bridge_bus = dev_tmp->subordinate->number;
2232 bridge_devfn = 0;
2233 } else {
2234 bridge_bus = dev_tmp->bus->number;
2235 bridge_devfn = dev_tmp->devfn;
2236 }
2237 spin_lock_irqsave(&device_domain_lock, flags);
2238 info = dmar_search_domain_by_dev_info(segment, bus, devfn);
2239 if (info) {
2240 iommu = info->iommu;
2241 domain = info->domain;
2242 }
2243 spin_unlock_irqrestore(&device_domain_lock, flags);
2244 /* pcie-pci bridge already has a domain, uses it */
2245 if (info)
2246 goto found_domain;
5a8f40e8 2247 }
ba395927
KA		 2248 }
2249
146922ec
DW		 2250 iommu = device_to_iommu(dev, &bus, &devfn);
2251 if (!iommu)
2252 goto error;
ba395927 2253
146922ec 2254 /* Allocate and initialize new domain for the device */
92d03cc8 2255 domain = alloc_domain(false);
745f2586
JL		 2256 if (!domain)
2257 goto error;
2258 if (iommu_attach_domain(domain, iommu)) {
2fe9723d 2259 free_domain_mem(domain);
ba395927 2260 goto error;
2c2e2c38 2261 }
e85bb5d4
JL		 2262 free = domain;
2263 if (domain_init(domain, gaw))
ba395927 2264 goto error;
ba395927
KA		 2265
2266 /* register pcie-to-pci device */
2267 if (dev_tmp) {
146922ec
DW		 2268 domain = dmar_insert_dev_info(iommu, bridge_bus, bridge_devfn,
2269 NULL, domain);
b718cd3d 2270 if (!domain)
ba395927 2271 goto error;
ba395927
KA		 2272 }
2273
2274found_domain:
146922ec 2275 domain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
ba395927 2276error:
b718cd3d 2277 if (free != domain)
e85bb5d4 2278 domain_exit(free);
b718cd3d
DW		 2279
2280 return domain;
ba395927
KA		 2281}
2282
2c2e2c38 2283static int iommu_identity_mapping;
e0fc7e0b
DW		 2284#define IDENTMAP_ALL 1
2285#define IDENTMAP_GFX 2
2286#define IDENTMAP_AZALIA 4
2c2e2c38 2287
b213203e
DW		 2288static int iommu_domain_identity_map(struct dmar_domain *domain,
2289 unsigned long long start,
2290 unsigned long long end)
ba395927 2291{
c5395d5c
DW		 2292 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2293 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2294
2295 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2296 dma_to_mm_pfn(last_vpfn))) {
ba395927 2297 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2298 return -ENOMEM;
ba395927
KA		 2299 }
2300
c5395d5c
DW		 2301 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2302 start, end, domain->id);
ba395927
KA		 2303 /*
2304 * RMRR range might have overlap with physical memory range,
2305 * clear it first
2306 */
c5395d5c 2307 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2308
c5395d5c
DW		 2309 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2310 last_vpfn - first_vpfn + 1,
61df7443 2311 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2312}
2313
0b9d9753 2314static int iommu_prepare_identity_map(struct device *dev,
b213203e
DW		 2315 unsigned long long start,
2316 unsigned long long end)
2317{
2318 struct dmar_domain *domain;
2319 int ret;
2320
0b9d9753 2321 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2322 if (!domain)
2323 return -ENOMEM;
2324
19943b0e
DW		 2325 /* For _hardware_ passthrough, don't bother. But for software
2326 passthrough, we do it anyway -- it may indicate a memory
2327 range which is reserved in E820, so which didn't get set
2328 up to start with in si_domain */
2329 if (domain == si_domain && hw_pass_through) {
2330 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2331 dev_name(dev), start, end);
19943b0e
DW		 2332 return 0;
2333 }
2334
2335 printk(KERN_INFO
2336 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2337 dev_name(dev), start, end);
2ff729f5 2338
5595b528
DW		 2339 if (end < start) {
2340 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2341 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2342 dmi_get_system_info(DMI_BIOS_VENDOR),
2343 dmi_get_system_info(DMI_BIOS_VERSION),
2344 dmi_get_system_info(DMI_PRODUCT_VERSION));
2345 ret = -EIO;
2346 goto error;
2347 }
2348
2ff729f5
DW		 2349 if (end >> agaw_to_width(domain->agaw)) {
2350 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2351 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2352 agaw_to_width(domain->agaw),
2353 dmi_get_system_info(DMI_BIOS_VENDOR),
2354 dmi_get_system_info(DMI_BIOS_VERSION),
2355 dmi_get_system_info(DMI_PRODUCT_VERSION));
2356 ret = -EIO;
2357 goto error;
2358 }
19943b0e 2359
b213203e 2360 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2361 if (ret)
2362 goto error;
2363
2364 /* context entry init */
0b9d9753 2365 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2366 if (ret)
2367 goto error;
2368
2369 return 0;
2370
2371 error:
ba395927
KA		 2372 domain_exit(domain);
2373 return ret;
ba395927
KA		 2374}
2375
2376static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
0b9d9753 2377 struct device *dev)
ba395927 2378{
0b9d9753 2379 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927 2380 return 0;
0b9d9753
DW		 2381 return iommu_prepare_identity_map(dev, rmrr->base_address,
2382 rmrr->end_address);
ba395927
KA		 2383}
2384
d3f13810 2385#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2386static inline void iommu_prepare_isa(void)
2387{
2388 struct pci_dev *pdev;
2389 int ret;
2390
2391 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2392 if (!pdev)
2393 return;
2394
c7ab48d2 2395 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
0b9d9753 2396 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2397
2398 if (ret)
c7ab48d2
DW		 2399 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2400 "floppy might not work\n");
49a0429e
KA		 2401
2402}
2403#else
2404static inline void iommu_prepare_isa(void)
2405{
2406 return;
2407}
d3f13810 2408#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2409
2c2e2c38 2410static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2411
071e1374 2412static int __init si_domain_init(int hw)
2c2e2c38
FY		 2413{
2414 struct dmar_drhd_unit *drhd;
2415 struct intel_iommu *iommu;
c7ab48d2 2416 int nid, ret = 0;
2c2e2c38 2417
92d03cc8 2418 si_domain = alloc_domain(false);
2c2e2c38
FY		 2419 if (!si_domain)
2420 return -EFAULT;
2421
92d03cc8
JL		 2422 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2423
2c2e2c38
FY		 2424 for_each_active_iommu(iommu, drhd) {
2425 ret = iommu_attach_domain(si_domain, iommu);
2426 if (ret) {
2427 domain_exit(si_domain);
2428 return -EFAULT;
2429 }
2430 }
2431
2432 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2433 domain_exit(si_domain);
2434 return -EFAULT;
2435 }
2436
9544c003
JL		 2437 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2438 si_domain->id);
2c2e2c38 2439
19943b0e
DW		 2440 if (hw)
2441 return 0;
2442
c7ab48d2 2443 for_each_online_node(nid) {
5dfe8660
TH		 2444 unsigned long start_pfn, end_pfn;
2445 int i;
2446
2447 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2448 ret = iommu_domain_identity_map(si_domain,
2449 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2450 if (ret)
2451 return ret;
2452 }
c7ab48d2
DW		 2453 }
2454
2c2e2c38
FY		 2455 return 0;
2456}
2457
9b226624 2458static int identity_mapping(struct device *dev)
2c2e2c38
FY		 2459{
2460 struct device_domain_info *info;
2461
2462 if (likely(!iommu_identity_mapping))
2463 return 0;
2464
9b226624 2465 info = dev->archdata.iommu;
cb452a40
MT		 2466 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2467 return (info->domain == si_domain);
2c2e2c38 2468
2c2e2c38
FY		 2469 return 0;
2470}
2471
2472static int domain_add_dev_info(struct dmar_domain *domain,
5913c9bf 2473 struct device *dev, int translation)
2c2e2c38 2474{
0ac72664 2475 struct dmar_domain *ndomain;
5a8f40e8 2476 struct intel_iommu *iommu;
156baca8 2477 u8 bus, devfn;
5fe60f4e 2478 int ret;
2c2e2c38 2479
5913c9bf 2480 iommu = device_to_iommu(dev, &bus, &devfn);
5a8f40e8
DW		 2481 if (!iommu)
2482 return -ENODEV;
2483
5913c9bf 2484 ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
0ac72664
DW		 2485 if (ndomain != domain)
2486 return -EBUSY;
2c2e2c38 2487
5913c9bf 2488 ret = domain_context_mapping(domain, dev, translation);
e2ad23d0 2489 if (ret) {
5913c9bf 2490 domain_remove_one_dev_info(domain, dev);
e2ad23d0
DW		 2491 return ret;
2492 }
2493
2c2e2c38
FY		 2494 return 0;
2495}
2496
0b9d9753 2497static bool device_has_rmrr(struct device *dev)
ea2447f7
TM		 2498{
2499 struct dmar_rmrr_unit *rmrr;
832bd858 2500 struct device *tmp;
ea2447f7
TM		 2501 int i;
2502
0e242612 2503 rcu_read_lock();
ea2447f7 2504 for_each_rmrr_units(rmrr) {
b683b230
JL		 2505 /*
2506 * Return TRUE if this RMRR contains the device that
2507 * is passed in.
2508 */
2509 for_each_active_dev_scope(rmrr->devices,
2510 rmrr->devices_cnt, i, tmp)
0b9d9753 2511 if (tmp == dev) {
0e242612 2512 rcu_read_unlock();
ea2447f7 2513 return true;
b683b230 2514 }
ea2447f7 2515 }
0e242612 2516 rcu_read_unlock();
ea2447f7
TM		 2517 return false;
2518}
2519
3bdb2591 2520static int iommu_should_identity_map(struct device *dev, int startup)
6941af28 2521{
ea2447f7 2522
3bdb2591
DW		 2523 if (dev_is_pci(dev)) {
2524 struct pci_dev *pdev = to_pci_dev(dev);
ea2447f7 2525
3bdb2591
DW		 2526 /*
2527 * We want to prevent any device associated with an RMRR from
2528 * getting placed into the SI Domain. This is done because
2529 * problems exist when devices are moved in and out of domains
2530 * and their respective RMRR info is lost. We exempt USB devices
2531 * from this process due to their usage of RMRRs that are known
2532 * to not be needed after BIOS hand-off to OS.
2533 */
2534 if (device_has_rmrr(dev) &&
2535 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2536 return 0;
e0fc7e0b 2537
3bdb2591
DW		 2538 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2539 return 1;
e0fc7e0b 2540
3bdb2591
DW		 2541 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2542 return 1;
6941af28 2543
3bdb2591 2544 if (!(iommu_identity_mapping & IDENTMAP_ALL))
3dfc813d 2545 return 0;
3bdb2591
DW		 2546
2547 /*
2548 * We want to start off with all devices in the 1:1 domain, and
2549 * take them out later if we find they can't access all of memory.
2550 *
2551 * However, we can't do this for PCI devices behind bridges,
2552 * because all PCI devices behind the same bridge will end up
2553 * with the same source-id on their transactions.
2554 *
2555 * Practically speaking, we can't change things around for these
2556 * devices at run-time, because we can't be sure there'll be no
2557 * DMA transactions in flight for any of their siblings.
2558 *
2559 * So PCI devices (unless they're on the root bus) as well as
2560 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2561 * the 1:1 domain, just in _case_ one of their siblings turns out
2562 * not to be able to map all of memory.
2563 */
2564 if (!pci_is_pcie(pdev)) {
2565 if (!pci_is_root_bus(pdev->bus))
2566 return 0;
2567 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2568 return 0;
2569 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d 2570 return 0;
3bdb2591
DW		 2571 } else {
2572 if (device_has_rmrr(dev))
2573 return 0;
2574 }
3dfc813d 2575
3bdb2591 2576 /*
3dfc813d 2577 * At boot time, we don't yet know if devices will be 64-bit capable.
3bdb2591 2578 * Assume that they will — if they turn out not to be, then we can
3dfc813d
DW		 2579 * take them out of the 1:1 domain later.
2580 */
8fcc5372
CW		 2581 if (!startup) {
2582 /*
2583 * If the device's dma_mask is less than the system's memory
2584 * size then this is not a candidate for identity mapping.
2585 */
3bdb2591 2586 u64 dma_mask = *dev->dma_mask;
8fcc5372 2587
3bdb2591
DW		 2588 if (dev->coherent_dma_mask &&
2589 dev->coherent_dma_mask < dma_mask)
2590 dma_mask = dev->coherent_dma_mask;
8fcc5372 2591
3bdb2591 2592 return dma_mask >= dma_get_required_mask(dev);
8fcc5372 2593 }
6941af28
DW		 2594
2595 return 1;
2596}
2597
071e1374 2598static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2599{
2c2e2c38
FY		 2600 struct pci_dev *pdev = NULL;
2601 int ret;
2602
19943b0e 2603 ret = si_domain_init(hw);
2c2e2c38
FY		 2604 if (ret)
2605 return -EFAULT;
2606
2c2e2c38 2607 for_each_pci_dev(pdev) {
3bdb2591 2608 if (iommu_should_identity_map(&pdev->dev, 1)) {
5913c9bf 2609 ret = domain_add_dev_info(si_domain, &pdev->dev,
eae460b6
MT		 2610 hw ? CONTEXT_TT_PASS_THROUGH :
2611 CONTEXT_TT_MULTI_LEVEL);
2612 if (ret) {
2613 /* device not associated with an iommu */
2614 if (ret == -ENODEV)
2615 continue;
62edf5dc 2616 return ret;
eae460b6
MT		 2617 }
2618 pr_info("IOMMU: %s identity mapping for device %s\n",
2619 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2620 }
2c2e2c38
FY		 2621 }
2622
2623 return 0;
2624}
2625
b779260b 2626static int __init init_dmars(void)
ba395927
KA		 2627{
2628 struct dmar_drhd_unit *drhd;
2629 struct dmar_rmrr_unit *rmrr;
832bd858 2630 struct device *dev;
ba395927 2631 struct intel_iommu *iommu;
9d783ba0 2632 int i, ret;
2c2e2c38 2633
ba395927
KA		 2634 /*
2635 * for each drhd
2636 * allocate root
2637 * initialize and program root entry to not present
2638 * endfor
2639 */
2640 for_each_drhd_unit(drhd) {
5e0d2a6f 2641 /*
2642 * lock not needed as this is only incremented in the single
2643 * threaded kernel __init code path all other access are read
2644 * only
2645 */
1b198bb0
MT		 2646 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2647 g_num_of_iommus++;
2648 continue;
2649 }
2650 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2651 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2652 }
2653
d9630fe9
WH		 2654 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2655 GFP_KERNEL);
2656 if (!g_iommus) {
2657 printk(KERN_ERR "Allocating global iommu array failed\n");
2658 ret = -ENOMEM;
2659 goto error;
2660 }
2661
80b20dd8 2662 deferred_flush = kzalloc(g_num_of_iommus *
2663 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2664 if (!deferred_flush) {
5e0d2a6f 2665 ret = -ENOMEM;
989d51fc 2666 goto free_g_iommus;
5e0d2a6f 2667 }
2668
7c919779 2669 for_each_active_iommu(iommu, drhd) {
d9630fe9 2670 g_iommus[iommu->seq_id] = iommu;
ba395927 2671
e61d98d8
SS		 2672 ret = iommu_init_domains(iommu);
2673 if (ret)
989d51fc 2674 goto free_iommu;
e61d98d8 2675
ba395927
KA		 2676 /*
2677 * TBD:
2678 * we could share the same root & context tables
25985edc 2679 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2680 */
2681 ret = iommu_alloc_root_entry(iommu);
2682 if (ret) {
2683 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2684 goto free_iommu;
ba395927 2685 }
4ed0d3e6 2686 if (!ecap_pass_through(iommu->ecap))
19943b0e 2687 hw_pass_through = 0;
ba395927
KA		 2688 }
2689
1531a6a6
SS		 2690 /*
2691 * Start from the sane iommu hardware state.
2692 */
7c919779 2693 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2694 /*
2695 * If the queued invalidation is already initialized by us
2696 * (for example, while enabling interrupt-remapping) then
2697 * we got the things already rolling from a sane state.
2698 */
2699 if (iommu->qi)
2700 continue;
2701
2702 /*
2703 * Clear any previous faults.
2704 */
2705 dmar_fault(-1, iommu);
2706 /*
2707 * Disable queued invalidation if supported and already enabled
2708 * before OS handover.
2709 */
2710 dmar_disable_qi(iommu);
2711 }
2712
7c919779 2713 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2714 if (dmar_enable_qi(iommu)) {
2715 /*
2716 * Queued Invalidate not enabled, use Register Based
2717 * Invalidate
2718 */
2719 iommu->flush.flush_context = __iommu_flush_context;
2720 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2721 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2722 "invalidation\n",
680a7524 2723 iommu->seq_id,
b4e0f9eb 2724 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2725 } else {
2726 iommu->flush.flush_context = qi_flush_context;
2727 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2728 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2729 "invalidation\n",
680a7524 2730 iommu->seq_id,
b4e0f9eb 2731 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2732 }
2733 }
2734
19943b0e 2735 if (iommu_pass_through)
e0fc7e0b
DW		 2736 iommu_identity_mapping |= IDENTMAP_ALL;
2737
d3f13810 2738#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2739 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2740#endif
e0fc7e0b
DW		 2741
2742 check_tylersburg_isoch();
2743
ba395927 2744 /*
19943b0e
DW		 2745 * If pass through is not set or not enabled, setup context entries for
2746 * identity mappings for rmrr, gfx, and isa and may fall back to static
2747 * identity mapping if iommu_identity_mapping is set.
ba395927 2748 */
19943b0e
DW		 2749 if (iommu_identity_mapping) {
2750 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2751 if (ret) {
19943b0e 2752 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2753 goto free_iommu;
ba395927
KA		 2754 }
2755 }
ba395927 2756 /*
19943b0e
DW		 2757 * For each rmrr
2758 * for each dev attached to rmrr
2759 * do
2760 * locate drhd for dev, alloc domain for dev
2761 * allocate free domain
2762 * allocate page table entries for rmrr
2763 * if context not allocated for bus
2764 * allocate and init context
2765 * set present in root table for this bus
2766 * init context with domain, translation etc
2767 * endfor
2768 * endfor
ba395927 2769 */
19943b0e
DW		 2770 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2771 for_each_rmrr_units(rmrr) {
b683b230
JL		 2772 /* some BIOS lists non-exist devices in DMAR table. */
2773 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858 2774 i, dev) {
0b9d9753 2775 ret = iommu_prepare_rmrr_dev(rmrr, dev);
19943b0e
DW		 2776 if (ret)
2777 printk(KERN_ERR
2778 "IOMMU: mapping reserved region failed\n");
ba395927 2779 }
4ed0d3e6 2780 }
49a0429e 2781
19943b0e
DW		 2782 iommu_prepare_isa();
2783
ba395927
KA		 2784 /*
2785 * for each drhd
2786 * enable fault log
2787 * global invalidate context cache
2788 * global invalidate iotlb
2789 * enable translation
2790 */
7c919779 2791 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2792 if (drhd->ignored) {
2793 /*
2794 * we always have to disable PMRs or DMA may fail on
2795 * this device
2796 */
2797 if (force_on)
7c919779 2798 iommu_disable_protect_mem_regions(iommu);
ba395927 2799 continue;
51a63e67 2800 }
ba395927
KA		 2801
2802 iommu_flush_write_buffer(iommu);
2803
3460a6d9
KA		 2804 ret = dmar_set_interrupt(iommu);
2805 if (ret)
989d51fc 2806 goto free_iommu;
3460a6d9 2807
ba395927
KA		 2808 iommu_set_root_entry(iommu);
2809
4c25a2c1 2810 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2811 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2812
ba395927
KA		 2813 ret = iommu_enable_translation(iommu);
2814 if (ret)
989d51fc 2815 goto free_iommu;
b94996c9
DW		 2816
2817 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2818 }
2819
2820 return 0;
989d51fc
JL		 2821
2822free_iommu:
7c919779 2823 for_each_active_iommu(iommu, drhd)
a868e6b7 2824 free_dmar_iommu(iommu);
9bdc531e 2825 kfree(deferred_flush);
989d51fc 2826free_g_iommus:
d9630fe9 2827 kfree(g_iommus);
989d51fc 2828error:
ba395927
KA		 2829 return ret;
2830}
2831
5a5e02a6 2832/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2833static struct iova *intel_alloc_iova(struct device *dev,
2834 struct dmar_domain *domain,
2835 unsigned long nrpages, uint64_t dma_mask)
ba395927 2836{
ba395927 2837 struct iova *iova = NULL;
ba395927 2838
875764de
DW		 2839 /* Restrict dma_mask to the width that the iommu can handle */
2840 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2841
2842 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2843 /*
2844 * First try to allocate an io virtual address in
284901a9 2845 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2846 * from higher range
ba395927 2847 */
875764de
DW		 2848 iova = alloc_iova(&domain->iovad, nrpages,
2849 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2850 if (iova)
2851 return iova;
2852 }
2853 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2854 if (unlikely(!iova)) {
2855 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
207e3592 2856 nrpages, dev_name(dev));
f76aec76
KA		 2857 return NULL;
2858 }
2859
2860 return iova;
2861}
2862
d4b709f4 2863static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
f76aec76
KA		 2864{
2865 struct dmar_domain *domain;
2866 int ret;
2867
d4b709f4 2868 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
f76aec76 2869 if (!domain) {
d4b709f4
DW		 2870 printk(KERN_ERR "Allocating domain for %s failed",
2871 dev_name(dev));
4fe05bbc 2872 return NULL;
ba395927
KA		 2873 }
2874
2875 /* make sure context mapping is ok */
d4b709f4
DW		 2876 if (unlikely(!domain_context_mapped(dev))) {
2877 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
f76aec76 2878 if (ret) {
d4b709f4
DW		 2879 printk(KERN_ERR "Domain context map for %s failed",
2880 dev_name(dev));
4fe05bbc 2881 return NULL;
f76aec76 2882 }
ba395927
KA		 2883 }
2884
f76aec76
KA		 2885 return domain;
2886}
2887
d4b709f4 2888static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
147202aa
DW		 2889{
2890 struct device_domain_info *info;
2891
2892 /* No lock here, assumes no domain exit in normal case */
d4b709f4 2893 info = dev->archdata.iommu;
147202aa
DW		 2894 if (likely(info))
2895 return info->domain;
2896
2897 return __get_valid_domain_for_dev(dev);
2898}
2899
3d89194a 2900static int iommu_dummy(struct device *dev)
2c2e2c38 2901{
3d89194a 2902 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2c2e2c38
FY		 2903}
2904
ecb509ec 2905/* Check if the dev needs to go through non-identity map and unmap process.*/
73676832 2906static int iommu_no_mapping(struct device *dev)
2c2e2c38
FY		 2907{
2908 int found;
2909
3d89194a 2910 if (iommu_dummy(dev))
1e4c64c4
DW		 2911 return 1;
2912
2c2e2c38 2913 if (!iommu_identity_mapping)
1e4c64c4 2914 return 0;
2c2e2c38 2915
9b226624 2916 found = identity_mapping(dev);
2c2e2c38 2917 if (found) {
ecb509ec 2918 if (iommu_should_identity_map(dev, 0))
2c2e2c38
FY		 2919 return 1;
2920 else {
2921 /*
2922 * 32 bit DMA is removed from si_domain and fall back
2923 * to non-identity mapping.
2924 */
bf9c9eda 2925 domain_remove_one_dev_info(si_domain, dev);
2c2e2c38 2926 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
ecb509ec 2927 dev_name(dev));
2c2e2c38
FY		 2928 return 0;
2929 }
2930 } else {
2931 /*
2932 * In case of a detached 64 bit DMA device from vm, the device
2933 * is put into si_domain for identity mapping.
2934 */
ecb509ec 2935 if (iommu_should_identity_map(dev, 0)) {
2c2e2c38 2936 int ret;
5913c9bf 2937 ret = domain_add_dev_info(si_domain, dev,
5fe60f4e
DW		 2938 hw_pass_through ?
2939 CONTEXT_TT_PASS_THROUGH :
2940 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2941 if (!ret) {
2942 printk(KERN_INFO "64bit %s uses identity mapping\n",
ecb509ec 2943 dev_name(dev));
2c2e2c38
FY		 2944 return 1;
2945 }
2946 }
2947 }
2948
1e4c64c4 2949 return 0;
2c2e2c38
FY		 2950}
2951
5040a918 2952static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
bb9e6d65 2953 size_t size, int dir, u64 dma_mask)
f76aec76 2954{
f76aec76 2955 struct dmar_domain *domain;
5b6985ce 2956 phys_addr_t start_paddr;
f76aec76
KA		 2957 struct iova *iova;
2958 int prot = 0;
6865f0d1 2959 int ret;
8c11e798 2960 struct intel_iommu *iommu;
33041ec0 2961 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2962
2963 BUG_ON(dir == DMA_NONE);
2c2e2c38 2964
5040a918 2965 if (iommu_no_mapping(dev))
6865f0d1 2966 return paddr;
f76aec76 2967
5040a918 2968 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 2969 if (!domain)
2970 return 0;
2971
8c11e798 2972 iommu = domain_get_iommu(domain);
88cb6a74 2973 size = aligned_nrpages(paddr, size);
f76aec76 2974
5040a918 2975 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2976 if (!iova)
2977 goto error;
2978
ba395927
KA		 2979 /*
2980 * Check if DMAR supports zero-length reads on write only
2981 * mappings..
2982 */
2983 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2984 !cap_zlr(iommu->cap))
ba395927
KA		 2985 prot |= DMA_PTE_READ;
2986 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2987 prot |= DMA_PTE_WRITE;
2988 /*
6865f0d1 2989 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2990 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2991 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2992 * is not a big problem
2993 */
0ab36de2 2994 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2995 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2996 if (ret)
2997 goto error;
2998
1f0ef2aa
DW		 2999 /* it's a non-present to present mapping. Only flush if caching mode */
3000 if (cap_caching_mode(iommu->cap))
ea8ea460 3001 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 3002 else
8c11e798 3003 iommu_flush_write_buffer(iommu);
f76aec76 3004
03d6a246
DW		 3005 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3006 start_paddr += paddr & ~PAGE_MASK;
3007 return start_paddr;
ba395927 3008
ba395927 3009error:
f76aec76
KA		 3010 if (iova)
3011 __free_iova(&domain->iovad, iova);
4cf2e75d 3012 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5040a918 3013 dev_name(dev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3014 return 0;
3015}
3016
ffbbef5c
FT		 3017static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3018 unsigned long offset, size_t size,
3019 enum dma_data_direction dir,
3020 struct dma_attrs *attrs)
bb9e6d65 3021{
ffbbef5c 3022 return __intel_map_single(dev, page_to_phys(page) + offset, size,
46333e37 3023 dir, *dev->dma_mask);
bb9e6d65
FT		 3024}
3025
5e0d2a6f 3026static void flush_unmaps(void)
3027{
80b20dd8 3028 int i, j;
5e0d2a6f 3029
5e0d2a6f 3030 timer_on = 0;
3031
3032 /* just flush them all */
3033 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3034 struct intel_iommu *iommu = g_iommus[i];
3035 if (!iommu)
3036 continue;
c42d9f32 3037
9dd2fe89
YZ		 3038 if (!deferred_flush[i].next)
3039 continue;
3040
78d5f0f5
NA		 3041 /* In caching mode, global flushes turn emulation expensive */
3042 if (!cap_caching_mode(iommu->cap))
3043 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3044 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3045 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3046 unsigned long mask;
3047 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3048 struct dmar_domain *domain = deferred_flush[i].domain[j];
3049
3050 /* On real hardware multiple invalidations are expensive */
3051 if (cap_caching_mode(iommu->cap))
3052 iommu_flush_iotlb_psi(iommu, domain->id,
ea8ea460
DW		 3053 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3054 !deferred_flush[i].freelist[j], 0);
78d5f0f5
NA		 3055 else {
3056 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3057 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3058 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3059 }
93a23a72 3060 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3061 if (deferred_flush[i].freelist[j])
3062 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3063 }
9dd2fe89 3064 deferred_flush[i].next = 0;
5e0d2a6f 3065 }
3066
5e0d2a6f 3067 list_size = 0;
5e0d2a6f 3068}
3069
3070static void flush_unmaps_timeout(unsigned long data)
3071{
80b20dd8 3072 unsigned long flags;
3073
3074 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3075 flush_unmaps();
80b20dd8 3076 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3077}
3078
ea8ea460 3079static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3080{
3081 unsigned long flags;
80b20dd8 3082 int next, iommu_id;
8c11e798 3083 struct intel_iommu *iommu;
5e0d2a6f 3084
3085 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3086 if (list_size == HIGH_WATER_MARK)
3087 flush_unmaps();
3088
8c11e798
WH		 3089 iommu = domain_get_iommu(dom);
3090 iommu_id = iommu->seq_id;
c42d9f32 3091
80b20dd8 3092 next = deferred_flush[iommu_id].next;
3093 deferred_flush[iommu_id].domain[next] = dom;
3094 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3095 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3096 deferred_flush[iommu_id].next++;
5e0d2a6f 3097
3098 if (!timer_on) {
3099 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3100 timer_on = 1;
3101 }
3102 list_size++;
3103 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3104}
3105
ffbbef5c
FT		 3106static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3107 size_t size, enum dma_data_direction dir,
3108 struct dma_attrs *attrs)
ba395927 3109{
f76aec76 3110 struct dmar_domain *domain;
d794dc9b 3111 unsigned long start_pfn, last_pfn;
ba395927 3112 struct iova *iova;
8c11e798 3113 struct intel_iommu *iommu;
ea8ea460 3114 struct page *freelist;
ba395927 3115
73676832 3116 if (iommu_no_mapping(dev))
f76aec76 3117 return;
2c2e2c38 3118
1525a29a 3119 domain = find_domain(dev);
ba395927
KA		 3120 BUG_ON(!domain);
3121
8c11e798
WH		 3122 iommu = domain_get_iommu(domain);
3123
ba395927 3124 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3125 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3126 (unsigned long long)dev_addr))
ba395927 3127 return;
ba395927 3128
d794dc9b
DW		 3129 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3130 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3131
d794dc9b 3132 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
207e3592 3133 dev_name(dev), start_pfn, last_pfn);
ba395927 3134
ea8ea460 3135 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3136
5e0d2a6f 3137 if (intel_iommu_strict) {
03d6a246 3138 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3139 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3140 /* free iova */
3141 __free_iova(&domain->iovad, iova);
ea8ea460 3142 dma_free_pagelist(freelist);
5e0d2a6f 3143 } else {
ea8ea460 3144 add_unmap(domain, iova, freelist);
5e0d2a6f 3145 /*
3146 * queue up the release of the unmap to save the 1/6th of the
3147 * cpu used up by the iotlb flush operation...
3148 */
5e0d2a6f 3149 }
ba395927
KA		 3150}
3151
5040a918 3152static void *intel_alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 3153 dma_addr_t *dma_handle, gfp_t flags,
3154 struct dma_attrs *attrs)
ba395927
KA		 3155{
3156 void *vaddr;
3157 int order;
3158
5b6985ce 3159 size = PAGE_ALIGN(size);
ba395927 3160 order = get_order(size);
e8bb910d 3161
5040a918 3162 if (!iommu_no_mapping(dev))
e8bb910d 3163 flags &= ~(GFP_DMA | GFP_DMA32);
5040a918
DW		 3164 else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3165 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
e8bb910d
AW		 3166 flags |= GFP_DMA;
3167 else
3168 flags |= GFP_DMA32;
3169 }
ba395927
KA		 3170
3171 vaddr = (void *)__get_free_pages(flags, order);
3172 if (!vaddr)
3173 return NULL;
3174 memset(vaddr, 0, size);
3175
5040a918 3176 *dma_handle = __intel_map_single(dev, virt_to_bus(vaddr), size,
bb9e6d65 3177 DMA_BIDIRECTIONAL,
5040a918 3178 dev->coherent_dma_mask);
ba395927
KA		 3179 if (*dma_handle)
3180 return vaddr;
3181 free_pages((unsigned long)vaddr, order);
3182 return NULL;
3183}
3184
5040a918 3185static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
baa676fc 3186 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3187{
3188 int order;
3189
5b6985ce 3190 size = PAGE_ALIGN(size);
ba395927
KA		 3191 order = get_order(size);
3192
5040a918 3193 intel_unmap_page(dev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 3194 free_pages((unsigned long)vaddr, order);
3195}
3196
5040a918 3197static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
d7ab5c46
FT		 3198 int nelems, enum dma_data_direction dir,
3199 struct dma_attrs *attrs)
ba395927 3200{
ba395927 3201 struct dmar_domain *domain;
d794dc9b 3202 unsigned long start_pfn, last_pfn;
f76aec76 3203 struct iova *iova;
8c11e798 3204 struct intel_iommu *iommu;
ea8ea460 3205 struct page *freelist;
ba395927 3206
5040a918 3207 if (iommu_no_mapping(dev))
ba395927
KA		 3208 return;
3209
5040a918 3210 domain = find_domain(dev);
8c11e798
WH		 3211 BUG_ON(!domain);
3212
3213 iommu = domain_get_iommu(domain);
ba395927 3214
c03ab37c 3215 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 3216 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3217 (unsigned long long)sglist[0].dma_address))
f76aec76 3218 return;
f76aec76 3219
d794dc9b
DW		 3220 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3221 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76 3222
ea8ea460 3223 freelist = domain_unmap(domain, start_pfn, last_pfn);
f76aec76 3224
acea0018
DW		 3225 if (intel_iommu_strict) {
3226 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3227 last_pfn - start_pfn + 1, !freelist, 0);
acea0018
DW		 3228 /* free iova */
3229 __free_iova(&domain->iovad, iova);
ea8ea460 3230 dma_free_pagelist(freelist);
acea0018 3231 } else {
ea8ea460 3232 add_unmap(domain, iova, freelist);
acea0018
DW		 3233 /*
3234 * queue up the release of the unmap to save the 1/6th of the
3235 * cpu used up by the iotlb flush operation...
3236 */
3237 }
ba395927
KA		 3238}
3239
ba395927 3240static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3241 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3242{
3243 int i;
c03ab37c 3244 struct scatterlist *sg;
ba395927 3245
c03ab37c 3246 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3247 BUG_ON(!sg_page(sg));
4cf2e75d 3248 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3249 sg->dma_length = sg->length;
ba395927
KA		 3250 }
3251 return nelems;
3252}
3253
5040a918 3254static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
d7ab5c46 3255 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3256{
ba395927 3257 int i;
ba395927 3258 struct dmar_domain *domain;
f76aec76
KA		 3259 size_t size = 0;
3260 int prot = 0;
f76aec76
KA		 3261 struct iova *iova = NULL;
3262 int ret;
c03ab37c 3263 struct scatterlist *sg;
b536d24d 3264 unsigned long start_vpfn;
8c11e798 3265 struct intel_iommu *iommu;
ba395927
KA		 3266
3267 BUG_ON(dir == DMA_NONE);
5040a918
DW		 3268 if (iommu_no_mapping(dev))
3269 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
ba395927 3270
5040a918 3271 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3272 if (!domain)
3273 return 0;
3274
8c11e798
WH		 3275 iommu = domain_get_iommu(domain);
3276
b536d24d 3277 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3278 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3279
5040a918
DW		 3280 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3281 *dev->dma_mask);
f76aec76 3282 if (!iova) {
c03ab37c 3283 sglist->dma_length = 0;
f76aec76
KA		 3284 return 0;
3285 }
3286
3287 /*
3288 * Check if DMAR supports zero-length reads on write only
3289 * mappings..
3290 */
3291 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3292 !cap_zlr(iommu->cap))
f76aec76
KA		 3293 prot |= DMA_PTE_READ;
3294 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3295 prot |= DMA_PTE_WRITE;
3296
b536d24d 3297 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3298
f532959b 3299 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3300 if (unlikely(ret)) {
3301 /* clear the page */
3302 dma_pte_clear_range(domain, start_vpfn,
3303 start_vpfn + size - 1);
3304 /* free page tables */
3305 dma_pte_free_pagetable(domain, start_vpfn,
3306 start_vpfn + size - 1);
3307 /* free iova */
3308 __free_iova(&domain->iovad, iova);
3309 return 0;
ba395927
KA		 3310 }
3311
1f0ef2aa
DW		 3312 /* it's a non-present to present mapping. Only flush if caching mode */
3313 if (cap_caching_mode(iommu->cap))
ea8ea460 3314 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3315 else
8c11e798 3316 iommu_flush_write_buffer(iommu);
1f0ef2aa 3317
ba395927
KA		 3318 return nelems;
3319}
3320
dfb805e8
FT		 3321static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3322{
3323 return !dma_addr;
3324}
3325
160c1d8e 3326struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3327 .alloc = intel_alloc_coherent,
3328 .free = intel_free_coherent,
ba395927
KA		 3329 .map_sg = intel_map_sg,
3330 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3331 .map_page = intel_map_page,
3332 .unmap_page = intel_unmap_page,
dfb805e8 3333 .mapping_error = intel_mapping_error,
ba395927
KA		 3334};
3335
3336static inline int iommu_domain_cache_init(void)
3337{
3338 int ret = 0;
3339
3340 iommu_domain_cache = kmem_cache_create("iommu_domain",
3341 sizeof(struct dmar_domain),
3342 0,
3343 SLAB_HWCACHE_ALIGN,
3344
3345 NULL);
3346 if (!iommu_domain_cache) {
3347 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3348 ret = -ENOMEM;
3349 }
3350
3351 return ret;
3352}
3353
3354static inline int iommu_devinfo_cache_init(void)
3355{
3356 int ret = 0;
3357
3358 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3359 sizeof(struct device_domain_info),
3360 0,
3361 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3362 NULL);
3363 if (!iommu_devinfo_cache) {
3364 printk(KERN_ERR "Couldn't create devinfo cache\n");
3365 ret = -ENOMEM;
3366 }
3367
3368 return ret;
3369}
3370
3371static inline int iommu_iova_cache_init(void)
3372{
3373 int ret = 0;
3374
3375 iommu_iova_cache = kmem_cache_create("iommu_iova",
3376 sizeof(struct iova),
3377 0,
3378 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3379 NULL);
3380 if (!iommu_iova_cache) {
3381 printk(KERN_ERR "Couldn't create iova cache\n");
3382 ret = -ENOMEM;
3383 }
3384
3385 return ret;
3386}
3387
3388static int __init iommu_init_mempool(void)
3389{
3390 int ret;
3391 ret = iommu_iova_cache_init();
3392 if (ret)
3393 return ret;
3394
3395 ret = iommu_domain_cache_init();
3396 if (ret)
3397 goto domain_error;
3398
3399 ret = iommu_devinfo_cache_init();
3400 if (!ret)
3401 return ret;
3402
3403 kmem_cache_destroy(iommu_domain_cache);
3404domain_error:
3405 kmem_cache_destroy(iommu_iova_cache);
3406
3407 return -ENOMEM;
3408}
3409
3410static void __init iommu_exit_mempool(void)
3411{
3412 kmem_cache_destroy(iommu_devinfo_cache);
3413 kmem_cache_destroy(iommu_domain_cache);
3414 kmem_cache_destroy(iommu_iova_cache);
3415
3416}
3417
556ab45f
DW		 3418static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3419{
3420 struct dmar_drhd_unit *drhd;
3421 u32 vtbar;
3422 int rc;
3423
3424 /* We know that this device on this chipset has its own IOMMU.
3425 * If we find it under a different IOMMU, then the BIOS is lying
3426 * to us. Hope that the IOMMU for this device is actually
3427 * disabled, and it needs no translation...
3428 */
3429 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3430 if (rc) {
3431 /* "can't" happen */
3432 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3433 return;
3434 }
3435 vtbar &= 0xffff0000;
3436
3437 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3438 drhd = dmar_find_matched_drhd_unit(pdev);
3439 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3440 TAINT_FIRMWARE_WORKAROUND,
3441 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3442 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3443}
3444DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3445
ba395927
KA		 3446static void __init init_no_remapping_devices(void)
3447{
3448 struct dmar_drhd_unit *drhd;
832bd858 3449 struct device *dev;
b683b230 3450 int i;
ba395927
KA		 3451
3452 for_each_drhd_unit(drhd) {
3453 if (!drhd->include_all) {
b683b230
JL		 3454 for_each_active_dev_scope(drhd->devices,
3455 drhd->devices_cnt, i, dev)
3456 break;
832bd858 3457 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3458 if (i == drhd->devices_cnt)
3459 drhd->ignored = 1;
3460 }
3461 }
3462
7c919779 3463 for_each_active_drhd_unit(drhd) {
7c919779 3464 if (drhd->include_all)
ba395927
KA		 3465 continue;
3466
b683b230
JL		 3467 for_each_active_dev_scope(drhd->devices,
3468 drhd->devices_cnt, i, dev)
832bd858 3469 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3470 break;
ba395927
KA		 3471 if (i < drhd->devices_cnt)
3472 continue;
3473
c0771df8
DW		 3474 /* This IOMMU has *only* gfx devices. Either bypass it or
3475 set the gfx_mapped flag, as appropriate */
3476 if (dmar_map_gfx) {
3477 intel_iommu_gfx_mapped = 1;
3478 } else {
3479 drhd->ignored = 1;
b683b230
JL		 3480 for_each_active_dev_scope(drhd->devices,
3481 drhd->devices_cnt, i, dev)
832bd858 3482 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3483 }
3484 }
3485}
3486
f59c7b69
FY		 3487#ifdef CONFIG_SUSPEND
3488static int init_iommu_hw(void)
3489{
3490 struct dmar_drhd_unit *drhd;
3491 struct intel_iommu *iommu = NULL;
3492
3493 for_each_active_iommu(iommu, drhd)
3494 if (iommu->qi)
3495 dmar_reenable_qi(iommu);
3496
b779260b
JC		 3497 for_each_iommu(iommu, drhd) {
3498 if (drhd->ignored) {
3499 /*
3500 * we always have to disable PMRs or DMA may fail on
3501 * this device
3502 */
3503 if (force_on)
3504 iommu_disable_protect_mem_regions(iommu);
3505 continue;
3506 }
3507
f59c7b69
FY		 3508 iommu_flush_write_buffer(iommu);
3509
3510 iommu_set_root_entry(iommu);
3511
3512 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3513 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3514 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3515 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3516 if (iommu_enable_translation(iommu))
3517 return 1;
b94996c9 3518 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3519 }
3520
3521 return 0;
3522}
3523
3524static void iommu_flush_all(void)
3525{
3526 struct dmar_drhd_unit *drhd;
3527 struct intel_iommu *iommu;
3528
3529 for_each_active_iommu(iommu, drhd) {
3530 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3531 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3532 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3533 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3534 }
3535}
3536
134fac3f 3537static int iommu_suspend(void)
f59c7b69
FY		 3538{
3539 struct dmar_drhd_unit *drhd;
3540 struct intel_iommu *iommu = NULL;
3541 unsigned long flag;
3542
3543 for_each_active_iommu(iommu, drhd) {
3544 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3545 GFP_ATOMIC);
3546 if (!iommu->iommu_state)
3547 goto nomem;
3548 }
3549
3550 iommu_flush_all();
3551
3552 for_each_active_iommu(iommu, drhd) {
3553 iommu_disable_translation(iommu);
3554
1f5b3c3f 3555 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3556
3557 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3558 readl(iommu->reg + DMAR_FECTL_REG);
3559 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3560 readl(iommu->reg + DMAR_FEDATA_REG);
3561 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3562 readl(iommu->reg + DMAR_FEADDR_REG);
3563 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3564 readl(iommu->reg + DMAR_FEUADDR_REG);
3565
1f5b3c3f 3566 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3567 }
3568 return 0;
3569
3570nomem:
3571 for_each_active_iommu(iommu, drhd)
3572 kfree(iommu->iommu_state);
3573
3574 return -ENOMEM;
3575}
3576
134fac3f 3577static void iommu_resume(void)
f59c7b69
FY		 3578{
3579 struct dmar_drhd_unit *drhd;
3580 struct intel_iommu *iommu = NULL;
3581 unsigned long flag;
3582
3583 if (init_iommu_hw()) {
b779260b
JC		 3584 if (force_on)
3585 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3586 else
3587 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3588 return;
f59c7b69
FY		 3589 }
3590
3591 for_each_active_iommu(iommu, drhd) {
3592
1f5b3c3f 3593 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3594
3595 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3596 iommu->reg + DMAR_FECTL_REG);
3597 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3598 iommu->reg + DMAR_FEDATA_REG);
3599 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3600 iommu->reg + DMAR_FEADDR_REG);
3601 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3602 iommu->reg + DMAR_FEUADDR_REG);
3603
1f5b3c3f 3604 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3605 }
3606
3607 for_each_active_iommu(iommu, drhd)
3608 kfree(iommu->iommu_state);
f59c7b69
FY		 3609}
3610
134fac3f 3611static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3612 .resume = iommu_resume,
3613 .suspend = iommu_suspend,
3614};
3615
134fac3f 3616static void __init init_iommu_pm_ops(void)
f59c7b69 3617{
134fac3f 3618 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3619}
3620
3621#else
99592ba4 3622static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3623#endif /* CONFIG_PM */
3624
318fe7df
SS		 3625
3626int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3627{
3628 struct acpi_dmar_reserved_memory *rmrr;
3629 struct dmar_rmrr_unit *rmrru;
3630
3631 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3632 if (!rmrru)
3633 return -ENOMEM;
3634
3635 rmrru->hdr = header;
3636 rmrr = (struct acpi_dmar_reserved_memory *)header;
3637 rmrru->base_address = rmrr->base_address;
3638 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3639 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3640 ((void *)rmrr) + rmrr->header.length,
3641 &rmrru->devices_cnt);
3642 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3643 kfree(rmrru);
3644 return -ENOMEM;
3645 }
318fe7df 3646
2e455289 3647 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3648
2e455289 3649 return 0;
318fe7df
SS		 3650}
3651
318fe7df
SS		 3652int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3653{
3654 struct acpi_dmar_atsr *atsr;
3655 struct dmar_atsr_unit *atsru;
3656
3657 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3658 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3659 if (!atsru)
3660 return -ENOMEM;
3661
3662 atsru->hdr = hdr;
3663 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3664 if (!atsru->include_all) {
3665 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3666 (void *)atsr + atsr->header.length,
3667 &atsru->devices_cnt);
3668 if (atsru->devices_cnt && atsru->devices == NULL) {
3669 kfree(atsru);
3670 return -ENOMEM;
3671 }
3672 }
318fe7df 3673
0e242612 3674 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3675
3676 return 0;
3677}
3678
9bdc531e
JL		 3679static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3680{
3681 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3682 kfree(atsru);
3683}
3684
3685static void intel_iommu_free_dmars(void)
3686{
3687 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3688 struct dmar_atsr_unit *atsru, *atsr_n;
3689
3690 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3691 list_del(&rmrru->list);
3692 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3693 kfree(rmrru);
318fe7df
SS		 3694 }
3695
9bdc531e
JL		 3696 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3697 list_del(&atsru->list);
3698 intel_iommu_free_atsr(atsru);
3699 }
318fe7df
SS		 3700}
3701
3702int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3703{
b683b230 3704 int i, ret = 1;
318fe7df 3705 struct pci_bus *bus;
832bd858
DW		 3706 struct pci_dev *bridge = NULL;
3707 struct device *tmp;
318fe7df
SS		 3708 struct acpi_dmar_atsr *atsr;
3709 struct dmar_atsr_unit *atsru;
3710
3711 dev = pci_physfn(dev);
318fe7df 3712 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3713 bridge = bus->self;
318fe7df 3714 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3715 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3716 return 0;
b5f82ddf 3717 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3718 break;
318fe7df 3719 }
b5f82ddf
JL		 3720 if (!bridge)
3721 return 0;
318fe7df 3722
0e242612 3723 rcu_read_lock();
b5f82ddf
JL		 3724 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3725 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3726 if (atsr->segment != pci_domain_nr(dev->bus))
3727 continue;
3728
b683b230 3729 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 3730 if (tmp == &bridge->dev)
b683b230 3731 goto out;
b5f82ddf
JL		 3732
3733 if (atsru->include_all)
b683b230 3734 goto out;
b5f82ddf 3735 }
b683b230
JL		 3736 ret = 0;
3737out:
0e242612 3738 rcu_read_unlock();
318fe7df 3739
b683b230 3740 return ret;
318fe7df
SS		 3741}
3742
59ce0515
JL		 3743int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3744{
3745 int ret = 0;
3746 struct dmar_rmrr_unit *rmrru;
3747 struct dmar_atsr_unit *atsru;
3748 struct acpi_dmar_atsr *atsr;
3749 struct acpi_dmar_reserved_memory *rmrr;
3750
3751 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3752 return 0;
3753
3754 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3755 rmrr = container_of(rmrru->hdr,
3756 struct acpi_dmar_reserved_memory, header);
3757 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3758 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3759 ((void *)rmrr) + rmrr->header.length,
3760 rmrr->segment, rmrru->devices,
3761 rmrru->devices_cnt);
3762 if (ret > 0)
3763 break;
3764 else if(ret < 0)
3765 return ret;
3766 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3767 if (dmar_remove_dev_scope(info, rmrr->segment,
3768 rmrru->devices, rmrru->devices_cnt))
3769 break;
3770 }
3771 }
3772
3773 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3774 if (atsru->include_all)
3775 continue;
3776
3777 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3778 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3779 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3780 (void *)atsr + atsr->header.length,
3781 atsr->segment, atsru->devices,
3782 atsru->devices_cnt);
3783 if (ret > 0)
3784 break;
3785 else if(ret < 0)
3786 return ret;
3787 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3788 if (dmar_remove_dev_scope(info, atsr->segment,
3789 atsru->devices, atsru->devices_cnt))
3790 break;
3791 }
3792 }
3793
3794 return 0;
3795}
3796
99dcaded
FY		 3797/*
3798 * Here we only respond to action of unbound device from driver.
3799 *
3800 * Added device is not attached to its DMAR domain here yet. That will happen
3801 * when mapping the device to iova.
3802 */
3803static int device_notifier(struct notifier_block *nb,
3804 unsigned long action, void *data)
3805{
3806 struct device *dev = data;
99dcaded
FY		 3807 struct dmar_domain *domain;
3808
3d89194a 3809 if (iommu_dummy(dev))
44cd613c
DW		 3810 return 0;
3811
7e7dfab7
JL		 3812 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3813 action != BUS_NOTIFY_DEL_DEVICE)
3814 return 0;
3815
1525a29a 3816 domain = find_domain(dev);
99dcaded
FY		 3817 if (!domain)
3818 return 0;
3819
3a5670e8 3820 down_read(&dmar_global_lock);
bf9c9eda 3821 domain_remove_one_dev_info(domain, dev);
7e7dfab7
JL		 3822 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3823 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3824 list_empty(&domain->devices))
3825 domain_exit(domain);
3a5670e8 3826 up_read(&dmar_global_lock);
a97590e5 3827
99dcaded
FY		 3828 return 0;
3829}
3830
3831static struct notifier_block device_nb = {
3832 .notifier_call = device_notifier,
3833};
3834
75f05569
JL		 3835static int intel_iommu_memory_notifier(struct notifier_block *nb,
3836 unsigned long val, void *v)
3837{
3838 struct memory_notify *mhp = v;
3839 unsigned long long start, end;
3840 unsigned long start_vpfn, last_vpfn;
3841
3842 switch (val) {
3843 case MEM_GOING_ONLINE:
3844 start = mhp->start_pfn << PAGE_SHIFT;
3845 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3846 if (iommu_domain_identity_map(si_domain, start, end)) {
3847 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3848 start, end);
3849 return NOTIFY_BAD;
3850 }
3851 break;
3852
3853 case MEM_OFFLINE:
3854 case MEM_CANCEL_ONLINE:
3855 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3856 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3857 while (start_vpfn <= last_vpfn) {
3858 struct iova *iova;
3859 struct dmar_drhd_unit *drhd;
3860 struct intel_iommu *iommu;
ea8ea460 3861 struct page *freelist;
75f05569
JL		 3862
3863 iova = find_iova(&si_domain->iovad, start_vpfn);
3864 if (iova == NULL) {
3865 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3866 start_vpfn);
3867 break;
3868 }
3869
3870 iova = split_and_remove_iova(&si_domain->iovad, iova,
3871 start_vpfn, last_vpfn);
3872 if (iova == NULL) {
3873 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3874 start_vpfn, last_vpfn);
3875 return NOTIFY_BAD;
3876 }
3877
ea8ea460
DW		 3878 freelist = domain_unmap(si_domain, iova->pfn_lo,
3879 iova->pfn_hi);
3880
75f05569
JL		 3881 rcu_read_lock();
3882 for_each_active_iommu(iommu, drhd)
3883 iommu_flush_iotlb_psi(iommu, si_domain->id,
3884 iova->pfn_lo,
ea8ea460
DW		 3885 iova->pfn_hi - iova->pfn_lo + 1,
3886 !freelist, 0);
75f05569 3887 rcu_read_unlock();
ea8ea460 3888 dma_free_pagelist(freelist);
75f05569
JL		 3889
3890 start_vpfn = iova->pfn_hi + 1;
3891 free_iova_mem(iova);
3892 }
3893 break;
3894 }
3895
3896 return NOTIFY_OK;
3897}
3898
3899static struct notifier_block intel_iommu_memory_nb = {
3900 .notifier_call = intel_iommu_memory_notifier,
3901 .priority = 0
3902};
3903
ba395927
KA		 3904int __init intel_iommu_init(void)
3905{
9bdc531e 3906 int ret = -ENODEV;
3a93c841 3907 struct dmar_drhd_unit *drhd;
7c919779 3908 struct intel_iommu *iommu;
ba395927 3909
a59b50e9
JC		 3910 /* VT-d is required for a TXT/tboot launch, so enforce that */
3911 force_on = tboot_force_iommu();
3912
3a5670e8
JL		 3913 if (iommu_init_mempool()) {
3914 if (force_on)
3915 panic("tboot: Failed to initialize iommu memory\n");
3916 return -ENOMEM;
3917 }
3918
3919 down_write(&dmar_global_lock);
a59b50e9
JC		 3920 if (dmar_table_init()) {
3921 if (force_on)
3922 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 3923 goto out_free_dmar;
a59b50e9 3924 }
ba395927 3925
3a93c841
TI		 3926 /*
3927 * Disable translation if already enabled prior to OS handover.
3928 */
7c919779 3929 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 3930 if (iommu->gcmd & DMA_GCMD_TE)
3931 iommu_disable_translation(iommu);
3a93c841 3932
c2c7286a 3933 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3934 if (force_on)
3935 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 3936 goto out_free_dmar;
a59b50e9 3937 }
1886e8a9 3938
75f1cdf1 3939 if (no_iommu || dmar_disabled)
9bdc531e 3940 goto out_free_dmar;
2ae21010 3941
318fe7df
SS		 3942 if (list_empty(&dmar_rmrr_units))
3943 printk(KERN_INFO "DMAR: No RMRR found\n");
3944
3945 if (list_empty(&dmar_atsr_units))
3946 printk(KERN_INFO "DMAR: No ATSR found\n");
3947
51a63e67
JC		 3948 if (dmar_init_reserved_ranges()) {
3949 if (force_on)
3950 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 3951 goto out_free_reserved_range;
51a63e67 3952 }
ba395927
KA		 3953
3954 init_no_remapping_devices();
3955
b779260b 3956 ret = init_dmars();
ba395927 3957 if (ret) {
a59b50e9
JC		 3958 if (force_on)
3959 panic("tboot: Failed to initialize DMARs\n");
ba395927 3960 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 3961 goto out_free_reserved_range;
ba395927 3962 }
3a5670e8 3963 up_write(&dmar_global_lock);
ba395927
KA		 3964 printk(KERN_INFO
3965 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3966
5e0d2a6f 3967 init_timer(&unmap_timer);
75f1cdf1
FT		 3968#ifdef CONFIG_SWIOTLB
3969 swiotlb = 0;
3970#endif
19943b0e 3971 dma_ops = &intel_dma_ops;
4ed0d3e6 3972
134fac3f 3973 init_iommu_pm_ops();
a8bcbb0d 3974
4236d97d 3975 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 3976 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 3977 if (si_domain && !hw_pass_through)
3978 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 3979
8bc1f85c
ED		 3980 intel_iommu_enabled = 1;
3981
ba395927 3982 return 0;
9bdc531e
JL		 3983
3984out_free_reserved_range:
3985 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 3986out_free_dmar:
3987 intel_iommu_free_dmars();
3a5670e8
JL		 3988 up_write(&dmar_global_lock);
3989 iommu_exit_mempool();
9bdc531e 3990 return ret;
ba395927 3991}
e820482c 3992
3199aa6b 3993static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 3994 struct device *dev)
3199aa6b 3995{
0bcb3e28 3996 struct pci_dev *tmp, *parent, *pdev;
3199aa6b 3997
0bcb3e28 3998 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 3999 return;
4000
0bcb3e28
DW		 4001 pdev = to_pci_dev(dev);
4002
3199aa6b
HW		 4003 /* dependent device detach */
4004 tmp = pci_find_upstream_pcie_bridge(pdev);
4005 /* Secondary interface's bus number and devfn 0 */
4006 if (tmp) {
4007 parent = pdev->bus->self;
4008 while (parent != tmp) {
4009 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 4010 parent->devfn);
3199aa6b
HW		 4011 parent = parent->bus->self;
4012 }
45e829ea 4013 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 4014 iommu_detach_dev(iommu,
4015 tmp->subordinate->number, 0);
4016 else /* this is a legacy PCI bridge */
276dbf99
DW		 4017 iommu_detach_dev(iommu, tmp->bus->number,
4018 tmp->devfn);
3199aa6b
HW		 4019 }
4020}
4021
2c2e2c38 4022static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 4023 struct device *dev)
c7151a8d 4024{
bca2b916 4025 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4026 struct intel_iommu *iommu;
4027 unsigned long flags;
4028 int found = 0;
156baca8 4029 u8 bus, devfn;
c7151a8d 4030
bf9c9eda 4031 iommu = device_to_iommu(dev, &bus, &devfn);
c7151a8d
WH		 4032 if (!iommu)
4033 return;
4034
4035 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4036 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
bf9c9eda
DW		 4037 if (info->iommu == iommu && info->bus == bus &&
4038 info->devfn == devfn) {
109b9b04 4039 unlink_domain_info(info);
c7151a8d
WH		 4040 spin_unlock_irqrestore(&device_domain_lock, flags);
4041
93a23a72 4042 iommu_disable_dev_iotlb(info);
c7151a8d 4043 iommu_detach_dev(iommu, info->bus, info->devfn);
bf9c9eda 4044 iommu_detach_dependent_devices(iommu, dev);
c7151a8d
WH		 4045 free_devinfo_mem(info);
4046
4047 spin_lock_irqsave(&device_domain_lock, flags);
4048
4049 if (found)
4050 break;
4051 else
4052 continue;
4053 }
4054
4055 /* if there is no other devices under the same iommu
4056 * owned by this domain, clear this iommu in iommu_bmp
4057 * update iommu count and coherency
4058 */
8bbc4410 4059 if (info->iommu == iommu)
c7151a8d
WH		 4060 found = 1;
4061 }
4062
3e7abe25
RD		 4063 spin_unlock_irqrestore(&device_domain_lock, flags);
4064
c7151a8d
WH		 4065 if (found == 0) {
4066 unsigned long tmp_flags;
4067 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
1b198bb0 4068 clear_bit(iommu->seq_id, domain->iommu_bmp);
c7151a8d 4069 domain->iommu_count--;
58c610bd 4070 domain_update_iommu_cap(domain);
c7151a8d 4071 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 4072
9b4554b2
AW		 4073 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
4074 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
4075 spin_lock_irqsave(&iommu->lock, tmp_flags);
4076 clear_bit(domain->id, iommu->domain_ids);
4077 iommu->domains[domain->id] = NULL;
4078 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
4079 }
c7151a8d 4080 }
c7151a8d
WH		 4081}
4082
2c2e2c38 4083static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4084{
4085 int adjust_width;
4086
4087 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 4088 domain_reserve_special_ranges(domain);
4089
4090 /* calculate AGAW */
4091 domain->gaw = guest_width;
4092 adjust_width = guestwidth_to_adjustwidth(guest_width);
4093 domain->agaw = width_to_agaw(adjust_width);
4094
5e98c4b1 4095 domain->iommu_coherency = 0;
c5b15255 4096 domain->iommu_snooping = 0;
6dd9a7c7 4097 domain->iommu_superpage = 0;
fe40f1e0 4098 domain->max_addr = 0;
4c923d47 4099 domain->nid = -1;
5e98c4b1
WH		 4100
4101 /* always allocate the top pgd */
4c923d47 4102 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4103 if (!domain->pgd)
4104 return -ENOMEM;
4105 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4106 return 0;
4107}
4108
5d450806 4109static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 4110{
5d450806 4111 struct dmar_domain *dmar_domain;
38717946 4112
92d03cc8 4113 dmar_domain = alloc_domain(true);
5d450806 4114 if (!dmar_domain) {
38717946 4115 printk(KERN_ERR
5d450806
JR		 4116 "intel_iommu_domain_init: dmar_domain == NULL\n");
4117 return -ENOMEM;
38717946 4118 }
2c2e2c38 4119 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 4120 printk(KERN_ERR
5d450806 4121 "intel_iommu_domain_init() failed\n");
92d03cc8 4122 domain_exit(dmar_domain);
5d450806 4123 return -ENOMEM;
38717946 4124 }
8140a95d 4125 domain_update_iommu_cap(dmar_domain);
5d450806 4126 domain->priv = dmar_domain;
faa3d6f5 4127
8a0e715b
JR		 4128 domain->geometry.aperture_start = 0;
4129 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4130 domain->geometry.force_aperture = true;
4131
5d450806 4132 return 0;
38717946 4133}
38717946 4134
5d450806 4135static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 4136{
5d450806
JR		 4137 struct dmar_domain *dmar_domain = domain->priv;
4138
4139 domain->priv = NULL;
92d03cc8 4140 domain_exit(dmar_domain);
38717946 4141}
38717946 4142
4c5478c9
JR		 4143static int intel_iommu_attach_device(struct iommu_domain *domain,
4144 struct device *dev)
38717946 4145{
4c5478c9 4146 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 4147 struct intel_iommu *iommu;
4148 int addr_width;
156baca8 4149 u8 bus, devfn;
faa3d6f5 4150
7207d8f9
DW		 4151 /* normally dev is not mapped */
4152 if (unlikely(domain_context_mapped(dev))) {
faa3d6f5
WH		 4153 struct dmar_domain *old_domain;
4154
1525a29a 4155 old_domain = find_domain(dev);
faa3d6f5 4156 if (old_domain) {
2c2e2c38
FY		 4157 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
4158 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
bf9c9eda 4159 domain_remove_one_dev_info(old_domain, dev);
faa3d6f5
WH		 4160 else
4161 domain_remove_dev_info(old_domain);
4162 }
4163 }
4164
156baca8 4165 iommu = device_to_iommu(dev, &bus, &devfn);
fe40f1e0
WH		 4166 if (!iommu)
4167 return -ENODEV;
4168
4169 /* check if this iommu agaw is sufficient for max mapped address */
4170 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4171 if (addr_width > cap_mgaw(iommu->cap))
4172 addr_width = cap_mgaw(iommu->cap);
4173
4174 if (dmar_domain->max_addr > (1LL << addr_width)) {
4175 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4176 "sufficient for the mapped address (%llx)\n",
a99c47a2 4177 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4178 return -EFAULT;
4179 }
a99c47a2
TL		 4180 dmar_domain->gaw = addr_width;
4181
4182 /*
4183 * Knock out extra levels of page tables if necessary
4184 */
4185 while (iommu->agaw < dmar_domain->agaw) {
4186 struct dma_pte *pte;
4187
4188 pte = dmar_domain->pgd;
4189 if (dma_pte_present(pte)) {
25cbff16
SY		 4190 dmar_domain->pgd = (struct dma_pte *)
4191 phys_to_virt(dma_pte_addr(pte));
7a661013 4192 free_pgtable_page(pte);
a99c47a2
TL		 4193 }
4194 dmar_domain->agaw--;
4195 }
fe40f1e0 4196
5913c9bf 4197 return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
38717946 4198}
38717946 4199
4c5478c9
JR		 4200static void intel_iommu_detach_device(struct iommu_domain *domain,
4201 struct device *dev)
38717946 4202{
4c5478c9 4203 struct dmar_domain *dmar_domain = domain->priv;
4c5478c9 4204
bf9c9eda 4205 domain_remove_one_dev_info(dmar_domain, dev);
faa3d6f5 4206}
c7151a8d 4207
b146a1c9
JR		 4208static int intel_iommu_map(struct iommu_domain *domain,
4209 unsigned long iova, phys_addr_t hpa,
5009065d 4210 size_t size, int iommu_prot)
faa3d6f5 4211{
dde57a21 4212 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4213 u64 max_addr;
dde57a21 4214 int prot = 0;
faa3d6f5 4215 int ret;
fe40f1e0 4216
dde57a21
JR		 4217 if (iommu_prot & IOMMU_READ)
4218 prot |= DMA_PTE_READ;
4219 if (iommu_prot & IOMMU_WRITE)
4220 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4221 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4222 prot |= DMA_PTE_SNP;
dde57a21 4223
163cc52c 4224 max_addr = iova + size;
dde57a21 4225 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4226 u64 end;
4227
4228 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4229 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4230 if (end < max_addr) {
8954da1f 4231 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4232 "sufficient for the mapped address (%llx)\n",
8954da1f 4233 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4234 return -EFAULT;
4235 }
dde57a21 4236 dmar_domain->max_addr = max_addr;
fe40f1e0 4237 }
ad051221
DW		 4238 /* Round up size to next multiple of PAGE_SIZE, if it and
4239 the low bits of hpa would take us onto the next page */
88cb6a74 4240 size = aligned_nrpages(hpa, size);
ad051221
DW		 4241 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4242 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4243 return ret;
38717946 4244}
38717946 4245
5009065d 4246static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4247 unsigned long iova, size_t size)
38717946 4248{
dde57a21 4249 struct dmar_domain *dmar_domain = domain->priv;
ea8ea460
DW		 4250 struct page *freelist = NULL;
4251 struct intel_iommu *iommu;
4252 unsigned long start_pfn, last_pfn;
4253 unsigned int npages;
4254 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4255
4256 /* Cope with horrid API which requires us to unmap more than the
4257 size argument if it happens to be a large-page mapping. */
4258 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4259 BUG();
4260
4261 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4262 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4263
ea8ea460
DW		 4264 start_pfn = iova >> VTD_PAGE_SHIFT;
4265 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4266
4267 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4268
4269 npages = last_pfn - start_pfn + 1;
4270
4271 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4272 iommu = g_iommus[iommu_id];
4273
4274 /*
4275 * find bit position of dmar_domain
4276 */
4277 ndomains = cap_ndoms(iommu->cap);
4278 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4279 if (iommu->domains[num] == dmar_domain)
4280 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4281 npages, !freelist, 0);
4282 }
4283
4284 }
4285
4286 dma_free_pagelist(freelist);
fe40f1e0 4287
163cc52c
DW		 4288 if (dmar_domain->max_addr == iova + size)
4289 dmar_domain->max_addr = iova;
b146a1c9 4290
5cf0a76f 4291 return size;
38717946 4292}
38717946 4293
d14d6577 4294static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4295 dma_addr_t iova)
38717946 4296{
d14d6577 4297 struct dmar_domain *dmar_domain = domain->priv;
38717946 4298 struct dma_pte *pte;
5cf0a76f 4299 int level = 0;
faa3d6f5 4300 u64 phys = 0;
38717946 4301
5cf0a76f 4302 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4303 if (pte)
faa3d6f5 4304 phys = dma_pte_addr(pte);
38717946 4305
faa3d6f5 4306 return phys;
38717946 4307}
a8bcbb0d 4308
dbb9fd86
SY		 4309static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4310 unsigned long cap)
4311{
4312 struct dmar_domain *dmar_domain = domain->priv;
4313
4314 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4315 return dmar_domain->iommu_snooping;
323f99cb 4316 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4317 return irq_remapping_enabled;
dbb9fd86
SY		 4318
4319 return 0;
4320}
4321
783f157b 4322#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
70ae6f0d 4323
abdfdde2
AW		 4324static int intel_iommu_add_device(struct device *dev)
4325{
4326 struct pci_dev *pdev = to_pci_dev(dev);
3da4af0a 4327 struct pci_dev *bridge, *dma_pdev = NULL;
abdfdde2
AW		 4328 struct iommu_group *group;
4329 int ret;
156baca8 4330 u8 bus, devfn;
70ae6f0d 4331
156baca8 4332 if (!device_to_iommu(dev, &bus, &devfn))
70ae6f0d
AW		 4333 return -ENODEV;
4334
4335 bridge = pci_find_upstream_pcie_bridge(pdev);
4336 if (bridge) {
abdfdde2
AW		 4337 if (pci_is_pcie(bridge))
4338 dma_pdev = pci_get_domain_bus_and_slot(
4339 pci_domain_nr(pdev->bus),
4340 bridge->subordinate->number, 0);
3da4af0a 4341 if (!dma_pdev)
abdfdde2
AW		 4342 dma_pdev = pci_dev_get(bridge);
4343 } else
4344 dma_pdev = pci_dev_get(pdev);
4345
a4ff1fc2 4346 /* Account for quirked devices */
783f157b
AW		 4347 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4348
a4ff1fc2
AW		 4349 /*
4350 * If it's a multifunction device that does not support our
c14d2690
AW		 4351 * required ACS flags, add to the same group as lowest numbered
4352 * function that also does not suport the required ACS flags.
a4ff1fc2 4353 */
783f157b 4354 if (dma_pdev->multifunction &&
c14d2690
AW		 4355 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4356 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4357
4358 for (i = 0; i < 8; i++) {
4359 struct pci_dev *tmp;
4360
4361 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4362 if (!tmp)
4363 continue;
4364
4365 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4366 swap_pci_ref(&dma_pdev, tmp);
4367 break;
4368 }
4369 pci_dev_put(tmp);
4370 }
4371 }
783f157b 4372
a4ff1fc2
AW		 4373 /*
4374 * Devices on the root bus go through the iommu. If that's not us,
4375 * find the next upstream device and test ACS up to the root bus.
4376 * Finding the next device may require skipping virtual buses.
4377 */
783f157b 4378 while (!pci_is_root_bus(dma_pdev->bus)) {
a4ff1fc2
AW		 4379 struct pci_bus *bus = dma_pdev->bus;
4380
4381 while (!bus->self) {
4382 if (!pci_is_root_bus(bus))
4383 bus = bus->parent;
4384 else
4385 goto root_bus;
4386 }
4387
4388 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
783f157b
AW		 4389 break;
4390
a4ff1fc2 4391 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
783f157b
AW		 4392 }
4393
a4ff1fc2 4394root_bus:
abdfdde2
AW		 4395 group = iommu_group_get(&dma_pdev->dev);
4396 pci_dev_put(dma_pdev);
4397 if (!group) {
4398 group = iommu_group_alloc();
4399 if (IS_ERR(group))
4400 return PTR_ERR(group);
70ae6f0d
AW		 4401 }
4402
abdfdde2 4403 ret = iommu_group_add_device(group, dev);
bcb71abe 4404
abdfdde2
AW		 4405 iommu_group_put(group);
4406 return ret;
4407}
70ae6f0d 4408
abdfdde2
AW		 4409static void intel_iommu_remove_device(struct device *dev)
4410{
4411 iommu_group_remove_device(dev);
70ae6f0d
AW		 4412}
4413
a8bcbb0d
JR		 4414static struct iommu_ops intel_iommu_ops = {
4415 .domain_init = intel_iommu_domain_init,
4416 .domain_destroy = intel_iommu_domain_destroy,
4417 .attach_dev = intel_iommu_attach_device,
4418 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4419 .map = intel_iommu_map,
4420 .unmap = intel_iommu_unmap,
a8bcbb0d 4421 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4422 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4423 .add_device = intel_iommu_add_device,
4424 .remove_device = intel_iommu_remove_device,
6d1c56a9 4425 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4426};
9af88143 4427
9452618e
DV		 4428static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4429{
4430 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4431 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4432 dmar_map_gfx = 0;
4433}
4434
4435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4442
d34d6517 4443static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4444{
4445 /*
4446 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4447 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4448 */
4449 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4450 rwbf_quirk = 1;
4451}
4452
4453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4454DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4457DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4460
eecfd57f
AJ		 4461#define GGC 0x52
4462#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4463#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4464#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4465#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4466#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4467#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4468#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4469#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4470
d34d6517 4471static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4472{
4473 unsigned short ggc;
4474
eecfd57f 4475 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4476 return;
4477
eecfd57f 4478 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4479 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4480 dmar_map_gfx = 0;
6fbcfb3e
DW		 4481 } else if (dmar_map_gfx) {
4482 /* we have to ensure the gfx device is idle before we flush */
4483 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4484 intel_iommu_strict = 1;
4485 }
9eecabcb
DW		 4486}
4487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4491
e0fc7e0b
DW		 4492/* On Tylersburg chipsets, some BIOSes have been known to enable the
4493 ISOCH DMAR unit for the Azalia sound device, but not give it any
4494 TLB entries, which causes it to deadlock. Check for that. We do
4495 this in a function called from init_dmars(), instead of in a PCI
4496 quirk, because we don't want to print the obnoxious "BIOS broken"
4497 message if VT-d is actually disabled.
4498*/
4499static void __init check_tylersburg_isoch(void)
4500{
4501 struct pci_dev *pdev;
4502 uint32_t vtisochctrl;
4503
4504 /* If there's no Azalia in the system anyway, forget it. */
4505 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4506 if (!pdev)
4507 return;
4508 pci_dev_put(pdev);
4509
4510 /* System Management Registers. Might be hidden, in which case
4511 we can't do the sanity check. But that's OK, because the
4512 known-broken BIOSes _don't_ actually hide it, so far. */
4513 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4514 if (!pdev)
4515 return;
4516
4517 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4518 pci_dev_put(pdev);
4519 return;
4520 }
4521
4522 pci_dev_put(pdev);
4523
4524 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4525 if (vtisochctrl & 1)
4526 return;
4527
4528 /* Drop all bits other than the number of TLB entries */
4529 vtisochctrl &= 0x1c;
4530
4531 /* If we have the recommended number of TLB entries (16), fine. */
4532 if (vtisochctrl == 0x10)
4533 return;
4534
4535 /* Zero TLB entries? You get to ride the short bus to school. */
4536 if (!vtisochctrl) {
4537 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4538 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4539 dmi_get_system_info(DMI_BIOS_VENDOR),
4540 dmi_get_system_info(DMI_BIOS_VERSION),
4541 dmi_get_system_info(DMI_PRODUCT_VERSION));
4542 iommu_identity_mapping |= IDENTMAP_AZALIA;
4543 return;
4544 }
4545
4546 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4547 vtisochctrl);
4548}
Linux kernel - Deliverables
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