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iommu/vt-d: Simplify iommu check in domain_remove_one_dev_info()
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 18 */
19
20#include <linux/init.h>
21#include <linux/bitmap.h>
5e0d2a6f 22#include <linux/debugfs.h>
54485c30 23#include <linux/export.h>
ba395927
KA		 24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
ba395927
KA		 27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/dmar.h>
30#include <linux/dma-mapping.h>
31#include <linux/mempool.h>
75f05569 32#include <linux/memory.h>
5e0d2a6f 33#include <linux/timer.h>
38717946 34#include <linux/iova.h>
5d450806 35#include <linux/iommu.h>
38717946 36#include <linux/intel-iommu.h>
134fac3f 37#include <linux/syscore_ops.h>
69575d38 38#include <linux/tboot.h>
adb2fe02 39#include <linux/dmi.h>
5cdede24 40#include <linux/pci-ats.h>
0ee332c1 41#include <linux/memblock.h>
8a8f422d 42#include <asm/irq_remapping.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
078e1ee2 46#include "irq_remapping.h"
61e015ac 47#include "pci.h"
078e1ee2 48
5b6985ce
FY		 49#define ROOT_SIZE VTD_PAGE_SIZE
50#define CONTEXT_SIZE VTD_PAGE_SIZE
51
ba395927
KA		 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 55
56#define IOAPIC_RANGE_START (0xfee00000)
57#define IOAPIC_RANGE_END (0xfeefffff)
58#define IOVA_START_ADDR (0x1000)
59
60#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
4ed0d3e6 62#define MAX_AGAW_WIDTH 64
5c645b35 63#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 64
2ebe3151
DW		 65#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 73
f27be03b 74#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 75#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 76#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 77
df08cdc7
AM		 78/* page table handling */
79#define LEVEL_STRIDE (9)
80#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
6d1c56a9
OBC		 82/*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
df08cdc7
AM		 100static inline int agaw_to_level(int agaw)
101{
102 return agaw + 2;
103}
104
105static inline int agaw_to_width(int agaw)
106{
5c645b35 107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 108}
109
110static inline int width_to_agaw(int width)
111{
5c645b35 112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 113}
114
115static inline unsigned int level_to_offset_bits(int level)
116{
117 return (level - 1) * LEVEL_STRIDE;
118}
119
120static inline int pfn_level_offset(unsigned long pfn, int level)
121{
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123}
124
125static inline unsigned long level_mask(int level)
126{
127 return -1UL << level_to_offset_bits(level);
128}
129
130static inline unsigned long level_size(int level)
131{
132 return 1UL << level_to_offset_bits(level);
133}
134
135static inline unsigned long align_to_level(unsigned long pfn, int level)
136{
137 return (pfn + level_size(level) - 1) & level_mask(level);
138}
fd18de50 139
6dd9a7c7
YS		 140static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141{
5c645b35 142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 143}
144
dd4e8319
DW		 145/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148{
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150}
151
152static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153{
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155}
156static inline unsigned long page_to_dma_pfn(struct page *pg)
157{
158 return mm_to_dma_pfn(page_to_pfn(pg));
159}
160static inline unsigned long virt_to_dma_pfn(void *p)
161{
162 return page_to_dma_pfn(virt_to_page(p));
163}
164
d9630fe9
WH		 165/* global iommu list, set NULL for ignored DMAR units */
166static struct intel_iommu **g_iommus;
167
e0fc7e0b 168static void __init check_tylersburg_isoch(void);
9af88143
DW		 169static int rwbf_quirk;
170
b779260b
JC		 171/*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175static int force_on = 0;
176
46b08e1a
MM		 177/*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183struct root_entry {
184 u64 val;
185 u64 rsvd1;
186};
187#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188static inline bool root_present(struct root_entry *root)
189{
190 return (root->val & 1);
191}
192static inline void set_root_present(struct root_entry *root)
193{
194 root->val |= 1;
195}
196static inline void set_root_value(struct root_entry *root, unsigned long value)
197{
198 root->val |= value & VTD_PAGE_MASK;
199}
200
201static inline struct context_entry *
202get_context_addr_from_root(struct root_entry *root)
203{
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208}
209
7a8fc25e
MM		 210/*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221struct context_entry {
222 u64 lo;
223 u64 hi;
224};
c07e7d21
MM		 225
226static inline bool context_present(struct context_entry *context)
227{
228 return (context->lo & 1);
229}
230static inline void context_set_present(struct context_entry *context)
231{
232 context->lo |= 1;
233}
234
235static inline void context_set_fault_enable(struct context_entry *context)
236{
237 context->lo &= (((u64)-1) << 2) | 1;
238}
239
c07e7d21
MM		 240static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242{
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245}
246
247static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249{
250 context->lo |= value & VTD_PAGE_MASK;
251}
252
253static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255{
256 context->hi |= value & 7;
257}
258
259static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261{
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263}
264
265static inline void context_clear_entry(struct context_entry *context)
266{
267 context->lo = 0;
268 context->hi = 0;
269}
7a8fc25e 270
622ba12a
MM		 271/*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
9cf06697
SY		 276 * 8-10: available
277 * 11: snoop behavior
622ba12a
MM		 278 * 12-63: Host physcial address
279 */
280struct dma_pte {
281 u64 val;
282};
622ba12a 283
19c239ce
MM		 284static inline void dma_clear_pte(struct dma_pte *pte)
285{
286 pte->val = 0;
287}
288
19c239ce
MM		 289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
19c239ce
MM		 299static inline bool dma_pte_present(struct dma_pte *pte)
300{
301 return (pte->val & 3) != 0;
302}
622ba12a 303
4399c8bf
AK		 304static inline bool dma_pte_superpage(struct dma_pte *pte)
305{
306 return (pte->val & (1 << 7));
307}
308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
3b5410e7 323/* devices under the same p2p bridge are owned in one domain */
cdc7b837 324#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 325
1ce28feb
WH		 326/* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
2c2e2c38
FY		 331/* si_domain contains mulitple devices */
332#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
1b198bb0
MT		 334/* define the limit of IOMMUs supported in each domain */
335#ifdef CONFIG_X86
336# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
337#else
338# define IOMMU_UNITS_SUPPORTED 64
339#endif
340
99126f7c
MM		 341struct dmar_domain {
342 int id; /* domain id */
4c923d47 343 int nid; /* node id */
1b198bb0
MT		 344 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
345 /* bitmap of iommus this domain uses*/
99126f7c
MM		 346
347 struct list_head devices; /* all devices' list */
348 struct iova_domain iovad; /* iova's that belong to this domain */
349
350 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 351 int gaw; /* max guest address width */
352
353 /* adjusted guest address width, 0 is level 2 30-bit */
354 int agaw;
355
3b5410e7 356 int flags; /* flags to find out type of domain */
8e604097
WH		 357
358 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 359 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 360 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 361 int iommu_superpage;/* Level of superpages supported:
362 0 == 4KiB (no superpages), 1 == 2MiB,
363 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 364 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 365 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 366};
367
a647dacb
MM		 368/* PCI domain-device relationship */
369struct device_domain_info {
370 struct list_head link; /* link to domain siblings */
371 struct list_head global; /* link to global list */
276dbf99
DW		 372 int segment; /* PCI domain */
373 u8 bus; /* PCI bus number */
a647dacb 374 u8 devfn; /* PCI devfn number */
0bcb3e28 375 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 376 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 377 struct dmar_domain *domain; /* pointer to domain */
378};
379
b94e4117
JL		 380struct dmar_rmrr_unit {
381 struct list_head list; /* list of rmrr units */
382 struct acpi_dmar_header *hdr; /* ACPI header */
383 u64 base_address; /* reserved base address*/
384 u64 end_address; /* reserved end address */
832bd858 385 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 386 int devices_cnt; /* target device count */
387};
388
389struct dmar_atsr_unit {
390 struct list_head list; /* list of ATSR units */
391 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 392 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 393 int devices_cnt; /* target device count */
394 u8 include_all:1; /* include all ports */
395};
396
397static LIST_HEAD(dmar_atsr_units);
398static LIST_HEAD(dmar_rmrr_units);
399
400#define for_each_rmrr_units(rmrr) \
401 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
402
5e0d2a6f 403static void flush_unmaps_timeout(unsigned long data);
404
b707cb02 405static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 406
80b20dd8 407#define HIGH_WATER_MARK 250
408struct deferred_flush_tables {
409 int next;
410 struct iova *iova[HIGH_WATER_MARK];
411 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 412 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 413};
414
415static struct deferred_flush_tables *deferred_flush;
416
5e0d2a6f 417/* bitmap for indexing intel_iommus */
5e0d2a6f 418static int g_num_of_iommus;
419
420static DEFINE_SPINLOCK(async_umap_flush_lock);
421static LIST_HEAD(unmaps_to_do);
422
423static int timer_on;
424static long list_size;
5e0d2a6f 425
92d03cc8 426static void domain_exit(struct dmar_domain *domain);
ba395927 427static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117
JL		 428static void domain_remove_one_dev_info(struct dmar_domain *domain,
429 struct pci_dev *pdev);
92d03cc8 430static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 431 struct device *dev);
ba395927 432
d3f13810 433#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 434int dmar_disabled = 0;
435#else
436int dmar_disabled = 1;
d3f13810 437#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 438
8bc1f85c
ED		 439int intel_iommu_enabled = 0;
440EXPORT_SYMBOL_GPL(intel_iommu_enabled);
441
2d9e667e 442static int dmar_map_gfx = 1;
7d3b03ce 443static int dmar_forcedac;
5e0d2a6f 444static int intel_iommu_strict;
6dd9a7c7 445static int intel_iommu_superpage = 1;
ba395927 446
c0771df8
DW		 447int intel_iommu_gfx_mapped;
448EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
449
ba395927
KA		 450#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
451static DEFINE_SPINLOCK(device_domain_lock);
452static LIST_HEAD(device_domain_list);
453
a8bcbb0d
JR		 454static struct iommu_ops intel_iommu_ops;
455
ba395927
KA		 456static int __init intel_iommu_setup(char *str)
457{
458 if (!str)
459 return -EINVAL;
460 while (*str) {
0cd5c3c8
KM		 461 if (!strncmp(str, "on", 2)) {
462 dmar_disabled = 0;
463 printk(KERN_INFO "Intel-IOMMU: enabled\n");
464 } else if (!strncmp(str, "off", 3)) {
ba395927 465 dmar_disabled = 1;
0cd5c3c8 466 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 467 } else if (!strncmp(str, "igfx_off", 8)) {
468 dmar_map_gfx = 0;
469 printk(KERN_INFO
470 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 471 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 472 printk(KERN_INFO
7d3b03ce
KA		 473 "Intel-IOMMU: Forcing DAC for PCI devices\n");
474 dmar_forcedac = 1;
5e0d2a6f 475 } else if (!strncmp(str, "strict", 6)) {
476 printk(KERN_INFO
477 "Intel-IOMMU: disable batched IOTLB flush\n");
478 intel_iommu_strict = 1;
6dd9a7c7
YS		 479 } else if (!strncmp(str, "sp_off", 6)) {
480 printk(KERN_INFO
481 "Intel-IOMMU: disable supported super page\n");
482 intel_iommu_superpage = 0;
ba395927
KA		 483 }
484
485 str += strcspn(str, ",");
486 while (*str == ',')
487 str++;
488 }
489 return 0;
490}
491__setup("intel_iommu=", intel_iommu_setup);
492
493static struct kmem_cache *iommu_domain_cache;
494static struct kmem_cache *iommu_devinfo_cache;
495static struct kmem_cache *iommu_iova_cache;
496
4c923d47 497static inline void *alloc_pgtable_page(int node)
eb3fa7cb 498{
4c923d47
SS		 499 struct page *page;
500 void *vaddr = NULL;
eb3fa7cb 501
4c923d47
SS		 502 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
503 if (page)
504 vaddr = page_address(page);
eb3fa7cb 505 return vaddr;
ba395927
KA		 506}
507
508static inline void free_pgtable_page(void *vaddr)
509{
510 free_page((unsigned long)vaddr);
511}
512
513static inline void *alloc_domain_mem(void)
514{
354bb65e 515 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 516}
517
38717946 518static void free_domain_mem(void *vaddr)
ba395927
KA		 519{
520 kmem_cache_free(iommu_domain_cache, vaddr);
521}
522
523static inline void * alloc_devinfo_mem(void)
524{
354bb65e 525 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 526}
527
528static inline void free_devinfo_mem(void *vaddr)
529{
530 kmem_cache_free(iommu_devinfo_cache, vaddr);
531}
532
533struct iova *alloc_iova_mem(void)
534{
354bb65e 535 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 536}
537
538void free_iova_mem(struct iova *iova)
539{
540 kmem_cache_free(iommu_iova_cache, iova);
541}
542
1b573683 543
4ed0d3e6 544static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 545{
546 unsigned long sagaw;
547 int agaw = -1;
548
549 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 550 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 551 agaw >= 0; agaw--) {
552 if (test_bit(agaw, &sagaw))
553 break;
554 }
555
556 return agaw;
557}
558
4ed0d3e6
FY		 559/*
560 * Calculate max SAGAW for each iommu.
561 */
562int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
563{
564 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
565}
566
567/*
568 * calculate agaw for each iommu.
569 * "SAGAW" may be different across iommus, use a default agaw, and
570 * get a supported less agaw for iommus that don't support the default agaw.
571 */
572int iommu_calculate_agaw(struct intel_iommu *iommu)
573{
574 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
575}
576
2c2e2c38 577/* This functionin only returns single iommu in a domain */
8c11e798
WH		 578static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
579{
580 int iommu_id;
581
2c2e2c38 582 /* si_domain and vm domain should not get here. */
1ce28feb 583 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 584 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 585
1b198bb0 586 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 587 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
588 return NULL;
589
590 return g_iommus[iommu_id];
591}
592
8e604097
WH		 593static void domain_update_iommu_coherency(struct dmar_domain *domain)
594{
d0501960
DW		 595 struct dmar_drhd_unit *drhd;
596 struct intel_iommu *iommu;
597 int i, found = 0;
2e12bc29 598
d0501960 599 domain->iommu_coherency = 1;
8e604097 600
1b198bb0 601 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
d0501960 602 found = 1;
8e604097
WH		 603 if (!ecap_coherent(g_iommus[i]->ecap)) {
604 domain->iommu_coherency = 0;
605 break;
606 }
8e604097 607 }
d0501960
DW		 608 if (found)
609 return;
610
611 /* No hardware attached; use lowest common denominator */
612 rcu_read_lock();
613 for_each_active_iommu(iommu, drhd) {
614 if (!ecap_coherent(iommu->ecap)) {
615 domain->iommu_coherency = 0;
616 break;
617 }
618 }
619 rcu_read_unlock();
8e604097
WH		 620}
621
58c610bd
SY		 622static void domain_update_iommu_snooping(struct dmar_domain *domain)
623{
624 int i;
625
626 domain->iommu_snooping = 1;
627
1b198bb0 628 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 629 if (!ecap_sc_support(g_iommus[i]->ecap)) {
630 domain->iommu_snooping = 0;
631 break;
632 }
58c610bd
SY		 633 }
634}
635
6dd9a7c7
YS		 636static void domain_update_iommu_superpage(struct dmar_domain *domain)
637{
8140a95d
AK		 638 struct dmar_drhd_unit *drhd;
639 struct intel_iommu *iommu = NULL;
640 int mask = 0xf;
6dd9a7c7
YS		 641
642 if (!intel_iommu_superpage) {
643 domain->iommu_superpage = 0;
644 return;
645 }
646
8140a95d 647 /* set iommu_superpage to the smallest common denominator */
0e242612 648 rcu_read_lock();
8140a95d
AK		 649 for_each_active_iommu(iommu, drhd) {
650 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 651 if (!mask) {
652 break;
653 }
654 }
0e242612
JL		 655 rcu_read_unlock();
656
6dd9a7c7
YS		 657 domain->iommu_superpage = fls(mask);
658}
659
58c610bd
SY		 660/* Some capabilities may be different across iommus */
661static void domain_update_iommu_cap(struct dmar_domain *domain)
662{
663 domain_update_iommu_coherency(domain);
664 domain_update_iommu_snooping(domain);
6dd9a7c7 665 domain_update_iommu_superpage(domain);
58c610bd
SY		 666}
667
276dbf99 668static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 669{
670 struct dmar_drhd_unit *drhd = NULL;
b683b230 671 struct intel_iommu *iommu;
832bd858
DW		 672 struct device *dev;
673 struct pci_dev *pdev;
c7151a8d
WH		 674 int i;
675
0e242612 676 rcu_read_lock();
b683b230 677 for_each_active_iommu(iommu, drhd) {
276dbf99
DW		 678 if (segment != drhd->segment)
679 continue;
c7151a8d 680
b683b230
JL		 681 for_each_active_dev_scope(drhd->devices,
682 drhd->devices_cnt, i, dev) {
832bd858
DW		 683 if (!dev_is_pci(dev))
684 continue;
685 pdev = to_pci_dev(dev);
686 if (pdev->bus->number == bus && pdev->devfn == devfn)
b683b230 687 goto out;
832bd858
DW		 688 if (pdev->subordinate &&
689 pdev->subordinate->number <= bus &&
690 pdev->subordinate->busn_res.end >= bus)
b683b230 691 goto out;
924b6231 692 }
c7151a8d
WH		 693
694 if (drhd->include_all)
b683b230 695 goto out;
c7151a8d 696 }
b683b230
JL		 697 iommu = NULL;
698out:
0e242612 699 rcu_read_unlock();
c7151a8d 700
b683b230 701 return iommu;
c7151a8d
WH		 702}
703
5331fe6f
WH		 704static void domain_flush_cache(struct dmar_domain *domain,
705 void *addr, int size)
706{
707 if (!domain->iommu_coherency)
708 clflush_cache_range(addr, size);
709}
710
ba395927
KA		 711/* Gets context entry for a given bus and devfn */
712static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
713 u8 bus, u8 devfn)
714{
715 struct root_entry *root;
716 struct context_entry *context;
717 unsigned long phy_addr;
718 unsigned long flags;
719
720 spin_lock_irqsave(&iommu->lock, flags);
721 root = &iommu->root_entry[bus];
722 context = get_context_addr_from_root(root);
723 if (!context) {
4c923d47
SS		 724 context = (struct context_entry *)
725 alloc_pgtable_page(iommu->node);
ba395927
KA		 726 if (!context) {
727 spin_unlock_irqrestore(&iommu->lock, flags);
728 return NULL;
729 }
5b6985ce 730 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 731 phy_addr = virt_to_phys((void *)context);
732 set_root_value(root, phy_addr);
733 set_root_present(root);
734 __iommu_flush_cache(iommu, root, sizeof(*root));
735 }
736 spin_unlock_irqrestore(&iommu->lock, flags);
737 return &context[devfn];
738}
739
740static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
741{
742 struct root_entry *root;
743 struct context_entry *context;
744 int ret;
745 unsigned long flags;
746
747 spin_lock_irqsave(&iommu->lock, flags);
748 root = &iommu->root_entry[bus];
749 context = get_context_addr_from_root(root);
750 if (!context) {
751 ret = 0;
752 goto out;
753 }
c07e7d21 754 ret = context_present(&context[devfn]);
ba395927
KA		 755out:
756 spin_unlock_irqrestore(&iommu->lock, flags);
757 return ret;
758}
759
760static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
761{
762 struct root_entry *root;
763 struct context_entry *context;
764 unsigned long flags;
765
766 spin_lock_irqsave(&iommu->lock, flags);
767 root = &iommu->root_entry[bus];
768 context = get_context_addr_from_root(root);
769 if (context) {
c07e7d21 770 context_clear_entry(&context[devfn]);
ba395927
KA		 771 __iommu_flush_cache(iommu, &context[devfn], \
772 sizeof(*context));
773 }
774 spin_unlock_irqrestore(&iommu->lock, flags);
775}
776
777static void free_context_table(struct intel_iommu *iommu)
778{
779 struct root_entry *root;
780 int i;
781 unsigned long flags;
782 struct context_entry *context;
783
784 spin_lock_irqsave(&iommu->lock, flags);
785 if (!iommu->root_entry) {
786 goto out;
787 }
788 for (i = 0; i < ROOT_ENTRY_NR; i++) {
789 root = &iommu->root_entry[i];
790 context = get_context_addr_from_root(root);
791 if (context)
792 free_pgtable_page(context);
793 }
794 free_pgtable_page(iommu->root_entry);
795 iommu->root_entry = NULL;
796out:
797 spin_unlock_irqrestore(&iommu->lock, flags);
798}
799
b026fd28 800static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 801 unsigned long pfn, int *target_level)
ba395927 802{
b026fd28 803 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 804 struct dma_pte *parent, *pte = NULL;
805 int level = agaw_to_level(domain->agaw);
4399c8bf 806 int offset;
ba395927
KA		 807
808 BUG_ON(!domain->pgd);
f9423606
JS		 809
810 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
811 /* Address beyond IOMMU's addressing capabilities. */
812 return NULL;
813
ba395927
KA		 814 parent = domain->pgd;
815
5cf0a76f 816 while (1) {
ba395927
KA		 817 void *tmp_page;
818
b026fd28 819 offset = pfn_level_offset(pfn, level);
ba395927 820 pte = &parent[offset];
5cf0a76f 821 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 822 break;
5cf0a76f 823 if (level == *target_level)
ba395927
KA		 824 break;
825
19c239ce 826 if (!dma_pte_present(pte)) {
c85994e4
DW		 827 uint64_t pteval;
828
4c923d47 829 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 830
206a73c1 831 if (!tmp_page)
ba395927 832 return NULL;
206a73c1 833
c85994e4 834 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 835 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 836 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
837 /* Someone else set it while we were thinking; use theirs. */
838 free_pgtable_page(tmp_page);
839 } else {
840 dma_pte_addr(pte);
841 domain_flush_cache(domain, pte, sizeof(*pte));
842 }
ba395927 843 }
5cf0a76f
DW		 844 if (level == 1)
845 break;
846
19c239ce 847 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 848 level--;
849 }
850
5cf0a76f
DW		 851 if (!*target_level)
852 *target_level = level;
853
ba395927
KA		 854 return pte;
855}
856
6dd9a7c7 857
ba395927 858/* return address's pte at specific level */
90dcfb5e
DW		 859static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
860 unsigned long pfn,
6dd9a7c7 861 int level, int *large_page)
ba395927
KA		 862{
863 struct dma_pte *parent, *pte = NULL;
864 int total = agaw_to_level(domain->agaw);
865 int offset;
866
867 parent = domain->pgd;
868 while (level <= total) {
90dcfb5e 869 offset = pfn_level_offset(pfn, total);
ba395927
KA		 870 pte = &parent[offset];
871 if (level == total)
872 return pte;
873
6dd9a7c7
YS		 874 if (!dma_pte_present(pte)) {
875 *large_page = total;
ba395927 876 break;
6dd9a7c7
YS		 877 }
878
879 if (pte->val & DMA_PTE_LARGE_PAGE) {
880 *large_page = total;
881 return pte;
882 }
883
19c239ce 884 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 885 total--;
886 }
887 return NULL;
888}
889
ba395927 890/* clear last level pte, a tlb flush should be followed */
5cf0a76f 891static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 892 unsigned long start_pfn,
893 unsigned long last_pfn)
ba395927 894{
04b18e65 895 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 896 unsigned int large_page = 1;
310a5ab9 897 struct dma_pte *first_pte, *pte;
66eae846 898
04b18e65 899 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 900 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 901 BUG_ON(start_pfn > last_pfn);
ba395927 902
04b18e65 903 /* we don't need lock here; nobody else touches the iova range */
59c36286 904 do {
6dd9a7c7
YS		 905 large_page = 1;
906 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 907 if (!pte) {
6dd9a7c7 908 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 909 continue;
910 }
6dd9a7c7 911 do {
310a5ab9 912 dma_clear_pte(pte);
6dd9a7c7 913 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 914 pte++;
75e6bf96
DW		 915 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
916
310a5ab9
DW		 917 domain_flush_cache(domain, first_pte,
918 (void *)pte - (void *)first_pte);
59c36286
DW		 919
920 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 921}
922
3269ee0b
AW		 923static void dma_pte_free_level(struct dmar_domain *domain, int level,
924 struct dma_pte *pte, unsigned long pfn,
925 unsigned long start_pfn, unsigned long last_pfn)
926{
927 pfn = max(start_pfn, pfn);
928 pte = &pte[pfn_level_offset(pfn, level)];
929
930 do {
931 unsigned long level_pfn;
932 struct dma_pte *level_pte;
933
934 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
935 goto next;
936
937 level_pfn = pfn & level_mask(level - 1);
938 level_pte = phys_to_virt(dma_pte_addr(pte));
939
940 if (level > 2)
941 dma_pte_free_level(domain, level - 1, level_pte,
942 level_pfn, start_pfn, last_pfn);
943
944 /* If range covers entire pagetable, free it */
945 if (!(start_pfn > level_pfn ||
08336fd2 946 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 947 dma_clear_pte(pte);
948 domain_flush_cache(domain, pte, sizeof(*pte));
949 free_pgtable_page(level_pte);
950 }
951next:
952 pfn += level_size(level);
953 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
954}
955
ba395927
KA		 956/* free page table pages. last level pte should already be cleared */
957static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 958 unsigned long start_pfn,
959 unsigned long last_pfn)
ba395927 960{
6660c63a 961 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 962
6660c63a
DW		 963 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
964 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 965 BUG_ON(start_pfn > last_pfn);
ba395927 966
f3a0a52f 967 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 968 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
969 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 970
ba395927 971 /* free pgd */
d794dc9b 972 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 973 free_pgtable_page(domain->pgd);
974 domain->pgd = NULL;
975 }
976}
977
ea8ea460
DW		 978/* When a page at a given level is being unlinked from its parent, we don't
979 need to *modify* it at all. All we need to do is make a list of all the
980 pages which can be freed just as soon as we've flushed the IOTLB and we
981 know the hardware page-walk will no longer touch them.
982 The 'pte' argument is the *parent* PTE, pointing to the page that is to
983 be freed. */
984static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
985 int level, struct dma_pte *pte,
986 struct page *freelist)
987{
988 struct page *pg;
989
990 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
991 pg->freelist = freelist;
992 freelist = pg;
993
994 if (level == 1)
995 return freelist;
996
997 for (pte = page_address(pg); !first_pte_in_page(pte); pte++) {
998 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
999 freelist = dma_pte_list_pagetables(domain, level - 1,
1000 pte, freelist);
1001 }
1002
1003 return freelist;
1004}
1005
1006static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1007 struct dma_pte *pte, unsigned long pfn,
1008 unsigned long start_pfn,
1009 unsigned long last_pfn,
1010 struct page *freelist)
1011{
1012 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1013
1014 pfn = max(start_pfn, pfn);
1015 pte = &pte[pfn_level_offset(pfn, level)];
1016
1017 do {
1018 unsigned long level_pfn;
1019
1020 if (!dma_pte_present(pte))
1021 goto next;
1022
1023 level_pfn = pfn & level_mask(level);
1024
1025 /* If range covers entire pagetable, free it */
1026 if (start_pfn <= level_pfn &&
1027 last_pfn >= level_pfn + level_size(level) - 1) {
1028 /* These suborbinate page tables are going away entirely. Don't
1029 bother to clear them; we're just going to *free* them. */
1030 if (level > 1 && !dma_pte_superpage(pte))
1031 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1032
1033 dma_clear_pte(pte);
1034 if (!first_pte)
1035 first_pte = pte;
1036 last_pte = pte;
1037 } else if (level > 1) {
1038 /* Recurse down into a level that isn't *entirely* obsolete */
1039 freelist = dma_pte_clear_level(domain, level - 1,
1040 phys_to_virt(dma_pte_addr(pte)),
1041 level_pfn, start_pfn, last_pfn,
1042 freelist);
1043 }
1044next:
1045 pfn += level_size(level);
1046 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1047
1048 if (first_pte)
1049 domain_flush_cache(domain, first_pte,
1050 (void *)++last_pte - (void *)first_pte);
1051
1052 return freelist;
1053}
1054
1055/* We can't just free the pages because the IOMMU may still be walking
1056 the page tables, and may have cached the intermediate levels. The
1057 pages can only be freed after the IOTLB flush has been done. */
1058struct page *domain_unmap(struct dmar_domain *domain,
1059 unsigned long start_pfn,
1060 unsigned long last_pfn)
1061{
1062 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1063 struct page *freelist = NULL;
1064
1065 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1066 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1067 BUG_ON(start_pfn > last_pfn);
1068
1069 /* we don't need lock here; nobody else touches the iova range */
1070 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1071 domain->pgd, 0, start_pfn, last_pfn, NULL);
1072
1073 /* free pgd */
1074 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1075 struct page *pgd_page = virt_to_page(domain->pgd);
1076 pgd_page->freelist = freelist;
1077 freelist = pgd_page;
1078
1079 domain->pgd = NULL;
1080 }
1081
1082 return freelist;
1083}
1084
1085void dma_free_pagelist(struct page *freelist)
1086{
1087 struct page *pg;
1088
1089 while ((pg = freelist)) {
1090 freelist = pg->freelist;
1091 free_pgtable_page(page_address(pg));
1092 }
1093}
1094
ba395927
KA		 1095/* iommu handling */
1096static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1097{
1098 struct root_entry *root;
1099 unsigned long flags;
1100
4c923d47 1101 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 1102 if (!root)
1103 return -ENOMEM;
1104
5b6985ce 1105 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1106
1107 spin_lock_irqsave(&iommu->lock, flags);
1108 iommu->root_entry = root;
1109 spin_unlock_irqrestore(&iommu->lock, flags);
1110
1111 return 0;
1112}
1113
ba395927
KA		 1114static void iommu_set_root_entry(struct intel_iommu *iommu)
1115{
1116 void *addr;
c416daa9 1117 u32 sts;
ba395927
KA		 1118 unsigned long flag;
1119
1120 addr = iommu->root_entry;
1121
1f5b3c3f 1122 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1123 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1124
c416daa9 1125 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1126
1127 /* Make sure hardware complete it */
1128 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1129 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1130
1f5b3c3f 1131 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1132}
1133
1134static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1135{
1136 u32 val;
1137 unsigned long flag;
1138
9af88143 1139 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1140 return;
ba395927 1141
1f5b3c3f 1142 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1143 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1144
1145 /* Make sure hardware complete it */
1146 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1147 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1148
1f5b3c3f 1149 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1150}
1151
1152/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1153static void __iommu_flush_context(struct intel_iommu *iommu,
1154 u16 did, u16 source_id, u8 function_mask,
1155 u64 type)
ba395927
KA		 1156{
1157 u64 val = 0;
1158 unsigned long flag;
1159
ba395927
KA		 1160 switch (type) {
1161 case DMA_CCMD_GLOBAL_INVL:
1162 val = DMA_CCMD_GLOBAL_INVL;
1163 break;
1164 case DMA_CCMD_DOMAIN_INVL:
1165 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1166 break;
1167 case DMA_CCMD_DEVICE_INVL:
1168 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1169 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1170 break;
1171 default:
1172 BUG();
1173 }
1174 val |= DMA_CCMD_ICC;
1175
1f5b3c3f 1176 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1177 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1178
1179 /* Make sure hardware complete it */
1180 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1181 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1182
1f5b3c3f 1183 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1184}
1185
ba395927 1186/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1187static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1188 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1189{
1190 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1191 u64 val = 0, val_iva = 0;
1192 unsigned long flag;
1193
ba395927
KA		 1194 switch (type) {
1195 case DMA_TLB_GLOBAL_FLUSH:
1196 /* global flush doesn't need set IVA_REG */
1197 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1198 break;
1199 case DMA_TLB_DSI_FLUSH:
1200 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1201 break;
1202 case DMA_TLB_PSI_FLUSH:
1203 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1204 /* IH bit is passed in as part of address */
ba395927
KA		 1205 val_iva = size_order | addr;
1206 break;
1207 default:
1208 BUG();
1209 }
1210 /* Note: set drain read/write */
1211#if 0
1212 /*
1213 * This is probably to be super secure.. Looks like we can
1214 * ignore it without any impact.
1215 */
1216 if (cap_read_drain(iommu->cap))
1217 val |= DMA_TLB_READ_DRAIN;
1218#endif
1219 if (cap_write_drain(iommu->cap))
1220 val |= DMA_TLB_WRITE_DRAIN;
1221
1f5b3c3f 1222 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1223 /* Note: Only uses first TLB reg currently */
1224 if (val_iva)
1225 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1226 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1227
1228 /* Make sure hardware complete it */
1229 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1230 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1231
1f5b3c3f 1232 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1233
1234 /* check IOTLB invalidation granularity */
1235 if (DMA_TLB_IAIG(val) == 0)
1236 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1237 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1238 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1239 (unsigned long long)DMA_TLB_IIRG(type),
1240 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1241}
1242
64ae892b
DW		 1243static struct device_domain_info *
1244iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1245 u8 bus, u8 devfn)
93a23a72
YZ		 1246{
1247 int found = 0;
1248 unsigned long flags;
1249 struct device_domain_info *info;
0bcb3e28 1250 struct pci_dev *pdev;
93a23a72
YZ		 1251
1252 if (!ecap_dev_iotlb_support(iommu->ecap))
1253 return NULL;
1254
1255 if (!iommu->qi)
1256 return NULL;
1257
1258 spin_lock_irqsave(&device_domain_lock, flags);
1259 list_for_each_entry(info, &domain->devices, link)
1260 if (info->bus == bus && info->devfn == devfn) {
1261 found = 1;
1262 break;
1263 }
1264 spin_unlock_irqrestore(&device_domain_lock, flags);
1265
0bcb3e28 1266 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1267 return NULL;
1268
0bcb3e28
DW		 1269 pdev = to_pci_dev(info->dev);
1270
1271 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1272 return NULL;
1273
0bcb3e28 1274 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1275 return NULL;
1276
93a23a72
YZ		 1277 return info;
1278}
1279
1280static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1281{
0bcb3e28 1282 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1283 return;
1284
0bcb3e28 1285 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1286}
1287
1288static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1289{
0bcb3e28
DW		 1290 if (!info->dev || !dev_is_pci(info->dev) ||
1291 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1292 return;
1293
0bcb3e28 1294 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1295}
1296
1297static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1298 u64 addr, unsigned mask)
1299{
1300 u16 sid, qdep;
1301 unsigned long flags;
1302 struct device_domain_info *info;
1303
1304 spin_lock_irqsave(&device_domain_lock, flags);
1305 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1306 struct pci_dev *pdev;
1307 if (!info->dev || !dev_is_pci(info->dev))
1308 continue;
1309
1310 pdev = to_pci_dev(info->dev);
1311 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1312 continue;
1313
1314 sid = info->bus << 8 | info->devfn;
0bcb3e28 1315 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1316 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1317 }
1318 spin_unlock_irqrestore(&device_domain_lock, flags);
1319}
1320
1f0ef2aa 1321static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1322 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1323{
9dd2fe89 1324 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1325 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1326
ba395927
KA		 1327 BUG_ON(pages == 0);
1328
ea8ea460
DW		 1329 if (ih)
1330 ih = 1 << 6;
ba395927 1331 /*
9dd2fe89
YZ		 1332 * Fallback to domain selective flush if no PSI support or the size is
1333 * too big.
ba395927
KA		 1334 * PSI requires page size to be 2 ^ x, and the base address is naturally
1335 * aligned to the size
1336 */
9dd2fe89
YZ		 1337 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1338 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1339 DMA_TLB_DSI_FLUSH);
9dd2fe89 1340 else
ea8ea460 1341 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1342 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1343
1344 /*
82653633
NA		 1345 * In caching mode, changes of pages from non-present to present require
1346 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1347 */
82653633 1348 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1349 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1350}
1351
f8bab735 1352static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1353{
1354 u32 pmen;
1355 unsigned long flags;
1356
1f5b3c3f 1357 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1358 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1359 pmen &= ~DMA_PMEN_EPM;
1360 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1361
1362 /* wait for the protected region status bit to clear */
1363 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1364 readl, !(pmen & DMA_PMEN_PRS), pmen);
1365
1f5b3c3f 1366 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1367}
1368
ba395927
KA		 1369static int iommu_enable_translation(struct intel_iommu *iommu)
1370{
1371 u32 sts;
1372 unsigned long flags;
1373
1f5b3c3f 1374 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1375 iommu->gcmd |= DMA_GCMD_TE;
1376 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1377
1378 /* Make sure hardware complete it */
1379 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1380 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1381
1f5b3c3f 1382 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1383 return 0;
1384}
1385
1386static int iommu_disable_translation(struct intel_iommu *iommu)
1387{
1388 u32 sts;
1389 unsigned long flag;
1390
1f5b3c3f 1391 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1392 iommu->gcmd &= ~DMA_GCMD_TE;
1393 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1394
1395 /* Make sure hardware complete it */
1396 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1397 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1398
1f5b3c3f 1399 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1400 return 0;
1401}
1402
3460a6d9 1403
ba395927
KA		 1404static int iommu_init_domains(struct intel_iommu *iommu)
1405{
1406 unsigned long ndomains;
1407 unsigned long nlongs;
1408
1409 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1410 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1411 iommu->seq_id, ndomains);
ba395927
KA		 1412 nlongs = BITS_TO_LONGS(ndomains);
1413
94a91b50
DD		 1414 spin_lock_init(&iommu->lock);
1415
ba395927
KA		 1416 /* TBD: there might be 64K domains,
1417 * consider other allocation for future chip
1418 */
1419 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1420 if (!iommu->domain_ids) {
852bdb04
JL		 1421 pr_err("IOMMU%d: allocating domain id array failed\n",
1422 iommu->seq_id);
ba395927
KA		 1423 return -ENOMEM;
1424 }
1425 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1426 GFP_KERNEL);
1427 if (!iommu->domains) {
852bdb04
JL		 1428 pr_err("IOMMU%d: allocating domain array failed\n",
1429 iommu->seq_id);
1430 kfree(iommu->domain_ids);
1431 iommu->domain_ids = NULL;
ba395927
KA		 1432 return -ENOMEM;
1433 }
1434
1435 /*
1436 * if Caching mode is set, then invalid translations are tagged
1437 * with domainid 0. Hence we need to pre-allocate it.
1438 */
1439 if (cap_caching_mode(iommu->cap))
1440 set_bit(0, iommu->domain_ids);
1441 return 0;
1442}
ba395927 1443
a868e6b7 1444static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1445{
1446 struct dmar_domain *domain;
5ced12af 1447 int i, count;
c7151a8d 1448 unsigned long flags;
ba395927 1449
94a91b50 1450 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1451 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1452 /*
1453 * Domain id 0 is reserved for invalid translation
1454 * if hardware supports caching mode.
1455 */
1456 if (cap_caching_mode(iommu->cap) && i == 0)
1457 continue;
1458
94a91b50
DD		 1459 domain = iommu->domains[i];
1460 clear_bit(i, iommu->domain_ids);
1461
1462 spin_lock_irqsave(&domain->iommu_lock, flags);
5ced12af
JL		 1463 count = --domain->iommu_count;
1464 spin_unlock_irqrestore(&domain->iommu_lock, flags);
92d03cc8
JL		 1465 if (count == 0)
1466 domain_exit(domain);
5e98c4b1 1467 }
ba395927
KA		 1468 }
1469
1470 if (iommu->gcmd & DMA_GCMD_TE)
1471 iommu_disable_translation(iommu);
1472
ba395927
KA		 1473 kfree(iommu->domains);
1474 kfree(iommu->domain_ids);
a868e6b7
JL		 1475 iommu->domains = NULL;
1476 iommu->domain_ids = NULL;
ba395927 1477
d9630fe9
WH		 1478 g_iommus[iommu->seq_id] = NULL;
1479
ba395927
KA		 1480 /* free context mapping */
1481 free_context_table(iommu);
ba395927
KA		 1482}
1483
92d03cc8 1484static struct dmar_domain *alloc_domain(bool vm)
ba395927 1485{
92d03cc8
JL		 1486 /* domain id for virtual machine, it won't be set in context */
1487 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1488 struct dmar_domain *domain;
ba395927
KA		 1489
1490 domain = alloc_domain_mem();
1491 if (!domain)
1492 return NULL;
1493
4c923d47 1494 domain->nid = -1;
92d03cc8 1495 domain->iommu_count = 0;
1b198bb0 1496 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
2c2e2c38 1497 domain->flags = 0;
92d03cc8
JL		 1498 spin_lock_init(&domain->iommu_lock);
1499 INIT_LIST_HEAD(&domain->devices);
1500 if (vm) {
1501 domain->id = atomic_inc_return(&vm_domid);
1502 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
1503 }
2c2e2c38
FY		 1504
1505 return domain;
1506}
1507
1508static int iommu_attach_domain(struct dmar_domain *domain,
1509 struct intel_iommu *iommu)
1510{
1511 int num;
1512 unsigned long ndomains;
1513 unsigned long flags;
1514
ba395927
KA		 1515 ndomains = cap_ndoms(iommu->cap);
1516
1517 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1518
ba395927
KA		 1519 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1520 if (num >= ndomains) {
1521 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1522 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1523 return -ENOMEM;
ba395927
KA		 1524 }
1525
ba395927 1526 domain->id = num;
9ebd682e 1527 domain->iommu_count++;
2c2e2c38 1528 set_bit(num, iommu->domain_ids);
1b198bb0 1529 set_bit(iommu->seq_id, domain->iommu_bmp);
ba395927
KA		 1530 iommu->domains[num] = domain;
1531 spin_unlock_irqrestore(&iommu->lock, flags);
1532
2c2e2c38 1533 return 0;
ba395927
KA		 1534}
1535
2c2e2c38
FY		 1536static void iommu_detach_domain(struct dmar_domain *domain,
1537 struct intel_iommu *iommu)
ba395927
KA		 1538{
1539 unsigned long flags;
2c2e2c38 1540 int num, ndomains;
ba395927 1541
8c11e798 1542 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1543 ndomains = cap_ndoms(iommu->cap);
a45946ab 1544 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38 1545 if (iommu->domains[num] == domain) {
92d03cc8
JL		 1546 clear_bit(num, iommu->domain_ids);
1547 iommu->domains[num] = NULL;
2c2e2c38
FY		 1548 break;
1549 }
2c2e2c38 1550 }
8c11e798 1551 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1552}
1553
1554static struct iova_domain reserved_iova_list;
8a443df4 1555static struct lock_class_key reserved_rbtree_key;
ba395927 1556
51a63e67 1557static int dmar_init_reserved_ranges(void)
ba395927
KA		 1558{
1559 struct pci_dev *pdev = NULL;
1560 struct iova *iova;
1561 int i;
ba395927 1562
f661197e 1563 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1564
8a443df4
MG		 1565 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1566 &reserved_rbtree_key);
1567
ba395927
KA		 1568 /* IOAPIC ranges shouldn't be accessed by DMA */
1569 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1570 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1571 if (!iova) {
ba395927 1572 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1573 return -ENODEV;
1574 }
ba395927
KA		 1575
1576 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1577 for_each_pci_dev(pdev) {
1578 struct resource *r;
1579
1580 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1581 r = &pdev->resource[i];
1582 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1583 continue;
1a4a4551
DW		 1584 iova = reserve_iova(&reserved_iova_list,
1585 IOVA_PFN(r->start),
1586 IOVA_PFN(r->end));
51a63e67 1587 if (!iova) {
ba395927 1588 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1589 return -ENODEV;
1590 }
ba395927
KA		 1591 }
1592 }
51a63e67 1593 return 0;
ba395927
KA		 1594}
1595
1596static void domain_reserve_special_ranges(struct dmar_domain *domain)
1597{
1598 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1599}
1600
1601static inline int guestwidth_to_adjustwidth(int gaw)
1602{
1603 int agaw;
1604 int r = (gaw - 12) % 9;
1605
1606 if (r == 0)
1607 agaw = gaw;
1608 else
1609 agaw = gaw + 9 - r;
1610 if (agaw > 64)
1611 agaw = 64;
1612 return agaw;
1613}
1614
1615static int domain_init(struct dmar_domain *domain, int guest_width)
1616{
1617 struct intel_iommu *iommu;
1618 int adjust_width, agaw;
1619 unsigned long sagaw;
1620
f661197e 1621 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927
KA		 1622 domain_reserve_special_ranges(domain);
1623
1624 /* calculate AGAW */
8c11e798 1625 iommu = domain_get_iommu(domain);
ba395927
KA		 1626 if (guest_width > cap_mgaw(iommu->cap))
1627 guest_width = cap_mgaw(iommu->cap);
1628 domain->gaw = guest_width;
1629 adjust_width = guestwidth_to_adjustwidth(guest_width);
1630 agaw = width_to_agaw(adjust_width);
1631 sagaw = cap_sagaw(iommu->cap);
1632 if (!test_bit(agaw, &sagaw)) {
1633 /* hardware doesn't support it, choose a bigger one */
1634 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1635 agaw = find_next_bit(&sagaw, 5, agaw);
1636 if (agaw >= 5)
1637 return -ENODEV;
1638 }
1639 domain->agaw = agaw;
ba395927 1640
8e604097
WH		 1641 if (ecap_coherent(iommu->ecap))
1642 domain->iommu_coherency = 1;
1643 else
1644 domain->iommu_coherency = 0;
1645
58c610bd
SY		 1646 if (ecap_sc_support(iommu->ecap))
1647 domain->iommu_snooping = 1;
1648 else
1649 domain->iommu_snooping = 0;
1650
214e39aa
DW		 1651 if (intel_iommu_superpage)
1652 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1653 else
1654 domain->iommu_superpage = 0;
1655
4c923d47 1656 domain->nid = iommu->node;
c7151a8d 1657
ba395927 1658 /* always allocate the top pgd */
4c923d47 1659 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1660 if (!domain->pgd)
1661 return -ENOMEM;
5b6985ce 1662 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1663 return 0;
1664}
1665
1666static void domain_exit(struct dmar_domain *domain)
1667{
2c2e2c38
FY		 1668 struct dmar_drhd_unit *drhd;
1669 struct intel_iommu *iommu;
ea8ea460 1670 struct page *freelist = NULL;
ba395927
KA		 1671
1672 /* Domain 0 is reserved, so dont process it */
1673 if (!domain)
1674 return;
1675
7b668357
AW		 1676 /* Flush any lazy unmaps that may reference this domain */
1677 if (!intel_iommu_strict)
1678 flush_unmaps_timeout(0);
1679
92d03cc8 1680 /* remove associated devices */
ba395927 1681 domain_remove_dev_info(domain);
92d03cc8 1682
ba395927
KA		 1683 /* destroy iovas */
1684 put_iova_domain(&domain->iovad);
ba395927 1685
ea8ea460 1686 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1687
92d03cc8 1688 /* clear attached or cached domains */
0e242612 1689 rcu_read_lock();
2c2e2c38 1690 for_each_active_iommu(iommu, drhd)
92d03cc8
JL		 1691 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1692 test_bit(iommu->seq_id, domain->iommu_bmp))
2c2e2c38 1693 iommu_detach_domain(domain, iommu);
0e242612 1694 rcu_read_unlock();
2c2e2c38 1695
ea8ea460
DW		 1696 dma_free_pagelist(freelist);
1697
ba395927
KA		 1698 free_domain_mem(domain);
1699}
1700
64ae892b
DW		 1701static int domain_context_mapping_one(struct dmar_domain *domain,
1702 struct intel_iommu *iommu,
1703 u8 bus, u8 devfn, int translation)
ba395927
KA		 1704{
1705 struct context_entry *context;
ba395927 1706 unsigned long flags;
ea6606b0
WH		 1707 struct dma_pte *pgd;
1708 unsigned long num;
1709 unsigned long ndomains;
1710 int id;
1711 int agaw;
93a23a72 1712 struct device_domain_info *info = NULL;
ba395927
KA		 1713
1714 pr_debug("Set context mapping for %02x:%02x.%d\n",
1715 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1716
ba395927 1717 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1718 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1719 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1720
ba395927
KA		 1721 context = device_to_context_entry(iommu, bus, devfn);
1722 if (!context)
1723 return -ENOMEM;
1724 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1725 if (context_present(context)) {
ba395927
KA		 1726 spin_unlock_irqrestore(&iommu->lock, flags);
1727 return 0;
1728 }
1729
ea6606b0
WH		 1730 id = domain->id;
1731 pgd = domain->pgd;
1732
2c2e2c38
FY		 1733 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1734 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1735 int found = 0;
1736
1737 /* find an available domain id for this device in iommu */
1738 ndomains = cap_ndoms(iommu->cap);
a45946ab 1739 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1740 if (iommu->domains[num] == domain) {
1741 id = num;
1742 found = 1;
1743 break;
1744 }
ea6606b0
WH		 1745 }
1746
1747 if (found == 0) {
1748 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1749 if (num >= ndomains) {
1750 spin_unlock_irqrestore(&iommu->lock, flags);
1751 printk(KERN_ERR "IOMMU: no free domain ids\n");
1752 return -EFAULT;
1753 }
1754
1755 set_bit(num, iommu->domain_ids);
1756 iommu->domains[num] = domain;
1757 id = num;
1758 }
1759
1760 /* Skip top levels of page tables for
1761 * iommu which has less agaw than default.
1672af11 1762 * Unnecessary for PT mode.
ea6606b0 1763 */
1672af11
CW		 1764 if (translation != CONTEXT_TT_PASS_THROUGH) {
1765 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1766 pgd = phys_to_virt(dma_pte_addr(pgd));
1767 if (!dma_pte_present(pgd)) {
1768 spin_unlock_irqrestore(&iommu->lock, flags);
1769 return -ENOMEM;
1770 }
ea6606b0
WH		 1771 }
1772 }
1773 }
1774
1775 context_set_domain_id(context, id);
4ed0d3e6 1776
93a23a72 1777 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1778 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1779 translation = info ? CONTEXT_TT_DEV_IOTLB :
1780 CONTEXT_TT_MULTI_LEVEL;
1781 }
4ed0d3e6
FY		 1782 /*
1783 * In pass through mode, AW must be programmed to indicate the largest
1784 * AGAW value supported by hardware. And ASR is ignored by hardware.
1785 */
93a23a72 1786 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1787 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1788 else {
1789 context_set_address_root(context, virt_to_phys(pgd));
1790 context_set_address_width(context, iommu->agaw);
1791 }
4ed0d3e6
FY		 1792
1793 context_set_translation_type(context, translation);
c07e7d21
MM		 1794 context_set_fault_enable(context);
1795 context_set_present(context);
5331fe6f 1796 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1797
4c25a2c1
DW		 1798 /*
1799 * It's a non-present to present mapping. If hardware doesn't cache
1800 * non-present entry we only need to flush the write-buffer. If the
1801 * _does_ cache non-present entries, then it does so in the special
1802 * domain #0, which we have to flush:
1803 */
1804 if (cap_caching_mode(iommu->cap)) {
1805 iommu->flush.flush_context(iommu, 0,
1806 (((u16)bus) << 8) | devfn,
1807 DMA_CCMD_MASK_NOBIT,
1808 DMA_CCMD_DEVICE_INVL);
82653633 1809 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1810 } else {
ba395927 1811 iommu_flush_write_buffer(iommu);
4c25a2c1 1812 }
93a23a72 1813 iommu_enable_dev_iotlb(info);
ba395927 1814 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1815
1816 spin_lock_irqsave(&domain->iommu_lock, flags);
1b198bb0 1817 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
c7151a8d 1818 domain->iommu_count++;
4c923d47
SS		 1819 if (domain->iommu_count == 1)
1820 domain->nid = iommu->node;
58c610bd 1821 domain_update_iommu_cap(domain);
c7151a8d
WH		 1822 }
1823 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1824 return 0;
1825}
1826
1827static int
4ed0d3e6
FY		 1828domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1829 int translation)
ba395927
KA		 1830{
1831 int ret;
1832 struct pci_dev *tmp, *parent;
64ae892b
DW		 1833 struct intel_iommu *iommu;
1834
1835 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1836 pdev->devfn);
1837 if (!iommu)
1838 return -ENODEV;
ba395927 1839
64ae892b 1840 ret = domain_context_mapping_one(domain, iommu,
4ed0d3e6
FY		 1841 pdev->bus->number, pdev->devfn,
1842 translation);
ba395927
KA		 1843 if (ret)
1844 return ret;
1845
1846 /* dependent device mapping */
1847 tmp = pci_find_upstream_pcie_bridge(pdev);
1848 if (!tmp)
1849 return 0;
1850 /* Secondary interface's bus number and devfn 0 */
1851 parent = pdev->bus->self;
1852 while (parent != tmp) {
64ae892b 1853 ret = domain_context_mapping_one(domain, iommu,
276dbf99 1854 parent->bus->number,
4ed0d3e6 1855 parent->devfn, translation);
ba395927
KA		 1856 if (ret)
1857 return ret;
1858 parent = parent->bus->self;
1859 }
45e829ea 1860 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
64ae892b 1861 return domain_context_mapping_one(domain, iommu,
4ed0d3e6
FY		 1862 tmp->subordinate->number, 0,
1863 translation);
ba395927 1864 else /* this is a legacy PCI bridge */
64ae892b 1865 return domain_context_mapping_one(domain, iommu,
276dbf99 1866 tmp->bus->number,
4ed0d3e6
FY		 1867 tmp->devfn,
1868 translation);
ba395927
KA		 1869}
1870
5331fe6f 1871static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1872{
1873 int ret;
1874 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1875 struct intel_iommu *iommu;
1876
276dbf99
DW		 1877 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1878 pdev->devfn);
5331fe6f
WH		 1879 if (!iommu)
1880 return -ENODEV;
ba395927 1881
276dbf99 1882 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1883 if (!ret)
1884 return ret;
1885 /* dependent device mapping */
1886 tmp = pci_find_upstream_pcie_bridge(pdev);
1887 if (!tmp)
1888 return ret;
1889 /* Secondary interface's bus number and devfn 0 */
1890 parent = pdev->bus->self;
1891 while (parent != tmp) {
8c11e798 1892 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1893 parent->devfn);
ba395927
KA		 1894 if (!ret)
1895 return ret;
1896 parent = parent->bus->self;
1897 }
5f4d91a1 1898 if (pci_is_pcie(tmp))
276dbf99
DW		 1899 return device_context_mapped(iommu, tmp->subordinate->number,
1900 0);
ba395927 1901 else
276dbf99
DW		 1902 return device_context_mapped(iommu, tmp->bus->number,
1903 tmp->devfn);
ba395927
KA		 1904}
1905
f532959b
FY		 1906/* Returns a number of VTD pages, but aligned to MM page size */
1907static inline unsigned long aligned_nrpages(unsigned long host_addr,
1908 size_t size)
1909{
1910 host_addr &= ~PAGE_MASK;
1911 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1912}
1913
6dd9a7c7
YS		 1914/* Return largest possible superpage level for a given mapping */
1915static inline int hardware_largepage_caps(struct dmar_domain *domain,
1916 unsigned long iov_pfn,
1917 unsigned long phy_pfn,
1918 unsigned long pages)
1919{
1920 int support, level = 1;
1921 unsigned long pfnmerge;
1922
1923 support = domain->iommu_superpage;
1924
1925 /* To use a large page, the virtual *and* physical addresses
1926 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1927 of them will mean we have to use smaller pages. So just
1928 merge them and check both at once. */
1929 pfnmerge = iov_pfn | phy_pfn;
1930
1931 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1932 pages >>= VTD_STRIDE_SHIFT;
1933 if (!pages)
1934 break;
1935 pfnmerge >>= VTD_STRIDE_SHIFT;
1936 level++;
1937 support--;
1938 }
1939 return level;
1940}
1941
9051aa02
DW		 1942static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1943 struct scatterlist *sg, unsigned long phys_pfn,
1944 unsigned long nr_pages, int prot)
e1605495
DW		 1945{
1946 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1947 phys_addr_t uninitialized_var(pteval);
e1605495 1948 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1949 unsigned long sg_res;
6dd9a7c7
YS		 1950 unsigned int largepage_lvl = 0;
1951 unsigned long lvl_pages = 0;
e1605495
DW		 1952
1953 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1954
1955 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1956 return -EINVAL;
1957
1958 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1959
9051aa02
DW		 1960 if (sg)
1961 sg_res = 0;
1962 else {
1963 sg_res = nr_pages + 1;
1964 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1965 }
1966
6dd9a7c7 1967 while (nr_pages > 0) {
c85994e4
DW		 1968 uint64_t tmp;
1969
e1605495 1970 if (!sg_res) {
f532959b 1971 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1972 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1973 sg->dma_length = sg->length;
1974 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1975 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1976 }
6dd9a7c7 1977
e1605495 1978 if (!pte) {
6dd9a7c7
YS		 1979 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1980
5cf0a76f 1981 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 1982 if (!pte)
1983 return -ENOMEM;
6dd9a7c7 1984 /* It is large page*/
6491d4d0 1985 if (largepage_lvl > 1) {
6dd9a7c7 1986 pteval |= DMA_PTE_LARGE_PAGE;
6491d4d0
WD		 1987 /* Ensure that old small page tables are removed to make room
1988 for superpage, if they exist. */
1989 dma_pte_clear_range(domain, iov_pfn,
1990 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1991 dma_pte_free_pagetable(domain, iov_pfn,
1992 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1993 } else {
6dd9a7c7 1994 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 1995 }
6dd9a7c7 1996
e1605495
DW		 1997 }
1998 /* We don't need lock here, nobody else
1999 * touches the iova range
2000 */
7766a3fb 2001 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2002 if (tmp) {
1bf20f0d 2003 static int dumps = 5;
c85994e4
DW		 2004 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2005 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2006 if (dumps) {
2007 dumps--;
2008 debug_dma_dump_mappings(NULL);
2009 }
2010 WARN_ON(1);
2011 }
6dd9a7c7
YS		 2012
2013 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2014
2015 BUG_ON(nr_pages < lvl_pages);
2016 BUG_ON(sg_res < lvl_pages);
2017
2018 nr_pages -= lvl_pages;
2019 iov_pfn += lvl_pages;
2020 phys_pfn += lvl_pages;
2021 pteval += lvl_pages * VTD_PAGE_SIZE;
2022 sg_res -= lvl_pages;
2023
2024 /* If the next PTE would be the first in a new page, then we
2025 need to flush the cache on the entries we've just written.
2026 And then we'll need to recalculate 'pte', so clear it and
2027 let it get set again in the if (!pte) block above.
2028
2029 If we're done (!nr_pages) we need to flush the cache too.
2030
2031 Also if we've been setting superpages, we may need to
2032 recalculate 'pte' and switch back to smaller pages for the
2033 end of the mapping, if the trailing size is not enough to
2034 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2035 pte++;
6dd9a7c7
YS		 2036 if (!nr_pages || first_pte_in_page(pte) ||
2037 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2038 domain_flush_cache(domain, first_pte,
2039 (void *)pte - (void *)first_pte);
2040 pte = NULL;
2041 }
6dd9a7c7
YS		 2042
2043 if (!sg_res && nr_pages)
e1605495
DW		 2044 sg = sg_next(sg);
2045 }
2046 return 0;
2047}
2048
9051aa02
DW		 2049static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2050 struct scatterlist *sg, unsigned long nr_pages,
2051 int prot)
ba395927 2052{
9051aa02
DW		 2053 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2054}
6f6a00e4 2055
9051aa02
DW		 2056static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2057 unsigned long phys_pfn, unsigned long nr_pages,
2058 int prot)
2059{
2060 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2061}
2062
c7151a8d 2063static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2064{
c7151a8d
WH		 2065 if (!iommu)
2066 return;
8c11e798
WH		 2067
2068 clear_context_table(iommu, bus, devfn);
2069 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2070 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2071 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2072}
2073
109b9b04
DW		 2074static inline void unlink_domain_info(struct device_domain_info *info)
2075{
2076 assert_spin_locked(&device_domain_lock);
2077 list_del(&info->link);
2078 list_del(&info->global);
2079 if (info->dev)
0bcb3e28 2080 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2081}
2082
ba395927
KA		 2083static void domain_remove_dev_info(struct dmar_domain *domain)
2084{
2085 struct device_domain_info *info;
92d03cc8 2086 unsigned long flags, flags2;
c7151a8d 2087 struct intel_iommu *iommu;
ba395927
KA		 2088
2089 spin_lock_irqsave(&device_domain_lock, flags);
2090 while (!list_empty(&domain->devices)) {
2091 info = list_entry(domain->devices.next,
2092 struct device_domain_info, link);
109b9b04 2093 unlink_domain_info(info);
ba395927
KA		 2094 spin_unlock_irqrestore(&device_domain_lock, flags);
2095
93a23a72 2096 iommu_disable_dev_iotlb(info);
276dbf99 2097 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 2098 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927 2099
92d03cc8
JL		 2100 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
2101 iommu_detach_dependent_devices(iommu, info->dev);
2102 /* clear this iommu in iommu_bmp, update iommu count
2103 * and capabilities
2104 */
2105 spin_lock_irqsave(&domain->iommu_lock, flags2);
2106 if (test_and_clear_bit(iommu->seq_id,
2107 domain->iommu_bmp)) {
2108 domain->iommu_count--;
2109 domain_update_iommu_cap(domain);
2110 }
2111 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2112 }
2113
2114 free_devinfo_mem(info);
ba395927
KA		 2115 spin_lock_irqsave(&device_domain_lock, flags);
2116 }
2117 spin_unlock_irqrestore(&device_domain_lock, flags);
2118}
2119
2120/*
2121 * find_domain
1525a29a 2122 * Note: we use struct device->archdata.iommu stores the info
ba395927 2123 */
1525a29a 2124static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2125{
2126 struct device_domain_info *info;
2127
2128 /* No lock here, assumes no domain exit in normal case */
1525a29a 2129 info = dev->archdata.iommu;
ba395927
KA		 2130 if (info)
2131 return info->domain;
2132 return NULL;
2133}
2134
5a8f40e8 2135static inline struct device_domain_info *
745f2586
JL		 2136dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2137{
2138 struct device_domain_info *info;
2139
2140 list_for_each_entry(info, &device_domain_list, global)
2141 if (info->segment == segment && info->bus == bus &&
2142 info->devfn == devfn)
5a8f40e8 2143 return info;
745f2586
JL		 2144
2145 return NULL;
2146}
2147
5a8f40e8
DW		 2148static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
2149 int segment, int bus, int devfn,
b718cd3d
DW		 2150 struct device *dev,
2151 struct dmar_domain *domain)
745f2586 2152{
5a8f40e8 2153 struct dmar_domain *found = NULL;
745f2586
JL		 2154 struct device_domain_info *info;
2155 unsigned long flags;
2156
2157 info = alloc_devinfo_mem();
2158 if (!info)
b718cd3d 2159 return NULL;
745f2586
JL		 2160
2161 info->segment = segment;
2162 info->bus = bus;
2163 info->devfn = devfn;
2164 info->dev = dev;
2165 info->domain = domain;
5a8f40e8 2166 info->iommu = iommu;
745f2586
JL		 2167 if (!dev)
2168 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2169
2170 spin_lock_irqsave(&device_domain_lock, flags);
2171 if (dev)
0bcb3e28 2172 found = find_domain(dev);
5a8f40e8
DW		 2173 else {
2174 struct device_domain_info *info2;
2175 info2 = dmar_search_domain_by_dev_info(segment, bus, devfn);
2176 if (info2)
2177 found = info2->domain;
2178 }
745f2586
JL		 2179 if (found) {
2180 spin_unlock_irqrestore(&device_domain_lock, flags);
2181 free_devinfo_mem(info);
b718cd3d
DW		 2182 /* Caller must free the original domain */
2183 return found;
745f2586
JL		 2184 }
2185
b718cd3d
DW		 2186 list_add(&info->link, &domain->devices);
2187 list_add(&info->global, &device_domain_list);
2188 if (dev)
2189 dev->archdata.iommu = info;
2190 spin_unlock_irqrestore(&device_domain_lock, flags);
2191
2192 return domain;
745f2586
JL		 2193}
2194
ba395927
KA		 2195/* domain is initialized */
2196static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
2197{
e85bb5d4 2198 struct dmar_domain *domain, *free = NULL;
5a8f40e8
DW		 2199 struct intel_iommu *iommu = NULL;
2200 struct device_domain_info *info;
ba395927 2201 struct dmar_drhd_unit *drhd;
ba395927
KA		 2202 struct pci_dev *dev_tmp;
2203 unsigned long flags;
2204 int bus = 0, devfn = 0;
276dbf99 2205 int segment;
ba395927 2206
1525a29a 2207 domain = find_domain(&pdev->dev);
ba395927
KA		 2208 if (domain)
2209 return domain;
2210
276dbf99
DW		 2211 segment = pci_domain_nr(pdev->bus);
2212
ba395927
KA		 2213 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
2214 if (dev_tmp) {
5f4d91a1 2215 if (pci_is_pcie(dev_tmp)) {
ba395927
KA		 2216 bus = dev_tmp->subordinate->number;
2217 devfn = 0;
2218 } else {
2219 bus = dev_tmp->bus->number;
2220 devfn = dev_tmp->devfn;
2221 }
2222 spin_lock_irqsave(&device_domain_lock, flags);
5a8f40e8
DW		 2223 info = dmar_search_domain_by_dev_info(segment, bus, devfn);
2224 if (info) {
2225 iommu = info->iommu;
2226 domain = info->domain;
2227 }
ba395927 2228 spin_unlock_irqrestore(&device_domain_lock, flags);
5a8f40e8 2229 if (info)
ba395927 2230 goto found_domain;
ba395927
KA		 2231 }
2232
ba395927
KA		 2233 drhd = dmar_find_matched_drhd_unit(pdev);
2234 if (!drhd) {
2235 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
2236 pci_name(pdev));
2237 return NULL;
2238 }
2239 iommu = drhd->iommu;
2240
745f2586 2241 /* Allocate and intialize new domain for the device */
92d03cc8 2242 domain = alloc_domain(false);
745f2586
JL		 2243 if (!domain)
2244 goto error;
2245 if (iommu_attach_domain(domain, iommu)) {
2fe9723d 2246 free_domain_mem(domain);
ba395927 2247 goto error;
2c2e2c38 2248 }
e85bb5d4
JL		 2249 free = domain;
2250 if (domain_init(domain, gaw))
ba395927 2251 goto error;
ba395927
KA		 2252
2253 /* register pcie-to-pci device */
2254 if (dev_tmp) {
5a8f40e8
DW		 2255 domain = dmar_insert_dev_info(iommu, segment, bus, devfn, NULL,
2256 domain);
b718cd3d 2257 if (!domain)
ba395927 2258 goto error;
ba395927
KA		 2259 }
2260
2261found_domain:
5a8f40e8
DW		 2262 domain = dmar_insert_dev_info(iommu, segment, pdev->bus->number,
2263 pdev->devfn, &pdev->dev, domain);
ba395927 2264error:
b718cd3d 2265 if (free != domain)
e85bb5d4 2266 domain_exit(free);
b718cd3d
DW		 2267
2268 return domain;
ba395927
KA		 2269}
2270
2c2e2c38 2271static int iommu_identity_mapping;
e0fc7e0b
DW		 2272#define IDENTMAP_ALL 1
2273#define IDENTMAP_GFX 2
2274#define IDENTMAP_AZALIA 4
2c2e2c38 2275
b213203e
DW		 2276static int iommu_domain_identity_map(struct dmar_domain *domain,
2277 unsigned long long start,
2278 unsigned long long end)
ba395927 2279{
c5395d5c
DW		 2280 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2281 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2282
2283 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2284 dma_to_mm_pfn(last_vpfn))) {
ba395927 2285 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2286 return -ENOMEM;
ba395927
KA		 2287 }
2288
c5395d5c
DW		 2289 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2290 start, end, domain->id);
ba395927
KA		 2291 /*
2292 * RMRR range might have overlap with physical memory range,
2293 * clear it first
2294 */
c5395d5c 2295 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2296
c5395d5c
DW		 2297 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2298 last_vpfn - first_vpfn + 1,
61df7443 2299 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2300}
2301
2302static int iommu_prepare_identity_map(struct pci_dev *pdev,
2303 unsigned long long start,
2304 unsigned long long end)
2305{
2306 struct dmar_domain *domain;
2307 int ret;
2308
c7ab48d2 2309 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2310 if (!domain)
2311 return -ENOMEM;
2312
19943b0e
DW		 2313 /* For _hardware_ passthrough, don't bother. But for software
2314 passthrough, we do it anyway -- it may indicate a memory
2315 range which is reserved in E820, so which didn't get set
2316 up to start with in si_domain */
2317 if (domain == si_domain && hw_pass_through) {
2318 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2319 pci_name(pdev), start, end);
2320 return 0;
2321 }
2322
2323 printk(KERN_INFO
2324 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2325 pci_name(pdev), start, end);
2ff729f5 2326
5595b528
DW		 2327 if (end < start) {
2328 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2329 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2330 dmi_get_system_info(DMI_BIOS_VENDOR),
2331 dmi_get_system_info(DMI_BIOS_VERSION),
2332 dmi_get_system_info(DMI_PRODUCT_VERSION));
2333 ret = -EIO;
2334 goto error;
2335 }
2336
2ff729f5
DW		 2337 if (end >> agaw_to_width(domain->agaw)) {
2338 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2339 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2340 agaw_to_width(domain->agaw),
2341 dmi_get_system_info(DMI_BIOS_VENDOR),
2342 dmi_get_system_info(DMI_BIOS_VERSION),
2343 dmi_get_system_info(DMI_PRODUCT_VERSION));
2344 ret = -EIO;
2345 goto error;
2346 }
19943b0e 2347
b213203e 2348 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2349 if (ret)
2350 goto error;
2351
2352 /* context entry init */
4ed0d3e6 2353 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2354 if (ret)
2355 goto error;
2356
2357 return 0;
2358
2359 error:
ba395927
KA		 2360 domain_exit(domain);
2361 return ret;
ba395927
KA		 2362}
2363
2364static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2365 struct pci_dev *pdev)
2366{
358dd8ac 2367 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2368 return 0;
2369 return iommu_prepare_identity_map(pdev, rmrr->base_address,
70e535d1 2370 rmrr->end_address);
ba395927
KA		 2371}
2372
d3f13810 2373#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2374static inline void iommu_prepare_isa(void)
2375{
2376 struct pci_dev *pdev;
2377 int ret;
2378
2379 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2380 if (!pdev)
2381 return;
2382
c7ab48d2 2383 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
70e535d1 2384 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2385
2386 if (ret)
c7ab48d2
DW		 2387 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2388 "floppy might not work\n");
49a0429e
KA		 2389
2390}
2391#else
2392static inline void iommu_prepare_isa(void)
2393{
2394 return;
2395}
d3f13810 2396#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2397
2c2e2c38 2398static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2399
071e1374 2400static int __init si_domain_init(int hw)
2c2e2c38
FY		 2401{
2402 struct dmar_drhd_unit *drhd;
2403 struct intel_iommu *iommu;
c7ab48d2 2404 int nid, ret = 0;
2c2e2c38 2405
92d03cc8 2406 si_domain = alloc_domain(false);
2c2e2c38
FY		 2407 if (!si_domain)
2408 return -EFAULT;
2409
92d03cc8
JL		 2410 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2411
2c2e2c38
FY		 2412 for_each_active_iommu(iommu, drhd) {
2413 ret = iommu_attach_domain(si_domain, iommu);
2414 if (ret) {
2415 domain_exit(si_domain);
2416 return -EFAULT;
2417 }
2418 }
2419
2420 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2421 domain_exit(si_domain);
2422 return -EFAULT;
2423 }
2424
9544c003
JL		 2425 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2426 si_domain->id);
2c2e2c38 2427
19943b0e
DW		 2428 if (hw)
2429 return 0;
2430
c7ab48d2 2431 for_each_online_node(nid) {
5dfe8660
TH		 2432 unsigned long start_pfn, end_pfn;
2433 int i;
2434
2435 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2436 ret = iommu_domain_identity_map(si_domain,
2437 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2438 if (ret)
2439 return ret;
2440 }
c7ab48d2
DW		 2441 }
2442
2c2e2c38
FY		 2443 return 0;
2444}
2445
2c2e2c38
FY		 2446static int identity_mapping(struct pci_dev *pdev)
2447{
2448 struct device_domain_info *info;
2449
2450 if (likely(!iommu_identity_mapping))
2451 return 0;
2452
cb452a40
MT		 2453 info = pdev->dev.archdata.iommu;
2454 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2455 return (info->domain == si_domain);
2c2e2c38 2456
2c2e2c38
FY		 2457 return 0;
2458}
2459
2460static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2461 struct pci_dev *pdev,
2462 int translation)
2c2e2c38 2463{
0ac72664 2464 struct dmar_domain *ndomain;
5a8f40e8 2465 struct intel_iommu *iommu;
5fe60f4e 2466 int ret;
2c2e2c38 2467
5a8f40e8
DW		 2468 iommu = device_to_iommu(pci_domain_nr(pdev->bus),
2469 pdev->bus->number, pdev->devfn);
2470 if (!iommu)
2471 return -ENODEV;
2472
2473 ndomain = dmar_insert_dev_info(iommu, pci_domain_nr(pdev->bus),
0ac72664
DW		 2474 pdev->bus->number, pdev->devfn,
2475 &pdev->dev, domain);
2476 if (ndomain != domain)
2477 return -EBUSY;
2c2e2c38 2478
e2ad23d0
DW		 2479 ret = domain_context_mapping(domain, pdev, translation);
2480 if (ret) {
e2f8c5f6 2481 domain_remove_one_dev_info(domain, pdev);
e2ad23d0
DW		 2482 return ret;
2483 }
2484
2c2e2c38
FY		 2485 return 0;
2486}
2487
ea2447f7
TM		 2488static bool device_has_rmrr(struct pci_dev *dev)
2489{
2490 struct dmar_rmrr_unit *rmrr;
832bd858 2491 struct device *tmp;
ea2447f7
TM		 2492 int i;
2493
0e242612 2494 rcu_read_lock();
ea2447f7 2495 for_each_rmrr_units(rmrr) {
b683b230
JL		 2496 /*
2497 * Return TRUE if this RMRR contains the device that
2498 * is passed in.
2499 */
2500 for_each_active_dev_scope(rmrr->devices,
2501 rmrr->devices_cnt, i, tmp)
832bd858 2502 if (tmp == &dev->dev) {
0e242612 2503 rcu_read_unlock();
ea2447f7 2504 return true;
b683b230 2505 }
ea2447f7 2506 }
0e242612 2507 rcu_read_unlock();
ea2447f7
TM		 2508 return false;
2509}
2510
6941af28
DW		 2511static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2512{
ea2447f7
TM		 2513
2514 /*
2515 * We want to prevent any device associated with an RMRR from
2516 * getting placed into the SI Domain. This is done because
2517 * problems exist when devices are moved in and out of domains
2518 * and their respective RMRR info is lost. We exempt USB devices
2519 * from this process due to their usage of RMRRs that are known
2520 * to not be needed after BIOS hand-off to OS.
2521 */
2522 if (device_has_rmrr(pdev) &&
2523 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2524 return 0;
2525
e0fc7e0b
DW		 2526 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2527 return 1;
2528
2529 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2530 return 1;
2531
2532 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2533 return 0;
6941af28 2534
3dfc813d
DW		 2535 /*
2536 * We want to start off with all devices in the 1:1 domain, and
2537 * take them out later if we find they can't access all of memory.
2538 *
2539 * However, we can't do this for PCI devices behind bridges,
2540 * because all PCI devices behind the same bridge will end up
2541 * with the same source-id on their transactions.
2542 *
2543 * Practically speaking, we can't change things around for these
2544 * devices at run-time, because we can't be sure there'll be no
2545 * DMA transactions in flight for any of their siblings.
2546 *
2547 * So PCI devices (unless they're on the root bus) as well as
2548 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2549 * the 1:1 domain, just in _case_ one of their siblings turns out
2550 * not to be able to map all of memory.
2551 */
5f4d91a1 2552 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2553 if (!pci_is_root_bus(pdev->bus))
2554 return 0;
2555 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2556 return 0;
62f87c0e 2557 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d
DW		 2558 return 0;
2559
2560 /*
2561 * At boot time, we don't yet know if devices will be 64-bit capable.
2562 * Assume that they will -- if they turn out not to be, then we can
2563 * take them out of the 1:1 domain later.
2564 */
8fcc5372
CW		 2565 if (!startup) {
2566 /*
2567 * If the device's dma_mask is less than the system's memory
2568 * size then this is not a candidate for identity mapping.
2569 */
2570 u64 dma_mask = pdev->dma_mask;
2571
2572 if (pdev->dev.coherent_dma_mask &&
2573 pdev->dev.coherent_dma_mask < dma_mask)
2574 dma_mask = pdev->dev.coherent_dma_mask;
2575
2576 return dma_mask >= dma_get_required_mask(&pdev->dev);
2577 }
6941af28
DW		 2578
2579 return 1;
2580}
2581
071e1374 2582static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2583{
2c2e2c38
FY		 2584 struct pci_dev *pdev = NULL;
2585 int ret;
2586
19943b0e 2587 ret = si_domain_init(hw);
2c2e2c38
FY		 2588 if (ret)
2589 return -EFAULT;
2590
2c2e2c38 2591 for_each_pci_dev(pdev) {
6941af28 2592 if (iommu_should_identity_map(pdev, 1)) {
5fe60f4e 2593 ret = domain_add_dev_info(si_domain, pdev,
eae460b6
MT		 2594 hw ? CONTEXT_TT_PASS_THROUGH :
2595 CONTEXT_TT_MULTI_LEVEL);
2596 if (ret) {
2597 /* device not associated with an iommu */
2598 if (ret == -ENODEV)
2599 continue;
62edf5dc 2600 return ret;
eae460b6
MT		 2601 }
2602 pr_info("IOMMU: %s identity mapping for device %s\n",
2603 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2604 }
2c2e2c38
FY		 2605 }
2606
2607 return 0;
2608}
2609
b779260b 2610static int __init init_dmars(void)
ba395927
KA		 2611{
2612 struct dmar_drhd_unit *drhd;
2613 struct dmar_rmrr_unit *rmrr;
832bd858 2614 struct device *dev;
ba395927 2615 struct intel_iommu *iommu;
9d783ba0 2616 int i, ret;
2c2e2c38 2617
ba395927
KA		 2618 /*
2619 * for each drhd
2620 * allocate root
2621 * initialize and program root entry to not present
2622 * endfor
2623 */
2624 for_each_drhd_unit(drhd) {
5e0d2a6f 2625 /*
2626 * lock not needed as this is only incremented in the single
2627 * threaded kernel __init code path all other access are read
2628 * only
2629 */
1b198bb0
MT		 2630 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2631 g_num_of_iommus++;
2632 continue;
2633 }
2634 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2635 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2636 }
2637
d9630fe9
WH		 2638 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2639 GFP_KERNEL);
2640 if (!g_iommus) {
2641 printk(KERN_ERR "Allocating global iommu array failed\n");
2642 ret = -ENOMEM;
2643 goto error;
2644 }
2645
80b20dd8 2646 deferred_flush = kzalloc(g_num_of_iommus *
2647 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2648 if (!deferred_flush) {
5e0d2a6f 2649 ret = -ENOMEM;
989d51fc 2650 goto free_g_iommus;
5e0d2a6f 2651 }
2652
7c919779 2653 for_each_active_iommu(iommu, drhd) {
d9630fe9 2654 g_iommus[iommu->seq_id] = iommu;
ba395927 2655
e61d98d8
SS		 2656 ret = iommu_init_domains(iommu);
2657 if (ret)
989d51fc 2658 goto free_iommu;
e61d98d8 2659
ba395927
KA		 2660 /*
2661 * TBD:
2662 * we could share the same root & context tables
25985edc 2663 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2664 */
2665 ret = iommu_alloc_root_entry(iommu);
2666 if (ret) {
2667 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2668 goto free_iommu;
ba395927 2669 }
4ed0d3e6 2670 if (!ecap_pass_through(iommu->ecap))
19943b0e 2671 hw_pass_through = 0;
ba395927
KA		 2672 }
2673
1531a6a6
SS		 2674 /*
2675 * Start from the sane iommu hardware state.
2676 */
7c919779 2677 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2678 /*
2679 * If the queued invalidation is already initialized by us
2680 * (for example, while enabling interrupt-remapping) then
2681 * we got the things already rolling from a sane state.
2682 */
2683 if (iommu->qi)
2684 continue;
2685
2686 /*
2687 * Clear any previous faults.
2688 */
2689 dmar_fault(-1, iommu);
2690 /*
2691 * Disable queued invalidation if supported and already enabled
2692 * before OS handover.
2693 */
2694 dmar_disable_qi(iommu);
2695 }
2696
7c919779 2697 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2698 if (dmar_enable_qi(iommu)) {
2699 /*
2700 * Queued Invalidate not enabled, use Register Based
2701 * Invalidate
2702 */
2703 iommu->flush.flush_context = __iommu_flush_context;
2704 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2705 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2706 "invalidation\n",
680a7524 2707 iommu->seq_id,
b4e0f9eb 2708 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2709 } else {
2710 iommu->flush.flush_context = qi_flush_context;
2711 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2712 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2713 "invalidation\n",
680a7524 2714 iommu->seq_id,
b4e0f9eb 2715 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2716 }
2717 }
2718
19943b0e 2719 if (iommu_pass_through)
e0fc7e0b
DW		 2720 iommu_identity_mapping |= IDENTMAP_ALL;
2721
d3f13810 2722#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2723 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2724#endif
e0fc7e0b
DW		 2725
2726 check_tylersburg_isoch();
2727
ba395927 2728 /*
19943b0e
DW		 2729 * If pass through is not set or not enabled, setup context entries for
2730 * identity mappings for rmrr, gfx, and isa and may fall back to static
2731 * identity mapping if iommu_identity_mapping is set.
ba395927 2732 */
19943b0e
DW		 2733 if (iommu_identity_mapping) {
2734 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2735 if (ret) {
19943b0e 2736 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2737 goto free_iommu;
ba395927
KA		 2738 }
2739 }
ba395927 2740 /*
19943b0e
DW		 2741 * For each rmrr
2742 * for each dev attached to rmrr
2743 * do
2744 * locate drhd for dev, alloc domain for dev
2745 * allocate free domain
2746 * allocate page table entries for rmrr
2747 * if context not allocated for bus
2748 * allocate and init context
2749 * set present in root table for this bus
2750 * init context with domain, translation etc
2751 * endfor
2752 * endfor
ba395927 2753 */
19943b0e
DW		 2754 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2755 for_each_rmrr_units(rmrr) {
b683b230
JL		 2756 /* some BIOS lists non-exist devices in DMAR table. */
2757 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858
DW		 2758 i, dev) {
2759 if (!dev_is_pci(dev))
2760 continue;
2761 ret = iommu_prepare_rmrr_dev(rmrr, to_pci_dev(dev));
19943b0e
DW		 2762 if (ret)
2763 printk(KERN_ERR
2764 "IOMMU: mapping reserved region failed\n");
ba395927 2765 }
4ed0d3e6 2766 }
49a0429e 2767
19943b0e
DW		 2768 iommu_prepare_isa();
2769
ba395927
KA		 2770 /*
2771 * for each drhd
2772 * enable fault log
2773 * global invalidate context cache
2774 * global invalidate iotlb
2775 * enable translation
2776 */
7c919779 2777 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2778 if (drhd->ignored) {
2779 /*
2780 * we always have to disable PMRs or DMA may fail on
2781 * this device
2782 */
2783 if (force_on)
7c919779 2784 iommu_disable_protect_mem_regions(iommu);
ba395927 2785 continue;
51a63e67 2786 }
ba395927
KA		 2787
2788 iommu_flush_write_buffer(iommu);
2789
3460a6d9
KA		 2790 ret = dmar_set_interrupt(iommu);
2791 if (ret)
989d51fc 2792 goto free_iommu;
3460a6d9 2793
ba395927
KA		 2794 iommu_set_root_entry(iommu);
2795
4c25a2c1 2796 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2797 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2798
ba395927
KA		 2799 ret = iommu_enable_translation(iommu);
2800 if (ret)
989d51fc 2801 goto free_iommu;
b94996c9
DW		 2802
2803 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2804 }
2805
2806 return 0;
989d51fc
JL		 2807
2808free_iommu:
7c919779 2809 for_each_active_iommu(iommu, drhd)
a868e6b7 2810 free_dmar_iommu(iommu);
9bdc531e 2811 kfree(deferred_flush);
989d51fc 2812free_g_iommus:
d9630fe9 2813 kfree(g_iommus);
989d51fc 2814error:
ba395927
KA		 2815 return ret;
2816}
2817
5a5e02a6 2818/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2819static struct iova *intel_alloc_iova(struct device *dev,
2820 struct dmar_domain *domain,
2821 unsigned long nrpages, uint64_t dma_mask)
ba395927 2822{
ba395927 2823 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2824 struct iova *iova = NULL;
ba395927 2825
875764de
DW		 2826 /* Restrict dma_mask to the width that the iommu can handle */
2827 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2828
2829 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2830 /*
2831 * First try to allocate an io virtual address in
284901a9 2832 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2833 * from higher range
ba395927 2834 */
875764de
DW		 2835 iova = alloc_iova(&domain->iovad, nrpages,
2836 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2837 if (iova)
2838 return iova;
2839 }
2840 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2841 if (unlikely(!iova)) {
2842 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2843 nrpages, pci_name(pdev));
f76aec76
KA		 2844 return NULL;
2845 }
2846
2847 return iova;
2848}
2849
147202aa 2850static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2851{
2852 struct dmar_domain *domain;
2853 int ret;
2854
2855 domain = get_domain_for_dev(pdev,
2856 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2857 if (!domain) {
2858 printk(KERN_ERR
2859 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2860 return NULL;
ba395927
KA		 2861 }
2862
2863 /* make sure context mapping is ok */
5331fe6f 2864 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2865 ret = domain_context_mapping(domain, pdev,
2866 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2867 if (ret) {
2868 printk(KERN_ERR
2869 "Domain context map for %s failed",
2870 pci_name(pdev));
4fe05bbc 2871 return NULL;
f76aec76 2872 }
ba395927
KA		 2873 }
2874
f76aec76
KA		 2875 return domain;
2876}
2877
147202aa
DW		 2878static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2879{
2880 struct device_domain_info *info;
2881
2882 /* No lock here, assumes no domain exit in normal case */
2883 info = dev->dev.archdata.iommu;
2884 if (likely(info))
2885 return info->domain;
2886
2887 return __get_valid_domain_for_dev(dev);
2888}
2889
3d89194a 2890static int iommu_dummy(struct device *dev)
2c2e2c38 2891{
3d89194a 2892 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2c2e2c38
FY		 2893}
2894
2895/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2896static int iommu_no_mapping(struct device *dev)
2c2e2c38 2897{
73676832 2898 struct pci_dev *pdev;
2c2e2c38
FY		 2899 int found;
2900
dbad0864 2901 if (unlikely(!dev_is_pci(dev)))
73676832
DW		 2902 return 1;
2903
3d89194a 2904 if (iommu_dummy(dev))
1e4c64c4
DW		 2905 return 1;
2906
2c2e2c38 2907 if (!iommu_identity_mapping)
1e4c64c4 2908 return 0;
2c2e2c38 2909
3d89194a 2910 pdev = to_pci_dev(dev);
2c2e2c38
FY		 2911 found = identity_mapping(pdev);
2912 if (found) {
6941af28 2913 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2914 return 1;
2915 else {
2916 /*
2917 * 32 bit DMA is removed from si_domain and fall back
2918 * to non-identity mapping.
2919 */
2920 domain_remove_one_dev_info(si_domain, pdev);
2921 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2922 pci_name(pdev));
2923 return 0;
2924 }
2925 } else {
2926 /*
2927 * In case of a detached 64 bit DMA device from vm, the device
2928 * is put into si_domain for identity mapping.
2929 */
6941af28 2930 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2931 int ret;
5fe60f4e
DW		 2932 ret = domain_add_dev_info(si_domain, pdev,
2933 hw_pass_through ?
2934 CONTEXT_TT_PASS_THROUGH :
2935 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2936 if (!ret) {
2937 printk(KERN_INFO "64bit %s uses identity mapping\n",
2938 pci_name(pdev));
2939 return 1;
2940 }
2941 }
2942 }
2943
1e4c64c4 2944 return 0;
2c2e2c38
FY		 2945}
2946
bb9e6d65
FT		 2947static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2948 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2949{
2950 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2951 struct dmar_domain *domain;
5b6985ce 2952 phys_addr_t start_paddr;
f76aec76
KA		 2953 struct iova *iova;
2954 int prot = 0;
6865f0d1 2955 int ret;
8c11e798 2956 struct intel_iommu *iommu;
33041ec0 2957 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2958
2959 BUG_ON(dir == DMA_NONE);
2c2e2c38 2960
73676832 2961 if (iommu_no_mapping(hwdev))
6865f0d1 2962 return paddr;
f76aec76
KA		 2963
2964 domain = get_valid_domain_for_dev(pdev);
2965 if (!domain)
2966 return 0;
2967
8c11e798 2968 iommu = domain_get_iommu(domain);
88cb6a74 2969 size = aligned_nrpages(paddr, size);
f76aec76 2970
c681d0ba 2971 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2972 if (!iova)
2973 goto error;
2974
ba395927
KA		 2975 /*
2976 * Check if DMAR supports zero-length reads on write only
2977 * mappings..
2978 */
2979 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2980 !cap_zlr(iommu->cap))
ba395927
KA		 2981 prot |= DMA_PTE_READ;
2982 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2983 prot |= DMA_PTE_WRITE;
2984 /*
6865f0d1 2985 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2986 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2987 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2988 * is not a big problem
2989 */
0ab36de2 2990 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2991 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2992 if (ret)
2993 goto error;
2994
1f0ef2aa
DW		 2995 /* it's a non-present to present mapping. Only flush if caching mode */
2996 if (cap_caching_mode(iommu->cap))
ea8ea460 2997 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 2998 else
8c11e798 2999 iommu_flush_write_buffer(iommu);
f76aec76 3000
03d6a246
DW		 3001 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3002 start_paddr += paddr & ~PAGE_MASK;
3003 return start_paddr;
ba395927 3004
ba395927 3005error:
f76aec76
KA		 3006 if (iova)
3007 __free_iova(&domain->iovad, iova);
4cf2e75d 3008 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 3009 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3010 return 0;
3011}
3012
ffbbef5c
FT		 3013static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3014 unsigned long offset, size_t size,
3015 enum dma_data_direction dir,
3016 struct dma_attrs *attrs)
bb9e6d65 3017{
ffbbef5c
FT		 3018 return __intel_map_single(dev, page_to_phys(page) + offset, size,
3019 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 3020}
3021
5e0d2a6f 3022static void flush_unmaps(void)
3023{
80b20dd8 3024 int i, j;
5e0d2a6f 3025
5e0d2a6f 3026 timer_on = 0;
3027
3028 /* just flush them all */
3029 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3030 struct intel_iommu *iommu = g_iommus[i];
3031 if (!iommu)
3032 continue;
c42d9f32 3033
9dd2fe89
YZ		 3034 if (!deferred_flush[i].next)
3035 continue;
3036
78d5f0f5
NA		 3037 /* In caching mode, global flushes turn emulation expensive */
3038 if (!cap_caching_mode(iommu->cap))
3039 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3040 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3041 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3042 unsigned long mask;
3043 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3044 struct dmar_domain *domain = deferred_flush[i].domain[j];
3045
3046 /* On real hardware multiple invalidations are expensive */
3047 if (cap_caching_mode(iommu->cap))
3048 iommu_flush_iotlb_psi(iommu, domain->id,
ea8ea460
DW		 3049 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3050 !deferred_flush[i].freelist[j], 0);
78d5f0f5
NA		 3051 else {
3052 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3053 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3054 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3055 }
93a23a72 3056 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3057 if (deferred_flush[i].freelist[j])
3058 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3059 }
9dd2fe89 3060 deferred_flush[i].next = 0;
5e0d2a6f 3061 }
3062
5e0d2a6f 3063 list_size = 0;
5e0d2a6f 3064}
3065
3066static void flush_unmaps_timeout(unsigned long data)
3067{
80b20dd8 3068 unsigned long flags;
3069
3070 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3071 flush_unmaps();
80b20dd8 3072 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3073}
3074
ea8ea460 3075static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3076{
3077 unsigned long flags;
80b20dd8 3078 int next, iommu_id;
8c11e798 3079 struct intel_iommu *iommu;
5e0d2a6f 3080
3081 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3082 if (list_size == HIGH_WATER_MARK)
3083 flush_unmaps();
3084
8c11e798
WH		 3085 iommu = domain_get_iommu(dom);
3086 iommu_id = iommu->seq_id;
c42d9f32 3087
80b20dd8 3088 next = deferred_flush[iommu_id].next;
3089 deferred_flush[iommu_id].domain[next] = dom;
3090 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3091 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3092 deferred_flush[iommu_id].next++;
5e0d2a6f 3093
3094 if (!timer_on) {
3095 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3096 timer_on = 1;
3097 }
3098 list_size++;
3099 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3100}
3101
ffbbef5c
FT		 3102static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3103 size_t size, enum dma_data_direction dir,
3104 struct dma_attrs *attrs)
ba395927 3105{
ba395927 3106 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 3107 struct dmar_domain *domain;
d794dc9b 3108 unsigned long start_pfn, last_pfn;
ba395927 3109 struct iova *iova;
8c11e798 3110 struct intel_iommu *iommu;
ea8ea460 3111 struct page *freelist;
ba395927 3112
73676832 3113 if (iommu_no_mapping(dev))
f76aec76 3114 return;
2c2e2c38 3115
1525a29a 3116 domain = find_domain(dev);
ba395927
KA		 3117 BUG_ON(!domain);
3118
8c11e798
WH		 3119 iommu = domain_get_iommu(domain);
3120
ba395927 3121 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3122 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3123 (unsigned long long)dev_addr))
ba395927 3124 return;
ba395927 3125
d794dc9b
DW		 3126 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3127 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3128
d794dc9b
DW		 3129 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3130 pci_name(pdev), start_pfn, last_pfn);
ba395927 3131
ea8ea460 3132 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3133
5e0d2a6f 3134 if (intel_iommu_strict) {
03d6a246 3135 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3136 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3137 /* free iova */
3138 __free_iova(&domain->iovad, iova);
ea8ea460 3139 dma_free_pagelist(freelist);
5e0d2a6f 3140 } else {
ea8ea460 3141 add_unmap(domain, iova, freelist);
5e0d2a6f 3142 /*
3143 * queue up the release of the unmap to save the 1/6th of the
3144 * cpu used up by the iotlb flush operation...
3145 */
5e0d2a6f 3146 }
ba395927
KA		 3147}
3148
d7ab5c46 3149static void *intel_alloc_coherent(struct device *hwdev, size_t size,
baa676fc
AP		 3150 dma_addr_t *dma_handle, gfp_t flags,
3151 struct dma_attrs *attrs)
ba395927
KA		 3152{
3153 void *vaddr;
3154 int order;
3155
5b6985ce 3156 size = PAGE_ALIGN(size);
ba395927 3157 order = get_order(size);
e8bb910d
AW		 3158
3159 if (!iommu_no_mapping(hwdev))
3160 flags &= ~(GFP_DMA | GFP_DMA32);
3161 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
3162 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
3163 flags |= GFP_DMA;
3164 else
3165 flags |= GFP_DMA32;
3166 }
ba395927
KA		 3167
3168 vaddr = (void *)__get_free_pages(flags, order);
3169 if (!vaddr)
3170 return NULL;
3171 memset(vaddr, 0, size);
3172
bb9e6d65
FT		 3173 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
3174 DMA_BIDIRECTIONAL,
3175 hwdev->coherent_dma_mask);
ba395927
KA		 3176 if (*dma_handle)
3177 return vaddr;
3178 free_pages((unsigned long)vaddr, order);
3179 return NULL;
3180}
3181
d7ab5c46 3182static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
baa676fc 3183 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3184{
3185 int order;
3186
5b6985ce 3187 size = PAGE_ALIGN(size);
ba395927
KA		 3188 order = get_order(size);
3189
0db9b7ae 3190 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 3191 free_pages((unsigned long)vaddr, order);
3192}
3193
d7ab5c46
FT		 3194static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
3195 int nelems, enum dma_data_direction dir,
3196 struct dma_attrs *attrs)
ba395927 3197{
ba395927 3198 struct dmar_domain *domain;
d794dc9b 3199 unsigned long start_pfn, last_pfn;
f76aec76 3200 struct iova *iova;
8c11e798 3201 struct intel_iommu *iommu;
ea8ea460 3202 struct page *freelist;
ba395927 3203
73676832 3204 if (iommu_no_mapping(hwdev))
ba395927
KA		 3205 return;
3206
1525a29a 3207 domain = find_domain(hwdev);
8c11e798
WH		 3208 BUG_ON(!domain);
3209
3210 iommu = domain_get_iommu(domain);
ba395927 3211
c03ab37c 3212 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 3213 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3214 (unsigned long long)sglist[0].dma_address))
f76aec76 3215 return;
f76aec76 3216
d794dc9b
DW		 3217 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3218 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76 3219
ea8ea460 3220 freelist = domain_unmap(domain, start_pfn, last_pfn);
f76aec76 3221
acea0018
DW		 3222 if (intel_iommu_strict) {
3223 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3224 last_pfn - start_pfn + 1, !freelist, 0);
acea0018
DW		 3225 /* free iova */
3226 __free_iova(&domain->iovad, iova);
ea8ea460 3227 dma_free_pagelist(freelist);
acea0018 3228 } else {
ea8ea460 3229 add_unmap(domain, iova, freelist);
acea0018
DW		 3230 /*
3231 * queue up the release of the unmap to save the 1/6th of the
3232 * cpu used up by the iotlb flush operation...
3233 */
3234 }
ba395927
KA		 3235}
3236
ba395927 3237static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3238 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3239{
3240 int i;
c03ab37c 3241 struct scatterlist *sg;
ba395927 3242
c03ab37c 3243 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3244 BUG_ON(!sg_page(sg));
4cf2e75d 3245 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3246 sg->dma_length = sg->length;
ba395927
KA		 3247 }
3248 return nelems;
3249}
3250
d7ab5c46
FT		 3251static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3252 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3253{
ba395927 3254 int i;
ba395927
KA		 3255 struct pci_dev *pdev = to_pci_dev(hwdev);
3256 struct dmar_domain *domain;
f76aec76
KA		 3257 size_t size = 0;
3258 int prot = 0;
f76aec76
KA		 3259 struct iova *iova = NULL;
3260 int ret;
c03ab37c 3261 struct scatterlist *sg;
b536d24d 3262 unsigned long start_vpfn;
8c11e798 3263 struct intel_iommu *iommu;
ba395927
KA		 3264
3265 BUG_ON(dir == DMA_NONE);
73676832 3266 if (iommu_no_mapping(hwdev))
c03ab37c 3267 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3268
f76aec76
KA		 3269 domain = get_valid_domain_for_dev(pdev);
3270 if (!domain)
3271 return 0;
3272
8c11e798
WH		 3273 iommu = domain_get_iommu(domain);
3274
b536d24d 3275 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3276 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3277
5a5e02a6
DW		 3278 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3279 pdev->dma_mask);
f76aec76 3280 if (!iova) {
c03ab37c 3281 sglist->dma_length = 0;
f76aec76
KA		 3282 return 0;
3283 }
3284
3285 /*
3286 * Check if DMAR supports zero-length reads on write only
3287 * mappings..
3288 */
3289 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3290 !cap_zlr(iommu->cap))
f76aec76
KA		 3291 prot |= DMA_PTE_READ;
3292 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3293 prot |= DMA_PTE_WRITE;
3294
b536d24d 3295 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3296
f532959b 3297 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3298 if (unlikely(ret)) {
3299 /* clear the page */
3300 dma_pte_clear_range(domain, start_vpfn,
3301 start_vpfn + size - 1);
3302 /* free page tables */
3303 dma_pte_free_pagetable(domain, start_vpfn,
3304 start_vpfn + size - 1);
3305 /* free iova */
3306 __free_iova(&domain->iovad, iova);
3307 return 0;
ba395927
KA		 3308 }
3309
1f0ef2aa
DW		 3310 /* it's a non-present to present mapping. Only flush if caching mode */
3311 if (cap_caching_mode(iommu->cap))
ea8ea460 3312 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3313 else
8c11e798 3314 iommu_flush_write_buffer(iommu);
1f0ef2aa 3315
ba395927
KA		 3316 return nelems;
3317}
3318
dfb805e8
FT		 3319static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3320{
3321 return !dma_addr;
3322}
3323
160c1d8e 3324struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3325 .alloc = intel_alloc_coherent,
3326 .free = intel_free_coherent,
ba395927
KA		 3327 .map_sg = intel_map_sg,
3328 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3329 .map_page = intel_map_page,
3330 .unmap_page = intel_unmap_page,
dfb805e8 3331 .mapping_error = intel_mapping_error,
ba395927
KA		 3332};
3333
3334static inline int iommu_domain_cache_init(void)
3335{
3336 int ret = 0;
3337
3338 iommu_domain_cache = kmem_cache_create("iommu_domain",
3339 sizeof(struct dmar_domain),
3340 0,
3341 SLAB_HWCACHE_ALIGN,
3342
3343 NULL);
3344 if (!iommu_domain_cache) {
3345 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3346 ret = -ENOMEM;
3347 }
3348
3349 return ret;
3350}
3351
3352static inline int iommu_devinfo_cache_init(void)
3353{
3354 int ret = 0;
3355
3356 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3357 sizeof(struct device_domain_info),
3358 0,
3359 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3360 NULL);
3361 if (!iommu_devinfo_cache) {
3362 printk(KERN_ERR "Couldn't create devinfo cache\n");
3363 ret = -ENOMEM;
3364 }
3365
3366 return ret;
3367}
3368
3369static inline int iommu_iova_cache_init(void)
3370{
3371 int ret = 0;
3372
3373 iommu_iova_cache = kmem_cache_create("iommu_iova",
3374 sizeof(struct iova),
3375 0,
3376 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3377 NULL);
3378 if (!iommu_iova_cache) {
3379 printk(KERN_ERR "Couldn't create iova cache\n");
3380 ret = -ENOMEM;
3381 }
3382
3383 return ret;
3384}
3385
3386static int __init iommu_init_mempool(void)
3387{
3388 int ret;
3389 ret = iommu_iova_cache_init();
3390 if (ret)
3391 return ret;
3392
3393 ret = iommu_domain_cache_init();
3394 if (ret)
3395 goto domain_error;
3396
3397 ret = iommu_devinfo_cache_init();
3398 if (!ret)
3399 return ret;
3400
3401 kmem_cache_destroy(iommu_domain_cache);
3402domain_error:
3403 kmem_cache_destroy(iommu_iova_cache);
3404
3405 return -ENOMEM;
3406}
3407
3408static void __init iommu_exit_mempool(void)
3409{
3410 kmem_cache_destroy(iommu_devinfo_cache);
3411 kmem_cache_destroy(iommu_domain_cache);
3412 kmem_cache_destroy(iommu_iova_cache);
3413
3414}
3415
556ab45f
DW		 3416static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3417{
3418 struct dmar_drhd_unit *drhd;
3419 u32 vtbar;
3420 int rc;
3421
3422 /* We know that this device on this chipset has its own IOMMU.
3423 * If we find it under a different IOMMU, then the BIOS is lying
3424 * to us. Hope that the IOMMU for this device is actually
3425 * disabled, and it needs no translation...
3426 */
3427 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3428 if (rc) {
3429 /* "can't" happen */
3430 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3431 return;
3432 }
3433 vtbar &= 0xffff0000;
3434
3435 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3436 drhd = dmar_find_matched_drhd_unit(pdev);
3437 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3438 TAINT_FIRMWARE_WORKAROUND,
3439 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3440 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3441}
3442DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3443
ba395927
KA		 3444static void __init init_no_remapping_devices(void)
3445{
3446 struct dmar_drhd_unit *drhd;
832bd858 3447 struct device *dev;
b683b230 3448 int i;
ba395927
KA		 3449
3450 for_each_drhd_unit(drhd) {
3451 if (!drhd->include_all) {
b683b230
JL		 3452 for_each_active_dev_scope(drhd->devices,
3453 drhd->devices_cnt, i, dev)
3454 break;
832bd858 3455 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3456 if (i == drhd->devices_cnt)
3457 drhd->ignored = 1;
3458 }
3459 }
3460
7c919779 3461 for_each_active_drhd_unit(drhd) {
7c919779 3462 if (drhd->include_all)
ba395927
KA		 3463 continue;
3464
b683b230
JL		 3465 for_each_active_dev_scope(drhd->devices,
3466 drhd->devices_cnt, i, dev)
832bd858 3467 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3468 break;
ba395927
KA		 3469 if (i < drhd->devices_cnt)
3470 continue;
3471
c0771df8
DW		 3472 /* This IOMMU has *only* gfx devices. Either bypass it or
3473 set the gfx_mapped flag, as appropriate */
3474 if (dmar_map_gfx) {
3475 intel_iommu_gfx_mapped = 1;
3476 } else {
3477 drhd->ignored = 1;
b683b230
JL		 3478 for_each_active_dev_scope(drhd->devices,
3479 drhd->devices_cnt, i, dev)
832bd858 3480 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3481 }
3482 }
3483}
3484
f59c7b69
FY		 3485#ifdef CONFIG_SUSPEND
3486static int init_iommu_hw(void)
3487{
3488 struct dmar_drhd_unit *drhd;
3489 struct intel_iommu *iommu = NULL;
3490
3491 for_each_active_iommu(iommu, drhd)
3492 if (iommu->qi)
3493 dmar_reenable_qi(iommu);
3494
b779260b
JC		 3495 for_each_iommu(iommu, drhd) {
3496 if (drhd->ignored) {
3497 /*
3498 * we always have to disable PMRs or DMA may fail on
3499 * this device
3500 */
3501 if (force_on)
3502 iommu_disable_protect_mem_regions(iommu);
3503 continue;
3504 }
3505
f59c7b69
FY		 3506 iommu_flush_write_buffer(iommu);
3507
3508 iommu_set_root_entry(iommu);
3509
3510 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3511 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3512 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3513 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3514 if (iommu_enable_translation(iommu))
3515 return 1;
b94996c9 3516 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3517 }
3518
3519 return 0;
3520}
3521
3522static void iommu_flush_all(void)
3523{
3524 struct dmar_drhd_unit *drhd;
3525 struct intel_iommu *iommu;
3526
3527 for_each_active_iommu(iommu, drhd) {
3528 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3529 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3530 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3531 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3532 }
3533}
3534
134fac3f 3535static int iommu_suspend(void)
f59c7b69
FY		 3536{
3537 struct dmar_drhd_unit *drhd;
3538 struct intel_iommu *iommu = NULL;
3539 unsigned long flag;
3540
3541 for_each_active_iommu(iommu, drhd) {
3542 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3543 GFP_ATOMIC);
3544 if (!iommu->iommu_state)
3545 goto nomem;
3546 }
3547
3548 iommu_flush_all();
3549
3550 for_each_active_iommu(iommu, drhd) {
3551 iommu_disable_translation(iommu);
3552
1f5b3c3f 3553 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3554
3555 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3556 readl(iommu->reg + DMAR_FECTL_REG);
3557 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3558 readl(iommu->reg + DMAR_FEDATA_REG);
3559 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3560 readl(iommu->reg + DMAR_FEADDR_REG);
3561 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3562 readl(iommu->reg + DMAR_FEUADDR_REG);
3563
1f5b3c3f 3564 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3565 }
3566 return 0;
3567
3568nomem:
3569 for_each_active_iommu(iommu, drhd)
3570 kfree(iommu->iommu_state);
3571
3572 return -ENOMEM;
3573}
3574
134fac3f 3575static void iommu_resume(void)
f59c7b69
FY		 3576{
3577 struct dmar_drhd_unit *drhd;
3578 struct intel_iommu *iommu = NULL;
3579 unsigned long flag;
3580
3581 if (init_iommu_hw()) {
b779260b
JC		 3582 if (force_on)
3583 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3584 else
3585 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3586 return;
f59c7b69
FY		 3587 }
3588
3589 for_each_active_iommu(iommu, drhd) {
3590
1f5b3c3f 3591 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3592
3593 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3594 iommu->reg + DMAR_FECTL_REG);
3595 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3596 iommu->reg + DMAR_FEDATA_REG);
3597 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3598 iommu->reg + DMAR_FEADDR_REG);
3599 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3600 iommu->reg + DMAR_FEUADDR_REG);
3601
1f5b3c3f 3602 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3603 }
3604
3605 for_each_active_iommu(iommu, drhd)
3606 kfree(iommu->iommu_state);
f59c7b69
FY		 3607}
3608
134fac3f 3609static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3610 .resume = iommu_resume,
3611 .suspend = iommu_suspend,
3612};
3613
134fac3f 3614static void __init init_iommu_pm_ops(void)
f59c7b69 3615{
134fac3f 3616 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3617}
3618
3619#else
99592ba4 3620static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3621#endif /* CONFIG_PM */
3622
318fe7df
SS		 3623
3624int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3625{
3626 struct acpi_dmar_reserved_memory *rmrr;
3627 struct dmar_rmrr_unit *rmrru;
3628
3629 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3630 if (!rmrru)
3631 return -ENOMEM;
3632
3633 rmrru->hdr = header;
3634 rmrr = (struct acpi_dmar_reserved_memory *)header;
3635 rmrru->base_address = rmrr->base_address;
3636 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3637 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3638 ((void *)rmrr) + rmrr->header.length,
3639 &rmrru->devices_cnt);
3640 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3641 kfree(rmrru);
3642 return -ENOMEM;
3643 }
318fe7df 3644
2e455289 3645 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3646
2e455289 3647 return 0;
318fe7df
SS		 3648}
3649
318fe7df
SS		 3650int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3651{
3652 struct acpi_dmar_atsr *atsr;
3653 struct dmar_atsr_unit *atsru;
3654
3655 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3656 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3657 if (!atsru)
3658 return -ENOMEM;
3659
3660 atsru->hdr = hdr;
3661 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3662 if (!atsru->include_all) {
3663 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3664 (void *)atsr + atsr->header.length,
3665 &atsru->devices_cnt);
3666 if (atsru->devices_cnt && atsru->devices == NULL) {
3667 kfree(atsru);
3668 return -ENOMEM;
3669 }
3670 }
318fe7df 3671
0e242612 3672 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3673
3674 return 0;
3675}
3676
9bdc531e
JL		 3677static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3678{
3679 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3680 kfree(atsru);
3681}
3682
3683static void intel_iommu_free_dmars(void)
3684{
3685 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3686 struct dmar_atsr_unit *atsru, *atsr_n;
3687
3688 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3689 list_del(&rmrru->list);
3690 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3691 kfree(rmrru);
318fe7df
SS		 3692 }
3693
9bdc531e
JL		 3694 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3695 list_del(&atsru->list);
3696 intel_iommu_free_atsr(atsru);
3697 }
318fe7df
SS		 3698}
3699
3700int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3701{
b683b230 3702 int i, ret = 1;
318fe7df 3703 struct pci_bus *bus;
832bd858
DW		 3704 struct pci_dev *bridge = NULL;
3705 struct device *tmp;
318fe7df
SS		 3706 struct acpi_dmar_atsr *atsr;
3707 struct dmar_atsr_unit *atsru;
3708
3709 dev = pci_physfn(dev);
318fe7df 3710 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3711 bridge = bus->self;
318fe7df 3712 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3713 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3714 return 0;
b5f82ddf 3715 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3716 break;
318fe7df 3717 }
b5f82ddf
JL		 3718 if (!bridge)
3719 return 0;
318fe7df 3720
0e242612 3721 rcu_read_lock();
b5f82ddf
JL		 3722 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3723 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3724 if (atsr->segment != pci_domain_nr(dev->bus))
3725 continue;
3726
b683b230 3727 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 3728 if (tmp == &bridge->dev)
b683b230 3729 goto out;
b5f82ddf
JL		 3730
3731 if (atsru->include_all)
b683b230 3732 goto out;
b5f82ddf 3733 }
b683b230
JL		 3734 ret = 0;
3735out:
0e242612 3736 rcu_read_unlock();
318fe7df 3737
b683b230 3738 return ret;
318fe7df
SS		 3739}
3740
59ce0515
JL		 3741int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3742{
3743 int ret = 0;
3744 struct dmar_rmrr_unit *rmrru;
3745 struct dmar_atsr_unit *atsru;
3746 struct acpi_dmar_atsr *atsr;
3747 struct acpi_dmar_reserved_memory *rmrr;
3748
3749 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3750 return 0;
3751
3752 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3753 rmrr = container_of(rmrru->hdr,
3754 struct acpi_dmar_reserved_memory, header);
3755 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3756 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3757 ((void *)rmrr) + rmrr->header.length,
3758 rmrr->segment, rmrru->devices,
3759 rmrru->devices_cnt);
3760 if (ret > 0)
3761 break;
3762 else if(ret < 0)
3763 return ret;
3764 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3765 if (dmar_remove_dev_scope(info, rmrr->segment,
3766 rmrru->devices, rmrru->devices_cnt))
3767 break;
3768 }
3769 }
3770
3771 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3772 if (atsru->include_all)
3773 continue;
3774
3775 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3776 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3777 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3778 (void *)atsr + atsr->header.length,
3779 atsr->segment, atsru->devices,
3780 atsru->devices_cnt);
3781 if (ret > 0)
3782 break;
3783 else if(ret < 0)
3784 return ret;
3785 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3786 if (dmar_remove_dev_scope(info, atsr->segment,
3787 atsru->devices, atsru->devices_cnt))
3788 break;
3789 }
3790 }
3791
3792 return 0;
3793}
3794
99dcaded
FY		 3795/*
3796 * Here we only respond to action of unbound device from driver.
3797 *
3798 * Added device is not attached to its DMAR domain here yet. That will happen
3799 * when mapping the device to iova.
3800 */
3801static int device_notifier(struct notifier_block *nb,
3802 unsigned long action, void *data)
3803{
3804 struct device *dev = data;
3805 struct pci_dev *pdev = to_pci_dev(dev);
3806 struct dmar_domain *domain;
3807
3d89194a 3808 if (iommu_dummy(dev))
44cd613c
DW		 3809 return 0;
3810
7e7dfab7
JL		 3811 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3812 action != BUS_NOTIFY_DEL_DEVICE)
3813 return 0;
3814
1525a29a 3815 domain = find_domain(dev);
99dcaded
FY		 3816 if (!domain)
3817 return 0;
3818
3a5670e8 3819 down_read(&dmar_global_lock);
7e7dfab7
JL		 3820 domain_remove_one_dev_info(domain, pdev);
3821 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3822 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3823 list_empty(&domain->devices))
3824 domain_exit(domain);
3a5670e8 3825 up_read(&dmar_global_lock);
a97590e5 3826
99dcaded
FY		 3827 return 0;
3828}
3829
3830static struct notifier_block device_nb = {
3831 .notifier_call = device_notifier,
3832};
3833
75f05569
JL		 3834static int intel_iommu_memory_notifier(struct notifier_block *nb,
3835 unsigned long val, void *v)
3836{
3837 struct memory_notify *mhp = v;
3838 unsigned long long start, end;
3839 unsigned long start_vpfn, last_vpfn;
3840
3841 switch (val) {
3842 case MEM_GOING_ONLINE:
3843 start = mhp->start_pfn << PAGE_SHIFT;
3844 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3845 if (iommu_domain_identity_map(si_domain, start, end)) {
3846 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3847 start, end);
3848 return NOTIFY_BAD;
3849 }
3850 break;
3851
3852 case MEM_OFFLINE:
3853 case MEM_CANCEL_ONLINE:
3854 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3855 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3856 while (start_vpfn <= last_vpfn) {
3857 struct iova *iova;
3858 struct dmar_drhd_unit *drhd;
3859 struct intel_iommu *iommu;
ea8ea460 3860 struct page *freelist;
75f05569
JL		 3861
3862 iova = find_iova(&si_domain->iovad, start_vpfn);
3863 if (iova == NULL) {
3864 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3865 start_vpfn);
3866 break;
3867 }
3868
3869 iova = split_and_remove_iova(&si_domain->iovad, iova,
3870 start_vpfn, last_vpfn);
3871 if (iova == NULL) {
3872 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3873 start_vpfn, last_vpfn);
3874 return NOTIFY_BAD;
3875 }
3876
ea8ea460
DW		 3877 freelist = domain_unmap(si_domain, iova->pfn_lo,
3878 iova->pfn_hi);
3879
75f05569
JL		 3880 rcu_read_lock();
3881 for_each_active_iommu(iommu, drhd)
3882 iommu_flush_iotlb_psi(iommu, si_domain->id,
3883 iova->pfn_lo,
ea8ea460
DW		 3884 iova->pfn_hi - iova->pfn_lo + 1,
3885 !freelist, 0);
75f05569 3886 rcu_read_unlock();
ea8ea460 3887 dma_free_pagelist(freelist);
75f05569
JL		 3888
3889 start_vpfn = iova->pfn_hi + 1;
3890 free_iova_mem(iova);
3891 }
3892 break;
3893 }
3894
3895 return NOTIFY_OK;
3896}
3897
3898static struct notifier_block intel_iommu_memory_nb = {
3899 .notifier_call = intel_iommu_memory_notifier,
3900 .priority = 0
3901};
3902
ba395927
KA		 3903int __init intel_iommu_init(void)
3904{
9bdc531e 3905 int ret = -ENODEV;
3a93c841 3906 struct dmar_drhd_unit *drhd;
7c919779 3907 struct intel_iommu *iommu;
ba395927 3908
a59b50e9
JC		 3909 /* VT-d is required for a TXT/tboot launch, so enforce that */
3910 force_on = tboot_force_iommu();
3911
3a5670e8
JL		 3912 if (iommu_init_mempool()) {
3913 if (force_on)
3914 panic("tboot: Failed to initialize iommu memory\n");
3915 return -ENOMEM;
3916 }
3917
3918 down_write(&dmar_global_lock);
a59b50e9
JC		 3919 if (dmar_table_init()) {
3920 if (force_on)
3921 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 3922 goto out_free_dmar;
a59b50e9 3923 }
ba395927 3924
3a93c841
TI		 3925 /*
3926 * Disable translation if already enabled prior to OS handover.
3927 */
7c919779 3928 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 3929 if (iommu->gcmd & DMA_GCMD_TE)
3930 iommu_disable_translation(iommu);
3a93c841 3931
c2c7286a 3932 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3933 if (force_on)
3934 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 3935 goto out_free_dmar;
a59b50e9 3936 }
1886e8a9 3937
75f1cdf1 3938 if (no_iommu || dmar_disabled)
9bdc531e 3939 goto out_free_dmar;
2ae21010 3940
318fe7df
SS		 3941 if (list_empty(&dmar_rmrr_units))
3942 printk(KERN_INFO "DMAR: No RMRR found\n");
3943
3944 if (list_empty(&dmar_atsr_units))
3945 printk(KERN_INFO "DMAR: No ATSR found\n");
3946
51a63e67
JC		 3947 if (dmar_init_reserved_ranges()) {
3948 if (force_on)
3949 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 3950 goto out_free_reserved_range;
51a63e67 3951 }
ba395927
KA		 3952
3953 init_no_remapping_devices();
3954
b779260b 3955 ret = init_dmars();
ba395927 3956 if (ret) {
a59b50e9
JC		 3957 if (force_on)
3958 panic("tboot: Failed to initialize DMARs\n");
ba395927 3959 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 3960 goto out_free_reserved_range;
ba395927 3961 }
3a5670e8 3962 up_write(&dmar_global_lock);
ba395927
KA		 3963 printk(KERN_INFO
3964 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3965
5e0d2a6f 3966 init_timer(&unmap_timer);
75f1cdf1
FT		 3967#ifdef CONFIG_SWIOTLB
3968 swiotlb = 0;
3969#endif
19943b0e 3970 dma_ops = &intel_dma_ops;
4ed0d3e6 3971
134fac3f 3972 init_iommu_pm_ops();
a8bcbb0d 3973
4236d97d 3974 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 3975 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 3976 if (si_domain && !hw_pass_through)
3977 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 3978
8bc1f85c
ED		 3979 intel_iommu_enabled = 1;
3980
ba395927 3981 return 0;
9bdc531e
JL		 3982
3983out_free_reserved_range:
3984 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 3985out_free_dmar:
3986 intel_iommu_free_dmars();
3a5670e8
JL		 3987 up_write(&dmar_global_lock);
3988 iommu_exit_mempool();
9bdc531e 3989 return ret;
ba395927 3990}
e820482c 3991
3199aa6b 3992static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 3993 struct device *dev)
3199aa6b 3994{
0bcb3e28 3995 struct pci_dev *tmp, *parent, *pdev;
3199aa6b 3996
0bcb3e28 3997 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 3998 return;
3999
0bcb3e28
DW		 4000 pdev = to_pci_dev(dev);
4001
3199aa6b
HW		 4002 /* dependent device detach */
4003 tmp = pci_find_upstream_pcie_bridge(pdev);
4004 /* Secondary interface's bus number and devfn 0 */
4005 if (tmp) {
4006 parent = pdev->bus->self;
4007 while (parent != tmp) {
4008 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 4009 parent->devfn);
3199aa6b
HW		 4010 parent = parent->bus->self;
4011 }
45e829ea 4012 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 4013 iommu_detach_dev(iommu,
4014 tmp->subordinate->number, 0);
4015 else /* this is a legacy PCI bridge */
276dbf99
DW		 4016 iommu_detach_dev(iommu, tmp->bus->number,
4017 tmp->devfn);
3199aa6b
HW		 4018 }
4019}
4020
2c2e2c38 4021static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 4022 struct pci_dev *pdev)
4023{
bca2b916 4024 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4025 struct intel_iommu *iommu;
4026 unsigned long flags;
4027 int found = 0;
c7151a8d 4028
276dbf99
DW		 4029 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4030 pdev->devfn);
c7151a8d
WH		 4031 if (!iommu)
4032 return;
4033
4034 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4035 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
8519dc44
MH		 4036 if (info->segment == pci_domain_nr(pdev->bus) &&
4037 info->bus == pdev->bus->number &&
c7151a8d 4038 info->devfn == pdev->devfn) {
109b9b04 4039 unlink_domain_info(info);
c7151a8d
WH		 4040 spin_unlock_irqrestore(&device_domain_lock, flags);
4041
93a23a72 4042 iommu_disable_dev_iotlb(info);
c7151a8d 4043 iommu_detach_dev(iommu, info->bus, info->devfn);
0bcb3e28 4044 iommu_detach_dependent_devices(iommu, &pdev->dev);
c7151a8d
WH		 4045 free_devinfo_mem(info);
4046
4047 spin_lock_irqsave(&device_domain_lock, flags);
4048
4049 if (found)
4050 break;
4051 else
4052 continue;
4053 }
4054
4055 /* if there is no other devices under the same iommu
4056 * owned by this domain, clear this iommu in iommu_bmp
4057 * update iommu count and coherency
4058 */
8bbc4410 4059 if (info->iommu == iommu)
c7151a8d
WH		 4060 found = 1;
4061 }
4062
3e7abe25
RD		 4063 spin_unlock_irqrestore(&device_domain_lock, flags);
4064
c7151a8d
WH		 4065 if (found == 0) {
4066 unsigned long tmp_flags;
4067 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
1b198bb0 4068 clear_bit(iommu->seq_id, domain->iommu_bmp);
c7151a8d 4069 domain->iommu_count--;
58c610bd 4070 domain_update_iommu_cap(domain);
c7151a8d 4071 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 4072
9b4554b2
AW		 4073 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
4074 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
4075 spin_lock_irqsave(&iommu->lock, tmp_flags);
4076 clear_bit(domain->id, iommu->domain_ids);
4077 iommu->domains[domain->id] = NULL;
4078 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
4079 }
c7151a8d 4080 }
c7151a8d
WH		 4081}
4082
2c2e2c38 4083static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4084{
4085 int adjust_width;
4086
4087 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 4088 domain_reserve_special_ranges(domain);
4089
4090 /* calculate AGAW */
4091 domain->gaw = guest_width;
4092 adjust_width = guestwidth_to_adjustwidth(guest_width);
4093 domain->agaw = width_to_agaw(adjust_width);
4094
5e98c4b1 4095 domain->iommu_coherency = 0;
c5b15255 4096 domain->iommu_snooping = 0;
6dd9a7c7 4097 domain->iommu_superpage = 0;
fe40f1e0 4098 domain->max_addr = 0;
4c923d47 4099 domain->nid = -1;
5e98c4b1
WH		 4100
4101 /* always allocate the top pgd */
4c923d47 4102 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4103 if (!domain->pgd)
4104 return -ENOMEM;
4105 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4106 return 0;
4107}
4108
5d450806 4109static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 4110{
5d450806 4111 struct dmar_domain *dmar_domain;
38717946 4112
92d03cc8 4113 dmar_domain = alloc_domain(true);
5d450806 4114 if (!dmar_domain) {
38717946 4115 printk(KERN_ERR
5d450806
JR		 4116 "intel_iommu_domain_init: dmar_domain == NULL\n");
4117 return -ENOMEM;
38717946 4118 }
2c2e2c38 4119 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 4120 printk(KERN_ERR
5d450806 4121 "intel_iommu_domain_init() failed\n");
92d03cc8 4122 domain_exit(dmar_domain);
5d450806 4123 return -ENOMEM;
38717946 4124 }
8140a95d 4125 domain_update_iommu_cap(dmar_domain);
5d450806 4126 domain->priv = dmar_domain;
faa3d6f5 4127
8a0e715b
JR		 4128 domain->geometry.aperture_start = 0;
4129 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4130 domain->geometry.force_aperture = true;
4131
5d450806 4132 return 0;
38717946 4133}
38717946 4134
5d450806 4135static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 4136{
5d450806
JR		 4137 struct dmar_domain *dmar_domain = domain->priv;
4138
4139 domain->priv = NULL;
92d03cc8 4140 domain_exit(dmar_domain);
38717946 4141}
38717946 4142
4c5478c9
JR		 4143static int intel_iommu_attach_device(struct iommu_domain *domain,
4144 struct device *dev)
38717946 4145{
4c5478c9
JR		 4146 struct dmar_domain *dmar_domain = domain->priv;
4147 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 4148 struct intel_iommu *iommu;
4149 int addr_width;
faa3d6f5
WH		 4150
4151 /* normally pdev is not mapped */
4152 if (unlikely(domain_context_mapped(pdev))) {
4153 struct dmar_domain *old_domain;
4154
1525a29a 4155 old_domain = find_domain(dev);
faa3d6f5 4156 if (old_domain) {
2c2e2c38
FY		 4157 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
4158 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
4159 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 4160 else
4161 domain_remove_dev_info(old_domain);
4162 }
4163 }
4164
276dbf99
DW		 4165 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4166 pdev->devfn);
fe40f1e0
WH		 4167 if (!iommu)
4168 return -ENODEV;
4169
4170 /* check if this iommu agaw is sufficient for max mapped address */
4171 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4172 if (addr_width > cap_mgaw(iommu->cap))
4173 addr_width = cap_mgaw(iommu->cap);
4174
4175 if (dmar_domain->max_addr > (1LL << addr_width)) {
4176 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4177 "sufficient for the mapped address (%llx)\n",
a99c47a2 4178 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4179 return -EFAULT;
4180 }
a99c47a2
TL		 4181 dmar_domain->gaw = addr_width;
4182
4183 /*
4184 * Knock out extra levels of page tables if necessary
4185 */
4186 while (iommu->agaw < dmar_domain->agaw) {
4187 struct dma_pte *pte;
4188
4189 pte = dmar_domain->pgd;
4190 if (dma_pte_present(pte)) {
25cbff16
SY		 4191 dmar_domain->pgd = (struct dma_pte *)
4192 phys_to_virt(dma_pte_addr(pte));
7a661013 4193 free_pgtable_page(pte);
a99c47a2
TL		 4194 }
4195 dmar_domain->agaw--;
4196 }
fe40f1e0 4197
5fe60f4e 4198 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 4199}
38717946 4200
4c5478c9
JR		 4201static void intel_iommu_detach_device(struct iommu_domain *domain,
4202 struct device *dev)
38717946 4203{
4c5478c9
JR		 4204 struct dmar_domain *dmar_domain = domain->priv;
4205 struct pci_dev *pdev = to_pci_dev(dev);
4206
2c2e2c38 4207 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 4208}
c7151a8d 4209
b146a1c9
JR		 4210static int intel_iommu_map(struct iommu_domain *domain,
4211 unsigned long iova, phys_addr_t hpa,
5009065d 4212 size_t size, int iommu_prot)
faa3d6f5 4213{
dde57a21 4214 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4215 u64 max_addr;
dde57a21 4216 int prot = 0;
faa3d6f5 4217 int ret;
fe40f1e0 4218
dde57a21
JR		 4219 if (iommu_prot & IOMMU_READ)
4220 prot |= DMA_PTE_READ;
4221 if (iommu_prot & IOMMU_WRITE)
4222 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4223 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4224 prot |= DMA_PTE_SNP;
dde57a21 4225
163cc52c 4226 max_addr = iova + size;
dde57a21 4227 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4228 u64 end;
4229
4230 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4231 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4232 if (end < max_addr) {
8954da1f 4233 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4234 "sufficient for the mapped address (%llx)\n",
8954da1f 4235 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4236 return -EFAULT;
4237 }
dde57a21 4238 dmar_domain->max_addr = max_addr;
fe40f1e0 4239 }
ad051221
DW		 4240 /* Round up size to next multiple of PAGE_SIZE, if it and
4241 the low bits of hpa would take us onto the next page */
88cb6a74 4242 size = aligned_nrpages(hpa, size);
ad051221
DW		 4243 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4244 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4245 return ret;
38717946 4246}
38717946 4247
5009065d 4248static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4249 unsigned long iova, size_t size)
38717946 4250{
dde57a21 4251 struct dmar_domain *dmar_domain = domain->priv;
ea8ea460
DW		 4252 struct page *freelist = NULL;
4253 struct intel_iommu *iommu;
4254 unsigned long start_pfn, last_pfn;
4255 unsigned int npages;
4256 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4257
4258 /* Cope with horrid API which requires us to unmap more than the
4259 size argument if it happens to be a large-page mapping. */
4260 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4261 BUG();
4262
4263 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4264 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4265
ea8ea460
DW		 4266 start_pfn = iova >> VTD_PAGE_SHIFT;
4267 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4268
4269 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4270
4271 npages = last_pfn - start_pfn + 1;
4272
4273 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4274 iommu = g_iommus[iommu_id];
4275
4276 /*
4277 * find bit position of dmar_domain
4278 */
4279 ndomains = cap_ndoms(iommu->cap);
4280 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4281 if (iommu->domains[num] == dmar_domain)
4282 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4283 npages, !freelist, 0);
4284 }
4285
4286 }
4287
4288 dma_free_pagelist(freelist);
fe40f1e0 4289
163cc52c
DW		 4290 if (dmar_domain->max_addr == iova + size)
4291 dmar_domain->max_addr = iova;
b146a1c9 4292
5cf0a76f 4293 return size;
38717946 4294}
38717946 4295
d14d6577 4296static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4297 dma_addr_t iova)
38717946 4298{
d14d6577 4299 struct dmar_domain *dmar_domain = domain->priv;
38717946 4300 struct dma_pte *pte;
5cf0a76f 4301 int level = 0;
faa3d6f5 4302 u64 phys = 0;
38717946 4303
5cf0a76f 4304 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4305 if (pte)
faa3d6f5 4306 phys = dma_pte_addr(pte);
38717946 4307
faa3d6f5 4308 return phys;
38717946 4309}
a8bcbb0d 4310
dbb9fd86
SY		 4311static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4312 unsigned long cap)
4313{
4314 struct dmar_domain *dmar_domain = domain->priv;
4315
4316 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4317 return dmar_domain->iommu_snooping;
323f99cb 4318 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4319 return irq_remapping_enabled;
dbb9fd86
SY		 4320
4321 return 0;
4322}
4323
783f157b 4324#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
70ae6f0d 4325
abdfdde2
AW		 4326static int intel_iommu_add_device(struct device *dev)
4327{
4328 struct pci_dev *pdev = to_pci_dev(dev);
3da4af0a 4329 struct pci_dev *bridge, *dma_pdev = NULL;
abdfdde2
AW		 4330 struct iommu_group *group;
4331 int ret;
70ae6f0d 4332
abdfdde2
AW		 4333 if (!device_to_iommu(pci_domain_nr(pdev->bus),
4334 pdev->bus->number, pdev->devfn))
70ae6f0d
AW		 4335 return -ENODEV;
4336
4337 bridge = pci_find_upstream_pcie_bridge(pdev);
4338 if (bridge) {
abdfdde2
AW		 4339 if (pci_is_pcie(bridge))
4340 dma_pdev = pci_get_domain_bus_and_slot(
4341 pci_domain_nr(pdev->bus),
4342 bridge->subordinate->number, 0);
3da4af0a 4343 if (!dma_pdev)
abdfdde2
AW		 4344 dma_pdev = pci_dev_get(bridge);
4345 } else
4346 dma_pdev = pci_dev_get(pdev);
4347
a4ff1fc2 4348 /* Account for quirked devices */
783f157b
AW		 4349 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4350
a4ff1fc2
AW		 4351 /*
4352 * If it's a multifunction device that does not support our
c14d2690
AW		 4353 * required ACS flags, add to the same group as lowest numbered
4354 * function that also does not suport the required ACS flags.
a4ff1fc2 4355 */
783f157b 4356 if (dma_pdev->multifunction &&
c14d2690
AW		 4357 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4358 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4359
4360 for (i = 0; i < 8; i++) {
4361 struct pci_dev *tmp;
4362
4363 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4364 if (!tmp)
4365 continue;
4366
4367 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4368 swap_pci_ref(&dma_pdev, tmp);
4369 break;
4370 }
4371 pci_dev_put(tmp);
4372 }
4373 }
783f157b 4374
a4ff1fc2
AW		 4375 /*
4376 * Devices on the root bus go through the iommu. If that's not us,
4377 * find the next upstream device and test ACS up to the root bus.
4378 * Finding the next device may require skipping virtual buses.
4379 */
783f157b 4380 while (!pci_is_root_bus(dma_pdev->bus)) {
a4ff1fc2
AW		 4381 struct pci_bus *bus = dma_pdev->bus;
4382
4383 while (!bus->self) {
4384 if (!pci_is_root_bus(bus))
4385 bus = bus->parent;
4386 else
4387 goto root_bus;
4388 }
4389
4390 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
783f157b
AW		 4391 break;
4392
a4ff1fc2 4393 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
783f157b
AW		 4394 }
4395
a4ff1fc2 4396root_bus:
abdfdde2
AW		 4397 group = iommu_group_get(&dma_pdev->dev);
4398 pci_dev_put(dma_pdev);
4399 if (!group) {
4400 group = iommu_group_alloc();
4401 if (IS_ERR(group))
4402 return PTR_ERR(group);
70ae6f0d
AW		 4403 }
4404
abdfdde2 4405 ret = iommu_group_add_device(group, dev);
bcb71abe 4406
abdfdde2
AW		 4407 iommu_group_put(group);
4408 return ret;
4409}
70ae6f0d 4410
abdfdde2
AW		 4411static void intel_iommu_remove_device(struct device *dev)
4412{
4413 iommu_group_remove_device(dev);
70ae6f0d
AW		 4414}
4415
a8bcbb0d
JR		 4416static struct iommu_ops intel_iommu_ops = {
4417 .domain_init = intel_iommu_domain_init,
4418 .domain_destroy = intel_iommu_domain_destroy,
4419 .attach_dev = intel_iommu_attach_device,
4420 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4421 .map = intel_iommu_map,
4422 .unmap = intel_iommu_unmap,
a8bcbb0d 4423 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4424 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4425 .add_device = intel_iommu_add_device,
4426 .remove_device = intel_iommu_remove_device,
6d1c56a9 4427 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4428};
9af88143 4429
9452618e
DV		 4430static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4431{
4432 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4433 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4434 dmar_map_gfx = 0;
4435}
4436
4437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4444
d34d6517 4445static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4446{
4447 /*
4448 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4449 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4450 */
4451 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4452 rwbf_quirk = 1;
4453}
4454
4455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4457DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4462
eecfd57f
AJ		 4463#define GGC 0x52
4464#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4465#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4466#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4467#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4468#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4469#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4470#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4471#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4472
d34d6517 4473static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4474{
4475 unsigned short ggc;
4476
eecfd57f 4477 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4478 return;
4479
eecfd57f 4480 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4481 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4482 dmar_map_gfx = 0;
6fbcfb3e
DW		 4483 } else if (dmar_map_gfx) {
4484 /* we have to ensure the gfx device is idle before we flush */
4485 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4486 intel_iommu_strict = 1;
4487 }
9eecabcb
DW		 4488}
4489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4492DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4493
e0fc7e0b
DW		 4494/* On Tylersburg chipsets, some BIOSes have been known to enable the
4495 ISOCH DMAR unit for the Azalia sound device, but not give it any
4496 TLB entries, which causes it to deadlock. Check for that. We do
4497 this in a function called from init_dmars(), instead of in a PCI
4498 quirk, because we don't want to print the obnoxious "BIOS broken"
4499 message if VT-d is actually disabled.
4500*/
4501static void __init check_tylersburg_isoch(void)
4502{
4503 struct pci_dev *pdev;
4504 uint32_t vtisochctrl;
4505
4506 /* If there's no Azalia in the system anyway, forget it. */
4507 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4508 if (!pdev)
4509 return;
4510 pci_dev_put(pdev);
4511
4512 /* System Management Registers. Might be hidden, in which case
4513 we can't do the sanity check. But that's OK, because the
4514 known-broken BIOSes _don't_ actually hide it, so far. */
4515 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4516 if (!pdev)
4517 return;
4518
4519 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4520 pci_dev_put(pdev);
4521 return;
4522 }
4523
4524 pci_dev_put(pdev);
4525
4526 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4527 if (vtisochctrl & 1)
4528 return;
4529
4530 /* Drop all bits other than the number of TLB entries */
4531 vtisochctrl &= 0x1c;
4532
4533 /* If we have the recommended number of TLB entries (16), fine. */
4534 if (vtisochctrl == 0x10)
4535 return;
4536
4537 /* Zero TLB entries? You get to ride the short bus to school. */
4538 if (!vtisochctrl) {
4539 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4540 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4541 dmi_get_system_info(DMI_BIOS_VENDOR),
4542 dmi_get_system_info(DMI_BIOS_VERSION),
4543 dmi_get_system_info(DMI_PRODUCT_VERSION));
4544 iommu_identity_mapping |= IDENTMAP_AZALIA;
4545 return;
4546 }
4547
4548 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4549 vtisochctrl);
4550}
Linux kernel - Deliverables
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