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iommu/vt-d: Add access functions for iommu->domains
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
9f10e5bf 18 * Joerg Roedel <jroedel@suse.de>
ba395927
KA		 19 */
20
9f10e5bf
JR		 21#define pr_fmt(fmt) "DMAR: " fmt
22
ba395927
KA		 23#include <linux/init.h>
24#include <linux/bitmap.h>
5e0d2a6f 25#include <linux/debugfs.h>
54485c30 26#include <linux/export.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
75f05569 35#include <linux/memory.h>
5e0d2a6f 36#include <linux/timer.h>
38717946 37#include <linux/iova.h>
5d450806 38#include <linux/iommu.h>
38717946 39#include <linux/intel-iommu.h>
134fac3f 40#include <linux/syscore_ops.h>
69575d38 41#include <linux/tboot.h>
adb2fe02 42#include <linux/dmi.h>
5cdede24 43#include <linux/pci-ats.h>
0ee332c1 44#include <linux/memblock.h>
36746436 45#include <linux/dma-contiguous.h>
091d42e4 46#include <linux/crash_dump.h>
8a8f422d 47#include <asm/irq_remapping.h>
ba395927 48#include <asm/cacheflush.h>
46a7fa27 49#include <asm/iommu.h>
ba395927 50
078e1ee2
JR		 51#include "irq_remapping.h"
52
5b6985ce
FY		 53#define ROOT_SIZE VTD_PAGE_SIZE
54#define CONTEXT_SIZE VTD_PAGE_SIZE
55
ba395927 56#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
18436afd 57#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
ba395927 58#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 59#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 60
61#define IOAPIC_RANGE_START (0xfee00000)
62#define IOAPIC_RANGE_END (0xfeefffff)
63#define IOVA_START_ADDR (0x1000)
64
65#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
66
4ed0d3e6 67#define MAX_AGAW_WIDTH 64
5c645b35 68#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 69
2ebe3151
DW		 70#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
71#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
72
73/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
74 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
75#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
76 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
77#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 78
1b722500
RM		 79/* IO virtual address start page frame number */
80#define IOVA_START_PFN (1)
81
f27be03b 82#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 83#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 84#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 85
df08cdc7
AM		 86/* page table handling */
87#define LEVEL_STRIDE (9)
88#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
89
6d1c56a9
OBC		 90/*
91 * This bitmap is used to advertise the page sizes our hardware support
92 * to the IOMMU core, which will then use this information to split
93 * physically contiguous memory regions it is mapping into page sizes
94 * that we support.
95 *
96 * Traditionally the IOMMU core just handed us the mappings directly,
97 * after making sure the size is an order of a 4KiB page and that the
98 * mapping has natural alignment.
99 *
100 * To retain this behavior, we currently advertise that we support
101 * all page sizes that are an order of 4KiB.
102 *
103 * If at some point we'd like to utilize the IOMMU core's new behavior,
104 * we could change this to advertise the real page sizes we support.
105 */
106#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
107
df08cdc7
AM		 108static inline int agaw_to_level(int agaw)
109{
110 return agaw + 2;
111}
112
113static inline int agaw_to_width(int agaw)
114{
5c645b35 115 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 116}
117
118static inline int width_to_agaw(int width)
119{
5c645b35 120 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 121}
122
123static inline unsigned int level_to_offset_bits(int level)
124{
125 return (level - 1) * LEVEL_STRIDE;
126}
127
128static inline int pfn_level_offset(unsigned long pfn, int level)
129{
130 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
131}
132
133static inline unsigned long level_mask(int level)
134{
135 return -1UL << level_to_offset_bits(level);
136}
137
138static inline unsigned long level_size(int level)
139{
140 return 1UL << level_to_offset_bits(level);
141}
142
143static inline unsigned long align_to_level(unsigned long pfn, int level)
144{
145 return (pfn + level_size(level) - 1) & level_mask(level);
146}
fd18de50 147
6dd9a7c7
YS		 148static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
149{
5c645b35 150 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 151}
152
dd4e8319
DW		 153/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
154 are never going to work. */
155static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
156{
157 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
158}
159
160static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
161{
162 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
163}
164static inline unsigned long page_to_dma_pfn(struct page *pg)
165{
166 return mm_to_dma_pfn(page_to_pfn(pg));
167}
168static inline unsigned long virt_to_dma_pfn(void *p)
169{
170 return page_to_dma_pfn(virt_to_page(p));
171}
172
d9630fe9
WH		 173/* global iommu list, set NULL for ignored DMAR units */
174static struct intel_iommu **g_iommus;
175
e0fc7e0b 176static void __init check_tylersburg_isoch(void);
9af88143
DW		 177static int rwbf_quirk;
178
b779260b
JC		 179/*
180 * set to 1 to panic kernel if can't successfully enable VT-d
181 * (used when kernel is launched w/ TXT)
182 */
183static int force_on = 0;
184
46b08e1a
MM		 185/*
186 * 0: Present
187 * 1-11: Reserved
188 * 12-63: Context Ptr (12 - (haw-1))
189 * 64-127: Reserved
190 */
191struct root_entry {
03ecc32c
DW		 192 u64 lo;
193 u64 hi;
46b08e1a
MM		 194};
195#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
46b08e1a 196
091d42e4
JR		 197/*
198 * Take a root_entry and return the Lower Context Table Pointer (LCTP)
199 * if marked present.
200 */
201static phys_addr_t root_entry_lctp(struct root_entry *re)
202{
203 if (!(re->lo & 1))
204 return 0;
205
206 return re->lo & VTD_PAGE_MASK;
207}
208
209/*
210 * Take a root_entry and return the Upper Context Table Pointer (UCTP)
211 * if marked present.
212 */
213static phys_addr_t root_entry_uctp(struct root_entry *re)
214{
215 if (!(re->hi & 1))
216 return 0;
46b08e1a 217
091d42e4
JR		 218 return re->hi & VTD_PAGE_MASK;
219}
7a8fc25e
MM		 220/*
221 * low 64 bits:
222 * 0: present
223 * 1: fault processing disable
224 * 2-3: translation type
225 * 12-63: address space root
226 * high 64 bits:
227 * 0-2: address width
228 * 3-6: aval
229 * 8-23: domain id
230 */
231struct context_entry {
232 u64 lo;
233 u64 hi;
234};
c07e7d21 235
cf484d0e
JR		 236static inline void context_clear_pasid_enable(struct context_entry *context)
237{
238 context->lo &= ~(1ULL << 11);
239}
240
241static inline bool context_pasid_enabled(struct context_entry *context)
242{
243 return !!(context->lo & (1ULL << 11));
244}
245
246static inline void context_set_copied(struct context_entry *context)
247{
248 context->hi |= (1ull << 3);
249}
250
251static inline bool context_copied(struct context_entry *context)
252{
253 return !!(context->hi & (1ULL << 3));
254}
255
256static inline bool __context_present(struct context_entry *context)
c07e7d21
MM		 257{
258 return (context->lo & 1);
259}
cf484d0e
JR		 260
261static inline bool context_present(struct context_entry *context)
262{
263 return context_pasid_enabled(context) ?
264 __context_present(context) :
265 __context_present(context) && !context_copied(context);
266}
267
c07e7d21
MM		 268static inline void context_set_present(struct context_entry *context)
269{
270 context->lo |= 1;
271}
272
273static inline void context_set_fault_enable(struct context_entry *context)
274{
275 context->lo &= (((u64)-1) << 2) | 1;
276}
277
c07e7d21
MM		 278static inline void context_set_translation_type(struct context_entry *context,
279 unsigned long value)
280{
281 context->lo &= (((u64)-1) << 4) | 3;
282 context->lo |= (value & 3) << 2;
283}
284
285static inline void context_set_address_root(struct context_entry *context,
286 unsigned long value)
287{
1a2262f9 288 context->lo &= ~VTD_PAGE_MASK;
c07e7d21
MM		 289 context->lo |= value & VTD_PAGE_MASK;
290}
291
292static inline void context_set_address_width(struct context_entry *context,
293 unsigned long value)
294{
295 context->hi |= value & 7;
296}
297
298static inline void context_set_domain_id(struct context_entry *context,
299 unsigned long value)
300{
301 context->hi |= (value & ((1 << 16) - 1)) << 8;
302}
303
dbcd861f
JR		 304static inline int context_domain_id(struct context_entry *c)
305{
306 return((c->hi >> 8) & 0xffff);
307}
308
c07e7d21
MM		 309static inline void context_clear_entry(struct context_entry *context)
310{
311 context->lo = 0;
312 context->hi = 0;
313}
7a8fc25e 314
622ba12a
MM		 315/*
316 * 0: readable
317 * 1: writable
318 * 2-6: reserved
319 * 7: super page
9cf06697
SY		 320 * 8-10: available
321 * 11: snoop behavior
622ba12a
MM		 322 * 12-63: Host physcial address
323 */
324struct dma_pte {
325 u64 val;
326};
622ba12a 327
19c239ce
MM		 328static inline void dma_clear_pte(struct dma_pte *pte)
329{
330 pte->val = 0;
331}
332
19c239ce
MM		 333static inline u64 dma_pte_addr(struct dma_pte *pte)
334{
c85994e4
DW		 335#ifdef CONFIG_64BIT
336 return pte->val & VTD_PAGE_MASK;
337#else
338 /* Must have a full atomic 64-bit read */
1a8bd481 339 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 340#endif
19c239ce
MM		 341}
342
19c239ce
MM		 343static inline bool dma_pte_present(struct dma_pte *pte)
344{
345 return (pte->val & 3) != 0;
346}
622ba12a 347
4399c8bf
AK		 348static inline bool dma_pte_superpage(struct dma_pte *pte)
349{
c3c75eb7 350 return (pte->val & DMA_PTE_LARGE_PAGE);
4399c8bf
AK		 351}
352
75e6bf96
DW		 353static inline int first_pte_in_page(struct dma_pte *pte)
354{
355 return !((unsigned long)pte & ~VTD_PAGE_MASK);
356}
357
2c2e2c38
FY		 358/*
359 * This domain is a statically identity mapping domain.
360 * 1. This domain creats a static 1:1 mapping to all usable memory.
361 * 2. It maps to each iommu if successful.
362 * 3. Each iommu mapps to this domain if successful.
363 */
19943b0e
DW		 364static struct dmar_domain *si_domain;
365static int hw_pass_through = 1;
2c2e2c38 366
1ce28feb
WH		 367/* domain represents a virtual machine, more than one devices
368 * across iommus may be owned in one domain, e.g. kvm guest.
369 */
ab8dfe25 370#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0)
1ce28feb 371
2c2e2c38 372/* si_domain contains mulitple devices */
ab8dfe25 373#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1)
2c2e2c38 374
99126f7c
MM		 375struct dmar_domain {
376 int id; /* domain id */
4c923d47 377 int nid; /* node id */
78d8e704 378 DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
1b198bb0 379 /* bitmap of iommus this domain uses*/
99126f7c 380
c0e8a6c8
JR		 381 u16 iommu_did[DMAR_UNITS_SUPPORTED];
382 /* Domain ids per IOMMU. Use u16 since
383 * domain ids are 16 bit wide according
384 * to VT-d spec, section 9.3 */
385
00a77deb 386 struct list_head devices; /* all devices' list */
99126f7c
MM		 387 struct iova_domain iovad; /* iova's that belong to this domain */
388
389 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 390 int gaw; /* max guest address width */
391
392 /* adjusted guest address width, 0 is level 2 30-bit */
393 int agaw;
394
3b5410e7 395 int flags; /* flags to find out type of domain */
8e604097
WH		 396
397 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 398 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 399 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 400 int iommu_superpage;/* Level of superpages supported:
401 0 == 4KiB (no superpages), 1 == 2MiB,
402 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 403 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 404 u64 max_addr; /* maximum mapped address */
00a77deb
JR		 405
406 struct iommu_domain domain; /* generic domain data structure for
407 iommu core */
99126f7c
MM		 408};
409
a647dacb
MM		 410/* PCI domain-device relationship */
411struct device_domain_info {
412 struct list_head link; /* link to domain siblings */
413 struct list_head global; /* link to global list */
276dbf99 414 u8 bus; /* PCI bus number */
a647dacb 415 u8 devfn; /* PCI devfn number */
0bcb3e28 416 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 417 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 418 struct dmar_domain *domain; /* pointer to domain */
419};
420
b94e4117
JL		 421struct dmar_rmrr_unit {
422 struct list_head list; /* list of rmrr units */
423 struct acpi_dmar_header *hdr; /* ACPI header */
424 u64 base_address; /* reserved base address*/
425 u64 end_address; /* reserved end address */
832bd858 426 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 427 int devices_cnt; /* target device count */
428};
429
430struct dmar_atsr_unit {
431 struct list_head list; /* list of ATSR units */
432 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 433 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 434 int devices_cnt; /* target device count */
435 u8 include_all:1; /* include all ports */
436};
437
438static LIST_HEAD(dmar_atsr_units);
439static LIST_HEAD(dmar_rmrr_units);
440
441#define for_each_rmrr_units(rmrr) \
442 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
443
5e0d2a6f 444static void flush_unmaps_timeout(unsigned long data);
445
b707cb02 446static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 447
80b20dd8 448#define HIGH_WATER_MARK 250
449struct deferred_flush_tables {
450 int next;
451 struct iova *iova[HIGH_WATER_MARK];
452 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 453 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 454};
455
456static struct deferred_flush_tables *deferred_flush;
457
5e0d2a6f 458/* bitmap for indexing intel_iommus */
5e0d2a6f 459static int g_num_of_iommus;
460
461static DEFINE_SPINLOCK(async_umap_flush_lock);
462static LIST_HEAD(unmaps_to_do);
463
464static int timer_on;
465static long list_size;
5e0d2a6f 466
92d03cc8 467static void domain_exit(struct dmar_domain *domain);
ba395927 468static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117 469static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 470 struct device *dev);
92d03cc8 471static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 472 struct device *dev);
2a46ddf7
JL		 473static int domain_detach_iommu(struct dmar_domain *domain,
474 struct intel_iommu *iommu);
ba395927 475
d3f13810 476#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 477int dmar_disabled = 0;
478#else
479int dmar_disabled = 1;
d3f13810 480#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 481
8bc1f85c
ED		 482int intel_iommu_enabled = 0;
483EXPORT_SYMBOL_GPL(intel_iommu_enabled);
484
2d9e667e 485static int dmar_map_gfx = 1;
7d3b03ce 486static int dmar_forcedac;
5e0d2a6f 487static int intel_iommu_strict;
6dd9a7c7 488static int intel_iommu_superpage = 1;
c83b2f20
DW		 489static int intel_iommu_ecs = 1;
490
491/* We only actually use ECS when PASID support (on the new bit 40)
492 * is also advertised. Some early implementations — the ones with
493 * PASID support on bit 28 — have issues even when we *only* use
494 * extended root/context tables. */
495#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
496 ecap_pasid(iommu->ecap))
ba395927 497
c0771df8
DW		 498int intel_iommu_gfx_mapped;
499EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
500
ba395927
KA		 501#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
502static DEFINE_SPINLOCK(device_domain_lock);
503static LIST_HEAD(device_domain_list);
504
b22f6434 505static const struct iommu_ops intel_iommu_ops;
a8bcbb0d 506
4158c2ec
JR		 507static bool translation_pre_enabled(struct intel_iommu *iommu)
508{
509 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
510}
511
091d42e4
JR		 512static void clear_translation_pre_enabled(struct intel_iommu *iommu)
513{
514 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED;
515}
516
4158c2ec
JR		 517static void init_translation_status(struct intel_iommu *iommu)
518{
519 u32 gsts;
520
521 gsts = readl(iommu->reg + DMAR_GSTS_REG);
522 if (gsts & DMA_GSTS_TES)
523 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
524}
525
00a77deb
JR		 526/* Convert generic 'struct iommu_domain to private struct dmar_domain */
527static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
528{
529 return container_of(dom, struct dmar_domain, domain);
530}
531
ba395927
KA		 532static int __init intel_iommu_setup(char *str)
533{
534 if (!str)
535 return -EINVAL;
536 while (*str) {
0cd5c3c8
KM		 537 if (!strncmp(str, "on", 2)) {
538 dmar_disabled = 0;
9f10e5bf 539 pr_info("IOMMU enabled\n");
0cd5c3c8 540 } else if (!strncmp(str, "off", 3)) {
ba395927 541 dmar_disabled = 1;
9f10e5bf 542 pr_info("IOMMU disabled\n");
ba395927
KA		 543 } else if (!strncmp(str, "igfx_off", 8)) {
544 dmar_map_gfx = 0;
9f10e5bf 545 pr_info("Disable GFX device mapping\n");
7d3b03ce 546 } else if (!strncmp(str, "forcedac", 8)) {
9f10e5bf 547 pr_info("Forcing DAC for PCI devices\n");
7d3b03ce 548 dmar_forcedac = 1;
5e0d2a6f 549 } else if (!strncmp(str, "strict", 6)) {
9f10e5bf 550 pr_info("Disable batched IOTLB flush\n");
5e0d2a6f 551 intel_iommu_strict = 1;
6dd9a7c7 552 } else if (!strncmp(str, "sp_off", 6)) {
9f10e5bf 553 pr_info("Disable supported super page\n");
6dd9a7c7 554 intel_iommu_superpage = 0;
c83b2f20
DW		 555 } else if (!strncmp(str, "ecs_off", 7)) {
556 printk(KERN_INFO
557 "Intel-IOMMU: disable extended context table support\n");
558 intel_iommu_ecs = 0;
ba395927
KA		 559 }
560
561 str += strcspn(str, ",");
562 while (*str == ',')
563 str++;
564 }
565 return 0;
566}
567__setup("intel_iommu=", intel_iommu_setup);
568
569static struct kmem_cache *iommu_domain_cache;
570static struct kmem_cache *iommu_devinfo_cache;
ba395927 571
9452d5bf
JR		 572static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did)
573{
574 return iommu->domains[did];
575}
576
577static void set_iommu_domain(struct intel_iommu *iommu, u16 did,
578 struct dmar_domain *domain)
579{
580 iommu->domains[did] = domain;
581}
582
4c923d47 583static inline void *alloc_pgtable_page(int node)
eb3fa7cb 584{
4c923d47
SS		 585 struct page *page;
586 void *vaddr = NULL;
eb3fa7cb 587
4c923d47
SS		 588 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
589 if (page)
590 vaddr = page_address(page);
eb3fa7cb 591 return vaddr;
ba395927
KA		 592}
593
594static inline void free_pgtable_page(void *vaddr)
595{
596 free_page((unsigned long)vaddr);
597}
598
599static inline void *alloc_domain_mem(void)
600{
354bb65e 601 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 602}
603
38717946 604static void free_domain_mem(void *vaddr)
ba395927
KA		 605{
606 kmem_cache_free(iommu_domain_cache, vaddr);
607}
608
609static inline void * alloc_devinfo_mem(void)
610{
354bb65e 611 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 612}
613
614static inline void free_devinfo_mem(void *vaddr)
615{
616 kmem_cache_free(iommu_devinfo_cache, vaddr);
617}
618
ab8dfe25
JL		 619static inline int domain_type_is_vm(struct dmar_domain *domain)
620{
621 return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
622}
623
624static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
625{
626 return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
627 DOMAIN_FLAG_STATIC_IDENTITY);
628}
1b573683 629
162d1b10
JL		 630static inline int domain_pfn_supported(struct dmar_domain *domain,
631 unsigned long pfn)
632{
633 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
634
635 return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
636}
637
4ed0d3e6 638static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 639{
640 unsigned long sagaw;
641 int agaw = -1;
642
643 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 644 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 645 agaw >= 0; agaw--) {
646 if (test_bit(agaw, &sagaw))
647 break;
648 }
649
650 return agaw;
651}
652
4ed0d3e6
FY		 653/*
654 * Calculate max SAGAW for each iommu.
655 */
656int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
657{
658 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
659}
660
661/*
662 * calculate agaw for each iommu.
663 * "SAGAW" may be different across iommus, use a default agaw, and
664 * get a supported less agaw for iommus that don't support the default agaw.
665 */
666int iommu_calculate_agaw(struct intel_iommu *iommu)
667{
668 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
669}
670
2c2e2c38 671/* This functionin only returns single iommu in a domain */
8c11e798
WH		 672static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
673{
674 int iommu_id;
675
2c2e2c38 676 /* si_domain and vm domain should not get here. */
ab8dfe25 677 BUG_ON(domain_type_is_vm_or_si(domain));
1b198bb0 678 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 679 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
680 return NULL;
681
682 return g_iommus[iommu_id];
683}
684
8e604097
WH		 685static void domain_update_iommu_coherency(struct dmar_domain *domain)
686{
d0501960
DW		 687 struct dmar_drhd_unit *drhd;
688 struct intel_iommu *iommu;
2f119c78
QL		 689 bool found = false;
690 int i;
2e12bc29 691
d0501960 692 domain->iommu_coherency = 1;
8e604097 693
1b198bb0 694 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
2f119c78 695 found = true;
8e604097
WH		 696 if (!ecap_coherent(g_iommus[i]->ecap)) {
697 domain->iommu_coherency = 0;
698 break;
699 }
8e604097 700 }
d0501960
DW		 701 if (found)
702 return;
703
704 /* No hardware attached; use lowest common denominator */
705 rcu_read_lock();
706 for_each_active_iommu(iommu, drhd) {
707 if (!ecap_coherent(iommu->ecap)) {
708 domain->iommu_coherency = 0;
709 break;
710 }
711 }
712 rcu_read_unlock();
8e604097
WH		 713}
714
161f6934 715static int domain_update_iommu_snooping(struct intel_iommu *skip)
58c610bd 716{
161f6934
JL		 717 struct dmar_drhd_unit *drhd;
718 struct intel_iommu *iommu;
719 int ret = 1;
58c610bd 720
161f6934
JL		 721 rcu_read_lock();
722 for_each_active_iommu(iommu, drhd) {
723 if (iommu != skip) {
724 if (!ecap_sc_support(iommu->ecap)) {
725 ret = 0;
726 break;
727 }
58c610bd 728 }
58c610bd 729 }
161f6934
JL		 730 rcu_read_unlock();
731
732 return ret;
58c610bd
SY		 733}
734
161f6934 735static int domain_update_iommu_superpage(struct intel_iommu *skip)
6dd9a7c7 736{
8140a95d 737 struct dmar_drhd_unit *drhd;
161f6934 738 struct intel_iommu *iommu;
8140a95d 739 int mask = 0xf;
6dd9a7c7
YS		 740
741 if (!intel_iommu_superpage) {
161f6934 742 return 0;
6dd9a7c7
YS		 743 }
744
8140a95d 745 /* set iommu_superpage to the smallest common denominator */
0e242612 746 rcu_read_lock();
8140a95d 747 for_each_active_iommu(iommu, drhd) {
161f6934
JL		 748 if (iommu != skip) {
749 mask &= cap_super_page_val(iommu->cap);
750 if (!mask)
751 break;
6dd9a7c7
YS		 752 }
753 }
0e242612
JL		 754 rcu_read_unlock();
755
161f6934 756 return fls(mask);
6dd9a7c7
YS		 757}
758
58c610bd
SY		 759/* Some capabilities may be different across iommus */
760static void domain_update_iommu_cap(struct dmar_domain *domain)
761{
762 domain_update_iommu_coherency(domain);
161f6934
JL		 763 domain->iommu_snooping = domain_update_iommu_snooping(NULL);
764 domain->iommu_superpage = domain_update_iommu_superpage(NULL);
58c610bd
SY		 765}
766
03ecc32c
DW		 767static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
768 u8 bus, u8 devfn, int alloc)
769{
770 struct root_entry *root = &iommu->root_entry[bus];
771 struct context_entry *context;
772 u64 *entry;
773
c83b2f20 774 if (ecs_enabled(iommu)) {
03ecc32c
DW		 775 if (devfn >= 0x80) {
776 devfn -= 0x80;
777 entry = &root->hi;
778 }
779 devfn *= 2;
780 }
781 entry = &root->lo;
782 if (*entry & 1)
783 context = phys_to_virt(*entry & VTD_PAGE_MASK);
784 else {
785 unsigned long phy_addr;
786 if (!alloc)
787 return NULL;
788
789 context = alloc_pgtable_page(iommu->node);
790 if (!context)
791 return NULL;
792
793 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
794 phy_addr = virt_to_phys((void *)context);
795 *entry = phy_addr | 1;
796 __iommu_flush_cache(iommu, entry, sizeof(*entry));
797 }
798 return &context[devfn];
799}
800
4ed6a540
DW		 801static int iommu_dummy(struct device *dev)
802{
803 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
804}
805
156baca8 806static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
c7151a8d
WH		 807{
808 struct dmar_drhd_unit *drhd = NULL;
b683b230 809 struct intel_iommu *iommu;
156baca8
DW		 810 struct device *tmp;
811 struct pci_dev *ptmp, *pdev = NULL;
aa4d066a 812 u16 segment = 0;
c7151a8d
WH		 813 int i;
814
4ed6a540
DW		 815 if (iommu_dummy(dev))
816 return NULL;
817
156baca8
DW		 818 if (dev_is_pci(dev)) {
819 pdev = to_pci_dev(dev);
820 segment = pci_domain_nr(pdev->bus);
ca5b74d2 821 } else if (has_acpi_companion(dev))
156baca8
DW		 822 dev = &ACPI_COMPANION(dev)->dev;
823
0e242612 824 rcu_read_lock();
b683b230 825 for_each_active_iommu(iommu, drhd) {
156baca8 826 if (pdev && segment != drhd->segment)
276dbf99 827 continue;
c7151a8d 828
b683b230 829 for_each_active_dev_scope(drhd->devices,
156baca8
DW		 830 drhd->devices_cnt, i, tmp) {
831 if (tmp == dev) {
832 *bus = drhd->devices[i].bus;
833 *devfn = drhd->devices[i].devfn;
b683b230 834 goto out;
156baca8
DW		 835 }
836
837 if (!pdev || !dev_is_pci(tmp))
838 continue;
839
840 ptmp = to_pci_dev(tmp);
841 if (ptmp->subordinate &&
842 ptmp->subordinate->number <= pdev->bus->number &&
843 ptmp->subordinate->busn_res.end >= pdev->bus->number)
844 goto got_pdev;
924b6231 845 }
c7151a8d 846
156baca8
DW		 847 if (pdev && drhd->include_all) {
848 got_pdev:
849 *bus = pdev->bus->number;
850 *devfn = pdev->devfn;
b683b230 851 goto out;
156baca8 852 }
c7151a8d 853 }
b683b230 854 iommu = NULL;
156baca8 855 out:
0e242612 856 rcu_read_unlock();
c7151a8d 857
b683b230 858 return iommu;
c7151a8d
WH		 859}
860
5331fe6f
WH		 861static void domain_flush_cache(struct dmar_domain *domain,
862 void *addr, int size)
863{
864 if (!domain->iommu_coherency)
865 clflush_cache_range(addr, size);
866}
867
ba395927
KA		 868static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
869{
ba395927 870 struct context_entry *context;
03ecc32c 871 int ret = 0;
ba395927
KA		 872 unsigned long flags;
873
874 spin_lock_irqsave(&iommu->lock, flags);
03ecc32c
DW		 875 context = iommu_context_addr(iommu, bus, devfn, 0);
876 if (context)
877 ret = context_present(context);
ba395927
KA		 878 spin_unlock_irqrestore(&iommu->lock, flags);
879 return ret;
880}
881
882static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
883{
ba395927
KA		 884 struct context_entry *context;
885 unsigned long flags;
886
887 spin_lock_irqsave(&iommu->lock, flags);
03ecc32c 888 context = iommu_context_addr(iommu, bus, devfn, 0);
ba395927 889 if (context) {
03ecc32c
DW		 890 context_clear_entry(context);
891 __iommu_flush_cache(iommu, context, sizeof(*context));
ba395927
KA		 892 }
893 spin_unlock_irqrestore(&iommu->lock, flags);
894}
895
896static void free_context_table(struct intel_iommu *iommu)
897{
ba395927
KA		 898 int i;
899 unsigned long flags;
900 struct context_entry *context;
901
902 spin_lock_irqsave(&iommu->lock, flags);
903 if (!iommu->root_entry) {
904 goto out;
905 }
906 for (i = 0; i < ROOT_ENTRY_NR; i++) {
03ecc32c 907 context = iommu_context_addr(iommu, i, 0, 0);
ba395927
KA		 908 if (context)
909 free_pgtable_page(context);
03ecc32c 910
c83b2f20 911 if (!ecs_enabled(iommu))
03ecc32c
DW		 912 continue;
913
914 context = iommu_context_addr(iommu, i, 0x80, 0);
915 if (context)
916 free_pgtable_page(context);
917
ba395927
KA		 918 }
919 free_pgtable_page(iommu->root_entry);
920 iommu->root_entry = NULL;
921out:
922 spin_unlock_irqrestore(&iommu->lock, flags);
923}
924
b026fd28 925static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 926 unsigned long pfn, int *target_level)
ba395927 927{
ba395927
KA		 928 struct dma_pte *parent, *pte = NULL;
929 int level = agaw_to_level(domain->agaw);
4399c8bf 930 int offset;
ba395927
KA		 931
932 BUG_ON(!domain->pgd);
f9423606 933
162d1b10 934 if (!domain_pfn_supported(domain, pfn))
f9423606
JS		 935 /* Address beyond IOMMU's addressing capabilities. */
936 return NULL;
937
ba395927
KA		 938 parent = domain->pgd;
939
5cf0a76f 940 while (1) {
ba395927
KA		 941 void *tmp_page;
942
b026fd28 943 offset = pfn_level_offset(pfn, level);
ba395927 944 pte = &parent[offset];
5cf0a76f 945 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 946 break;
5cf0a76f 947 if (level == *target_level)
ba395927
KA		 948 break;
949
19c239ce 950 if (!dma_pte_present(pte)) {
c85994e4
DW		 951 uint64_t pteval;
952
4c923d47 953 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 954
206a73c1 955 if (!tmp_page)
ba395927 956 return NULL;
206a73c1 957
c85994e4 958 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 959 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
effad4b5 960 if (cmpxchg64(&pte->val, 0ULL, pteval))
c85994e4
DW		 961 /* Someone else set it while we were thinking; use theirs. */
962 free_pgtable_page(tmp_page);
effad4b5 963 else
c85994e4 964 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927 965 }
5cf0a76f
DW		 966 if (level == 1)
967 break;
968
19c239ce 969 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 970 level--;
971 }
972
5cf0a76f
DW		 973 if (!*target_level)
974 *target_level = level;
975
ba395927
KA		 976 return pte;
977}
978
6dd9a7c7 979
ba395927 980/* return address's pte at specific level */
90dcfb5e
DW		 981static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
982 unsigned long pfn,
6dd9a7c7 983 int level, int *large_page)
ba395927
KA		 984{
985 struct dma_pte *parent, *pte = NULL;
986 int total = agaw_to_level(domain->agaw);
987 int offset;
988
989 parent = domain->pgd;
990 while (level <= total) {
90dcfb5e 991 offset = pfn_level_offset(pfn, total);
ba395927
KA		 992 pte = &parent[offset];
993 if (level == total)
994 return pte;
995
6dd9a7c7
YS		 996 if (!dma_pte_present(pte)) {
997 *large_page = total;
ba395927 998 break;
6dd9a7c7
YS		 999 }
1000
e16922af 1001 if (dma_pte_superpage(pte)) {
6dd9a7c7
YS		 1002 *large_page = total;
1003 return pte;
1004 }
1005
19c239ce 1006 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 1007 total--;
1008 }
1009 return NULL;
1010}
1011
ba395927 1012/* clear last level pte, a tlb flush should be followed */
5cf0a76f 1013static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 1014 unsigned long start_pfn,
1015 unsigned long last_pfn)
ba395927 1016{
6dd9a7c7 1017 unsigned int large_page = 1;
310a5ab9 1018 struct dma_pte *first_pte, *pte;
66eae846 1019
162d1b10
JL		 1020 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1021 BUG_ON(!domain_pfn_supported(domain, last_pfn));
59c36286 1022 BUG_ON(start_pfn > last_pfn);
ba395927 1023
04b18e65 1024 /* we don't need lock here; nobody else touches the iova range */
59c36286 1025 do {
6dd9a7c7
YS		 1026 large_page = 1;
1027 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 1028 if (!pte) {
6dd9a7c7 1029 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 1030 continue;
1031 }
6dd9a7c7 1032 do {
310a5ab9 1033 dma_clear_pte(pte);
6dd9a7c7 1034 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 1035 pte++;
75e6bf96
DW		 1036 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
1037
310a5ab9
DW		 1038 domain_flush_cache(domain, first_pte,
1039 (void *)pte - (void *)first_pte);
59c36286
DW		 1040
1041 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 1042}
1043
3269ee0b
AW		 1044static void dma_pte_free_level(struct dmar_domain *domain, int level,
1045 struct dma_pte *pte, unsigned long pfn,
1046 unsigned long start_pfn, unsigned long last_pfn)
1047{
1048 pfn = max(start_pfn, pfn);
1049 pte = &pte[pfn_level_offset(pfn, level)];
1050
1051 do {
1052 unsigned long level_pfn;
1053 struct dma_pte *level_pte;
1054
1055 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
1056 goto next;
1057
1058 level_pfn = pfn & level_mask(level - 1);
1059 level_pte = phys_to_virt(dma_pte_addr(pte));
1060
1061 if (level > 2)
1062 dma_pte_free_level(domain, level - 1, level_pte,
1063 level_pfn, start_pfn, last_pfn);
1064
1065 /* If range covers entire pagetable, free it */
1066 if (!(start_pfn > level_pfn ||
08336fd2 1067 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 1068 dma_clear_pte(pte);
1069 domain_flush_cache(domain, pte, sizeof(*pte));
1070 free_pgtable_page(level_pte);
1071 }
1072next:
1073 pfn += level_size(level);
1074 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1075}
1076
ba395927
KA		 1077/* free page table pages. last level pte should already be cleared */
1078static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 1079 unsigned long start_pfn,
1080 unsigned long last_pfn)
ba395927 1081{
162d1b10
JL		 1082 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1083 BUG_ON(!domain_pfn_supported(domain, last_pfn));
59c36286 1084 BUG_ON(start_pfn > last_pfn);
ba395927 1085
d41a4adb
JL		 1086 dma_pte_clear_range(domain, start_pfn, last_pfn);
1087
f3a0a52f 1088 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 1089 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
1090 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 1091
ba395927 1092 /* free pgd */
d794dc9b 1093 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 1094 free_pgtable_page(domain->pgd);
1095 domain->pgd = NULL;
1096 }
1097}
1098
ea8ea460
DW		 1099/* When a page at a given level is being unlinked from its parent, we don't
1100 need to *modify* it at all. All we need to do is make a list of all the
1101 pages which can be freed just as soon as we've flushed the IOTLB and we
1102 know the hardware page-walk will no longer touch them.
1103 The 'pte' argument is the *parent* PTE, pointing to the page that is to
1104 be freed. */
1105static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1106 int level, struct dma_pte *pte,
1107 struct page *freelist)
1108{
1109 struct page *pg;
1110
1111 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1112 pg->freelist = freelist;
1113 freelist = pg;
1114
1115 if (level == 1)
1116 return freelist;
1117
adeb2590
JL		 1118 pte = page_address(pg);
1119 do {
ea8ea460
DW		 1120 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1121 freelist = dma_pte_list_pagetables(domain, level - 1,
1122 pte, freelist);
adeb2590
JL		 1123 pte++;
1124 } while (!first_pte_in_page(pte));
ea8ea460
DW		 1125
1126 return freelist;
1127}
1128
1129static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1130 struct dma_pte *pte, unsigned long pfn,
1131 unsigned long start_pfn,
1132 unsigned long last_pfn,
1133 struct page *freelist)
1134{
1135 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1136
1137 pfn = max(start_pfn, pfn);
1138 pte = &pte[pfn_level_offset(pfn, level)];
1139
1140 do {
1141 unsigned long level_pfn;
1142
1143 if (!dma_pte_present(pte))
1144 goto next;
1145
1146 level_pfn = pfn & level_mask(level);
1147
1148 /* If range covers entire pagetable, free it */
1149 if (start_pfn <= level_pfn &&
1150 last_pfn >= level_pfn + level_size(level) - 1) {
1151 /* These suborbinate page tables are going away entirely. Don't
1152 bother to clear them; we're just going to *free* them. */
1153 if (level > 1 && !dma_pte_superpage(pte))
1154 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1155
1156 dma_clear_pte(pte);
1157 if (!first_pte)
1158 first_pte = pte;
1159 last_pte = pte;
1160 } else if (level > 1) {
1161 /* Recurse down into a level that isn't *entirely* obsolete */
1162 freelist = dma_pte_clear_level(domain, level - 1,
1163 phys_to_virt(dma_pte_addr(pte)),
1164 level_pfn, start_pfn, last_pfn,
1165 freelist);
1166 }
1167next:
1168 pfn += level_size(level);
1169 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1170
1171 if (first_pte)
1172 domain_flush_cache(domain, first_pte,
1173 (void *)++last_pte - (void *)first_pte);
1174
1175 return freelist;
1176}
1177
1178/* We can't just free the pages because the IOMMU may still be walking
1179 the page tables, and may have cached the intermediate levels. The
1180 pages can only be freed after the IOTLB flush has been done. */
1181struct page *domain_unmap(struct dmar_domain *domain,
1182 unsigned long start_pfn,
1183 unsigned long last_pfn)
1184{
ea8ea460
DW		 1185 struct page *freelist = NULL;
1186
162d1b10
JL		 1187 BUG_ON(!domain_pfn_supported(domain, start_pfn));
1188 BUG_ON(!domain_pfn_supported(domain, last_pfn));
ea8ea460
DW		 1189 BUG_ON(start_pfn > last_pfn);
1190
1191 /* we don't need lock here; nobody else touches the iova range */
1192 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1193 domain->pgd, 0, start_pfn, last_pfn, NULL);
1194
1195 /* free pgd */
1196 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1197 struct page *pgd_page = virt_to_page(domain->pgd);
1198 pgd_page->freelist = freelist;
1199 freelist = pgd_page;
1200
1201 domain->pgd = NULL;
1202 }
1203
1204 return freelist;
1205}
1206
1207void dma_free_pagelist(struct page *freelist)
1208{
1209 struct page *pg;
1210
1211 while ((pg = freelist)) {
1212 freelist = pg->freelist;
1213 free_pgtable_page(page_address(pg));
1214 }
1215}
1216
ba395927
KA		 1217/* iommu handling */
1218static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1219{
1220 struct root_entry *root;
1221 unsigned long flags;
1222
4c923d47 1223 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ffebeb46 1224 if (!root) {
9f10e5bf 1225 pr_err("Allocating root entry for %s failed\n",
ffebeb46 1226 iommu->name);
ba395927 1227 return -ENOMEM;
ffebeb46 1228 }
ba395927 1229
5b6985ce 1230 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1231
1232 spin_lock_irqsave(&iommu->lock, flags);
1233 iommu->root_entry = root;
1234 spin_unlock_irqrestore(&iommu->lock, flags);
1235
1236 return 0;
1237}
1238
ba395927
KA		 1239static void iommu_set_root_entry(struct intel_iommu *iommu)
1240{
03ecc32c 1241 u64 addr;
c416daa9 1242 u32 sts;
ba395927
KA		 1243 unsigned long flag;
1244
03ecc32c 1245 addr = virt_to_phys(iommu->root_entry);
c83b2f20 1246 if (ecs_enabled(iommu))
03ecc32c 1247 addr |= DMA_RTADDR_RTT;
ba395927 1248
1f5b3c3f 1249 raw_spin_lock_irqsave(&iommu->register_lock, flag);
03ecc32c 1250 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
ba395927 1251
c416daa9 1252 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1253
1254 /* Make sure hardware complete it */
1255 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1256 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1257
1f5b3c3f 1258 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1259}
1260
1261static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1262{
1263 u32 val;
1264 unsigned long flag;
1265
9af88143 1266 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1267 return;
ba395927 1268
1f5b3c3f 1269 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1270 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1271
1272 /* Make sure hardware complete it */
1273 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1274 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1275
1f5b3c3f 1276 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1277}
1278
1279/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1280static void __iommu_flush_context(struct intel_iommu *iommu,
1281 u16 did, u16 source_id, u8 function_mask,
1282 u64 type)
ba395927
KA		 1283{
1284 u64 val = 0;
1285 unsigned long flag;
1286
ba395927
KA		 1287 switch (type) {
1288 case DMA_CCMD_GLOBAL_INVL:
1289 val = DMA_CCMD_GLOBAL_INVL;
1290 break;
1291 case DMA_CCMD_DOMAIN_INVL:
1292 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1293 break;
1294 case DMA_CCMD_DEVICE_INVL:
1295 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1296 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1297 break;
1298 default:
1299 BUG();
1300 }
1301 val |= DMA_CCMD_ICC;
1302
1f5b3c3f 1303 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1304 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1305
1306 /* Make sure hardware complete it */
1307 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1308 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1309
1f5b3c3f 1310 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1311}
1312
ba395927 1313/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1314static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1315 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1316{
1317 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1318 u64 val = 0, val_iva = 0;
1319 unsigned long flag;
1320
ba395927
KA		 1321 switch (type) {
1322 case DMA_TLB_GLOBAL_FLUSH:
1323 /* global flush doesn't need set IVA_REG */
1324 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1325 break;
1326 case DMA_TLB_DSI_FLUSH:
1327 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1328 break;
1329 case DMA_TLB_PSI_FLUSH:
1330 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1331 /* IH bit is passed in as part of address */
ba395927
KA		 1332 val_iva = size_order | addr;
1333 break;
1334 default:
1335 BUG();
1336 }
1337 /* Note: set drain read/write */
1338#if 0
1339 /*
1340 * This is probably to be super secure.. Looks like we can
1341 * ignore it without any impact.
1342 */
1343 if (cap_read_drain(iommu->cap))
1344 val |= DMA_TLB_READ_DRAIN;
1345#endif
1346 if (cap_write_drain(iommu->cap))
1347 val |= DMA_TLB_WRITE_DRAIN;
1348
1f5b3c3f 1349 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1350 /* Note: Only uses first TLB reg currently */
1351 if (val_iva)
1352 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1353 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1354
1355 /* Make sure hardware complete it */
1356 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1357 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1358
1f5b3c3f 1359 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1360
1361 /* check IOTLB invalidation granularity */
1362 if (DMA_TLB_IAIG(val) == 0)
9f10e5bf 1363 pr_err("Flush IOTLB failed\n");
ba395927 1364 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
9f10e5bf 1365 pr_debug("TLB flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1366 (unsigned long long)DMA_TLB_IIRG(type),
1367 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1368}
1369
64ae892b
DW		 1370static struct device_domain_info *
1371iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1372 u8 bus, u8 devfn)
93a23a72 1373{
2f119c78 1374 bool found = false;
93a23a72
YZ		 1375 unsigned long flags;
1376 struct device_domain_info *info;
0bcb3e28 1377 struct pci_dev *pdev;
93a23a72
YZ		 1378
1379 if (!ecap_dev_iotlb_support(iommu->ecap))
1380 return NULL;
1381
1382 if (!iommu->qi)
1383 return NULL;
1384
1385 spin_lock_irqsave(&device_domain_lock, flags);
1386 list_for_each_entry(info, &domain->devices, link)
c3b497c6
JL		 1387 if (info->iommu == iommu && info->bus == bus &&
1388 info->devfn == devfn) {
2f119c78 1389 found = true;
93a23a72
YZ		 1390 break;
1391 }
1392 spin_unlock_irqrestore(&device_domain_lock, flags);
1393
0bcb3e28 1394 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1395 return NULL;
1396
0bcb3e28
DW		 1397 pdev = to_pci_dev(info->dev);
1398
1399 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1400 return NULL;
1401
0bcb3e28 1402 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1403 return NULL;
1404
93a23a72
YZ		 1405 return info;
1406}
1407
1408static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1409{
0bcb3e28 1410 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1411 return;
1412
0bcb3e28 1413 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1414}
1415
1416static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1417{
0bcb3e28
DW		 1418 if (!info->dev || !dev_is_pci(info->dev) ||
1419 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1420 return;
1421
0bcb3e28 1422 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1423}
1424
1425static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1426 u64 addr, unsigned mask)
1427{
1428 u16 sid, qdep;
1429 unsigned long flags;
1430 struct device_domain_info *info;
1431
1432 spin_lock_irqsave(&device_domain_lock, flags);
1433 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1434 struct pci_dev *pdev;
1435 if (!info->dev || !dev_is_pci(info->dev))
1436 continue;
1437
1438 pdev = to_pci_dev(info->dev);
1439 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1440 continue;
1441
1442 sid = info->bus << 8 | info->devfn;
0bcb3e28 1443 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1444 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1445 }
1446 spin_unlock_irqrestore(&device_domain_lock, flags);
1447}
1448
1f0ef2aa 1449static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1450 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1451{
9dd2fe89 1452 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1453 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1454
ba395927
KA		 1455 BUG_ON(pages == 0);
1456
ea8ea460
DW		 1457 if (ih)
1458 ih = 1 << 6;
ba395927 1459 /*
9dd2fe89
YZ		 1460 * Fallback to domain selective flush if no PSI support or the size is
1461 * too big.
ba395927
KA		 1462 * PSI requires page size to be 2 ^ x, and the base address is naturally
1463 * aligned to the size
1464 */
9dd2fe89
YZ		 1465 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1466 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1467 DMA_TLB_DSI_FLUSH);
9dd2fe89 1468 else
ea8ea460 1469 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1470 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1471
1472 /*
82653633
NA		 1473 * In caching mode, changes of pages from non-present to present require
1474 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1475 */
82653633 1476 if (!cap_caching_mode(iommu->cap) || !map)
9452d5bf
JR		 1477 iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
1478 addr, mask);
ba395927
KA		 1479}
1480
f8bab735 1481static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1482{
1483 u32 pmen;
1484 unsigned long flags;
1485
1f5b3c3f 1486 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1487 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1488 pmen &= ~DMA_PMEN_EPM;
1489 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1490
1491 /* wait for the protected region status bit to clear */
1492 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1493 readl, !(pmen & DMA_PMEN_PRS), pmen);
1494
1f5b3c3f 1495 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1496}
1497
2a41ccee 1498static void iommu_enable_translation(struct intel_iommu *iommu)
ba395927
KA		 1499{
1500 u32 sts;
1501 unsigned long flags;
1502
1f5b3c3f 1503 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1504 iommu->gcmd |= DMA_GCMD_TE;
1505 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1506
1507 /* Make sure hardware complete it */
1508 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1509 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1510
1f5b3c3f 1511 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1512}
1513
2a41ccee 1514static void iommu_disable_translation(struct intel_iommu *iommu)
ba395927
KA		 1515{
1516 u32 sts;
1517 unsigned long flag;
1518
1f5b3c3f 1519 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1520 iommu->gcmd &= ~DMA_GCMD_TE;
1521 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1522
1523 /* Make sure hardware complete it */
1524 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1525 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1526
1f5b3c3f 1527 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1528}
1529
3460a6d9 1530
ba395927
KA		 1531static int iommu_init_domains(struct intel_iommu *iommu)
1532{
1533 unsigned long ndomains;
1534 unsigned long nlongs;
1535
1536 ndomains = cap_ndoms(iommu->cap);
9f10e5bf
JR		 1537 pr_debug("%s: Number of Domains supported <%ld>\n",
1538 iommu->name, ndomains);
ba395927
KA		 1539 nlongs = BITS_TO_LONGS(ndomains);
1540
94a91b50
DD		 1541 spin_lock_init(&iommu->lock);
1542
ba395927
KA		 1543 /* TBD: there might be 64K domains,
1544 * consider other allocation for future chip
1545 */
1546 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1547 if (!iommu->domain_ids) {
9f10e5bf
JR		 1548 pr_err("%s: Allocating domain id array failed\n",
1549 iommu->name);
ba395927
KA		 1550 return -ENOMEM;
1551 }
1552 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1553 GFP_KERNEL);
1554 if (!iommu->domains) {
9f10e5bf
JR		 1555 pr_err("%s: Allocating domain array failed\n",
1556 iommu->name);
852bdb04
JL		 1557 kfree(iommu->domain_ids);
1558 iommu->domain_ids = NULL;
ba395927
KA		 1559 return -ENOMEM;
1560 }
1561
1562 /*
c0e8a6c8
JR		 1563 * If Caching mode is set, then invalid translations are tagged
1564 * with domain-id 0, hence we need to pre-allocate it. We also
1565 * use domain-id 0 as a marker for non-allocated domain-id, so
1566 * make sure it is not used for a real domain.
ba395927 1567 */
c0e8a6c8
JR		 1568 set_bit(0, iommu->domain_ids);
1569
ba395927
KA		 1570 return 0;
1571}
ba395927 1572
ffebeb46 1573static void disable_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1574{
1575 struct dmar_domain *domain;
2a46ddf7 1576 int i;
ba395927 1577
94a91b50 1578 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1579 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1580 /*
1581 * Domain id 0 is reserved for invalid translation
c0e8a6c8
JR		 1582 * if hardware supports caching mode and used as
1583 * a non-allocated marker.
a4eaa86c 1584 */
c0e8a6c8 1585 if (i == 0)
a4eaa86c
JL		 1586 continue;
1587
9452d5bf 1588 domain = get_iommu_domain(iommu, i);
94a91b50 1589 clear_bit(i, iommu->domain_ids);
129ad281
JL		 1590 if (domain_detach_iommu(domain, iommu) == 0 &&
1591 !domain_type_is_vm(domain))
92d03cc8 1592 domain_exit(domain);
5e98c4b1 1593 }
ba395927
KA		 1594 }
1595
1596 if (iommu->gcmd & DMA_GCMD_TE)
1597 iommu_disable_translation(iommu);
ffebeb46 1598}
ba395927 1599
ffebeb46
JL		 1600static void free_dmar_iommu(struct intel_iommu *iommu)
1601{
1602 if ((iommu->domains) && (iommu->domain_ids)) {
1603 kfree(iommu->domains);
1604 kfree(iommu->domain_ids);
1605 iommu->domains = NULL;
1606 iommu->domain_ids = NULL;
1607 }
ba395927 1608
d9630fe9
WH		 1609 g_iommus[iommu->seq_id] = NULL;
1610
ba395927
KA		 1611 /* free context mapping */
1612 free_context_table(iommu);
ba395927
KA		 1613}
1614
ab8dfe25 1615static struct dmar_domain *alloc_domain(int flags)
ba395927 1616{
92d03cc8
JL		 1617 /* domain id for virtual machine, it won't be set in context */
1618 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1619 struct dmar_domain *domain;
ba395927
KA		 1620
1621 domain = alloc_domain_mem();
1622 if (!domain)
1623 return NULL;
1624
ab8dfe25 1625 memset(domain, 0, sizeof(*domain));
4c923d47 1626 domain->nid = -1;
ab8dfe25 1627 domain->flags = flags;
92d03cc8
JL		 1628 spin_lock_init(&domain->iommu_lock);
1629 INIT_LIST_HEAD(&domain->devices);
ab8dfe25 1630 if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
92d03cc8 1631 domain->id = atomic_inc_return(&vm_domid);
2c2e2c38
FY		 1632
1633 return domain;
1634}
1635
fb170fb4
JL		 1636static int __iommu_attach_domain(struct dmar_domain *domain,
1637 struct intel_iommu *iommu)
2c2e2c38
FY		 1638{
1639 int num;
1640 unsigned long ndomains;
2c2e2c38 1641
ba395927 1642 ndomains = cap_ndoms(iommu->cap);
ba395927 1643 num = find_first_zero_bit(iommu->domain_ids, ndomains);
fb170fb4
JL		 1644 if (num < ndomains) {
1645 set_bit(num, iommu->domain_ids);
9452d5bf 1646 set_iommu_domain(iommu, num, domain);
c0e8a6c8 1647 domain->iommu_did[iommu->seq_id] = num;
fb170fb4
JL		 1648 } else {
1649 num = -ENOSPC;
ba395927
KA		 1650 }
1651
fb170fb4
JL		 1652 return num;
1653}
1654
1655static int iommu_attach_domain(struct dmar_domain *domain,
1656 struct intel_iommu *iommu)
1657{
1658 int num;
1659 unsigned long flags;
1660
1661 spin_lock_irqsave(&iommu->lock, flags);
1662 num = __iommu_attach_domain(domain, iommu);
44bde614 1663 spin_unlock_irqrestore(&iommu->lock, flags);
fb170fb4 1664 if (num < 0)
9f10e5bf 1665 pr_err("%s: No free domain ids\n", iommu->name);
ba395927 1666
fb170fb4 1667 return num;
ba395927
KA		 1668}
1669
44bde614
JL		 1670static int iommu_attach_vm_domain(struct dmar_domain *domain,
1671 struct intel_iommu *iommu)
1672{
1673 int num;
44bde614 1674
c0e8a6c8
JR		 1675 num = domain->iommu_did[iommu->seq_id];
1676 if (num)
1677 return num;
44bde614
JL		 1678
1679 return __iommu_attach_domain(domain, iommu);
1680}
1681
2c2e2c38
FY		 1682static void iommu_detach_domain(struct dmar_domain *domain,
1683 struct intel_iommu *iommu)
ba395927
KA		 1684{
1685 unsigned long flags;
c0e8a6c8 1686 int num;
ba395927 1687
8c11e798 1688 spin_lock_irqsave(&iommu->lock, flags);
c0e8a6c8
JR		 1689
1690 num = domain->iommu_did[iommu->seq_id];
1691
1692 if (num == 0)
1693 return;
1694
1695 clear_bit(num, iommu->domain_ids);
9452d5bf 1696 set_iommu_domain(iommu, num, NULL);
c0e8a6c8 1697
8c11e798 1698 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1699}
1700
fb170fb4
JL		 1701static void domain_attach_iommu(struct dmar_domain *domain,
1702 struct intel_iommu *iommu)
1703{
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&domain->iommu_lock, flags);
1707 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1708 domain->iommu_count++;
1709 if (domain->iommu_count == 1)
1710 domain->nid = iommu->node;
1711 domain_update_iommu_cap(domain);
1712 }
1713 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1714}
1715
1716static int domain_detach_iommu(struct dmar_domain *domain,
1717 struct intel_iommu *iommu)
1718{
1719 unsigned long flags;
1720 int count = INT_MAX;
1721
1722 spin_lock_irqsave(&domain->iommu_lock, flags);
1723 if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
1724 count = --domain->iommu_count;
1725 domain_update_iommu_cap(domain);
c0e8a6c8 1726 domain->iommu_did[iommu->seq_id] = 0;
fb170fb4
JL		 1727 }
1728 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1729
1730 return count;
1731}
1732
ba395927 1733static struct iova_domain reserved_iova_list;
8a443df4 1734static struct lock_class_key reserved_rbtree_key;
ba395927 1735
51a63e67 1736static int dmar_init_reserved_ranges(void)
ba395927
KA		 1737{
1738 struct pci_dev *pdev = NULL;
1739 struct iova *iova;
1740 int i;
ba395927 1741
0fb5fe87
RM		 1742 init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
1743 DMA_32BIT_PFN);
ba395927 1744
8a443df4
MG		 1745 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1746 &reserved_rbtree_key);
1747
ba395927
KA		 1748 /* IOAPIC ranges shouldn't be accessed by DMA */
1749 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1750 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1751 if (!iova) {
9f10e5bf 1752 pr_err("Reserve IOAPIC range failed\n");
51a63e67
JC		 1753 return -ENODEV;
1754 }
ba395927
KA		 1755
1756 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1757 for_each_pci_dev(pdev) {
1758 struct resource *r;
1759
1760 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1761 r = &pdev->resource[i];
1762 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1763 continue;
1a4a4551
DW		 1764 iova = reserve_iova(&reserved_iova_list,
1765 IOVA_PFN(r->start),
1766 IOVA_PFN(r->end));
51a63e67 1767 if (!iova) {
9f10e5bf 1768 pr_err("Reserve iova failed\n");
51a63e67
JC		 1769 return -ENODEV;
1770 }
ba395927
KA		 1771 }
1772 }
51a63e67 1773 return 0;
ba395927
KA		 1774}
1775
1776static void domain_reserve_special_ranges(struct dmar_domain *domain)
1777{
1778 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1779}
1780
1781static inline int guestwidth_to_adjustwidth(int gaw)
1782{
1783 int agaw;
1784 int r = (gaw - 12) % 9;
1785
1786 if (r == 0)
1787 agaw = gaw;
1788 else
1789 agaw = gaw + 9 - r;
1790 if (agaw > 64)
1791 agaw = 64;
1792 return agaw;
1793}
1794
1795static int domain_init(struct dmar_domain *domain, int guest_width)
1796{
1797 struct intel_iommu *iommu;
1798 int adjust_width, agaw;
1799 unsigned long sagaw;
1800
0fb5fe87
RM		 1801 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
1802 DMA_32BIT_PFN);
ba395927
KA		 1803 domain_reserve_special_ranges(domain);
1804
1805 /* calculate AGAW */
8c11e798 1806 iommu = domain_get_iommu(domain);
ba395927
KA		 1807 if (guest_width > cap_mgaw(iommu->cap))
1808 guest_width = cap_mgaw(iommu->cap);
1809 domain->gaw = guest_width;
1810 adjust_width = guestwidth_to_adjustwidth(guest_width);
1811 agaw = width_to_agaw(adjust_width);
1812 sagaw = cap_sagaw(iommu->cap);
1813 if (!test_bit(agaw, &sagaw)) {
1814 /* hardware doesn't support it, choose a bigger one */
9f10e5bf 1815 pr_debug("Hardware doesn't support agaw %d\n", agaw);
ba395927
KA		 1816 agaw = find_next_bit(&sagaw, 5, agaw);
1817 if (agaw >= 5)
1818 return -ENODEV;
1819 }
1820 domain->agaw = agaw;
ba395927 1821
8e604097
WH		 1822 if (ecap_coherent(iommu->ecap))
1823 domain->iommu_coherency = 1;
1824 else
1825 domain->iommu_coherency = 0;
1826
58c610bd
SY		 1827 if (ecap_sc_support(iommu->ecap))
1828 domain->iommu_snooping = 1;
1829 else
1830 domain->iommu_snooping = 0;
1831
214e39aa
DW		 1832 if (intel_iommu_superpage)
1833 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1834 else
1835 domain->iommu_superpage = 0;
1836
4c923d47 1837 domain->nid = iommu->node;
c7151a8d 1838
ba395927 1839 /* always allocate the top pgd */
4c923d47 1840 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1841 if (!domain->pgd)
1842 return -ENOMEM;
5b6985ce 1843 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1844 return 0;
1845}
1846
1847static void domain_exit(struct dmar_domain *domain)
1848{
46ebb7af
AW		 1849 struct dmar_drhd_unit *drhd;
1850 struct intel_iommu *iommu;
ea8ea460 1851 struct page *freelist = NULL;
ba395927
KA		 1852
1853 /* Domain 0 is reserved, so dont process it */
1854 if (!domain)
1855 return;
1856
7b668357
AW		 1857 /* Flush any lazy unmaps that may reference this domain */
1858 if (!intel_iommu_strict)
1859 flush_unmaps_timeout(0);
1860
92d03cc8 1861 /* remove associated devices */
ba395927 1862 domain_remove_dev_info(domain);
92d03cc8 1863
ba395927
KA		 1864 /* destroy iovas */
1865 put_iova_domain(&domain->iovad);
ba395927 1866
ea8ea460 1867 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1868
92d03cc8 1869 /* clear attached or cached domains */
0e242612 1870 rcu_read_lock();
46ebb7af
AW		 1871 for_each_active_iommu(iommu, drhd)
1872 if (domain_type_is_vm(domain) ||
1873 test_bit(iommu->seq_id, domain->iommu_bmp))
1874 iommu_detach_domain(domain, iommu);
0e242612 1875 rcu_read_unlock();
2c2e2c38 1876
ea8ea460
DW		 1877 dma_free_pagelist(freelist);
1878
ba395927
KA		 1879 free_domain_mem(domain);
1880}
1881
64ae892b
DW		 1882static int domain_context_mapping_one(struct dmar_domain *domain,
1883 struct intel_iommu *iommu,
1884 u8 bus, u8 devfn, int translation)
ba395927
KA		 1885{
1886 struct context_entry *context;
ba395927 1887 unsigned long flags;
ea6606b0 1888 struct dma_pte *pgd;
ea6606b0
WH		 1889 int id;
1890 int agaw;
93a23a72 1891 struct device_domain_info *info = NULL;
ba395927
KA		 1892
1893 pr_debug("Set context mapping for %02x:%02x.%d\n",
1894 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1895
ba395927 1896 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1897 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1898 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1899
03ecc32c
DW		 1900 spin_lock_irqsave(&iommu->lock, flags);
1901 context = iommu_context_addr(iommu, bus, devfn, 1);
1902 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1903 if (!context)
1904 return -ENOMEM;
1905 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1906 if (context_present(context)) {
ba395927
KA		 1907 spin_unlock_irqrestore(&iommu->lock, flags);
1908 return 0;
1909 }
1910
cf484d0e
JR		 1911 context_clear_entry(context);
1912
ea6606b0
WH		 1913 id = domain->id;
1914 pgd = domain->pgd;
1915
ab8dfe25 1916 if (domain_type_is_vm_or_si(domain)) {
44bde614
JL		 1917 if (domain_type_is_vm(domain)) {
1918 id = iommu_attach_vm_domain(domain, iommu);
fb170fb4 1919 if (id < 0) {
ea6606b0 1920 spin_unlock_irqrestore(&iommu->lock, flags);
9f10e5bf 1921 pr_err("%s: No free domain ids\n", iommu->name);
ea6606b0
WH		 1922 return -EFAULT;
1923 }
ea6606b0
WH		 1924 }
1925
1926 /* Skip top levels of page tables for
1927 * iommu which has less agaw than default.
1672af11 1928 * Unnecessary for PT mode.
ea6606b0 1929 */
1672af11
CW		 1930 if (translation != CONTEXT_TT_PASS_THROUGH) {
1931 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1932 pgd = phys_to_virt(dma_pte_addr(pgd));
1933 if (!dma_pte_present(pgd)) {
1934 spin_unlock_irqrestore(&iommu->lock, flags);
1935 return -ENOMEM;
1936 }
ea6606b0
WH		 1937 }
1938 }
1939 }
1940
1941 context_set_domain_id(context, id);
4ed0d3e6 1942
93a23a72 1943 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1944 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1945 translation = info ? CONTEXT_TT_DEV_IOTLB :
1946 CONTEXT_TT_MULTI_LEVEL;
1947 }
4ed0d3e6
FY		 1948 /*
1949 * In pass through mode, AW must be programmed to indicate the largest
1950 * AGAW value supported by hardware. And ASR is ignored by hardware.
1951 */
93a23a72 1952 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1953 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1954 else {
1955 context_set_address_root(context, virt_to_phys(pgd));
1956 context_set_address_width(context, iommu->agaw);
1957 }
4ed0d3e6
FY		 1958
1959 context_set_translation_type(context, translation);
c07e7d21
MM		 1960 context_set_fault_enable(context);
1961 context_set_present(context);
5331fe6f 1962 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1963
4c25a2c1
DW		 1964 /*
1965 * It's a non-present to present mapping. If hardware doesn't cache
1966 * non-present entry we only need to flush the write-buffer. If the
1967 * _does_ cache non-present entries, then it does so in the special
1968 * domain #0, which we have to flush:
1969 */
1970 if (cap_caching_mode(iommu->cap)) {
1971 iommu->flush.flush_context(iommu, 0,
1972 (((u16)bus) << 8) | devfn,
1973 DMA_CCMD_MASK_NOBIT,
1974 DMA_CCMD_DEVICE_INVL);
18fd779a 1975 iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1976 } else {
ba395927 1977 iommu_flush_write_buffer(iommu);
4c25a2c1 1978 }
93a23a72 1979 iommu_enable_dev_iotlb(info);
ba395927 1980 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d 1981
fb170fb4
JL		 1982 domain_attach_iommu(domain, iommu);
1983
ba395927
KA		 1984 return 0;
1985}
1986
579305f7
AW		 1987struct domain_context_mapping_data {
1988 struct dmar_domain *domain;
1989 struct intel_iommu *iommu;
1990 int translation;
1991};
1992
1993static int domain_context_mapping_cb(struct pci_dev *pdev,
1994 u16 alias, void *opaque)
1995{
1996 struct domain_context_mapping_data *data = opaque;
1997
1998 return domain_context_mapping_one(data->domain, data->iommu,
1999 PCI_BUS_NUM(alias), alias & 0xff,
2000 data->translation);
2001}
2002
ba395927 2003static int
e1f167f3
DW		 2004domain_context_mapping(struct dmar_domain *domain, struct device *dev,
2005 int translation)
ba395927 2006{
64ae892b 2007 struct intel_iommu *iommu;
156baca8 2008 u8 bus, devfn;
579305f7 2009 struct domain_context_mapping_data data;
64ae892b 2010
e1f167f3 2011 iommu = device_to_iommu(dev, &bus, &devfn);
64ae892b
DW		 2012 if (!iommu)
2013 return -ENODEV;
ba395927 2014
579305f7
AW		 2015 if (!dev_is_pci(dev))
2016 return domain_context_mapping_one(domain, iommu, bus, devfn,
4ed0d3e6 2017 translation);
579305f7
AW		 2018
2019 data.domain = domain;
2020 data.iommu = iommu;
2021 data.translation = translation;
2022
2023 return pci_for_each_dma_alias(to_pci_dev(dev),
2024 &domain_context_mapping_cb, &data);
2025}
2026
2027static int domain_context_mapped_cb(struct pci_dev *pdev,
2028 u16 alias, void *opaque)
2029{
2030 struct intel_iommu *iommu = opaque;
2031
2032 return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
ba395927
KA		 2033}
2034
e1f167f3 2035static int domain_context_mapped(struct device *dev)
ba395927 2036{
5331fe6f 2037 struct intel_iommu *iommu;
156baca8 2038 u8 bus, devfn;
5331fe6f 2039
e1f167f3 2040 iommu = device_to_iommu(dev, &bus, &devfn);
5331fe6f
WH		 2041 if (!iommu)
2042 return -ENODEV;
ba395927 2043
579305f7
AW		 2044 if (!dev_is_pci(dev))
2045 return device_context_mapped(iommu, bus, devfn);
e1f167f3 2046
579305f7
AW		 2047 return !pci_for_each_dma_alias(to_pci_dev(dev),
2048 domain_context_mapped_cb, iommu);
ba395927
KA		 2049}
2050
f532959b
FY		 2051/* Returns a number of VTD pages, but aligned to MM page size */
2052static inline unsigned long aligned_nrpages(unsigned long host_addr,
2053 size_t size)
2054{
2055 host_addr &= ~PAGE_MASK;
2056 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2057}
2058
6dd9a7c7
YS		 2059/* Return largest possible superpage level for a given mapping */
2060static inline int hardware_largepage_caps(struct dmar_domain *domain,
2061 unsigned long iov_pfn,
2062 unsigned long phy_pfn,
2063 unsigned long pages)
2064{
2065 int support, level = 1;
2066 unsigned long pfnmerge;
2067
2068 support = domain->iommu_superpage;
2069
2070 /* To use a large page, the virtual *and* physical addresses
2071 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
2072 of them will mean we have to use smaller pages. So just
2073 merge them and check both at once. */
2074 pfnmerge = iov_pfn | phy_pfn;
2075
2076 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
2077 pages >>= VTD_STRIDE_SHIFT;
2078 if (!pages)
2079 break;
2080 pfnmerge >>= VTD_STRIDE_SHIFT;
2081 level++;
2082 support--;
2083 }
2084 return level;
2085}
2086
9051aa02
DW		 2087static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2088 struct scatterlist *sg, unsigned long phys_pfn,
2089 unsigned long nr_pages, int prot)
e1605495
DW		 2090{
2091 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 2092 phys_addr_t uninitialized_var(pteval);
cc4f14aa 2093 unsigned long sg_res = 0;
6dd9a7c7
YS		 2094 unsigned int largepage_lvl = 0;
2095 unsigned long lvl_pages = 0;
e1605495 2096
162d1b10 2097 BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
e1605495
DW		 2098
2099 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
2100 return -EINVAL;
2101
2102 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
2103
cc4f14aa
JL		 2104 if (!sg) {
2105 sg_res = nr_pages;
9051aa02
DW		 2106 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
2107 }
2108
6dd9a7c7 2109 while (nr_pages > 0) {
c85994e4
DW		 2110 uint64_t tmp;
2111
e1605495 2112 if (!sg_res) {
f532959b 2113 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 2114 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
2115 sg->dma_length = sg->length;
2116 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 2117 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 2118 }
6dd9a7c7 2119
e1605495 2120 if (!pte) {
6dd9a7c7
YS		 2121 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
2122
5cf0a76f 2123 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 2124 if (!pte)
2125 return -ENOMEM;
6dd9a7c7 2126 /* It is large page*/
6491d4d0 2127 if (largepage_lvl > 1) {
6dd9a7c7 2128 pteval |= DMA_PTE_LARGE_PAGE;
d41a4adb
JL		 2129 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2130 /*
2131 * Ensure that old small page tables are
2132 * removed to make room for superpage,
2133 * if they exist.
2134 */
6491d4d0 2135 dma_pte_free_pagetable(domain, iov_pfn,
d41a4adb 2136 iov_pfn + lvl_pages - 1);
6491d4d0 2137 } else {
6dd9a7c7 2138 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 2139 }
6dd9a7c7 2140
e1605495
DW		 2141 }
2142 /* We don't need lock here, nobody else
2143 * touches the iova range
2144 */
7766a3fb 2145 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2146 if (tmp) {
1bf20f0d 2147 static int dumps = 5;
9f10e5bf
JR		 2148 pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2149 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2150 if (dumps) {
2151 dumps--;
2152 debug_dma_dump_mappings(NULL);
2153 }
2154 WARN_ON(1);
2155 }
6dd9a7c7
YS		 2156
2157 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2158
2159 BUG_ON(nr_pages < lvl_pages);
2160 BUG_ON(sg_res < lvl_pages);
2161
2162 nr_pages -= lvl_pages;
2163 iov_pfn += lvl_pages;
2164 phys_pfn += lvl_pages;
2165 pteval += lvl_pages * VTD_PAGE_SIZE;
2166 sg_res -= lvl_pages;
2167
2168 /* If the next PTE would be the first in a new page, then we
2169 need to flush the cache on the entries we've just written.
2170 And then we'll need to recalculate 'pte', so clear it and
2171 let it get set again in the if (!pte) block above.
2172
2173 If we're done (!nr_pages) we need to flush the cache too.
2174
2175 Also if we've been setting superpages, we may need to
2176 recalculate 'pte' and switch back to smaller pages for the
2177 end of the mapping, if the trailing size is not enough to
2178 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2179 pte++;
6dd9a7c7
YS		 2180 if (!nr_pages || first_pte_in_page(pte) ||
2181 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2182 domain_flush_cache(domain, first_pte,
2183 (void *)pte - (void *)first_pte);
2184 pte = NULL;
2185 }
6dd9a7c7
YS		 2186
2187 if (!sg_res && nr_pages)
e1605495
DW		 2188 sg = sg_next(sg);
2189 }
2190 return 0;
2191}
2192
9051aa02
DW		 2193static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2194 struct scatterlist *sg, unsigned long nr_pages,
2195 int prot)
ba395927 2196{
9051aa02
DW		 2197 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2198}
6f6a00e4 2199
9051aa02
DW		 2200static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2201 unsigned long phys_pfn, unsigned long nr_pages,
2202 int prot)
2203{
2204 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2205}
2206
c7151a8d 2207static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2208{
c7151a8d
WH		 2209 if (!iommu)
2210 return;
8c11e798
WH		 2211
2212 clear_context_table(iommu, bus, devfn);
2213 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2214 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2215 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2216}
2217
109b9b04
DW		 2218static inline void unlink_domain_info(struct device_domain_info *info)
2219{
2220 assert_spin_locked(&device_domain_lock);
2221 list_del(&info->link);
2222 list_del(&info->global);
2223 if (info->dev)
0bcb3e28 2224 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2225}
2226
ba395927
KA		 2227static void domain_remove_dev_info(struct dmar_domain *domain)
2228{
3a74ca01 2229 struct device_domain_info *info, *tmp;
fb170fb4 2230 unsigned long flags;
ba395927
KA		 2231
2232 spin_lock_irqsave(&device_domain_lock, flags);
3a74ca01 2233 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
109b9b04 2234 unlink_domain_info(info);
ba395927
KA		 2235 spin_unlock_irqrestore(&device_domain_lock, flags);
2236
93a23a72 2237 iommu_disable_dev_iotlb(info);
7c7faa11 2238 iommu_detach_dev(info->iommu, info->bus, info->devfn);
ba395927 2239
ab8dfe25 2240 if (domain_type_is_vm(domain)) {
7c7faa11 2241 iommu_detach_dependent_devices(info->iommu, info->dev);
fb170fb4 2242 domain_detach_iommu(domain, info->iommu);
92d03cc8
JL		 2243 }
2244
2245 free_devinfo_mem(info);
ba395927
KA		 2246 spin_lock_irqsave(&device_domain_lock, flags);
2247 }
2248 spin_unlock_irqrestore(&device_domain_lock, flags);
2249}
2250
2251/*
2252 * find_domain
1525a29a 2253 * Note: we use struct device->archdata.iommu stores the info
ba395927 2254 */
1525a29a 2255static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2256{
2257 struct device_domain_info *info;
2258
2259 /* No lock here, assumes no domain exit in normal case */
1525a29a 2260 info = dev->archdata.iommu;
ba395927
KA		 2261 if (info)
2262 return info->domain;
2263 return NULL;
2264}
2265
5a8f40e8 2266static inline struct device_domain_info *
745f2586
JL		 2267dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2268{
2269 struct device_domain_info *info;
2270
2271 list_for_each_entry(info, &device_domain_list, global)
41e80dca 2272 if (info->iommu->segment == segment && info->bus == bus &&
745f2586 2273 info->devfn == devfn)
5a8f40e8 2274 return info;
745f2586
JL		 2275
2276 return NULL;
2277}
2278
5a8f40e8 2279static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
41e80dca 2280 int bus, int devfn,
b718cd3d
DW		 2281 struct device *dev,
2282 struct dmar_domain *domain)
745f2586 2283{
5a8f40e8 2284 struct dmar_domain *found = NULL;
745f2586
JL		 2285 struct device_domain_info *info;
2286 unsigned long flags;
2287
2288 info = alloc_devinfo_mem();
2289 if (!info)
b718cd3d 2290 return NULL;
745f2586 2291
745f2586
JL		 2292 info->bus = bus;
2293 info->devfn = devfn;
2294 info->dev = dev;
2295 info->domain = domain;
5a8f40e8 2296 info->iommu = iommu;
745f2586
JL		 2297
2298 spin_lock_irqsave(&device_domain_lock, flags);
2299 if (dev)
0bcb3e28 2300 found = find_domain(dev);
5a8f40e8
DW		 2301 else {
2302 struct device_domain_info *info2;
41e80dca 2303 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
5a8f40e8
DW		 2304 if (info2)
2305 found = info2->domain;
2306 }
745f2586
JL		 2307 if (found) {
2308 spin_unlock_irqrestore(&device_domain_lock, flags);
2309 free_devinfo_mem(info);
b718cd3d
DW		 2310 /* Caller must free the original domain */
2311 return found;
745f2586
JL		 2312 }
2313
b718cd3d
DW		 2314 list_add(&info->link, &domain->devices);
2315 list_add(&info->global, &device_domain_list);
2316 if (dev)
2317 dev->archdata.iommu = info;
2318 spin_unlock_irqrestore(&device_domain_lock, flags);
2319
2320 return domain;
745f2586
JL		 2321}
2322
579305f7
AW		 2323static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
2324{
2325 *(u16 *)opaque = alias;
2326 return 0;
2327}
2328
ba395927 2329/* domain is initialized */
146922ec 2330static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
ba395927 2331{
579305f7
AW		 2332 struct dmar_domain *domain, *tmp;
2333 struct intel_iommu *iommu;
5a8f40e8 2334 struct device_domain_info *info;
579305f7 2335 u16 dma_alias;
ba395927 2336 unsigned long flags;
aa4d066a 2337 u8 bus, devfn;
ba395927 2338
146922ec 2339 domain = find_domain(dev);
ba395927
KA		 2340 if (domain)
2341 return domain;
2342
579305f7
AW		 2343 iommu = device_to_iommu(dev, &bus, &devfn);
2344 if (!iommu)
2345 return NULL;
2346
146922ec
DW		 2347 if (dev_is_pci(dev)) {
2348 struct pci_dev *pdev = to_pci_dev(dev);
276dbf99 2349
579305f7
AW		 2350 pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
2351
2352 spin_lock_irqsave(&device_domain_lock, flags);
2353 info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
2354 PCI_BUS_NUM(dma_alias),
2355 dma_alias & 0xff);
2356 if (info) {
2357 iommu = info->iommu;
2358 domain = info->domain;
5a8f40e8 2359 }
579305f7 2360 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2361
579305f7
AW		 2362 /* DMA alias already has a domain, uses it */
2363 if (info)
2364 goto found_domain;
2365 }
ba395927 2366
146922ec 2367 /* Allocate and initialize new domain for the device */
ab8dfe25 2368 domain = alloc_domain(0);
745f2586 2369 if (!domain)
579305f7 2370 return NULL;
44bde614
JL		 2371 domain->id = iommu_attach_domain(domain, iommu);
2372 if (domain->id < 0) {
2fe9723d 2373 free_domain_mem(domain);
579305f7 2374 return NULL;
2c2e2c38 2375 }
fb170fb4 2376 domain_attach_iommu(domain, iommu);
579305f7
AW		 2377 if (domain_init(domain, gaw)) {
2378 domain_exit(domain);
2379 return NULL;
2c2e2c38 2380 }
ba395927 2381
579305f7
AW		 2382 /* register PCI DMA alias device */
2383 if (dev_is_pci(dev)) {
2384 tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias),
2385 dma_alias & 0xff, NULL, domain);
2386
2387 if (!tmp || tmp != domain) {
2388 domain_exit(domain);
2389 domain = tmp;
2390 }
2391
b718cd3d 2392 if (!domain)
579305f7 2393 return NULL;
ba395927
KA		 2394 }
2395
2396found_domain:
579305f7
AW		 2397 tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
2398
2399 if (!tmp || tmp != domain) {
2400 domain_exit(domain);
2401 domain = tmp;
2402 }
b718cd3d
DW		 2403
2404 return domain;
ba395927
KA		 2405}
2406
2c2e2c38 2407static int iommu_identity_mapping;
e0fc7e0b
DW		 2408#define IDENTMAP_ALL 1
2409#define IDENTMAP_GFX 2
2410#define IDENTMAP_AZALIA 4
2c2e2c38 2411
b213203e
DW		 2412static int iommu_domain_identity_map(struct dmar_domain *domain,
2413 unsigned long long start,
2414 unsigned long long end)
ba395927 2415{
c5395d5c
DW		 2416 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2417 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2418
2419 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2420 dma_to_mm_pfn(last_vpfn))) {
9f10e5bf 2421 pr_err("Reserving iova failed\n");
b213203e 2422 return -ENOMEM;
ba395927
KA		 2423 }
2424
c5395d5c
DW		 2425 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2426 start, end, domain->id);
ba395927
KA		 2427 /*
2428 * RMRR range might have overlap with physical memory range,
2429 * clear it first
2430 */
c5395d5c 2431 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2432
c5395d5c
DW		 2433 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2434 last_vpfn - first_vpfn + 1,
61df7443 2435 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2436}
2437
0b9d9753 2438static int iommu_prepare_identity_map(struct device *dev,
b213203e
DW		 2439 unsigned long long start,
2440 unsigned long long end)
2441{
2442 struct dmar_domain *domain;
2443 int ret;
2444
0b9d9753 2445 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2446 if (!domain)
2447 return -ENOMEM;
2448
19943b0e
DW		 2449 /* For _hardware_ passthrough, don't bother. But for software
2450 passthrough, we do it anyway -- it may indicate a memory
2451 range which is reserved in E820, so which didn't get set
2452 up to start with in si_domain */
2453 if (domain == si_domain && hw_pass_through) {
9f10e5bf
JR		 2454 pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2455 dev_name(dev), start, end);
19943b0e
DW		 2456 return 0;
2457 }
2458
9f10e5bf
JR		 2459 pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2460 dev_name(dev), start, end);
2461
5595b528
DW		 2462 if (end < start) {
2463 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2464 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2465 dmi_get_system_info(DMI_BIOS_VENDOR),
2466 dmi_get_system_info(DMI_BIOS_VERSION),
2467 dmi_get_system_info(DMI_PRODUCT_VERSION));
2468 ret = -EIO;
2469 goto error;
2470 }
2471
2ff729f5
DW		 2472 if (end >> agaw_to_width(domain->agaw)) {
2473 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2474 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2475 agaw_to_width(domain->agaw),
2476 dmi_get_system_info(DMI_BIOS_VENDOR),
2477 dmi_get_system_info(DMI_BIOS_VERSION),
2478 dmi_get_system_info(DMI_PRODUCT_VERSION));
2479 ret = -EIO;
2480 goto error;
2481 }
19943b0e 2482
b213203e 2483 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2484 if (ret)
2485 goto error;
2486
2487 /* context entry init */
0b9d9753 2488 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2489 if (ret)
2490 goto error;
2491
2492 return 0;
2493
2494 error:
ba395927
KA		 2495 domain_exit(domain);
2496 return ret;
ba395927
KA		 2497}
2498
2499static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
0b9d9753 2500 struct device *dev)
ba395927 2501{
0b9d9753 2502 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927 2503 return 0;
0b9d9753
DW		 2504 return iommu_prepare_identity_map(dev, rmrr->base_address,
2505 rmrr->end_address);
ba395927
KA		 2506}
2507
d3f13810 2508#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2509static inline void iommu_prepare_isa(void)
2510{
2511 struct pci_dev *pdev;
2512 int ret;
2513
2514 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2515 if (!pdev)
2516 return;
2517
9f10e5bf 2518 pr_info("Prepare 0-16MiB unity mapping for LPC\n");
0b9d9753 2519 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2520
2521 if (ret)
9f10e5bf 2522 pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
49a0429e 2523
9b27e82d 2524 pci_dev_put(pdev);
49a0429e
KA		 2525}
2526#else
2527static inline void iommu_prepare_isa(void)
2528{
2529 return;
2530}
d3f13810 2531#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2532
2c2e2c38 2533static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2534
071e1374 2535static int __init si_domain_init(int hw)
2c2e2c38
FY		 2536{
2537 struct dmar_drhd_unit *drhd;
2538 struct intel_iommu *iommu;
c7ab48d2 2539 int nid, ret = 0;
44bde614 2540 bool first = true;
2c2e2c38 2541
ab8dfe25 2542 si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2c2e2c38
FY		 2543 if (!si_domain)
2544 return -EFAULT;
2545
2c2e2c38
FY		 2546 for_each_active_iommu(iommu, drhd) {
2547 ret = iommu_attach_domain(si_domain, iommu);
fb170fb4 2548 if (ret < 0) {
2c2e2c38
FY		 2549 domain_exit(si_domain);
2550 return -EFAULT;
44bde614
JL		 2551 } else if (first) {
2552 si_domain->id = ret;
2553 first = false;
2554 } else if (si_domain->id != ret) {
2555 domain_exit(si_domain);
2556 return -EFAULT;
2c2e2c38 2557 }
fb170fb4 2558 domain_attach_iommu(si_domain, iommu);
2c2e2c38
FY		 2559 }
2560
2561 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2562 domain_exit(si_domain);
2563 return -EFAULT;
2564 }
2565
9f10e5bf 2566 pr_debug("Identity mapping domain is domain %d\n",
9544c003 2567 si_domain->id);
2c2e2c38 2568
19943b0e
DW		 2569 if (hw)
2570 return 0;
2571
c7ab48d2 2572 for_each_online_node(nid) {
5dfe8660
TH		 2573 unsigned long start_pfn, end_pfn;
2574 int i;
2575
2576 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2577 ret = iommu_domain_identity_map(si_domain,
2578 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2579 if (ret)
2580 return ret;
2581 }
c7ab48d2
DW		 2582 }
2583
2c2e2c38
FY		 2584 return 0;
2585}
2586
9b226624 2587static int identity_mapping(struct device *dev)
2c2e2c38
FY		 2588{
2589 struct device_domain_info *info;
2590
2591 if (likely(!iommu_identity_mapping))
2592 return 0;
2593
9b226624 2594 info = dev->archdata.iommu;
cb452a40
MT		 2595 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2596 return (info->domain == si_domain);
2c2e2c38 2597
2c2e2c38
FY		 2598 return 0;
2599}
2600
2601static int domain_add_dev_info(struct dmar_domain *domain,
5913c9bf 2602 struct device *dev, int translation)
2c2e2c38 2603{
0ac72664 2604 struct dmar_domain *ndomain;
5a8f40e8 2605 struct intel_iommu *iommu;
156baca8 2606 u8 bus, devfn;
5fe60f4e 2607 int ret;
2c2e2c38 2608
5913c9bf 2609 iommu = device_to_iommu(dev, &bus, &devfn);
5a8f40e8
DW		 2610 if (!iommu)
2611 return -ENODEV;
2612
5913c9bf 2613 ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
0ac72664
DW		 2614 if (ndomain != domain)
2615 return -EBUSY;
2c2e2c38 2616
5913c9bf 2617 ret = domain_context_mapping(domain, dev, translation);
e2ad23d0 2618 if (ret) {
5913c9bf 2619 domain_remove_one_dev_info(domain, dev);
e2ad23d0
DW		 2620 return ret;
2621 }
2622
2c2e2c38
FY		 2623 return 0;
2624}
2625
0b9d9753 2626static bool device_has_rmrr(struct device *dev)
ea2447f7
TM		 2627{
2628 struct dmar_rmrr_unit *rmrr;
832bd858 2629 struct device *tmp;
ea2447f7
TM		 2630 int i;
2631
0e242612 2632 rcu_read_lock();
ea2447f7 2633 for_each_rmrr_units(rmrr) {
b683b230
JL		 2634 /*
2635 * Return TRUE if this RMRR contains the device that
2636 * is passed in.
2637 */
2638 for_each_active_dev_scope(rmrr->devices,
2639 rmrr->devices_cnt, i, tmp)
0b9d9753 2640 if (tmp == dev) {
0e242612 2641 rcu_read_unlock();
ea2447f7 2642 return true;
b683b230 2643 }
ea2447f7 2644 }
0e242612 2645 rcu_read_unlock();
ea2447f7
TM		 2646 return false;
2647}
2648
c875d2c1
AW		 2649/*
2650 * There are a couple cases where we need to restrict the functionality of
2651 * devices associated with RMRRs. The first is when evaluating a device for
2652 * identity mapping because problems exist when devices are moved in and out
2653 * of domains and their respective RMRR information is lost. This means that
2654 * a device with associated RMRRs will never be in a "passthrough" domain.
2655 * The second is use of the device through the IOMMU API. This interface
2656 * expects to have full control of the IOVA space for the device. We cannot
2657 * satisfy both the requirement that RMRR access is maintained and have an
2658 * unencumbered IOVA space. We also have no ability to quiesce the device's
2659 * use of the RMRR space or even inform the IOMMU API user of the restriction.
2660 * We therefore prevent devices associated with an RMRR from participating in
2661 * the IOMMU API, which eliminates them from device assignment.
2662 *
2663 * In both cases we assume that PCI USB devices with RMRRs have them largely
2664 * for historical reasons and that the RMRR space is not actively used post
2665 * boot. This exclusion may change if vendors begin to abuse it.
18436afd
DW		 2666 *
2667 * The same exception is made for graphics devices, with the requirement that
2668 * any use of the RMRR regions will be torn down before assigning the device
2669 * to a guest.
c875d2c1
AW		 2670 */
2671static bool device_is_rmrr_locked(struct device *dev)
2672{
2673 if (!device_has_rmrr(dev))
2674 return false;
2675
2676 if (dev_is_pci(dev)) {
2677 struct pci_dev *pdev = to_pci_dev(dev);
2678
18436afd 2679 if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
c875d2c1
AW		 2680 return false;
2681 }
2682
2683 return true;
2684}
2685
3bdb2591 2686static int iommu_should_identity_map(struct device *dev, int startup)
6941af28 2687{
ea2447f7 2688
3bdb2591
DW		 2689 if (dev_is_pci(dev)) {
2690 struct pci_dev *pdev = to_pci_dev(dev);
ea2447f7 2691
c875d2c1 2692 if (device_is_rmrr_locked(dev))
3bdb2591 2693 return 0;
e0fc7e0b 2694
3bdb2591
DW		 2695 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2696 return 1;
e0fc7e0b 2697
3bdb2591
DW		 2698 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2699 return 1;
6941af28 2700
3bdb2591 2701 if (!(iommu_identity_mapping & IDENTMAP_ALL))
3dfc813d 2702 return 0;
3bdb2591
DW		 2703
2704 /*
2705 * We want to start off with all devices in the 1:1 domain, and
2706 * take them out later if we find they can't access all of memory.
2707 *
2708 * However, we can't do this for PCI devices behind bridges,
2709 * because all PCI devices behind the same bridge will end up
2710 * with the same source-id on their transactions.
2711 *
2712 * Practically speaking, we can't change things around for these
2713 * devices at run-time, because we can't be sure there'll be no
2714 * DMA transactions in flight for any of their siblings.
2715 *
2716 * So PCI devices (unless they're on the root bus) as well as
2717 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2718 * the 1:1 domain, just in _case_ one of their siblings turns out
2719 * not to be able to map all of memory.
2720 */
2721 if (!pci_is_pcie(pdev)) {
2722 if (!pci_is_root_bus(pdev->bus))
2723 return 0;
2724 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2725 return 0;
2726 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d 2727 return 0;
3bdb2591
DW		 2728 } else {
2729 if (device_has_rmrr(dev))
2730 return 0;
2731 }
3dfc813d 2732
3bdb2591 2733 /*
3dfc813d 2734 * At boot time, we don't yet know if devices will be 64-bit capable.
3bdb2591 2735 * Assume that they will — if they turn out not to be, then we can
3dfc813d
DW		 2736 * take them out of the 1:1 domain later.
2737 */
8fcc5372
CW		 2738 if (!startup) {
2739 /*
2740 * If the device's dma_mask is less than the system's memory
2741 * size then this is not a candidate for identity mapping.
2742 */
3bdb2591 2743 u64 dma_mask = *dev->dma_mask;
8fcc5372 2744
3bdb2591
DW		 2745 if (dev->coherent_dma_mask &&
2746 dev->coherent_dma_mask < dma_mask)
2747 dma_mask = dev->coherent_dma_mask;
8fcc5372 2748
3bdb2591 2749 return dma_mask >= dma_get_required_mask(dev);
8fcc5372 2750 }
6941af28
DW		 2751
2752 return 1;
2753}
2754
cf04eee8
DW		 2755static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
2756{
2757 int ret;
2758
2759 if (!iommu_should_identity_map(dev, 1))
2760 return 0;
2761
2762 ret = domain_add_dev_info(si_domain, dev,
2763 hw ? CONTEXT_TT_PASS_THROUGH :
2764 CONTEXT_TT_MULTI_LEVEL);
2765 if (!ret)
9f10e5bf
JR		 2766 pr_info("%s identity mapping for device %s\n",
2767 hw ? "Hardware" : "Software", dev_name(dev));
cf04eee8
DW		 2768 else if (ret == -ENODEV)
2769 /* device not associated with an iommu */
2770 ret = 0;
2771
2772 return ret;
2773}
2774
2775
071e1374 2776static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2777{
2c2e2c38 2778 struct pci_dev *pdev = NULL;
cf04eee8
DW		 2779 struct dmar_drhd_unit *drhd;
2780 struct intel_iommu *iommu;
2781 struct device *dev;
2782 int i;
2783 int ret = 0;
2c2e2c38 2784
2c2e2c38 2785 for_each_pci_dev(pdev) {
cf04eee8
DW		 2786 ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
2787 if (ret)
2788 return ret;
2789 }
2790
2791 for_each_active_iommu(iommu, drhd)
2792 for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
2793 struct acpi_device_physical_node *pn;
2794 struct acpi_device *adev;
2795
2796 if (dev->bus != &acpi_bus_type)
2797 continue;
86080ccc 2798
cf04eee8
DW		 2799 adev= to_acpi_device(dev);
2800 mutex_lock(&adev->physical_node_lock);
2801 list_for_each_entry(pn, &adev->physical_node_list, node) {
2802 ret = dev_prepare_static_identity_mapping(pn->dev, hw);
2803 if (ret)
2804 break;
eae460b6 2805 }
cf04eee8
DW		 2806 mutex_unlock(&adev->physical_node_lock);
2807 if (ret)
2808 return ret;
62edf5dc 2809 }
2c2e2c38
FY		 2810
2811 return 0;
2812}
2813
ffebeb46
JL		 2814static void intel_iommu_init_qi(struct intel_iommu *iommu)
2815{
2816 /*
2817 * Start from the sane iommu hardware state.
2818 * If the queued invalidation is already initialized by us
2819 * (for example, while enabling interrupt-remapping) then
2820 * we got the things already rolling from a sane state.
2821 */
2822 if (!iommu->qi) {
2823 /*
2824 * Clear any previous faults.
2825 */
2826 dmar_fault(-1, iommu);
2827 /*
2828 * Disable queued invalidation if supported and already enabled
2829 * before OS handover.
2830 */
2831 dmar_disable_qi(iommu);
2832 }
2833
2834 if (dmar_enable_qi(iommu)) {
2835 /*
2836 * Queued Invalidate not enabled, use Register Based Invalidate
2837 */
2838 iommu->flush.flush_context = __iommu_flush_context;
2839 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
9f10e5bf 2840 pr_info("%s: Using Register based invalidation\n",
ffebeb46
JL		 2841 iommu->name);
2842 } else {
2843 iommu->flush.flush_context = qi_flush_context;
2844 iommu->flush.flush_iotlb = qi_flush_iotlb;
9f10e5bf 2845 pr_info("%s: Using Queued invalidation\n", iommu->name);
ffebeb46
JL		 2846 }
2847}
2848
091d42e4
JR		 2849static int copy_context_table(struct intel_iommu *iommu,
2850 struct root_entry *old_re,
2851 struct context_entry **tbl,
2852 int bus, bool ext)
2853{
2854 struct context_entry *old_ce = NULL, *new_ce = NULL, ce;
dbcd861f 2855 int tbl_idx, pos = 0, idx, devfn, ret = 0, did;
091d42e4
JR		 2856 phys_addr_t old_ce_phys;
2857
2858 tbl_idx = ext ? bus * 2 : bus;
2859
2860 for (devfn = 0; devfn < 256; devfn++) {
2861 /* First calculate the correct index */
2862 idx = (ext ? devfn * 2 : devfn) % 256;
2863
2864 if (idx == 0) {
2865 /* First save what we may have and clean up */
2866 if (new_ce) {
2867 tbl[tbl_idx] = new_ce;
2868 __iommu_flush_cache(iommu, new_ce,
2869 VTD_PAGE_SIZE);
2870 pos = 1;
2871 }
2872
2873 if (old_ce)
2874 iounmap(old_ce);
2875
2876 ret = 0;
2877 if (devfn < 0x80)
2878 old_ce_phys = root_entry_lctp(old_re);
2879 else
2880 old_ce_phys = root_entry_uctp(old_re);
2881
2882 if (!old_ce_phys) {
2883 if (ext && devfn == 0) {
2884 /* No LCTP, try UCTP */
2885 devfn = 0x7f;
2886 continue;
2887 } else {
2888 goto out;
2889 }
2890 }
2891
2892 ret = -ENOMEM;
2893 old_ce = ioremap_cache(old_ce_phys, PAGE_SIZE);
2894 if (!old_ce)
2895 goto out;
2896
2897 new_ce = alloc_pgtable_page(iommu->node);
2898 if (!new_ce)
2899 goto out_unmap;
2900
2901 ret = 0;
2902 }
2903
2904 /* Now copy the context entry */
2905 ce = old_ce[idx];
2906
cf484d0e 2907 if (!__context_present(&ce))
091d42e4
JR		 2908 continue;
2909
dbcd861f
JR		 2910 did = context_domain_id(&ce);
2911 if (did >= 0 && did < cap_ndoms(iommu->cap))
2912 set_bit(did, iommu->domain_ids);
2913
cf484d0e
JR		 2914 /*
2915 * We need a marker for copied context entries. This
2916 * marker needs to work for the old format as well as
2917 * for extended context entries.
2918 *
2919 * Bit 67 of the context entry is used. In the old
2920 * format this bit is available to software, in the
2921 * extended format it is the PGE bit, but PGE is ignored
2922 * by HW if PASIDs are disabled (and thus still
2923 * available).
2924 *
2925 * So disable PASIDs first and then mark the entry
2926 * copied. This means that we don't copy PASID
2927 * translations from the old kernel, but this is fine as
2928 * faults there are not fatal.
2929 */
2930 context_clear_pasid_enable(&ce);
2931 context_set_copied(&ce);
2932
091d42e4
JR		 2933 new_ce[idx] = ce;
2934 }
2935
2936 tbl[tbl_idx + pos] = new_ce;
2937
2938 __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE);
2939
2940out_unmap:
2941 iounmap(old_ce);
2942
2943out:
2944 return ret;
2945}
2946
2947static int copy_translation_tables(struct intel_iommu *iommu)
2948{
2949 struct context_entry **ctxt_tbls;
2950 struct root_entry *old_rt;
2951 phys_addr_t old_rt_phys;
2952 int ctxt_table_entries;
2953 unsigned long flags;
2954 u64 rtaddr_reg;
2955 int bus, ret;
c3361f2f 2956 bool new_ext, ext;
091d42e4
JR		 2957
2958 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
2959 ext = !!(rtaddr_reg & DMA_RTADDR_RTT);
c3361f2f
JR		 2960 new_ext = !!ecap_ecs(iommu->ecap);
2961
2962 /*
2963 * The RTT bit can only be changed when translation is disabled,
2964 * but disabling translation means to open a window for data
2965 * corruption. So bail out and don't copy anything if we would
2966 * have to change the bit.
2967 */
2968 if (new_ext != ext)
2969 return -EINVAL;
091d42e4
JR		 2970
2971 old_rt_phys = rtaddr_reg & VTD_PAGE_MASK;
2972 if (!old_rt_phys)
2973 return -EINVAL;
2974
2975 old_rt = ioremap_cache(old_rt_phys, PAGE_SIZE);
2976 if (!old_rt)
2977 return -ENOMEM;
2978
2979 /* This is too big for the stack - allocate it from slab */
2980 ctxt_table_entries = ext ? 512 : 256;
2981 ret = -ENOMEM;
2982 ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL);
2983 if (!ctxt_tbls)
2984 goto out_unmap;
2985
2986 for (bus = 0; bus < 256; bus++) {
2987 ret = copy_context_table(iommu, &old_rt[bus],
2988 ctxt_tbls, bus, ext);
2989 if (ret) {
2990 pr_err("%s: Failed to copy context table for bus %d\n",
2991 iommu->name, bus);
2992 continue;
2993 }
2994 }
2995
2996 spin_lock_irqsave(&iommu->lock, flags);
2997
2998 /* Context tables are copied, now write them to the root_entry table */
2999 for (bus = 0; bus < 256; bus++) {
3000 int idx = ext ? bus * 2 : bus;
3001 u64 val;
3002
3003 if (ctxt_tbls[idx]) {
3004 val = virt_to_phys(ctxt_tbls[idx]) | 1;
3005 iommu->root_entry[bus].lo = val;
3006 }
3007
3008 if (!ext || !ctxt_tbls[idx + 1])
3009 continue;
3010
3011 val = virt_to_phys(ctxt_tbls[idx + 1]) | 1;
3012 iommu->root_entry[bus].hi = val;
3013 }
3014
3015 spin_unlock_irqrestore(&iommu->lock, flags);
3016
3017 kfree(ctxt_tbls);
3018
3019 __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE);
3020
3021 ret = 0;
3022
3023out_unmap:
3024 iounmap(old_rt);
3025
3026 return ret;
3027}
3028
b779260b 3029static int __init init_dmars(void)
ba395927
KA		 3030{
3031 struct dmar_drhd_unit *drhd;
3032 struct dmar_rmrr_unit *rmrr;
a87f4918 3033 bool copied_tables = false;
832bd858 3034 struct device *dev;
ba395927 3035 struct intel_iommu *iommu;
9d783ba0 3036 int i, ret;
2c2e2c38 3037
ba395927
KA		 3038 /*
3039 * for each drhd
3040 * allocate root
3041 * initialize and program root entry to not present
3042 * endfor
3043 */
3044 for_each_drhd_unit(drhd) {
5e0d2a6f 3045 /*
3046 * lock not needed as this is only incremented in the single
3047 * threaded kernel __init code path all other access are read
3048 * only
3049 */
78d8e704 3050 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
1b198bb0
MT		 3051 g_num_of_iommus++;
3052 continue;
3053 }
9f10e5bf 3054 pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
5e0d2a6f 3055 }
3056
ffebeb46
JL		 3057 /* Preallocate enough resources for IOMMU hot-addition */
3058 if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
3059 g_num_of_iommus = DMAR_UNITS_SUPPORTED;
3060
d9630fe9
WH		 3061 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
3062 GFP_KERNEL);
3063 if (!g_iommus) {
9f10e5bf 3064 pr_err("Allocating global iommu array failed\n");
d9630fe9
WH		 3065 ret = -ENOMEM;
3066 goto error;
3067 }
3068
80b20dd8 3069 deferred_flush = kzalloc(g_num_of_iommus *
3070 sizeof(struct deferred_flush_tables), GFP_KERNEL);
3071 if (!deferred_flush) {
5e0d2a6f 3072 ret = -ENOMEM;
989d51fc 3073 goto free_g_iommus;
5e0d2a6f 3074 }
3075
7c919779 3076 for_each_active_iommu(iommu, drhd) {
d9630fe9 3077 g_iommus[iommu->seq_id] = iommu;
ba395927 3078
b63d80d1
JR		 3079 intel_iommu_init_qi(iommu);
3080
e61d98d8
SS		 3081 ret = iommu_init_domains(iommu);
3082 if (ret)
989d51fc 3083 goto free_iommu;
e61d98d8 3084
4158c2ec
JR		 3085 init_translation_status(iommu);
3086
091d42e4
JR		 3087 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
3088 iommu_disable_translation(iommu);
3089 clear_translation_pre_enabled(iommu);
3090 pr_warn("Translation was enabled for %s but we are not in kdump mode\n",
3091 iommu->name);
3092 }
4158c2ec 3093
ba395927
KA		 3094 /*
3095 * TBD:
3096 * we could share the same root & context tables
25985edc 3097 * among all IOMMU's. Need to Split it later.
ba395927
KA		 3098 */
3099 ret = iommu_alloc_root_entry(iommu);
ffebeb46 3100 if (ret)
989d51fc 3101 goto free_iommu;
5f0a7f76 3102
091d42e4
JR		 3103 if (translation_pre_enabled(iommu)) {
3104 pr_info("Translation already enabled - trying to copy translation structures\n");
3105
3106 ret = copy_translation_tables(iommu);
3107 if (ret) {
3108 /*
3109 * We found the IOMMU with translation
3110 * enabled - but failed to copy over the
3111 * old root-entry table. Try to proceed
3112 * by disabling translation now and
3113 * allocating a clean root-entry table.
3114 * This might cause DMAR faults, but
3115 * probably the dump will still succeed.
3116 */
3117 pr_err("Failed to copy translation tables from previous kernel for %s\n",
3118 iommu->name);
3119 iommu_disable_translation(iommu);
3120 clear_translation_pre_enabled(iommu);
3121 } else {
3122 pr_info("Copied translation tables from previous kernel for %s\n",
3123 iommu->name);
a87f4918 3124 copied_tables = true;
091d42e4
JR		 3125 }
3126 }
3127
5f0a7f76
JR		 3128 iommu_flush_write_buffer(iommu);
3129 iommu_set_root_entry(iommu);
3130 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
3131 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3132
4ed0d3e6 3133 if (!ecap_pass_through(iommu->ecap))
19943b0e 3134 hw_pass_through = 0;
ba395927
KA		 3135 }
3136
19943b0e 3137 if (iommu_pass_through)
e0fc7e0b
DW		 3138 iommu_identity_mapping |= IDENTMAP_ALL;
3139
d3f13810 3140#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 3141 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 3142#endif
e0fc7e0b 3143
86080ccc
JR		 3144 if (iommu_identity_mapping) {
3145 ret = si_domain_init(hw_pass_through);
3146 if (ret)
3147 goto free_iommu;
3148 }
3149
e0fc7e0b
DW		 3150 check_tylersburg_isoch();
3151
a87f4918
JR		 3152 /*
3153 * If we copied translations from a previous kernel in the kdump
3154 * case, we can not assign the devices to domains now, as that
3155 * would eliminate the old mappings. So skip this part and defer
3156 * the assignment to device driver initialization time.
3157 */
3158 if (copied_tables)
3159 goto domains_done;
3160
ba395927 3161 /*
19943b0e
DW		 3162 * If pass through is not set or not enabled, setup context entries for
3163 * identity mappings for rmrr, gfx, and isa and may fall back to static
3164 * identity mapping if iommu_identity_mapping is set.
ba395927 3165 */
19943b0e
DW		 3166 if (iommu_identity_mapping) {
3167 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 3168 if (ret) {
9f10e5bf 3169 pr_crit("Failed to setup IOMMU pass-through\n");
989d51fc 3170 goto free_iommu;
ba395927
KA		 3171 }
3172 }
ba395927 3173 /*
19943b0e
DW		 3174 * For each rmrr
3175 * for each dev attached to rmrr
3176 * do
3177 * locate drhd for dev, alloc domain for dev
3178 * allocate free domain
3179 * allocate page table entries for rmrr
3180 * if context not allocated for bus
3181 * allocate and init context
3182 * set present in root table for this bus
3183 * init context with domain, translation etc
3184 * endfor
3185 * endfor
ba395927 3186 */
9f10e5bf 3187 pr_info("Setting RMRR:\n");
19943b0e 3188 for_each_rmrr_units(rmrr) {
b683b230
JL		 3189 /* some BIOS lists non-exist devices in DMAR table. */
3190 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858 3191 i, dev) {
0b9d9753 3192 ret = iommu_prepare_rmrr_dev(rmrr, dev);
19943b0e 3193 if (ret)
9f10e5bf 3194 pr_err("Mapping reserved region failed\n");
ba395927 3195 }
4ed0d3e6 3196 }
49a0429e 3197
19943b0e
DW		 3198 iommu_prepare_isa();
3199
a87f4918
JR		 3200domains_done:
3201
ba395927
KA		 3202 /*
3203 * for each drhd
3204 * enable fault log
3205 * global invalidate context cache
3206 * global invalidate iotlb
3207 * enable translation
3208 */
7c919779 3209 for_each_iommu(iommu, drhd) {
51a63e67
JC		 3210 if (drhd->ignored) {
3211 /*
3212 * we always have to disable PMRs or DMA may fail on
3213 * this device
3214 */
3215 if (force_on)
7c919779 3216 iommu_disable_protect_mem_regions(iommu);
ba395927 3217 continue;
51a63e67 3218 }
ba395927
KA		 3219
3220 iommu_flush_write_buffer(iommu);
3221
3460a6d9
KA		 3222 ret = dmar_set_interrupt(iommu);
3223 if (ret)
989d51fc 3224 goto free_iommu;
3460a6d9 3225
8939ddf6
JR		 3226 if (!translation_pre_enabled(iommu))
3227 iommu_enable_translation(iommu);
3228
b94996c9 3229 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 3230 }
3231
3232 return 0;
989d51fc
JL		 3233
3234free_iommu:
ffebeb46
JL		 3235 for_each_active_iommu(iommu, drhd) {
3236 disable_dmar_iommu(iommu);
a868e6b7 3237 free_dmar_iommu(iommu);
ffebeb46 3238 }
9bdc531e 3239 kfree(deferred_flush);
989d51fc 3240free_g_iommus:
d9630fe9 3241 kfree(g_iommus);
989d51fc 3242error:
ba395927
KA		 3243 return ret;
3244}
3245
5a5e02a6 3246/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 3247static struct iova *intel_alloc_iova(struct device *dev,
3248 struct dmar_domain *domain,
3249 unsigned long nrpages, uint64_t dma_mask)
ba395927 3250{
ba395927 3251 struct iova *iova = NULL;
ba395927 3252
875764de
DW		 3253 /* Restrict dma_mask to the width that the iommu can handle */
3254 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
3255
3256 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 3257 /*
3258 * First try to allocate an io virtual address in
284901a9 3259 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 3260 * from higher range
ba395927 3261 */
875764de
DW		 3262 iova = alloc_iova(&domain->iovad, nrpages,
3263 IOVA_PFN(DMA_BIT_MASK(32)), 1);
3264 if (iova)
3265 return iova;
3266 }
3267 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
3268 if (unlikely(!iova)) {
9f10e5bf 3269 pr_err("Allocating %ld-page iova for %s failed",
207e3592 3270 nrpages, dev_name(dev));
f76aec76
KA		 3271 return NULL;
3272 }
3273
3274 return iova;
3275}
3276
d4b709f4 3277static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
f76aec76
KA		 3278{
3279 struct dmar_domain *domain;
3280 int ret;
3281
d4b709f4 3282 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
f76aec76 3283 if (!domain) {
9f10e5bf 3284 pr_err("Allocating domain for %s failed\n",
d4b709f4 3285 dev_name(dev));
4fe05bbc 3286 return NULL;
ba395927
KA		 3287 }
3288
3289 /* make sure context mapping is ok */
d4b709f4
DW		 3290 if (unlikely(!domain_context_mapped(dev))) {
3291 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
f76aec76 3292 if (ret) {
9f10e5bf 3293 pr_err("Domain context map for %s failed\n",
d4b709f4 3294 dev_name(dev));
4fe05bbc 3295 return NULL;
f76aec76 3296 }
ba395927
KA		 3297 }
3298
f76aec76
KA		 3299 return domain;
3300}
3301
d4b709f4 3302static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
147202aa
DW		 3303{
3304 struct device_domain_info *info;
3305
3306 /* No lock here, assumes no domain exit in normal case */
d4b709f4 3307 info = dev->archdata.iommu;
147202aa
DW		 3308 if (likely(info))
3309 return info->domain;
3310
3311 return __get_valid_domain_for_dev(dev);
3312}
3313
ecb509ec 3314/* Check if the dev needs to go through non-identity map and unmap process.*/
73676832 3315static int iommu_no_mapping(struct device *dev)
2c2e2c38
FY		 3316{
3317 int found;
3318
3d89194a 3319 if (iommu_dummy(dev))
1e4c64c4
DW		 3320 return 1;
3321
2c2e2c38 3322 if (!iommu_identity_mapping)
1e4c64c4 3323 return 0;
2c2e2c38 3324
9b226624 3325 found = identity_mapping(dev);
2c2e2c38 3326 if (found) {
ecb509ec 3327 if (iommu_should_identity_map(dev, 0))
2c2e2c38
FY		 3328 return 1;
3329 else {
3330 /*
3331 * 32 bit DMA is removed from si_domain and fall back
3332 * to non-identity mapping.
3333 */
bf9c9eda 3334 domain_remove_one_dev_info(si_domain, dev);
9f10e5bf
JR		 3335 pr_info("32bit %s uses non-identity mapping\n",
3336 dev_name(dev));
2c2e2c38
FY		 3337 return 0;
3338 }
3339 } else {
3340 /*
3341 * In case of a detached 64 bit DMA device from vm, the device
3342 * is put into si_domain for identity mapping.
3343 */
ecb509ec 3344 if (iommu_should_identity_map(dev, 0)) {
2c2e2c38 3345 int ret;
5913c9bf 3346 ret = domain_add_dev_info(si_domain, dev,
5fe60f4e
DW		 3347 hw_pass_through ?
3348 CONTEXT_TT_PASS_THROUGH :
3349 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38 3350 if (!ret) {
9f10e5bf
JR		 3351 pr_info("64bit %s uses identity mapping\n",
3352 dev_name(dev));
2c2e2c38
FY		 3353 return 1;
3354 }
3355 }
3356 }
3357
1e4c64c4 3358 return 0;
2c2e2c38
FY		 3359}
3360
5040a918 3361static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
bb9e6d65 3362 size_t size, int dir, u64 dma_mask)
f76aec76 3363{
f76aec76 3364 struct dmar_domain *domain;
5b6985ce 3365 phys_addr_t start_paddr;
f76aec76
KA		 3366 struct iova *iova;
3367 int prot = 0;
6865f0d1 3368 int ret;
8c11e798 3369 struct intel_iommu *iommu;
33041ec0 3370 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 3371
3372 BUG_ON(dir == DMA_NONE);
2c2e2c38 3373
5040a918 3374 if (iommu_no_mapping(dev))
6865f0d1 3375 return paddr;
f76aec76 3376
5040a918 3377 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3378 if (!domain)
3379 return 0;
3380
8c11e798 3381 iommu = domain_get_iommu(domain);
88cb6a74 3382 size = aligned_nrpages(paddr, size);
f76aec76 3383
5040a918 3384 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 3385 if (!iova)
3386 goto error;
3387
ba395927
KA		 3388 /*
3389 * Check if DMAR supports zero-length reads on write only
3390 * mappings..
3391 */
3392 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3393 !cap_zlr(iommu->cap))
ba395927
KA		 3394 prot |= DMA_PTE_READ;
3395 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3396 prot |= DMA_PTE_WRITE;
3397 /*
6865f0d1 3398 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 3399 * page. Note: if two part of one page are separately mapped, we
6865f0d1 3400 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 3401 * is not a big problem
3402 */
0ab36de2 3403 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 3404 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 3405 if (ret)
3406 goto error;
3407
1f0ef2aa
DW		 3408 /* it's a non-present to present mapping. Only flush if caching mode */
3409 if (cap_caching_mode(iommu->cap))
ea8ea460 3410 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 3411 else
8c11e798 3412 iommu_flush_write_buffer(iommu);
f76aec76 3413
03d6a246
DW		 3414 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3415 start_paddr += paddr & ~PAGE_MASK;
3416 return start_paddr;
ba395927 3417
ba395927 3418error:
f76aec76
KA		 3419 if (iova)
3420 __free_iova(&domain->iovad, iova);
9f10e5bf 3421 pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
5040a918 3422 dev_name(dev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3423 return 0;
3424}
3425
ffbbef5c
FT		 3426static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3427 unsigned long offset, size_t size,
3428 enum dma_data_direction dir,
3429 struct dma_attrs *attrs)
bb9e6d65 3430{
ffbbef5c 3431 return __intel_map_single(dev, page_to_phys(page) + offset, size,
46333e37 3432 dir, *dev->dma_mask);
bb9e6d65
FT		 3433}
3434
5e0d2a6f 3435static void flush_unmaps(void)
3436{
80b20dd8 3437 int i, j;
5e0d2a6f 3438
5e0d2a6f 3439 timer_on = 0;
3440
3441 /* just flush them all */
3442 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3443 struct intel_iommu *iommu = g_iommus[i];
3444 if (!iommu)
3445 continue;
c42d9f32 3446
9dd2fe89
YZ		 3447 if (!deferred_flush[i].next)
3448 continue;
3449
78d5f0f5
NA		 3450 /* In caching mode, global flushes turn emulation expensive */
3451 if (!cap_caching_mode(iommu->cap))
3452 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3453 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3454 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3455 unsigned long mask;
3456 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3457 struct dmar_domain *domain = deferred_flush[i].domain[j];
3458
3459 /* On real hardware multiple invalidations are expensive */
3460 if (cap_caching_mode(iommu->cap))
3461 iommu_flush_iotlb_psi(iommu, domain->id,
a156ef99 3462 iova->pfn_lo, iova_size(iova),
ea8ea460 3463 !deferred_flush[i].freelist[j], 0);
78d5f0f5 3464 else {
a156ef99 3465 mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
78d5f0f5
NA		 3466 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3467 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3468 }
93a23a72 3469 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3470 if (deferred_flush[i].freelist[j])
3471 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3472 }
9dd2fe89 3473 deferred_flush[i].next = 0;
5e0d2a6f 3474 }
3475
5e0d2a6f 3476 list_size = 0;
5e0d2a6f 3477}
3478
3479static void flush_unmaps_timeout(unsigned long data)
3480{
80b20dd8 3481 unsigned long flags;
3482
3483 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3484 flush_unmaps();
80b20dd8 3485 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3486}
3487
ea8ea460 3488static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3489{
3490 unsigned long flags;
80b20dd8 3491 int next, iommu_id;
8c11e798 3492 struct intel_iommu *iommu;
5e0d2a6f 3493
3494 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3495 if (list_size == HIGH_WATER_MARK)
3496 flush_unmaps();
3497
8c11e798
WH		 3498 iommu = domain_get_iommu(dom);
3499 iommu_id = iommu->seq_id;
c42d9f32 3500
80b20dd8 3501 next = deferred_flush[iommu_id].next;
3502 deferred_flush[iommu_id].domain[next] = dom;
3503 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3504 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3505 deferred_flush[iommu_id].next++;
5e0d2a6f 3506
3507 if (!timer_on) {
3508 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3509 timer_on = 1;
3510 }
3511 list_size++;
3512 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3513}
3514
d41a4adb 3515static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
ba395927 3516{
f76aec76 3517 struct dmar_domain *domain;
d794dc9b 3518 unsigned long start_pfn, last_pfn;
ba395927 3519 struct iova *iova;
8c11e798 3520 struct intel_iommu *iommu;
ea8ea460 3521 struct page *freelist;
ba395927 3522
73676832 3523 if (iommu_no_mapping(dev))
f76aec76 3524 return;
2c2e2c38 3525
1525a29a 3526 domain = find_domain(dev);
ba395927
KA		 3527 BUG_ON(!domain);
3528
8c11e798
WH		 3529 iommu = domain_get_iommu(domain);
3530
ba395927 3531 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3532 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3533 (unsigned long long)dev_addr))
ba395927 3534 return;
ba395927 3535
d794dc9b
DW		 3536 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3537 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3538
d794dc9b 3539 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
207e3592 3540 dev_name(dev), start_pfn, last_pfn);
ba395927 3541
ea8ea460 3542 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3543
5e0d2a6f 3544 if (intel_iommu_strict) {
03d6a246 3545 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3546 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3547 /* free iova */
3548 __free_iova(&domain->iovad, iova);
ea8ea460 3549 dma_free_pagelist(freelist);
5e0d2a6f 3550 } else {
ea8ea460 3551 add_unmap(domain, iova, freelist);
5e0d2a6f 3552 /*
3553 * queue up the release of the unmap to save the 1/6th of the
3554 * cpu used up by the iotlb flush operation...
3555 */
5e0d2a6f 3556 }
ba395927
KA		 3557}
3558
d41a4adb
JL		 3559static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3560 size_t size, enum dma_data_direction dir,
3561 struct dma_attrs *attrs)
3562{
3563 intel_unmap(dev, dev_addr);
3564}
3565
5040a918 3566static void *intel_alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 3567 dma_addr_t *dma_handle, gfp_t flags,
3568 struct dma_attrs *attrs)
ba395927 3569{
36746436 3570 struct page *page = NULL;
ba395927
KA		 3571 int order;
3572
5b6985ce 3573 size = PAGE_ALIGN(size);
ba395927 3574 order = get_order(size);
e8bb910d 3575
5040a918 3576 if (!iommu_no_mapping(dev))
e8bb910d 3577 flags &= ~(GFP_DMA | GFP_DMA32);
5040a918
DW		 3578 else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3579 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
e8bb910d
AW		 3580 flags |= GFP_DMA;
3581 else
3582 flags |= GFP_DMA32;
3583 }
ba395927 3584
36746436
AM		 3585 if (flags & __GFP_WAIT) {
3586 unsigned int count = size >> PAGE_SHIFT;
3587
3588 page = dma_alloc_from_contiguous(dev, count, order);
3589 if (page && iommu_no_mapping(dev) &&
3590 page_to_phys(page) + size > dev->coherent_dma_mask) {
3591 dma_release_from_contiguous(dev, page, count);
3592 page = NULL;
3593 }
3594 }
3595
3596 if (!page)
3597 page = alloc_pages(flags, order);
3598 if (!page)
ba395927 3599 return NULL;
36746436 3600 memset(page_address(page), 0, size);
ba395927 3601
36746436 3602 *dma_handle = __intel_map_single(dev, page_to_phys(page), size,
bb9e6d65 3603 DMA_BIDIRECTIONAL,
5040a918 3604 dev->coherent_dma_mask);
ba395927 3605 if (*dma_handle)
36746436
AM		 3606 return page_address(page);
3607 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3608 __free_pages(page, order);
3609
ba395927
KA		 3610 return NULL;
3611}
3612
5040a918 3613static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
baa676fc 3614 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3615{
3616 int order;
36746436 3617 struct page *page = virt_to_page(vaddr);
ba395927 3618
5b6985ce 3619 size = PAGE_ALIGN(size);
ba395927
KA		 3620 order = get_order(size);
3621
d41a4adb 3622 intel_unmap(dev, dma_handle);
36746436
AM		 3623 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3624 __free_pages(page, order);
ba395927
KA		 3625}
3626
5040a918 3627static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
d7ab5c46
FT		 3628 int nelems, enum dma_data_direction dir,
3629 struct dma_attrs *attrs)
ba395927 3630{
d41a4adb 3631 intel_unmap(dev, sglist[0].dma_address);
ba395927
KA		 3632}
3633
ba395927 3634static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3635 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3636{
3637 int i;
c03ab37c 3638 struct scatterlist *sg;
ba395927 3639
c03ab37c 3640 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3641 BUG_ON(!sg_page(sg));
4cf2e75d 3642 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3643 sg->dma_length = sg->length;
ba395927
KA		 3644 }
3645 return nelems;
3646}
3647
5040a918 3648static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
d7ab5c46 3649 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3650{
ba395927 3651 int i;
ba395927 3652 struct dmar_domain *domain;
f76aec76
KA		 3653 size_t size = 0;
3654 int prot = 0;
f76aec76
KA		 3655 struct iova *iova = NULL;
3656 int ret;
c03ab37c 3657 struct scatterlist *sg;
b536d24d 3658 unsigned long start_vpfn;
8c11e798 3659 struct intel_iommu *iommu;
ba395927
KA		 3660
3661 BUG_ON(dir == DMA_NONE);
5040a918
DW		 3662 if (iommu_no_mapping(dev))
3663 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
ba395927 3664
5040a918 3665 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3666 if (!domain)
3667 return 0;
3668
8c11e798
WH		 3669 iommu = domain_get_iommu(domain);
3670
b536d24d 3671 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3672 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3673
5040a918
DW		 3674 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3675 *dev->dma_mask);
f76aec76 3676 if (!iova) {
c03ab37c 3677 sglist->dma_length = 0;
f76aec76
KA		 3678 return 0;
3679 }
3680
3681 /*
3682 * Check if DMAR supports zero-length reads on write only
3683 * mappings..
3684 */
3685 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3686 !cap_zlr(iommu->cap))
f76aec76
KA		 3687 prot |= DMA_PTE_READ;
3688 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3689 prot |= DMA_PTE_WRITE;
3690
b536d24d 3691 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3692
f532959b 3693 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495 3694 if (unlikely(ret)) {
e1605495
DW		 3695 dma_pte_free_pagetable(domain, start_vpfn,
3696 start_vpfn + size - 1);
e1605495
DW		 3697 __free_iova(&domain->iovad, iova);
3698 return 0;
ba395927
KA		 3699 }
3700
1f0ef2aa
DW		 3701 /* it's a non-present to present mapping. Only flush if caching mode */
3702 if (cap_caching_mode(iommu->cap))
ea8ea460 3703 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3704 else
8c11e798 3705 iommu_flush_write_buffer(iommu);
1f0ef2aa 3706
ba395927
KA		 3707 return nelems;
3708}
3709
dfb805e8
FT		 3710static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3711{
3712 return !dma_addr;
3713}
3714
160c1d8e 3715struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3716 .alloc = intel_alloc_coherent,
3717 .free = intel_free_coherent,
ba395927
KA		 3718 .map_sg = intel_map_sg,
3719 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3720 .map_page = intel_map_page,
3721 .unmap_page = intel_unmap_page,
dfb805e8 3722 .mapping_error = intel_mapping_error,
ba395927
KA		 3723};
3724
3725static inline int iommu_domain_cache_init(void)
3726{
3727 int ret = 0;
3728
3729 iommu_domain_cache = kmem_cache_create("iommu_domain",
3730 sizeof(struct dmar_domain),
3731 0,
3732 SLAB_HWCACHE_ALIGN,
3733
3734 NULL);
3735 if (!iommu_domain_cache) {
9f10e5bf 3736 pr_err("Couldn't create iommu_domain cache\n");
ba395927
KA		 3737 ret = -ENOMEM;
3738 }
3739
3740 return ret;
3741}
3742
3743static inline int iommu_devinfo_cache_init(void)
3744{
3745 int ret = 0;
3746
3747 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3748 sizeof(struct device_domain_info),
3749 0,
3750 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3751 NULL);
3752 if (!iommu_devinfo_cache) {
9f10e5bf 3753 pr_err("Couldn't create devinfo cache\n");
ba395927
KA		 3754 ret = -ENOMEM;
3755 }
3756
3757 return ret;
3758}
3759
ba395927
KA		 3760static int __init iommu_init_mempool(void)
3761{
3762 int ret;
3763 ret = iommu_iova_cache_init();
3764 if (ret)
3765 return ret;
3766
3767 ret = iommu_domain_cache_init();
3768 if (ret)
3769 goto domain_error;
3770
3771 ret = iommu_devinfo_cache_init();
3772 if (!ret)
3773 return ret;
3774
3775 kmem_cache_destroy(iommu_domain_cache);
3776domain_error:
85b45456 3777 iommu_iova_cache_destroy();
ba395927
KA		 3778
3779 return -ENOMEM;
3780}
3781
3782static void __init iommu_exit_mempool(void)
3783{
3784 kmem_cache_destroy(iommu_devinfo_cache);
3785 kmem_cache_destroy(iommu_domain_cache);
85b45456 3786 iommu_iova_cache_destroy();
ba395927
KA		 3787}
3788
556ab45f
DW		 3789static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3790{
3791 struct dmar_drhd_unit *drhd;
3792 u32 vtbar;
3793 int rc;
3794
3795 /* We know that this device on this chipset has its own IOMMU.
3796 * If we find it under a different IOMMU, then the BIOS is lying
3797 * to us. Hope that the IOMMU for this device is actually
3798 * disabled, and it needs no translation...
3799 */
3800 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3801 if (rc) {
3802 /* "can't" happen */
3803 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3804 return;
3805 }
3806 vtbar &= 0xffff0000;
3807
3808 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3809 drhd = dmar_find_matched_drhd_unit(pdev);
3810 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3811 TAINT_FIRMWARE_WORKAROUND,
3812 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3813 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3814}
3815DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3816
ba395927
KA		 3817static void __init init_no_remapping_devices(void)
3818{
3819 struct dmar_drhd_unit *drhd;
832bd858 3820 struct device *dev;
b683b230 3821 int i;
ba395927
KA		 3822
3823 for_each_drhd_unit(drhd) {
3824 if (!drhd->include_all) {
b683b230
JL		 3825 for_each_active_dev_scope(drhd->devices,
3826 drhd->devices_cnt, i, dev)
3827 break;
832bd858 3828 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3829 if (i == drhd->devices_cnt)
3830 drhd->ignored = 1;
3831 }
3832 }
3833
7c919779 3834 for_each_active_drhd_unit(drhd) {
7c919779 3835 if (drhd->include_all)
ba395927
KA		 3836 continue;
3837
b683b230
JL		 3838 for_each_active_dev_scope(drhd->devices,
3839 drhd->devices_cnt, i, dev)
832bd858 3840 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3841 break;
ba395927
KA		 3842 if (i < drhd->devices_cnt)
3843 continue;
3844
c0771df8
DW		 3845 /* This IOMMU has *only* gfx devices. Either bypass it or
3846 set the gfx_mapped flag, as appropriate */
3847 if (dmar_map_gfx) {
3848 intel_iommu_gfx_mapped = 1;
3849 } else {
3850 drhd->ignored = 1;
b683b230
JL		 3851 for_each_active_dev_scope(drhd->devices,
3852 drhd->devices_cnt, i, dev)
832bd858 3853 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3854 }
3855 }
3856}
3857
f59c7b69
FY		 3858#ifdef CONFIG_SUSPEND
3859static int init_iommu_hw(void)
3860{
3861 struct dmar_drhd_unit *drhd;
3862 struct intel_iommu *iommu = NULL;
3863
3864 for_each_active_iommu(iommu, drhd)
3865 if (iommu->qi)
3866 dmar_reenable_qi(iommu);
3867
b779260b
JC		 3868 for_each_iommu(iommu, drhd) {
3869 if (drhd->ignored) {
3870 /*
3871 * we always have to disable PMRs or DMA may fail on
3872 * this device
3873 */
3874 if (force_on)
3875 iommu_disable_protect_mem_regions(iommu);
3876 continue;
3877 }
3878
f59c7b69
FY		 3879 iommu_flush_write_buffer(iommu);
3880
3881 iommu_set_root_entry(iommu);
3882
3883 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3884 DMA_CCMD_GLOBAL_INVL);
2a41ccee
JL		 3885 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3886 iommu_enable_translation(iommu);
b94996c9 3887 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3888 }
3889
3890 return 0;
3891}
3892
3893static void iommu_flush_all(void)
3894{
3895 struct dmar_drhd_unit *drhd;
3896 struct intel_iommu *iommu;
3897
3898 for_each_active_iommu(iommu, drhd) {
3899 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3900 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3901 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3902 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3903 }
3904}
3905
134fac3f 3906static int iommu_suspend(void)
f59c7b69
FY		 3907{
3908 struct dmar_drhd_unit *drhd;
3909 struct intel_iommu *iommu = NULL;
3910 unsigned long flag;
3911
3912 for_each_active_iommu(iommu, drhd) {
3913 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3914 GFP_ATOMIC);
3915 if (!iommu->iommu_state)
3916 goto nomem;
3917 }
3918
3919 iommu_flush_all();
3920
3921 for_each_active_iommu(iommu, drhd) {
3922 iommu_disable_translation(iommu);
3923
1f5b3c3f 3924 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3925
3926 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3927 readl(iommu->reg + DMAR_FECTL_REG);
3928 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3929 readl(iommu->reg + DMAR_FEDATA_REG);
3930 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3931 readl(iommu->reg + DMAR_FEADDR_REG);
3932 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3933 readl(iommu->reg + DMAR_FEUADDR_REG);
3934
1f5b3c3f 3935 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3936 }
3937 return 0;
3938
3939nomem:
3940 for_each_active_iommu(iommu, drhd)
3941 kfree(iommu->iommu_state);
3942
3943 return -ENOMEM;
3944}
3945
134fac3f 3946static void iommu_resume(void)
f59c7b69
FY		 3947{
3948 struct dmar_drhd_unit *drhd;
3949 struct intel_iommu *iommu = NULL;
3950 unsigned long flag;
3951
3952 if (init_iommu_hw()) {
b779260b
JC		 3953 if (force_on)
3954 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3955 else
3956 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3957 return;
f59c7b69
FY		 3958 }
3959
3960 for_each_active_iommu(iommu, drhd) {
3961
1f5b3c3f 3962 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3963
3964 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3965 iommu->reg + DMAR_FECTL_REG);
3966 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3967 iommu->reg + DMAR_FEDATA_REG);
3968 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3969 iommu->reg + DMAR_FEADDR_REG);
3970 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3971 iommu->reg + DMAR_FEUADDR_REG);
3972
1f5b3c3f 3973 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3974 }
3975
3976 for_each_active_iommu(iommu, drhd)
3977 kfree(iommu->iommu_state);
f59c7b69
FY		 3978}
3979
134fac3f 3980static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3981 .resume = iommu_resume,
3982 .suspend = iommu_suspend,
3983};
3984
134fac3f 3985static void __init init_iommu_pm_ops(void)
f59c7b69 3986{
134fac3f 3987 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3988}
3989
3990#else
99592ba4 3991static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3992#endif /* CONFIG_PM */
3993
318fe7df 3994
c2a0b538 3995int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
318fe7df
SS		 3996{
3997 struct acpi_dmar_reserved_memory *rmrr;
3998 struct dmar_rmrr_unit *rmrru;
3999
4000 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
4001 if (!rmrru)
4002 return -ENOMEM;
4003
4004 rmrru->hdr = header;
4005 rmrr = (struct acpi_dmar_reserved_memory *)header;
4006 rmrru->base_address = rmrr->base_address;
4007 rmrru->end_address = rmrr->end_address;
2e455289
JL		 4008 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
4009 ((void *)rmrr) + rmrr->header.length,
4010 &rmrru->devices_cnt);
4011 if (rmrru->devices_cnt && rmrru->devices == NULL) {
4012 kfree(rmrru);
4013 return -ENOMEM;
4014 }
318fe7df 4015
2e455289 4016 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 4017
2e455289 4018 return 0;
318fe7df
SS		 4019}
4020
6b197249
JL		 4021static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
4022{
4023 struct dmar_atsr_unit *atsru;
4024 struct acpi_dmar_atsr *tmp;
4025
4026 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
4027 tmp = (struct acpi_dmar_atsr *)atsru->hdr;
4028 if (atsr->segment != tmp->segment)
4029 continue;
4030 if (atsr->header.length != tmp->header.length)
4031 continue;
4032 if (memcmp(atsr, tmp, atsr->header.length) == 0)
4033 return atsru;
4034 }
4035
4036 return NULL;
4037}
4038
4039int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
318fe7df
SS		 4040{
4041 struct acpi_dmar_atsr *atsr;
4042 struct dmar_atsr_unit *atsru;
4043
6b197249
JL		 4044 if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
4045 return 0;
4046
318fe7df 4047 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
6b197249
JL		 4048 atsru = dmar_find_atsr(atsr);
4049 if (atsru)
4050 return 0;
4051
4052 atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
318fe7df
SS		 4053 if (!atsru)
4054 return -ENOMEM;
4055
6b197249
JL		 4056 /*
4057 * If memory is allocated from slab by ACPI _DSM method, we need to
4058 * copy the memory content because the memory buffer will be freed
4059 * on return.
4060 */
4061 atsru->hdr = (void *)(atsru + 1);
4062 memcpy(atsru->hdr, hdr, hdr->length);
318fe7df 4063 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 4064 if (!atsru->include_all) {
4065 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
4066 (void *)atsr + atsr->header.length,
4067 &atsru->devices_cnt);
4068 if (atsru->devices_cnt && atsru->devices == NULL) {
4069 kfree(atsru);
4070 return -ENOMEM;
4071 }
4072 }
318fe7df 4073
0e242612 4074 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 4075
4076 return 0;
4077}
4078
9bdc531e
JL		 4079static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
4080{
4081 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
4082 kfree(atsru);
4083}
4084
6b197249
JL		 4085int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4086{
4087 struct acpi_dmar_atsr *atsr;
4088 struct dmar_atsr_unit *atsru;
4089
4090 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4091 atsru = dmar_find_atsr(atsr);
4092 if (atsru) {
4093 list_del_rcu(&atsru->list);
4094 synchronize_rcu();
4095 intel_iommu_free_atsr(atsru);
4096 }
4097
4098 return 0;
4099}
4100
4101int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4102{
4103 int i;
4104 struct device *dev;
4105 struct acpi_dmar_atsr *atsr;
4106 struct dmar_atsr_unit *atsru;
4107
4108 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4109 atsru = dmar_find_atsr(atsr);
4110 if (!atsru)
4111 return 0;
4112
4113 if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
4114 for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
4115 i, dev)
4116 return -EBUSY;
4117
4118 return 0;
4119}
4120
ffebeb46
JL		 4121static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
4122{
4123 int sp, ret = 0;
4124 struct intel_iommu *iommu = dmaru->iommu;
4125
4126 if (g_iommus[iommu->seq_id])
4127 return 0;
4128
4129 if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
9f10e5bf 4130 pr_warn("%s: Doesn't support hardware pass through.\n",
ffebeb46
JL		 4131 iommu->name);
4132 return -ENXIO;
4133 }
4134 if (!ecap_sc_support(iommu->ecap) &&
4135 domain_update_iommu_snooping(iommu)) {
9f10e5bf 4136 pr_warn("%s: Doesn't support snooping.\n",
ffebeb46
JL		 4137 iommu->name);
4138 return -ENXIO;
4139 }
4140 sp = domain_update_iommu_superpage(iommu) - 1;
4141 if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
9f10e5bf 4142 pr_warn("%s: Doesn't support large page.\n",
ffebeb46
JL		 4143 iommu->name);
4144 return -ENXIO;
4145 }
4146
4147 /*
4148 * Disable translation if already enabled prior to OS handover.
4149 */
4150 if (iommu->gcmd & DMA_GCMD_TE)
4151 iommu_disable_translation(iommu);
4152
4153 g_iommus[iommu->seq_id] = iommu;
4154 ret = iommu_init_domains(iommu);
4155 if (ret == 0)
4156 ret = iommu_alloc_root_entry(iommu);
4157 if (ret)
4158 goto out;
4159
4160 if (dmaru->ignored) {
4161 /*
4162 * we always have to disable PMRs or DMA may fail on this device
4163 */
4164 if (force_on)
4165 iommu_disable_protect_mem_regions(iommu);
4166 return 0;
4167 }
4168
4169 intel_iommu_init_qi(iommu);
4170 iommu_flush_write_buffer(iommu);
4171 ret = dmar_set_interrupt(iommu);
4172 if (ret)
4173 goto disable_iommu;
4174
4175 iommu_set_root_entry(iommu);
4176 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
4177 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
4178 iommu_enable_translation(iommu);
4179
4180 if (si_domain) {
4181 ret = iommu_attach_domain(si_domain, iommu);
4182 if (ret < 0 || si_domain->id != ret)
4183 goto disable_iommu;
4184 domain_attach_iommu(si_domain, iommu);
4185 }
4186
4187 iommu_disable_protect_mem_regions(iommu);
4188 return 0;
4189
4190disable_iommu:
4191 disable_dmar_iommu(iommu);
4192out:
4193 free_dmar_iommu(iommu);
4194 return ret;
4195}
4196
6b197249
JL		 4197int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
4198{
ffebeb46
JL		 4199 int ret = 0;
4200 struct intel_iommu *iommu = dmaru->iommu;
4201
4202 if (!intel_iommu_enabled)
4203 return 0;
4204 if (iommu == NULL)
4205 return -EINVAL;
4206
4207 if (insert) {
4208 ret = intel_iommu_add(dmaru);
4209 } else {
4210 disable_dmar_iommu(iommu);
4211 free_dmar_iommu(iommu);
4212 }
4213
4214 return ret;
6b197249
JL		 4215}
4216
9bdc531e
JL		 4217static void intel_iommu_free_dmars(void)
4218{
4219 struct dmar_rmrr_unit *rmrru, *rmrr_n;
4220 struct dmar_atsr_unit *atsru, *atsr_n;
4221
4222 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
4223 list_del(&rmrru->list);
4224 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
4225 kfree(rmrru);
318fe7df
SS		 4226 }
4227
9bdc531e
JL		 4228 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
4229 list_del(&atsru->list);
4230 intel_iommu_free_atsr(atsru);
4231 }
318fe7df
SS		 4232}
4233
4234int dmar_find_matched_atsr_unit(struct pci_dev *dev)
4235{
b683b230 4236 int i, ret = 1;
318fe7df 4237 struct pci_bus *bus;
832bd858
DW		 4238 struct pci_dev *bridge = NULL;
4239 struct device *tmp;
318fe7df
SS		 4240 struct acpi_dmar_atsr *atsr;
4241 struct dmar_atsr_unit *atsru;
4242
4243 dev = pci_physfn(dev);
318fe7df 4244 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 4245 bridge = bus->self;
318fe7df 4246 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 4247 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 4248 return 0;
b5f82ddf 4249 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 4250 break;
318fe7df 4251 }
b5f82ddf
JL		 4252 if (!bridge)
4253 return 0;
318fe7df 4254
0e242612 4255 rcu_read_lock();
b5f82ddf
JL		 4256 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
4257 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4258 if (atsr->segment != pci_domain_nr(dev->bus))
4259 continue;
4260
b683b230 4261 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 4262 if (tmp == &bridge->dev)
b683b230 4263 goto out;
b5f82ddf
JL		 4264
4265 if (atsru->include_all)
b683b230 4266 goto out;
b5f82ddf 4267 }
b683b230
JL		 4268 ret = 0;
4269out:
0e242612 4270 rcu_read_unlock();
318fe7df 4271
b683b230 4272 return ret;
318fe7df
SS		 4273}
4274
59ce0515
JL		 4275int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
4276{
4277 int ret = 0;
4278 struct dmar_rmrr_unit *rmrru;
4279 struct dmar_atsr_unit *atsru;
4280 struct acpi_dmar_atsr *atsr;
4281 struct acpi_dmar_reserved_memory *rmrr;
4282
4283 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
4284 return 0;
4285
4286 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
4287 rmrr = container_of(rmrru->hdr,
4288 struct acpi_dmar_reserved_memory, header);
4289 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4290 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
4291 ((void *)rmrr) + rmrr->header.length,
4292 rmrr->segment, rmrru->devices,
4293 rmrru->devices_cnt);
27e24950 4294 if(ret < 0)
59ce0515
JL		 4295 return ret;
4296 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
27e24950
JL		 4297 dmar_remove_dev_scope(info, rmrr->segment,
4298 rmrru->devices, rmrru->devices_cnt);
59ce0515
JL		 4299 }
4300 }
4301
4302 list_for_each_entry(atsru, &dmar_atsr_units, list) {
4303 if (atsru->include_all)
4304 continue;
4305
4306 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
4307 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
4308 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
4309 (void *)atsr + atsr->header.length,
4310 atsr->segment, atsru->devices,
4311 atsru->devices_cnt);
4312 if (ret > 0)
4313 break;
4314 else if(ret < 0)
4315 return ret;
4316 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
4317 if (dmar_remove_dev_scope(info, atsr->segment,
4318 atsru->devices, atsru->devices_cnt))
4319 break;
4320 }
4321 }
4322
4323 return 0;
4324}
4325
99dcaded
FY		 4326/*
4327 * Here we only respond to action of unbound device from driver.
4328 *
4329 * Added device is not attached to its DMAR domain here yet. That will happen
4330 * when mapping the device to iova.
4331 */
4332static int device_notifier(struct notifier_block *nb,
4333 unsigned long action, void *data)
4334{
4335 struct device *dev = data;
99dcaded
FY		 4336 struct dmar_domain *domain;
4337
3d89194a 4338 if (iommu_dummy(dev))
44cd613c
DW		 4339 return 0;
4340
1196c2fb 4341 if (action != BUS_NOTIFY_REMOVED_DEVICE)
7e7dfab7
JL		 4342 return 0;
4343
1525a29a 4344 domain = find_domain(dev);
99dcaded
FY		 4345 if (!domain)
4346 return 0;
4347
3a5670e8 4348 down_read(&dmar_global_lock);
bf9c9eda 4349 domain_remove_one_dev_info(domain, dev);
ab8dfe25 4350 if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
7e7dfab7 4351 domain_exit(domain);
3a5670e8 4352 up_read(&dmar_global_lock);
a97590e5 4353
99dcaded
FY		 4354 return 0;
4355}
4356
4357static struct notifier_block device_nb = {
4358 .notifier_call = device_notifier,
4359};
4360
75f05569
JL		 4361static int intel_iommu_memory_notifier(struct notifier_block *nb,
4362 unsigned long val, void *v)
4363{
4364 struct memory_notify *mhp = v;
4365 unsigned long long start, end;
4366 unsigned long start_vpfn, last_vpfn;
4367
4368 switch (val) {
4369 case MEM_GOING_ONLINE:
4370 start = mhp->start_pfn << PAGE_SHIFT;
4371 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
4372 if (iommu_domain_identity_map(si_domain, start, end)) {
9f10e5bf 4373 pr_warn("Failed to build identity map for [%llx-%llx]\n",
75f05569
JL		 4374 start, end);
4375 return NOTIFY_BAD;
4376 }
4377 break;
4378
4379 case MEM_OFFLINE:
4380 case MEM_CANCEL_ONLINE:
4381 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
4382 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
4383 while (start_vpfn <= last_vpfn) {
4384 struct iova *iova;
4385 struct dmar_drhd_unit *drhd;
4386 struct intel_iommu *iommu;
ea8ea460 4387 struct page *freelist;
75f05569
JL		 4388
4389 iova = find_iova(&si_domain->iovad, start_vpfn);
4390 if (iova == NULL) {
9f10e5bf 4391 pr_debug("Failed get IOVA for PFN %lx\n",
75f05569
JL		 4392 start_vpfn);
4393 break;
4394 }
4395
4396 iova = split_and_remove_iova(&si_domain->iovad, iova,
4397 start_vpfn, last_vpfn);
4398 if (iova == NULL) {
9f10e5bf 4399 pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
75f05569
JL		 4400 start_vpfn, last_vpfn);
4401 return NOTIFY_BAD;
4402 }
4403
ea8ea460
DW		 4404 freelist = domain_unmap(si_domain, iova->pfn_lo,
4405 iova->pfn_hi);
4406
75f05569
JL		 4407 rcu_read_lock();
4408 for_each_active_iommu(iommu, drhd)
4409 iommu_flush_iotlb_psi(iommu, si_domain->id,
a156ef99 4410 iova->pfn_lo, iova_size(iova),
ea8ea460 4411 !freelist, 0);
75f05569 4412 rcu_read_unlock();
ea8ea460 4413 dma_free_pagelist(freelist);
75f05569
JL		 4414
4415 start_vpfn = iova->pfn_hi + 1;
4416 free_iova_mem(iova);
4417 }
4418 break;
4419 }
4420
4421 return NOTIFY_OK;
4422}
4423
4424static struct notifier_block intel_iommu_memory_nb = {
4425 .notifier_call = intel_iommu_memory_notifier,
4426 .priority = 0
4427};
4428
a5459cfe
AW		 4429
4430static ssize_t intel_iommu_show_version(struct device *dev,
4431 struct device_attribute *attr,
4432 char *buf)
4433{
4434 struct intel_iommu *iommu = dev_get_drvdata(dev);
4435 u32 ver = readl(iommu->reg + DMAR_VER_REG);
4436 return sprintf(buf, "%d:%d\n",
4437 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
4438}
4439static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
4440
4441static ssize_t intel_iommu_show_address(struct device *dev,
4442 struct device_attribute *attr,
4443 char *buf)
4444{
4445 struct intel_iommu *iommu = dev_get_drvdata(dev);
4446 return sprintf(buf, "%llx\n", iommu->reg_phys);
4447}
4448static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
4449
4450static ssize_t intel_iommu_show_cap(struct device *dev,
4451 struct device_attribute *attr,
4452 char *buf)
4453{
4454 struct intel_iommu *iommu = dev_get_drvdata(dev);
4455 return sprintf(buf, "%llx\n", iommu->cap);
4456}
4457static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
4458
4459static ssize_t intel_iommu_show_ecap(struct device *dev,
4460 struct device_attribute *attr,
4461 char *buf)
4462{
4463 struct intel_iommu *iommu = dev_get_drvdata(dev);
4464 return sprintf(buf, "%llx\n", iommu->ecap);
4465}
4466static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
4467
2238c082
AW		 4468static ssize_t intel_iommu_show_ndoms(struct device *dev,
4469 struct device_attribute *attr,
4470 char *buf)
4471{
4472 struct intel_iommu *iommu = dev_get_drvdata(dev);
4473 return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap));
4474}
4475static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL);
4476
4477static ssize_t intel_iommu_show_ndoms_used(struct device *dev,
4478 struct device_attribute *attr,
4479 char *buf)
4480{
4481 struct intel_iommu *iommu = dev_get_drvdata(dev);
4482 return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids,
4483 cap_ndoms(iommu->cap)));
4484}
4485static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL);
4486
a5459cfe
AW		 4487static struct attribute *intel_iommu_attrs[] = {
4488 &dev_attr_version.attr,
4489 &dev_attr_address.attr,
4490 &dev_attr_cap.attr,
4491 &dev_attr_ecap.attr,
2238c082
AW		 4492 &dev_attr_domains_supported.attr,
4493 &dev_attr_domains_used.attr,
a5459cfe
AW		 4494 NULL,
4495};
4496
4497static struct attribute_group intel_iommu_group = {
4498 .name = "intel-iommu",
4499 .attrs = intel_iommu_attrs,
4500};
4501
4502const struct attribute_group *intel_iommu_groups[] = {
4503 &intel_iommu_group,
4504 NULL,
4505};
4506
ba395927
KA		 4507int __init intel_iommu_init(void)
4508{
9bdc531e 4509 int ret = -ENODEV;
3a93c841 4510 struct dmar_drhd_unit *drhd;
7c919779 4511 struct intel_iommu *iommu;
ba395927 4512
a59b50e9
JC		 4513 /* VT-d is required for a TXT/tboot launch, so enforce that */
4514 force_on = tboot_force_iommu();
4515
3a5670e8
JL		 4516 if (iommu_init_mempool()) {
4517 if (force_on)
4518 panic("tboot: Failed to initialize iommu memory\n");
4519 return -ENOMEM;
4520 }
4521
4522 down_write(&dmar_global_lock);
a59b50e9
JC		 4523 if (dmar_table_init()) {
4524 if (force_on)
4525 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 4526 goto out_free_dmar;
a59b50e9 4527 }
ba395927 4528
c2c7286a 4529 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 4530 if (force_on)
4531 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 4532 goto out_free_dmar;
a59b50e9 4533 }
1886e8a9 4534
75f1cdf1 4535 if (no_iommu || dmar_disabled)
9bdc531e 4536 goto out_free_dmar;
2ae21010 4537
318fe7df 4538 if (list_empty(&dmar_rmrr_units))
9f10e5bf 4539 pr_info("No RMRR found\n");
318fe7df
SS		 4540
4541 if (list_empty(&dmar_atsr_units))
9f10e5bf 4542 pr_info("No ATSR found\n");
318fe7df 4543
51a63e67
JC		 4544 if (dmar_init_reserved_ranges()) {
4545 if (force_on)
4546 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 4547 goto out_free_reserved_range;
51a63e67 4548 }
ba395927
KA		 4549
4550 init_no_remapping_devices();
4551
b779260b 4552 ret = init_dmars();
ba395927 4553 if (ret) {
a59b50e9
JC		 4554 if (force_on)
4555 panic("tboot: Failed to initialize DMARs\n");
9f10e5bf 4556 pr_err("Initialization failed\n");
9bdc531e 4557 goto out_free_reserved_range;
ba395927 4558 }
3a5670e8 4559 up_write(&dmar_global_lock);
9f10e5bf 4560 pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
ba395927 4561
5e0d2a6f 4562 init_timer(&unmap_timer);
75f1cdf1
FT		 4563#ifdef CONFIG_SWIOTLB
4564 swiotlb = 0;
4565#endif
19943b0e 4566 dma_ops = &intel_dma_ops;
4ed0d3e6 4567
134fac3f 4568 init_iommu_pm_ops();
a8bcbb0d 4569
a5459cfe
AW		 4570 for_each_active_iommu(iommu, drhd)
4571 iommu->iommu_dev = iommu_device_create(NULL, iommu,
4572 intel_iommu_groups,
2439d4aa 4573 "%s", iommu->name);
a5459cfe 4574
4236d97d 4575 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 4576 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 4577 if (si_domain && !hw_pass_through)
4578 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 4579
8bc1f85c
ED		 4580 intel_iommu_enabled = 1;
4581
ba395927 4582 return 0;
9bdc531e
JL		 4583
4584out_free_reserved_range:
4585 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 4586out_free_dmar:
4587 intel_iommu_free_dmars();
3a5670e8
JL		 4588 up_write(&dmar_global_lock);
4589 iommu_exit_mempool();
9bdc531e 4590 return ret;
ba395927 4591}
e820482c 4592
579305f7
AW		 4593static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4594{
4595 struct intel_iommu *iommu = opaque;
4596
4597 iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4598 return 0;
4599}
4600
4601/*
4602 * NB - intel-iommu lacks any sort of reference counting for the users of
4603 * dependent devices. If multiple endpoints have intersecting dependent
4604 * devices, unbinding the driver from any one of them will possibly leave
4605 * the others unable to operate.
4606 */
3199aa6b 4607static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 4608 struct device *dev)
3199aa6b 4609{
0bcb3e28 4610 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 4611 return;
4612
579305f7 4613 pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu);
3199aa6b
HW		 4614}
4615
2c2e2c38 4616static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 4617 struct device *dev)
c7151a8d 4618{
bca2b916 4619 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4620 struct intel_iommu *iommu;
4621 unsigned long flags;
2f119c78 4622 bool found = false;
156baca8 4623 u8 bus, devfn;
c7151a8d 4624
bf9c9eda 4625 iommu = device_to_iommu(dev, &bus, &devfn);
c7151a8d
WH		 4626 if (!iommu)
4627 return;
4628
4629 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4630 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
bf9c9eda
DW		 4631 if (info->iommu == iommu && info->bus == bus &&
4632 info->devfn == devfn) {
109b9b04 4633 unlink_domain_info(info);
c7151a8d
WH		 4634 spin_unlock_irqrestore(&device_domain_lock, flags);
4635
93a23a72 4636 iommu_disable_dev_iotlb(info);
c7151a8d 4637 iommu_detach_dev(iommu, info->bus, info->devfn);
bf9c9eda 4638 iommu_detach_dependent_devices(iommu, dev);
c7151a8d
WH		 4639 free_devinfo_mem(info);
4640
4641 spin_lock_irqsave(&device_domain_lock, flags);
4642
4643 if (found)
4644 break;
4645 else
4646 continue;
4647 }
4648
4649 /* if there is no other devices under the same iommu
4650 * owned by this domain, clear this iommu in iommu_bmp
4651 * update iommu count and coherency
4652 */
8bbc4410 4653 if (info->iommu == iommu)
2f119c78 4654 found = true;
c7151a8d
WH		 4655 }
4656
3e7abe25
RD		 4657 spin_unlock_irqrestore(&device_domain_lock, flags);
4658
c7151a8d 4659 if (found == 0) {
fb170fb4
JL		 4660 domain_detach_iommu(domain, iommu);
4661 if (!domain_type_is_vm_or_si(domain))
4662 iommu_detach_domain(domain, iommu);
c7151a8d 4663 }
c7151a8d
WH		 4664}
4665
2c2e2c38 4666static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4667{
4668 int adjust_width;
4669
0fb5fe87
RM		 4670 init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
4671 DMA_32BIT_PFN);
5e98c4b1
WH		 4672 domain_reserve_special_ranges(domain);
4673
4674 /* calculate AGAW */
4675 domain->gaw = guest_width;
4676 adjust_width = guestwidth_to_adjustwidth(guest_width);
4677 domain->agaw = width_to_agaw(adjust_width);
4678
5e98c4b1 4679 domain->iommu_coherency = 0;
c5b15255 4680 domain->iommu_snooping = 0;
6dd9a7c7 4681 domain->iommu_superpage = 0;
fe40f1e0 4682 domain->max_addr = 0;
5e98c4b1
WH		 4683
4684 /* always allocate the top pgd */
4c923d47 4685 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4686 if (!domain->pgd)
4687 return -ENOMEM;
4688 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4689 return 0;
4690}
4691
00a77deb 4692static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
38717946 4693{
5d450806 4694 struct dmar_domain *dmar_domain;
00a77deb
JR		 4695 struct iommu_domain *domain;
4696
4697 if (type != IOMMU_DOMAIN_UNMANAGED)
4698 return NULL;
38717946 4699
ab8dfe25 4700 dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
5d450806 4701 if (!dmar_domain) {
9f10e5bf 4702 pr_err("Can't allocate dmar_domain\n");
00a77deb 4703 return NULL;
38717946 4704 }
2c2e2c38 4705 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
9f10e5bf 4706 pr_err("Domain initialization failed\n");
92d03cc8 4707 domain_exit(dmar_domain);
00a77deb 4708 return NULL;
38717946 4709 }
8140a95d 4710 domain_update_iommu_cap(dmar_domain);
faa3d6f5 4711
00a77deb 4712 domain = &dmar_domain->domain;
8a0e715b
JR		 4713 domain->geometry.aperture_start = 0;
4714 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4715 domain->geometry.force_aperture = true;
4716
00a77deb 4717 return domain;
38717946 4718}
38717946 4719
00a77deb 4720static void intel_iommu_domain_free(struct iommu_domain *domain)
38717946 4721{
00a77deb 4722 domain_exit(to_dmar_domain(domain));
38717946 4723}
38717946 4724
4c5478c9
JR		 4725static int intel_iommu_attach_device(struct iommu_domain *domain,
4726 struct device *dev)
38717946 4727{
00a77deb 4728 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
fe40f1e0
WH		 4729 struct intel_iommu *iommu;
4730 int addr_width;
156baca8 4731 u8 bus, devfn;
faa3d6f5 4732
c875d2c1
AW		 4733 if (device_is_rmrr_locked(dev)) {
4734 dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n");
4735 return -EPERM;
4736 }
4737
7207d8f9
DW		 4738 /* normally dev is not mapped */
4739 if (unlikely(domain_context_mapped(dev))) {
faa3d6f5
WH		 4740 struct dmar_domain *old_domain;
4741
1525a29a 4742 old_domain = find_domain(dev);
faa3d6f5 4743 if (old_domain) {
ab8dfe25 4744 if (domain_type_is_vm_or_si(dmar_domain))
bf9c9eda 4745 domain_remove_one_dev_info(old_domain, dev);
faa3d6f5
WH		 4746 else
4747 domain_remove_dev_info(old_domain);
62c22167
JR		 4748
4749 if (!domain_type_is_vm_or_si(old_domain) &&
4750 list_empty(&old_domain->devices))
4751 domain_exit(old_domain);
faa3d6f5
WH		 4752 }
4753 }
4754
156baca8 4755 iommu = device_to_iommu(dev, &bus, &devfn);
fe40f1e0
WH		 4756 if (!iommu)
4757 return -ENODEV;
4758
4759 /* check if this iommu agaw is sufficient for max mapped address */
4760 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4761 if (addr_width > cap_mgaw(iommu->cap))
4762 addr_width = cap_mgaw(iommu->cap);
4763
4764 if (dmar_domain->max_addr > (1LL << addr_width)) {
9f10e5bf 4765 pr_err("%s: iommu width (%d) is not "
fe40f1e0 4766 "sufficient for the mapped address (%llx)\n",
a99c47a2 4767 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4768 return -EFAULT;
4769 }
a99c47a2
TL		 4770 dmar_domain->gaw = addr_width;
4771
4772 /*
4773 * Knock out extra levels of page tables if necessary
4774 */
4775 while (iommu->agaw < dmar_domain->agaw) {
4776 struct dma_pte *pte;
4777
4778 pte = dmar_domain->pgd;
4779 if (dma_pte_present(pte)) {
25cbff16
SY		 4780 dmar_domain->pgd = (struct dma_pte *)
4781 phys_to_virt(dma_pte_addr(pte));
7a661013 4782 free_pgtable_page(pte);
a99c47a2
TL		 4783 }
4784 dmar_domain->agaw--;
4785 }
fe40f1e0 4786
5913c9bf 4787 return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
38717946 4788}
38717946 4789
4c5478c9
JR		 4790static void intel_iommu_detach_device(struct iommu_domain *domain,
4791 struct device *dev)
38717946 4792{
00a77deb 4793 domain_remove_one_dev_info(to_dmar_domain(domain), dev);
faa3d6f5 4794}
c7151a8d 4795
b146a1c9
JR		 4796static int intel_iommu_map(struct iommu_domain *domain,
4797 unsigned long iova, phys_addr_t hpa,
5009065d 4798 size_t size, int iommu_prot)
faa3d6f5 4799{
00a77deb 4800 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
fe40f1e0 4801 u64 max_addr;
dde57a21 4802 int prot = 0;
faa3d6f5 4803 int ret;
fe40f1e0 4804
dde57a21
JR		 4805 if (iommu_prot & IOMMU_READ)
4806 prot |= DMA_PTE_READ;
4807 if (iommu_prot & IOMMU_WRITE)
4808 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4809 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4810 prot |= DMA_PTE_SNP;
dde57a21 4811
163cc52c 4812 max_addr = iova + size;
dde57a21 4813 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4814 u64 end;
4815
4816 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4817 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4818 if (end < max_addr) {
9f10e5bf 4819 pr_err("%s: iommu width (%d) is not "
fe40f1e0 4820 "sufficient for the mapped address (%llx)\n",
8954da1f 4821 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4822 return -EFAULT;
4823 }
dde57a21 4824 dmar_domain->max_addr = max_addr;
fe40f1e0 4825 }
ad051221
DW		 4826 /* Round up size to next multiple of PAGE_SIZE, if it and
4827 the low bits of hpa would take us onto the next page */
88cb6a74 4828 size = aligned_nrpages(hpa, size);
ad051221
DW		 4829 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4830 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4831 return ret;
38717946 4832}
38717946 4833
5009065d 4834static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4835 unsigned long iova, size_t size)
38717946 4836{
00a77deb 4837 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
ea8ea460
DW		 4838 struct page *freelist = NULL;
4839 struct intel_iommu *iommu;
4840 unsigned long start_pfn, last_pfn;
4841 unsigned int npages;
4842 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4843
4844 /* Cope with horrid API which requires us to unmap more than the
4845 size argument if it happens to be a large-page mapping. */
4846 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4847 BUG();
4848
4849 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4850 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4851
ea8ea460
DW		 4852 start_pfn = iova >> VTD_PAGE_SHIFT;
4853 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4854
4855 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4856
4857 npages = last_pfn - start_pfn + 1;
4858
4859 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4860 iommu = g_iommus[iommu_id];
4861
4862 /*
4863 * find bit position of dmar_domain
4864 */
4865 ndomains = cap_ndoms(iommu->cap);
4866 for_each_set_bit(num, iommu->domain_ids, ndomains) {
9452d5bf 4867 if (get_iommu_domain(iommu, num) == dmar_domain)
ea8ea460
DW		 4868 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4869 npages, !freelist, 0);
4870 }
4871
4872 }
4873
4874 dma_free_pagelist(freelist);
fe40f1e0 4875
163cc52c
DW		 4876 if (dmar_domain->max_addr == iova + size)
4877 dmar_domain->max_addr = iova;
b146a1c9 4878
5cf0a76f 4879 return size;
38717946 4880}
38717946 4881
d14d6577 4882static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4883 dma_addr_t iova)
38717946 4884{
00a77deb 4885 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
38717946 4886 struct dma_pte *pte;
5cf0a76f 4887 int level = 0;
faa3d6f5 4888 u64 phys = 0;
38717946 4889
5cf0a76f 4890 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4891 if (pte)
faa3d6f5 4892 phys = dma_pte_addr(pte);
38717946 4893
faa3d6f5 4894 return phys;
38717946 4895}
a8bcbb0d 4896
5d587b8d 4897static bool intel_iommu_capable(enum iommu_cap cap)
dbb9fd86 4898{
dbb9fd86 4899 if (cap == IOMMU_CAP_CACHE_COHERENCY)
5d587b8d 4900 return domain_update_iommu_snooping(NULL) == 1;
323f99cb 4901 if (cap == IOMMU_CAP_INTR_REMAP)
5d587b8d 4902 return irq_remapping_enabled == 1;
dbb9fd86 4903
5d587b8d 4904 return false;
dbb9fd86
SY		 4905}
4906
abdfdde2
AW		 4907static int intel_iommu_add_device(struct device *dev)
4908{
a5459cfe 4909 struct intel_iommu *iommu;
abdfdde2 4910 struct iommu_group *group;
156baca8 4911 u8 bus, devfn;
70ae6f0d 4912
a5459cfe
AW		 4913 iommu = device_to_iommu(dev, &bus, &devfn);
4914 if (!iommu)
70ae6f0d
AW		 4915 return -ENODEV;
4916
a5459cfe 4917 iommu_device_link(iommu->iommu_dev, dev);
a4ff1fc2 4918
e17f9ff4 4919 group = iommu_group_get_for_dev(dev);
783f157b 4920
e17f9ff4
AW		 4921 if (IS_ERR(group))
4922 return PTR_ERR(group);
bcb71abe 4923
abdfdde2 4924 iommu_group_put(group);
e17f9ff4 4925 return 0;
abdfdde2 4926}
70ae6f0d 4927
abdfdde2
AW		 4928static void intel_iommu_remove_device(struct device *dev)
4929{
a5459cfe
AW		 4930 struct intel_iommu *iommu;
4931 u8 bus, devfn;
4932
4933 iommu = device_to_iommu(dev, &bus, &devfn);
4934 if (!iommu)
4935 return;
4936
abdfdde2 4937 iommu_group_remove_device(dev);
a5459cfe
AW		 4938
4939 iommu_device_unlink(iommu->iommu_dev, dev);
70ae6f0d
AW		 4940}
4941
b22f6434 4942static const struct iommu_ops intel_iommu_ops = {
5d587b8d 4943 .capable = intel_iommu_capable,
00a77deb
JR		 4944 .domain_alloc = intel_iommu_domain_alloc,
4945 .domain_free = intel_iommu_domain_free,
a8bcbb0d
JR		 4946 .attach_dev = intel_iommu_attach_device,
4947 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4948 .map = intel_iommu_map,
4949 .unmap = intel_iommu_unmap,
315786eb 4950 .map_sg = default_iommu_map_sg,
a8bcbb0d 4951 .iova_to_phys = intel_iommu_iova_to_phys,
abdfdde2
AW		 4952 .add_device = intel_iommu_add_device,
4953 .remove_device = intel_iommu_remove_device,
6d1c56a9 4954 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4955};
9af88143 4956
9452618e
DV		 4957static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4958{
4959 /* G4x/GM45 integrated gfx dmar support is totally busted. */
9f10e5bf 4960 pr_info("Disabling IOMMU for graphics on this chipset\n");
9452618e
DV		 4961 dmar_map_gfx = 0;
4962}
4963
4964DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4965DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4969DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4970DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4971
d34d6517 4972static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4973{
4974 /*
4975 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4976 * but needs it. Same seems to hold for the desktop versions.
9af88143 4977 */
9f10e5bf 4978 pr_info("Forcing write-buffer flush capability\n");
9af88143
DW		 4979 rwbf_quirk = 1;
4980}
4981
4982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4983DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4984DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4989
eecfd57f
AJ		 4990#define GGC 0x52
4991#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4992#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4993#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4994#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4995#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4996#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4997#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4998#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4999
d34d6517 5000static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 5001{
5002 unsigned short ggc;
5003
eecfd57f 5004 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 5005 return;
5006
eecfd57f 5007 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9f10e5bf 5008 pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
9eecabcb 5009 dmar_map_gfx = 0;
6fbcfb3e
DW		 5010 } else if (dmar_map_gfx) {
5011 /* we have to ensure the gfx device is idle before we flush */
9f10e5bf 5012 pr_info("Disabling batched IOTLB flush on Ironlake\n");
6fbcfb3e
DW		 5013 intel_iommu_strict = 1;
5014 }
9eecabcb
DW		 5015}
5016DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
5017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
5018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
5019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
5020
e0fc7e0b
DW		 5021/* On Tylersburg chipsets, some BIOSes have been known to enable the
5022 ISOCH DMAR unit for the Azalia sound device, but not give it any
5023 TLB entries, which causes it to deadlock. Check for that. We do
5024 this in a function called from init_dmars(), instead of in a PCI
5025 quirk, because we don't want to print the obnoxious "BIOS broken"
5026 message if VT-d is actually disabled.
5027*/
5028static void __init check_tylersburg_isoch(void)
5029{
5030 struct pci_dev *pdev;
5031 uint32_t vtisochctrl;
5032
5033 /* If there's no Azalia in the system anyway, forget it. */
5034 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
5035 if (!pdev)
5036 return;
5037 pci_dev_put(pdev);
5038
5039 /* System Management Registers. Might be hidden, in which case
5040 we can't do the sanity check. But that's OK, because the
5041 known-broken BIOSes _don't_ actually hide it, so far. */
5042 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
5043 if (!pdev)
5044 return;
5045
5046 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
5047 pci_dev_put(pdev);
5048 return;
5049 }
5050
5051 pci_dev_put(pdev);
5052
5053 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
5054 if (vtisochctrl & 1)
5055 return;
5056
5057 /* Drop all bits other than the number of TLB entries */
5058 vtisochctrl &= 0x1c;
5059
5060 /* If we have the recommended number of TLB entries (16), fine. */
5061 if (vtisochctrl == 0x10)
5062 return;
5063
5064 /* Zero TLB entries? You get to ride the short bus to school. */
5065 if (!vtisochctrl) {
5066 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
5067 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
5068 dmi_get_system_info(DMI_BIOS_VENDOR),
5069 dmi_get_system_info(DMI_BIOS_VERSION),
5070 dmi_get_system_info(DMI_PRODUCT_VERSION));
5071 iommu_identity_mapping |= IDENTMAP_AZALIA;
5072 return;
5073 }
9f10e5bf
JR		 5074
5075 pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
e0fc7e0b
DW		 5076 vtisochctrl);
5077}
Linux kernel - Deliverables
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