Commit | Line | Data |
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8a94ade4 DW |
1 | /* |
2 | * Copyright © 2015 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * Authors: David Woodhouse <dwmw2@infradead.org> | |
14 | */ | |
15 | ||
16 | #include <linux/intel-iommu.h> | |
2f26e0a9 DW |
17 | #include <linux/mmu_notifier.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/intel-svm.h> | |
21 | #include <linux/rculist.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/pci-ats.h> | |
a222a7f0 DW |
24 | #include <linux/dmar.h> |
25 | #include <linux/interrupt.h> | |
26 | ||
27 | static irqreturn_t prq_event_thread(int irq, void *d); | |
2f26e0a9 DW |
28 | |
29 | struct pasid_entry { | |
30 | u64 val; | |
31 | }; | |
8a94ade4 | 32 | |
907fea34 DW |
33 | struct pasid_state_entry { |
34 | u64 val; | |
35 | }; | |
36 | ||
8a94ade4 DW |
37 | int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) |
38 | { | |
39 | struct page *pages; | |
40 | int order; | |
41 | ||
42 | order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; | |
43 | if (order < 0) | |
44 | order = 0; | |
45 | ||
46 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); | |
47 | if (!pages) { | |
48 | pr_warn("IOMMU: %s: Failed to allocate PASID table\n", | |
49 | iommu->name); | |
50 | return -ENOMEM; | |
51 | } | |
52 | iommu->pasid_table = page_address(pages); | |
53 | pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order); | |
54 | ||
55 | if (ecap_dis(iommu->ecap)) { | |
56 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); | |
57 | if (pages) | |
58 | iommu->pasid_state_table = page_address(pages); | |
59 | else | |
60 | pr_warn("IOMMU: %s: Failed to allocate PASID state table\n", | |
61 | iommu->name); | |
62 | } | |
63 | ||
2f26e0a9 DW |
64 | idr_init(&iommu->pasid_idr); |
65 | ||
8a94ade4 DW |
66 | return 0; |
67 | } | |
68 | ||
69 | int intel_svm_free_pasid_tables(struct intel_iommu *iommu) | |
70 | { | |
71 | int order; | |
72 | ||
73 | order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; | |
74 | if (order < 0) | |
75 | order = 0; | |
76 | ||
77 | if (iommu->pasid_table) { | |
78 | free_pages((unsigned long)iommu->pasid_table, order); | |
79 | iommu->pasid_table = NULL; | |
80 | } | |
81 | if (iommu->pasid_state_table) { | |
82 | free_pages((unsigned long)iommu->pasid_state_table, order); | |
83 | iommu->pasid_state_table = NULL; | |
84 | } | |
2f26e0a9 | 85 | idr_destroy(&iommu->pasid_idr); |
8a94ade4 DW |
86 | return 0; |
87 | } | |
2f26e0a9 | 88 | |
a222a7f0 DW |
89 | #define PRQ_ORDER 0 |
90 | ||
91 | int intel_svm_enable_prq(struct intel_iommu *iommu) | |
92 | { | |
93 | struct page *pages; | |
94 | int irq, ret; | |
95 | ||
96 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER); | |
97 | if (!pages) { | |
98 | pr_warn("IOMMU: %s: Failed to allocate page request queue\n", | |
99 | iommu->name); | |
100 | return -ENOMEM; | |
101 | } | |
102 | iommu->prq = page_address(pages); | |
103 | ||
104 | irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu); | |
105 | if (irq <= 0) { | |
106 | pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n", | |
107 | iommu->name); | |
108 | ret = -EINVAL; | |
109 | err: | |
110 | free_pages((unsigned long)iommu->prq, PRQ_ORDER); | |
111 | iommu->prq = NULL; | |
112 | return ret; | |
113 | } | |
114 | iommu->pr_irq = irq; | |
115 | ||
116 | snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id); | |
117 | ||
118 | ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT, | |
119 | iommu->prq_name, iommu); | |
120 | if (ret) { | |
121 | pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n", | |
122 | iommu->name); | |
123 | dmar_free_hwirq(irq); | |
124 | goto err; | |
125 | } | |
126 | dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); | |
127 | dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); | |
128 | dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | int intel_svm_finish_prq(struct intel_iommu *iommu) | |
134 | { | |
135 | dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); | |
136 | dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); | |
137 | dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); | |
138 | ||
139 | free_irq(iommu->pr_irq, iommu); | |
140 | dmar_free_hwirq(iommu->pr_irq); | |
141 | iommu->pr_irq = 0; | |
142 | ||
143 | free_pages((unsigned long)iommu->prq, PRQ_ORDER); | |
144 | iommu->prq = NULL; | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
2f26e0a9 | 149 | static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev, |
5d52f482 | 150 | unsigned long address, unsigned long pages, int ih, int gl) |
2f26e0a9 DW |
151 | { |
152 | struct qi_desc desc; | |
2f26e0a9 | 153 | |
5d52f482 | 154 | if (pages == -1) { |
e0349921 DW |
155 | /* For global kernel pages we have to flush them in *all* PASIDs |
156 | * because that's the only option the hardware gives us. Despite | |
157 | * the fact that they are actually only accessible through one. */ | |
158 | if (gl) | |
159 | desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | | |
160 | QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE; | |
161 | else | |
162 | desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | | |
163 | QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE; | |
2f26e0a9 DW |
164 | desc.high = 0; |
165 | } else { | |
5d52f482 DW |
166 | int mask = ilog2(__roundup_pow_of_two(pages)); |
167 | ||
2f26e0a9 DW |
168 | desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | |
169 | QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE; | |
e0349921 | 170 | desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) | |
2f26e0a9 DW |
171 | QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask); |
172 | } | |
2f26e0a9 DW |
173 | qi_submit_sync(&desc, svm->iommu); |
174 | ||
175 | if (sdev->dev_iotlb) { | |
176 | desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) | | |
177 | QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE; | |
5d52f482 DW |
178 | if (pages == -1) { |
179 | desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE; | |
180 | } else if (pages > 1) { | |
181 | /* The least significant zero bit indicates the size. So, | |
182 | * for example, an "address" value of 0x12345f000 will | |
183 | * flush from 0x123440000 to 0x12347ffff (256KiB). */ | |
184 | unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT); | |
185 | unsigned long mask = __rounddown_pow_of_two(address ^ last);; | |
186 | ||
187 | desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE; | |
2f26e0a9 DW |
188 | } else { |
189 | desc.high = QI_DEV_EIOTLB_ADDR(address); | |
190 | } | |
191 | qi_submit_sync(&desc, svm->iommu); | |
192 | } | |
193 | } | |
194 | ||
195 | static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address, | |
5d52f482 | 196 | unsigned long pages, int ih, int gl) |
2f26e0a9 DW |
197 | { |
198 | struct intel_svm_dev *sdev; | |
199 | ||
907fea34 DW |
200 | /* Try deferred invalidate if available */ |
201 | if (svm->iommu->pasid_state_table && | |
202 | !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63)) | |
203 | return; | |
204 | ||
2f26e0a9 DW |
205 | rcu_read_lock(); |
206 | list_for_each_entry_rcu(sdev, &svm->devs, list) | |
e0349921 | 207 | intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl); |
2f26e0a9 DW |
208 | rcu_read_unlock(); |
209 | } | |
210 | ||
211 | static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm, | |
212 | unsigned long address, pte_t pte) | |
213 | { | |
214 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
215 | ||
e0349921 | 216 | intel_flush_svm_range(svm, address, 1, 1, 0); |
2f26e0a9 DW |
217 | } |
218 | ||
219 | static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm, | |
220 | unsigned long address) | |
221 | { | |
222 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
223 | ||
e0349921 | 224 | intel_flush_svm_range(svm, address, 1, 1, 0); |
2f26e0a9 DW |
225 | } |
226 | ||
227 | /* Pages have been freed at this point */ | |
228 | static void intel_invalidate_range(struct mmu_notifier *mn, | |
229 | struct mm_struct *mm, | |
230 | unsigned long start, unsigned long end) | |
231 | { | |
232 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
233 | ||
234 | intel_flush_svm_range(svm, start, | |
e0349921 | 235 | (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0); |
2f26e0a9 DW |
236 | } |
237 | ||
238 | ||
5a10ba27 | 239 | static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid) |
2f26e0a9 DW |
240 | { |
241 | struct qi_desc desc; | |
242 | ||
243 | desc.high = 0; | |
5a10ba27 | 244 | desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid); |
2f26e0a9 DW |
245 | |
246 | qi_submit_sync(&desc, svm->iommu); | |
247 | } | |
248 | ||
249 | static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) | |
250 | { | |
251 | struct intel_svm *svm = container_of(mn, struct intel_svm, notifier); | |
252 | ||
253 | svm->iommu->pasid_table[svm->pasid].val = 0; | |
254 | ||
255 | /* There's no need to do any flush because we can't get here if there | |
256 | * are any devices left anyway. */ | |
257 | WARN_ON(!list_empty(&svm->devs)); | |
258 | } | |
259 | ||
260 | static const struct mmu_notifier_ops intel_mmuops = { | |
261 | .release = intel_mm_release, | |
262 | .change_pte = intel_change_pte, | |
263 | .invalidate_page = intel_invalidate_page, | |
264 | .invalidate_range = intel_invalidate_range, | |
265 | }; | |
266 | ||
267 | static DEFINE_MUTEX(pasid_mutex); | |
268 | ||
0204a496 | 269 | int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops) |
2f26e0a9 DW |
270 | { |
271 | struct intel_iommu *iommu = intel_svm_device_to_iommu(dev); | |
272 | struct intel_svm_dev *sdev; | |
273 | struct intel_svm *svm = NULL; | |
5cec7537 | 274 | struct mm_struct *mm = NULL; |
2f26e0a9 DW |
275 | int pasid_max; |
276 | int ret; | |
277 | ||
2f26e0a9 DW |
278 | if (WARN_ON(!iommu)) |
279 | return -EINVAL; | |
280 | ||
281 | if (dev_is_pci(dev)) { | |
282 | pasid_max = pci_max_pasids(to_pci_dev(dev)); | |
283 | if (pasid_max < 0) | |
284 | return -EINVAL; | |
285 | } else | |
286 | pasid_max = 1 << 20; | |
287 | ||
5cec7537 DW |
288 | if ((flags & SVM_FLAG_SUPERVISOR_MODE)) { |
289 | if (!ecap_srs(iommu->ecap)) | |
290 | return -EINVAL; | |
291 | } else if (pasid) { | |
292 | mm = get_task_mm(current); | |
293 | BUG_ON(!mm); | |
294 | } | |
295 | ||
2f26e0a9 | 296 | mutex_lock(&pasid_mutex); |
569e4f77 | 297 | if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) { |
2f26e0a9 DW |
298 | int i; |
299 | ||
300 | idr_for_each_entry(&iommu->pasid_idr, svm, i) { | |
5cec7537 | 301 | if (svm->mm != mm || |
569e4f77 | 302 | (svm->flags & SVM_FLAG_PRIVATE_PASID)) |
2f26e0a9 DW |
303 | continue; |
304 | ||
305 | if (svm->pasid >= pasid_max) { | |
306 | dev_warn(dev, | |
307 | "Limited PASID width. Cannot use existing PASID %d\n", | |
308 | svm->pasid); | |
309 | ret = -ENOSPC; | |
310 | goto out; | |
311 | } | |
312 | ||
313 | list_for_each_entry(sdev, &svm->devs, list) { | |
314 | if (dev == sdev->dev) { | |
0204a496 DW |
315 | if (sdev->ops != ops) { |
316 | ret = -EBUSY; | |
317 | goto out; | |
318 | } | |
2f26e0a9 DW |
319 | sdev->users++; |
320 | goto success; | |
321 | } | |
322 | } | |
323 | ||
324 | break; | |
325 | } | |
326 | } | |
327 | ||
328 | sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); | |
329 | if (!sdev) { | |
330 | ret = -ENOMEM; | |
331 | goto out; | |
332 | } | |
333 | sdev->dev = dev; | |
334 | ||
335 | ret = intel_iommu_enable_pasid(iommu, sdev); | |
336 | if (ret || !pasid) { | |
337 | /* If they don't actually want to assign a PASID, this is | |
338 | * just an enabling check/preparation. */ | |
339 | kfree(sdev); | |
340 | goto out; | |
341 | } | |
342 | /* Finish the setup now we know we're keeping it */ | |
343 | sdev->users = 1; | |
0204a496 | 344 | sdev->ops = ops; |
2f26e0a9 DW |
345 | init_rcu_head(&sdev->rcu); |
346 | ||
347 | if (!svm) { | |
348 | svm = kzalloc(sizeof(*svm), GFP_KERNEL); | |
349 | if (!svm) { | |
350 | ret = -ENOMEM; | |
351 | kfree(sdev); | |
352 | goto out; | |
353 | } | |
354 | svm->iommu = iommu; | |
355 | ||
356 | if (pasid_max > 2 << ecap_pss(iommu->ecap)) | |
357 | pasid_max = 2 << ecap_pss(iommu->ecap); | |
358 | ||
5a10ba27 DW |
359 | /* Do not use PASID 0 in caching mode (virtualised IOMMU) */ |
360 | ret = idr_alloc(&iommu->pasid_idr, svm, | |
361 | !!cap_caching_mode(iommu->cap), | |
362 | pasid_max - 1, GFP_KERNEL); | |
2f26e0a9 DW |
363 | if (ret < 0) { |
364 | kfree(svm); | |
365 | goto out; | |
366 | } | |
367 | svm->pasid = ret; | |
368 | svm->notifier.ops = &intel_mmuops; | |
5cec7537 | 369 | svm->mm = mm; |
569e4f77 | 370 | svm->flags = flags; |
2f26e0a9 DW |
371 | INIT_LIST_HEAD_RCU(&svm->devs); |
372 | ret = -ENOMEM; | |
5cec7537 DW |
373 | if (mm) { |
374 | ret = mmu_notifier_register(&svm->notifier, mm); | |
375 | if (ret) { | |
376 | idr_remove(&svm->iommu->pasid_idr, svm->pasid); | |
377 | kfree(svm); | |
378 | kfree(sdev); | |
379 | goto out; | |
380 | } | |
381 | iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1; | |
382 | mm = NULL; | |
383 | } else | |
384 | iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11); | |
2f26e0a9 | 385 | wmb(); |
5a10ba27 DW |
386 | /* In caching mode, we still have to flush with PASID 0 when |
387 | * a PASID table entry becomes present. Not entirely clear | |
388 | * *why* that would be the case — surely we could just issue | |
389 | * a flush with the PASID value that we've changed? The PASID | |
390 | * is the index into the table, after all. It's not like domain | |
391 | * IDs in the case of the equivalent context-entry change in | |
392 | * caching mode. And for that matter it's not entirely clear why | |
393 | * a VMM would be in the business of caching the PASID table | |
394 | * anyway. Surely that can be left entirely to the guest? */ | |
395 | if (cap_caching_mode(iommu->cap)) | |
396 | intel_flush_pasid_dev(svm, sdev, 0); | |
2f26e0a9 DW |
397 | } |
398 | list_add_rcu(&sdev->list, &svm->devs); | |
399 | ||
400 | success: | |
401 | *pasid = svm->pasid; | |
402 | ret = 0; | |
403 | out: | |
404 | mutex_unlock(&pasid_mutex); | |
5cec7537 DW |
405 | if (mm) |
406 | mmput(mm); | |
2f26e0a9 DW |
407 | return ret; |
408 | } | |
409 | EXPORT_SYMBOL_GPL(intel_svm_bind_mm); | |
410 | ||
411 | int intel_svm_unbind_mm(struct device *dev, int pasid) | |
412 | { | |
413 | struct intel_svm_dev *sdev; | |
414 | struct intel_iommu *iommu; | |
415 | struct intel_svm *svm; | |
416 | int ret = -EINVAL; | |
417 | ||
418 | mutex_lock(&pasid_mutex); | |
419 | iommu = intel_svm_device_to_iommu(dev); | |
420 | if (!iommu || !iommu->pasid_table) | |
421 | goto out; | |
422 | ||
423 | svm = idr_find(&iommu->pasid_idr, pasid); | |
424 | if (!svm) | |
425 | goto out; | |
426 | ||
427 | list_for_each_entry(sdev, &svm->devs, list) { | |
428 | if (dev == sdev->dev) { | |
429 | ret = 0; | |
430 | sdev->users--; | |
431 | if (!sdev->users) { | |
432 | list_del_rcu(&sdev->list); | |
433 | /* Flush the PASID cache and IOTLB for this device. | |
434 | * Note that we do depend on the hardware *not* using | |
435 | * the PASID any more. Just as we depend on other | |
436 | * devices never using PASIDs that they have no right | |
437 | * to use. We have a *shared* PASID table, because it's | |
438 | * large and has to be physically contiguous. So it's | |
439 | * hard to be as defensive as we might like. */ | |
5a10ba27 | 440 | intel_flush_pasid_dev(svm, sdev, svm->pasid); |
e0349921 | 441 | intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm); |
2f26e0a9 DW |
442 | kfree_rcu(sdev, rcu); |
443 | ||
444 | if (list_empty(&svm->devs)) { | |
445 | mmu_notifier_unregister(&svm->notifier, svm->mm); | |
446 | ||
447 | idr_remove(&svm->iommu->pasid_idr, svm->pasid); | |
5cec7537 DW |
448 | if (svm->mm) |
449 | mmput(svm->mm); | |
2f26e0a9 DW |
450 | /* We mandate that no page faults may be outstanding |
451 | * for the PASID when intel_svm_unbind_mm() is called. | |
452 | * If that is not obeyed, subtle errors will happen. | |
453 | * Let's make them less subtle... */ | |
454 | memset(svm, 0x6b, sizeof(*svm)); | |
455 | kfree(svm); | |
456 | } | |
457 | } | |
458 | break; | |
459 | } | |
460 | } | |
461 | out: | |
462 | mutex_unlock(&pasid_mutex); | |
463 | ||
464 | return ret; | |
465 | } | |
466 | EXPORT_SYMBOL_GPL(intel_svm_unbind_mm); | |
a222a7f0 DW |
467 | |
468 | /* Page request queue descriptor */ | |
469 | struct page_req_dsc { | |
470 | u64 srr:1; | |
471 | u64 bof:1; | |
472 | u64 pasid_present:1; | |
473 | u64 lpig:1; | |
474 | u64 pasid:20; | |
475 | u64 bus:8; | |
476 | u64 private:23; | |
477 | u64 prg_index:9; | |
478 | u64 rd_req:1; | |
479 | u64 wr_req:1; | |
480 | u64 exe_req:1; | |
481 | u64 priv_req:1; | |
482 | u64 devfn:8; | |
483 | u64 addr:52; | |
484 | }; | |
485 | ||
486 | #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10) | |
487 | static irqreturn_t prq_event_thread(int irq, void *d) | |
488 | { | |
489 | struct intel_iommu *iommu = d; | |
490 | struct intel_svm *svm = NULL; | |
491 | int head, tail, handled = 0; | |
492 | ||
493 | tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; | |
494 | head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; | |
495 | while (head != tail) { | |
0204a496 | 496 | struct intel_svm_dev *sdev; |
a222a7f0 DW |
497 | struct vm_area_struct *vma; |
498 | struct page_req_dsc *req; | |
499 | struct qi_desc resp; | |
500 | int ret, result; | |
501 | u64 address; | |
502 | ||
503 | handled = 1; | |
504 | ||
505 | req = &iommu->prq[head / sizeof(*req)]; | |
506 | ||
507 | result = QI_RESP_FAILURE; | |
7f92a2e9 | 508 | address = (u64)req->addr << VTD_PAGE_SHIFT; |
a222a7f0 DW |
509 | if (!req->pasid_present) { |
510 | pr_err("%s: Page request without PASID: %08llx %08llx\n", | |
511 | iommu->name, ((unsigned long long *)req)[0], | |
512 | ((unsigned long long *)req)[1]); | |
513 | goto bad_req; | |
514 | } | |
515 | ||
516 | if (!svm || svm->pasid != req->pasid) { | |
517 | rcu_read_lock(); | |
518 | svm = idr_find(&iommu->pasid_idr, req->pasid); | |
519 | /* It *can't* go away, because the driver is not permitted | |
520 | * to unbind the mm while any page faults are outstanding. | |
521 | * So we only need RCU to protect the internal idr code. */ | |
522 | rcu_read_unlock(); | |
523 | ||
524 | if (!svm) { | |
525 | pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n", | |
526 | iommu->name, req->pasid, ((unsigned long long *)req)[0], | |
527 | ((unsigned long long *)req)[1]); | |
26322ab5 | 528 | goto no_pasid; |
a222a7f0 DW |
529 | } |
530 | } | |
531 | ||
532 | result = QI_RESP_INVALID; | |
5cec7537 DW |
533 | /* Since we're using init_mm.pgd directly, we should never take |
534 | * any faults on kernel addresses. */ | |
535 | if (!svm->mm) | |
536 | goto bad_req; | |
a222a7f0 DW |
537 | down_read(&svm->mm->mmap_sem); |
538 | vma = find_extend_vma(svm->mm, address); | |
539 | if (!vma || address < vma->vm_start) | |
540 | goto invalid; | |
541 | ||
542 | ret = handle_mm_fault(svm->mm, vma, address, | |
543 | req->wr_req ? FAULT_FLAG_WRITE : 0); | |
544 | if (ret & VM_FAULT_ERROR) | |
545 | goto invalid; | |
546 | ||
547 | result = QI_RESP_SUCCESS; | |
548 | invalid: | |
549 | up_read(&svm->mm->mmap_sem); | |
550 | bad_req: | |
551 | /* Accounting for major/minor faults? */ | |
0204a496 DW |
552 | rcu_read_lock(); |
553 | list_for_each_entry_rcu(sdev, &svm->devs, list) { | |
3c7c2f32 | 554 | if (sdev->sid == PCI_DEVID(req->bus, req->devfn)) |
0204a496 DW |
555 | break; |
556 | } | |
557 | /* Other devices can go away, but the drivers are not permitted | |
558 | * to unbind while any page faults might be in flight. So it's | |
559 | * OK to drop the 'lock' here now we have it. */ | |
560 | rcu_read_unlock(); | |
561 | ||
562 | if (WARN_ON(&sdev->list == &svm->devs)) | |
563 | sdev = NULL; | |
564 | ||
565 | if (sdev && sdev->ops && sdev->ops->fault_cb) { | |
566 | int rwxp = (req->rd_req << 3) | (req->wr_req << 2) | | |
0bdec95c | 567 | (req->exe_req << 1) | (req->priv_req); |
0204a496 DW |
568 | sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result); |
569 | } | |
26322ab5 DW |
570 | /* We get here in the error case where the PASID lookup failed, |
571 | and these can be NULL. Do not use them below this point! */ | |
572 | sdev = NULL; | |
573 | svm = NULL; | |
574 | no_pasid: | |
a222a7f0 DW |
575 | if (req->lpig) { |
576 | /* Page Group Response */ | |
577 | resp.low = QI_PGRP_PASID(req->pasid) | | |
578 | QI_PGRP_DID((req->bus << 8) | req->devfn) | | |
579 | QI_PGRP_PASID_P(req->pasid_present) | | |
580 | QI_PGRP_RESP_TYPE; | |
581 | resp.high = QI_PGRP_IDX(req->prg_index) | | |
582 | QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result); | |
583 | ||
26322ab5 | 584 | qi_submit_sync(&resp, iommu); |
a222a7f0 DW |
585 | } else if (req->srr) { |
586 | /* Page Stream Response */ | |
587 | resp.low = QI_PSTRM_IDX(req->prg_index) | | |
588 | QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) | | |
589 | QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE; | |
590 | resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) | | |
591 | QI_PSTRM_RESP_CODE(result); | |
592 | ||
26322ab5 | 593 | qi_submit_sync(&resp, iommu); |
a222a7f0 DW |
594 | } |
595 | ||
596 | head = (head + sizeof(*req)) & PRQ_RING_MASK; | |
597 | } | |
598 | ||
599 | dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); | |
600 | ||
601 | return IRQ_RETVAL(handled); | |
602 | } |