Commit | Line | Data |
---|---|---|
9f10e5bf JR |
1 | |
2 | #define pr_fmt(fmt) "DMAR-IR: " fmt | |
3 | ||
5aeecaf4 | 4 | #include <linux/interrupt.h> |
ad3ad3f6 | 5 | #include <linux/dmar.h> |
2ae21010 | 6 | #include <linux/spinlock.h> |
5a0e3ad6 | 7 | #include <linux/slab.h> |
2ae21010 | 8 | #include <linux/jiffies.h> |
20f3097b | 9 | #include <linux/hpet.h> |
2ae21010 | 10 | #include <linux/pci.h> |
b6fcb33a | 11 | #include <linux/irq.h> |
8b48463f LZ |
12 | #include <linux/intel-iommu.h> |
13 | #include <linux/acpi.h> | |
af3b358e | 14 | #include <linux/crash_dump.h> |
ad3ad3f6 | 15 | #include <asm/io_apic.h> |
17483a1f | 16 | #include <asm/smp.h> |
6d652ea1 | 17 | #include <asm/cpu.h> |
8a8f422d | 18 | #include <asm/irq_remapping.h> |
f007e99c | 19 | #include <asm/pci-direct.h> |
5e2b930b | 20 | #include <asm/msidef.h> |
ad3ad3f6 | 21 | |
8a8f422d | 22 | #include "irq_remapping.h" |
736baef4 | 23 | |
eef93fdb JR |
24 | struct ioapic_scope { |
25 | struct intel_iommu *iommu; | |
26 | unsigned int id; | |
27 | unsigned int bus; /* PCI bus number */ | |
28 | unsigned int devfn; /* PCI devfn number */ | |
29 | }; | |
30 | ||
31 | struct hpet_scope { | |
32 | struct intel_iommu *iommu; | |
33 | u8 id; | |
34 | unsigned int bus; | |
35 | unsigned int devfn; | |
36 | }; | |
37 | ||
38 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
13d09b66 | 39 | #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) |
eef93fdb | 40 | |
13d09b66 | 41 | static int __read_mostly eim_mode; |
ad3ad3f6 | 42 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b | 43 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
d1423d56 | 44 | |
3a5670e8 JL |
45 | /* |
46 | * Lock ordering: | |
47 | * ->dmar_global_lock | |
48 | * ->irq_2_ir_lock | |
49 | * ->qi->q_lock | |
50 | * ->iommu->register_lock | |
51 | * Note: | |
52 | * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called | |
53 | * in single-threaded environment with interrupt disabled, so no need to tabke | |
54 | * the dmar_global_lock. | |
55 | */ | |
96f8e98b | 56 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 57 | |
af3b358e | 58 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu); |
694835dc JL |
59 | static int __init parse_ioapics_under_ir(void); |
60 | ||
af3b358e JR |
61 | static bool ir_pre_enabled(struct intel_iommu *iommu) |
62 | { | |
63 | return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); | |
64 | } | |
65 | ||
66 | static void clear_ir_pre_enabled(struct intel_iommu *iommu) | |
67 | { | |
68 | iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
69 | } | |
70 | ||
71 | static void init_ir_status(struct intel_iommu *iommu) | |
72 | { | |
73 | u32 gsts; | |
74 | ||
75 | gsts = readl(iommu->reg + DMAR_GSTS_REG); | |
76 | if (gsts & DMA_GSTS_IRES) | |
77 | iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; | |
78 | } | |
79 | ||
e420dfb4 YL |
80 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
81 | { | |
91411da1 | 82 | struct irq_cfg *cfg = irq_cfg(irq); |
349d6767 | 83 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
84 | } |
85 | ||
6a7885c4 | 86 | static int get_irte(int irq, struct irte *entry) |
b6fcb33a | 87 | { |
d585d060 | 88 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 89 | unsigned long flags; |
d585d060 | 90 | int index; |
b6fcb33a | 91 | |
d585d060 | 92 | if (!entry || !irq_iommu) |
b6fcb33a SS |
93 | return -1; |
94 | ||
96f8e98b | 95 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 96 | |
af437469 GE |
97 | if (unlikely(!irq_iommu->iommu)) { |
98 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); | |
99 | return -1; | |
100 | } | |
101 | ||
e420dfb4 YL |
102 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
103 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 104 | |
96f8e98b | 105 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
106 | return 0; |
107 | } | |
108 | ||
263b5e86 | 109 | static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
b6fcb33a SS |
110 | { |
111 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 112 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
91411da1 | 113 | struct irq_cfg *cfg = irq_cfg(irq); |
b6fcb33a | 114 | unsigned int mask = 0; |
4c5502b1 | 115 | unsigned long flags; |
9f4c7448 | 116 | int index; |
b6fcb33a | 117 | |
d585d060 | 118 | if (!count || !irq_iommu) |
e420dfb4 | 119 | return -1; |
e420dfb4 | 120 | |
b6fcb33a SS |
121 | if (count > 1) { |
122 | count = __roundup_pow_of_two(count); | |
123 | mask = ilog2(count); | |
124 | } | |
125 | ||
126 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
9f10e5bf | 127 | pr_err("Requested mask %x exceeds the max invalidation handle" |
b6fcb33a SS |
128 | " mask value %Lx\n", mask, |
129 | ecap_max_handle_mask(iommu->ecap)); | |
130 | return -1; | |
131 | } | |
132 | ||
96f8e98b | 133 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
134 | index = bitmap_find_free_region(table->bitmap, |
135 | INTR_REMAP_TABLE_ENTRIES, mask); | |
136 | if (index < 0) { | |
137 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
138 | } else { | |
139 | cfg->remapped = 1; | |
140 | irq_iommu->iommu = iommu; | |
141 | irq_iommu->irte_index = index; | |
142 | irq_iommu->sub_handle = 0; | |
143 | irq_iommu->irte_mask = mask; | |
144 | } | |
96f8e98b | 145 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
146 | |
147 | return index; | |
148 | } | |
149 | ||
704126ad | 150 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
151 | { |
152 | struct qi_desc desc; | |
153 | ||
154 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
155 | | QI_IEC_SELECTIVE; | |
156 | desc.high = 0; | |
157 | ||
704126ad | 158 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
159 | } |
160 | ||
263b5e86 | 161 | static int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
b6fcb33a | 162 | { |
d585d060 | 163 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 164 | unsigned long flags; |
d585d060 | 165 | int index; |
b6fcb33a | 166 | |
d585d060 | 167 | if (!irq_iommu) |
b6fcb33a | 168 | return -1; |
b6fcb33a | 169 | |
96f8e98b | 170 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
171 | *sub_handle = irq_iommu->sub_handle; |
172 | index = irq_iommu->irte_index; | |
96f8e98b | 173 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
174 | return index; |
175 | } | |
176 | ||
263b5e86 | 177 | static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
b6fcb33a | 178 | { |
d585d060 | 179 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
91411da1 | 180 | struct irq_cfg *cfg = irq_cfg(irq); |
4c5502b1 | 181 | unsigned long flags; |
e420dfb4 | 182 | |
d585d060 | 183 | if (!irq_iommu) |
0b8f1efa | 184 | return -1; |
d585d060 | 185 | |
96f8e98b | 186 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 187 | |
9b1b0e42 | 188 | cfg->remapped = 1; |
e420dfb4 YL |
189 | irq_iommu->iommu = iommu; |
190 | irq_iommu->irte_index = index; | |
191 | irq_iommu->sub_handle = subhandle; | |
192 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 193 | |
96f8e98b | 194 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
195 | |
196 | return 0; | |
197 | } | |
198 | ||
263b5e86 | 199 | static int modify_irte(int irq, struct irte *irte_modified) |
b6fcb33a | 200 | { |
d585d060 | 201 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 202 | struct intel_iommu *iommu; |
4c5502b1 | 203 | unsigned long flags; |
d585d060 TG |
204 | struct irte *irte; |
205 | int rc, index; | |
b6fcb33a | 206 | |
d585d060 | 207 | if (!irq_iommu) |
b6fcb33a | 208 | return -1; |
d585d060 | 209 | |
96f8e98b | 210 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 211 | |
e420dfb4 | 212 | iommu = irq_iommu->iommu; |
b6fcb33a | 213 | |
e420dfb4 | 214 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
215 | irte = &iommu->ir_table->base[index]; |
216 | ||
c513b67e LT |
217 | set_64bit(&irte->low, irte_modified->low); |
218 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
219 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
220 | ||
704126ad | 221 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 222 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
223 | |
224 | return rc; | |
b6fcb33a SS |
225 | } |
226 | ||
263b5e86 | 227 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
228 | { |
229 | int i; | |
230 | ||
231 | for (i = 0; i < MAX_HPET_TBS; i++) | |
a7a3dad9 | 232 | if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) |
20f3097b SS |
233 | return ir_hpet[i].iommu; |
234 | return NULL; | |
235 | } | |
236 | ||
263b5e86 | 237 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
238 | { |
239 | int i; | |
240 | ||
241 | for (i = 0; i < MAX_IO_APICS; i++) | |
a7a3dad9 | 242 | if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) |
89027d35 SS |
243 | return ir_ioapic[i].iommu; |
244 | return NULL; | |
245 | } | |
246 | ||
263b5e86 | 247 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
248 | { |
249 | struct dmar_drhd_unit *drhd; | |
250 | ||
251 | drhd = dmar_find_matched_drhd_unit(dev); | |
252 | if (!drhd) | |
253 | return NULL; | |
254 | ||
255 | return drhd->iommu; | |
256 | } | |
257 | ||
c4658b4e WH |
258 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
259 | { | |
260 | struct irte *start, *entry, *end; | |
261 | struct intel_iommu *iommu; | |
262 | int index; | |
263 | ||
264 | if (irq_iommu->sub_handle) | |
265 | return 0; | |
266 | ||
267 | iommu = irq_iommu->iommu; | |
268 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
269 | ||
270 | start = iommu->ir_table->base + index; | |
271 | end = start + (1 << irq_iommu->irte_mask); | |
272 | ||
273 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
274 | set_64bit(&entry->low, 0); |
275 | set_64bit(&entry->high, 0); | |
c4658b4e | 276 | } |
360eb3c5 JL |
277 | bitmap_release_region(iommu->ir_table->bitmap, index, |
278 | irq_iommu->irte_mask); | |
c4658b4e WH |
279 | |
280 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
281 | } | |
282 | ||
9d619f65 | 283 | static int free_irte(int irq) |
b6fcb33a | 284 | { |
d585d060 | 285 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 286 | unsigned long flags; |
d585d060 | 287 | int rc; |
b6fcb33a | 288 | |
d585d060 | 289 | if (!irq_iommu) |
b6fcb33a | 290 | return -1; |
d585d060 | 291 | |
96f8e98b | 292 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 293 | |
c4658b4e | 294 | rc = clear_entries(irq_iommu); |
b6fcb33a | 295 | |
e420dfb4 YL |
296 | irq_iommu->iommu = NULL; |
297 | irq_iommu->irte_index = 0; | |
298 | irq_iommu->sub_handle = 0; | |
299 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 300 | |
96f8e98b | 301 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 302 | |
704126ad | 303 | return rc; |
b6fcb33a SS |
304 | } |
305 | ||
f007e99c WH |
306 | /* |
307 | * source validation type | |
308 | */ | |
309 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 310 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
311 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
312 | ||
313 | /* | |
314 | * source-id qualifier | |
315 | */ | |
316 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
317 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
318 | * the third least significant bit | |
319 | */ | |
320 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
321 | * the second and third least significant bits | |
322 | */ | |
323 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
324 | * the least three significant bits | |
325 | */ | |
326 | ||
327 | /* | |
328 | * set SVT, SQ and SID fields of irte to verify | |
329 | * source ids of interrupt requests | |
330 | */ | |
331 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
332 | unsigned int sq, unsigned int sid) | |
333 | { | |
d1423d56 CW |
334 | if (disable_sourceid_checking) |
335 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
336 | irte->svt = svt; |
337 | irte->sq = sq; | |
338 | irte->sid = sid; | |
339 | } | |
340 | ||
263b5e86 | 341 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
342 | { |
343 | int i; | |
344 | u16 sid = 0; | |
345 | ||
346 | if (!irte) | |
347 | return -1; | |
348 | ||
3a5670e8 | 349 | down_read(&dmar_global_lock); |
f007e99c | 350 | for (i = 0; i < MAX_IO_APICS; i++) { |
a7a3dad9 | 351 | if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { |
f007e99c WH |
352 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
353 | break; | |
354 | } | |
355 | } | |
3a5670e8 | 356 | up_read(&dmar_global_lock); |
f007e99c WH |
357 | |
358 | if (sid == 0) { | |
9f10e5bf | 359 | pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); |
f007e99c WH |
360 | return -1; |
361 | } | |
362 | ||
2fe2c602 | 363 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
364 | |
365 | return 0; | |
366 | } | |
367 | ||
263b5e86 | 368 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
369 | { |
370 | int i; | |
371 | u16 sid = 0; | |
372 | ||
373 | if (!irte) | |
374 | return -1; | |
375 | ||
3a5670e8 | 376 | down_read(&dmar_global_lock); |
20f3097b | 377 | for (i = 0; i < MAX_HPET_TBS; i++) { |
a7a3dad9 | 378 | if (ir_hpet[i].iommu && ir_hpet[i].id == id) { |
20f3097b SS |
379 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
380 | break; | |
381 | } | |
382 | } | |
3a5670e8 | 383 | up_read(&dmar_global_lock); |
20f3097b SS |
384 | |
385 | if (sid == 0) { | |
9f10e5bf | 386 | pr_warn("Failed to set source-id of HPET block (%d)\n", id); |
20f3097b SS |
387 | return -1; |
388 | } | |
389 | ||
390 | /* | |
391 | * Should really use SQ_ALL_16. Some platforms are broken. | |
392 | * While we figure out the right quirks for these broken platforms, use | |
393 | * SQ_13_IGNORE_3 for now. | |
394 | */ | |
395 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
579305f7 AW |
400 | struct set_msi_sid_data { |
401 | struct pci_dev *pdev; | |
402 | u16 alias; | |
403 | }; | |
404 | ||
405 | static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) | |
406 | { | |
407 | struct set_msi_sid_data *data = opaque; | |
408 | ||
409 | data->pdev = pdev; | |
410 | data->alias = alias; | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
263b5e86 | 415 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c | 416 | { |
579305f7 | 417 | struct set_msi_sid_data data; |
f007e99c WH |
418 | |
419 | if (!irte || !dev) | |
420 | return -1; | |
421 | ||
579305f7 | 422 | pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); |
f007e99c | 423 | |
579305f7 AW |
424 | /* |
425 | * DMA alias provides us with a PCI device and alias. The only case | |
426 | * where the it will return an alias on a different bus than the | |
427 | * device is the case of a PCIe-to-PCI bridge, where the alias is for | |
428 | * the subordinate bus. In this case we can only verify the bus. | |
429 | * | |
430 | * If the alias device is on a different bus than our source device | |
431 | * then we have a topology based alias, use it. | |
432 | * | |
433 | * Otherwise, the alias is for a device DMA quirk and we cannot | |
434 | * assume that MSI uses the same requester ID. Therefore use the | |
435 | * original device. | |
436 | */ | |
437 | if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) | |
438 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
439 | PCI_DEVID(PCI_BUS_NUM(data.alias), | |
440 | dev->bus->number)); | |
441 | else if (data.pdev->bus->number != dev->bus->number) | |
442 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); | |
443 | else | |
444 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
445 | PCI_DEVID(dev->bus->number, dev->devfn)); | |
f007e99c WH |
446 | |
447 | return 0; | |
448 | } | |
449 | ||
af3b358e JR |
450 | static int iommu_load_old_irte(struct intel_iommu *iommu) |
451 | { | |
452 | struct irte *old_ir_table; | |
453 | phys_addr_t irt_phys; | |
7c3c9876 | 454 | unsigned int i; |
af3b358e JR |
455 | size_t size; |
456 | u64 irta; | |
457 | ||
458 | if (!is_kdump_kernel()) { | |
459 | pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n", | |
460 | iommu->name); | |
461 | clear_ir_pre_enabled(iommu); | |
462 | iommu_disable_irq_remapping(iommu); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | /* Check whether the old ir-table has the same size as ours */ | |
467 | irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); | |
468 | if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK) | |
469 | != INTR_REMAP_TABLE_REG_SIZE) | |
470 | return -EINVAL; | |
471 | ||
472 | irt_phys = irta & VTD_PAGE_MASK; | |
473 | size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte); | |
474 | ||
475 | /* Map the old IR table */ | |
476 | old_ir_table = ioremap_cache(irt_phys, size); | |
477 | if (!old_ir_table) | |
478 | return -ENOMEM; | |
479 | ||
480 | /* Copy data over */ | |
481 | memcpy(iommu->ir_table->base, old_ir_table, size); | |
482 | ||
483 | __iommu_flush_cache(iommu, iommu->ir_table->base, size); | |
484 | ||
7c3c9876 JR |
485 | /* |
486 | * Now check the table for used entries and mark those as | |
487 | * allocated in the bitmap | |
488 | */ | |
489 | for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) { | |
490 | if (iommu->ir_table->base[i].present) | |
491 | bitmap_set(iommu->ir_table->bitmap, i, 1); | |
492 | } | |
493 | ||
af3b358e JR |
494 | return 0; |
495 | } | |
496 | ||
497 | ||
95a02e97 | 498 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 | 499 | { |
d4d1c0f3 | 500 | unsigned long flags; |
2ae21010 | 501 | u64 addr; |
c416daa9 | 502 | u32 sts; |
2ae21010 SS |
503 | |
504 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
505 | ||
1f5b3c3f | 506 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
507 | |
508 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
509 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
510 | ||
511 | /* Set interrupt-remapping table pointer */ | |
f63ef690 | 512 | writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
513 | |
514 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
515 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 516 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
517 | |
518 | /* | |
d4d1c0f3 JR |
519 | * Global invalidation of interrupt entry cache to make sure the |
520 | * hardware uses the new irq remapping table. | |
2ae21010 SS |
521 | */ |
522 | qi_global_iec(iommu); | |
d4d1c0f3 JR |
523 | } |
524 | ||
525 | static void iommu_enable_irq_remapping(struct intel_iommu *iommu) | |
526 | { | |
527 | unsigned long flags; | |
528 | u32 sts; | |
2ae21010 | 529 | |
1f5b3c3f | 530 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
531 | |
532 | /* Enable interrupt-remapping */ | |
2ae21010 | 533 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 534 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 535 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
536 | |
537 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
538 | readl, (sts & DMA_GSTS_IRES), sts); | |
539 | ||
af8d102f AL |
540 | /* |
541 | * With CFI clear in the Global Command register, we should be | |
542 | * protected from dangerous (i.e. compatibility) interrupts | |
543 | * regardless of x2apic status. Check just to be sure. | |
544 | */ | |
545 | if (sts & DMA_GSTS_CFIS) | |
546 | WARN(1, KERN_WARNING | |
547 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
548 | "you are vulnerable to IRQ injection.\n"); | |
549 | ||
1f5b3c3f | 550 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
551 | } |
552 | ||
a7a3dad9 | 553 | static int intel_setup_irq_remapping(struct intel_iommu *iommu) |
2ae21010 SS |
554 | { |
555 | struct ir_table *ir_table; | |
556 | struct page *pages; | |
360eb3c5 | 557 | unsigned long *bitmap; |
2ae21010 | 558 | |
a7a3dad9 JL |
559 | if (iommu->ir_table) |
560 | return 0; | |
2ae21010 | 561 | |
e3a981d6 | 562 | ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); |
a7a3dad9 | 563 | if (!ir_table) |
2ae21010 SS |
564 | return -ENOMEM; |
565 | ||
e3a981d6 | 566 | pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, |
824cd75b | 567 | INTR_REMAP_PAGE_ORDER); |
2ae21010 SS |
568 | |
569 | if (!pages) { | |
360eb3c5 JL |
570 | pr_err("IR%d: failed to allocate pages of order %d\n", |
571 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
a7a3dad9 | 572 | goto out_free_table; |
2ae21010 SS |
573 | } |
574 | ||
360eb3c5 JL |
575 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
576 | sizeof(long), GFP_ATOMIC); | |
577 | if (bitmap == NULL) { | |
578 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
a7a3dad9 | 579 | goto out_free_pages; |
360eb3c5 JL |
580 | } |
581 | ||
2ae21010 | 582 | ir_table->base = page_address(pages); |
360eb3c5 | 583 | ir_table->bitmap = bitmap; |
a7a3dad9 | 584 | iommu->ir_table = ir_table; |
9e4e49df JR |
585 | |
586 | /* | |
587 | * If the queued invalidation is already initialized, | |
588 | * shouldn't disable it. | |
589 | */ | |
590 | if (!iommu->qi) { | |
591 | /* | |
592 | * Clear previous faults. | |
593 | */ | |
594 | dmar_fault(-1, iommu); | |
595 | dmar_disable_qi(iommu); | |
596 | ||
597 | if (dmar_enable_qi(iommu)) { | |
598 | pr_err("Failed to enable queued invalidation\n"); | |
599 | goto out_free_bitmap; | |
600 | } | |
601 | } | |
602 | ||
af3b358e JR |
603 | init_ir_status(iommu); |
604 | ||
605 | if (ir_pre_enabled(iommu)) { | |
606 | if (iommu_load_old_irte(iommu)) | |
607 | pr_err("Failed to copy IR table for %s from previous kernel\n", | |
608 | iommu->name); | |
609 | else | |
610 | pr_info("Copied IR table for %s from previous kernel\n", | |
611 | iommu->name); | |
612 | } | |
613 | ||
d4d1c0f3 JR |
614 | iommu_set_irq_remapping(iommu, eim_mode); |
615 | ||
2ae21010 | 616 | return 0; |
a7a3dad9 | 617 | |
9e4e49df JR |
618 | out_free_bitmap: |
619 | kfree(bitmap); | |
a7a3dad9 JL |
620 | out_free_pages: |
621 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
622 | out_free_table: | |
623 | kfree(ir_table); | |
9e4e49df JR |
624 | |
625 | iommu->ir_table = NULL; | |
626 | ||
a7a3dad9 JL |
627 | return -ENOMEM; |
628 | } | |
629 | ||
630 | static void intel_teardown_irq_remapping(struct intel_iommu *iommu) | |
631 | { | |
632 | if (iommu && iommu->ir_table) { | |
633 | free_pages((unsigned long)iommu->ir_table->base, | |
634 | INTR_REMAP_PAGE_ORDER); | |
635 | kfree(iommu->ir_table->bitmap); | |
636 | kfree(iommu->ir_table); | |
637 | iommu->ir_table = NULL; | |
638 | } | |
2ae21010 SS |
639 | } |
640 | ||
eba67e5d SS |
641 | /* |
642 | * Disable Interrupt Remapping. | |
643 | */ | |
95a02e97 | 644 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
645 | { |
646 | unsigned long flags; | |
647 | u32 sts; | |
648 | ||
649 | if (!ecap_ir_support(iommu->ecap)) | |
650 | return; | |
651 | ||
b24696bc FY |
652 | /* |
653 | * global invalidation of interrupt entry cache before disabling | |
654 | * interrupt-remapping. | |
655 | */ | |
656 | qi_global_iec(iommu); | |
657 | ||
1f5b3c3f | 658 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
659 | |
660 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
661 | if (!(sts & DMA_GSTS_IRES)) | |
662 | goto end; | |
663 | ||
664 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
665 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
666 | ||
667 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
668 | readl, !(sts & DMA_GSTS_IRES), sts); | |
669 | ||
670 | end: | |
1f5b3c3f | 671 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
672 | } |
673 | ||
41750d31 SS |
674 | static int __init dmar_x2apic_optout(void) |
675 | { | |
676 | struct acpi_table_dmar *dmar; | |
677 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
678 | if (!dmar || no_x2apic_optout) | |
679 | return 0; | |
680 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
681 | } | |
682 | ||
11190302 TG |
683 | static void __init intel_cleanup_irq_remapping(void) |
684 | { | |
685 | struct dmar_drhd_unit *drhd; | |
686 | struct intel_iommu *iommu; | |
687 | ||
688 | for_each_iommu(iommu, drhd) { | |
689 | if (ecap_ir_support(iommu->ecap)) { | |
690 | iommu_disable_irq_remapping(iommu); | |
691 | intel_teardown_irq_remapping(iommu); | |
692 | } | |
693 | } | |
694 | ||
695 | if (x2apic_supported()) | |
9f10e5bf | 696 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); |
11190302 TG |
697 | } |
698 | ||
699 | static int __init intel_prepare_irq_remapping(void) | |
2ae21010 SS |
700 | { |
701 | struct dmar_drhd_unit *drhd; | |
7c919779 | 702 | struct intel_iommu *iommu; |
23256d0b | 703 | int eim = 0; |
2ae21010 | 704 | |
2966d956 | 705 | if (irq_remap_broken) { |
9f10e5bf | 706 | pr_warn("This system BIOS has enabled interrupt remapping\n" |
2966d956 JL |
707 | "on a chipset that contains an erratum making that\n" |
708 | "feature unstable. To maintain system stability\n" | |
709 | "interrupt remapping is being disabled. Please\n" | |
710 | "contact your BIOS vendor for an update\n"); | |
711 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
2966d956 JL |
712 | return -ENODEV; |
713 | } | |
714 | ||
11190302 | 715 | if (dmar_table_init() < 0) |
2966d956 JL |
716 | return -ENODEV; |
717 | ||
718 | if (!dmar_ir_support()) | |
719 | return -ENODEV; | |
af8d102f | 720 | |
e936d077 | 721 | if (parse_ioapics_under_ir() != 1) { |
9f10e5bf | 722 | pr_info("Not enabling interrupt remapping\n"); |
af8d102f | 723 | goto error; |
e936d077 YS |
724 | } |
725 | ||
69cf1d8a | 726 | /* First make sure all IOMMUs support IRQ remapping */ |
2966d956 | 727 | for_each_iommu(iommu, drhd) |
69cf1d8a JR |
728 | if (!ecap_ir_support(iommu->ecap)) |
729 | goto error; | |
730 | ||
23256d0b JR |
731 | /* Detect remapping mode: lapic or x2apic */ |
732 | if (x2apic_supported()) { | |
733 | eim = !dmar_x2apic_optout(); | |
734 | if (!eim) { | |
735 | pr_info("x2apic is disabled because BIOS sets x2apic opt out bit."); | |
736 | pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n"); | |
737 | } | |
738 | } | |
739 | ||
740 | for_each_iommu(iommu, drhd) { | |
741 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
742 | pr_info("%s does not support EIM\n", iommu->name); | |
743 | eim = 0; | |
744 | } | |
c676f587 JR |
745 | |
746 | /* Disable IRQ remapping if it is already enabled */ | |
747 | iommu_disable_irq_remapping(iommu); | |
23256d0b JR |
748 | } |
749 | ||
750 | eim_mode = eim; | |
751 | if (eim) | |
752 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); | |
753 | ||
9e4e49df JR |
754 | /* Do the initializations early */ |
755 | for_each_iommu(iommu, drhd) { | |
756 | if (intel_setup_irq_remapping(iommu)) { | |
757 | pr_err("Failed to setup irq remapping for %s\n", | |
758 | iommu->name); | |
11190302 | 759 | goto error; |
9e4e49df JR |
760 | } |
761 | } | |
69cf1d8a | 762 | |
11190302 | 763 | return 0; |
2966d956 | 764 | |
11190302 TG |
765 | error: |
766 | intel_cleanup_irq_remapping(); | |
2966d956 | 767 | return -ENODEV; |
11190302 TG |
768 | } |
769 | ||
770 | static int __init intel_enable_irq_remapping(void) | |
771 | { | |
772 | struct dmar_drhd_unit *drhd; | |
773 | struct intel_iommu *iommu; | |
2f119c78 | 774 | bool setup = false; |
41750d31 | 775 | |
2ae21010 SS |
776 | /* |
777 | * Setup Interrupt-remapping for all the DRHD's now. | |
778 | */ | |
7c919779 | 779 | for_each_iommu(iommu, drhd) { |
d4d1c0f3 | 780 | iommu_enable_irq_remapping(iommu); |
2f119c78 | 781 | setup = true; |
2ae21010 SS |
782 | } |
783 | ||
784 | if (!setup) | |
785 | goto error; | |
786 | ||
95a02e97 | 787 | irq_remapping_enabled = 1; |
afcc8a40 JR |
788 | |
789 | /* | |
790 | * VT-d has a different layout for IO-APIC entries when | |
791 | * interrupt remapping is enabled. So it needs a special routine | |
792 | * to print IO-APIC entries for debugging purposes too. | |
793 | */ | |
794 | x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries; | |
795 | ||
23256d0b | 796 | pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic"); |
2ae21010 | 797 | |
23256d0b | 798 | return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
799 | |
800 | error: | |
11190302 | 801 | intel_cleanup_irq_remapping(); |
2ae21010 SS |
802 | return -1; |
803 | } | |
ad3ad3f6 | 804 | |
a7a3dad9 JL |
805 | static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
806 | struct intel_iommu *iommu, | |
807 | struct acpi_dmar_hardware_unit *drhd) | |
20f3097b SS |
808 | { |
809 | struct acpi_dmar_pci_path *path; | |
810 | u8 bus; | |
a7a3dad9 | 811 | int count, free = -1; |
20f3097b SS |
812 | |
813 | bus = scope->bus; | |
814 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
815 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
816 | / sizeof(struct acpi_dmar_pci_path); | |
817 | ||
818 | while (--count > 0) { | |
819 | /* | |
820 | * Access PCI directly due to the PCI | |
821 | * subsystem isn't initialized yet. | |
822 | */ | |
fa5f508f | 823 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
824 | PCI_SECONDARY_BUS); |
825 | path++; | |
826 | } | |
a7a3dad9 JL |
827 | |
828 | for (count = 0; count < MAX_HPET_TBS; count++) { | |
829 | if (ir_hpet[count].iommu == iommu && | |
830 | ir_hpet[count].id == scope->enumeration_id) | |
831 | return 0; | |
832 | else if (ir_hpet[count].iommu == NULL && free == -1) | |
833 | free = count; | |
834 | } | |
835 | if (free == -1) { | |
836 | pr_warn("Exceeded Max HPET blocks\n"); | |
837 | return -ENOSPC; | |
838 | } | |
839 | ||
840 | ir_hpet[free].iommu = iommu; | |
841 | ir_hpet[free].id = scope->enumeration_id; | |
842 | ir_hpet[free].bus = bus; | |
843 | ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); | |
844 | pr_info("HPET id %d under DRHD base 0x%Lx\n", | |
845 | scope->enumeration_id, drhd->address); | |
846 | ||
847 | return 0; | |
20f3097b SS |
848 | } |
849 | ||
a7a3dad9 JL |
850 | static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
851 | struct intel_iommu *iommu, | |
852 | struct acpi_dmar_hardware_unit *drhd) | |
f007e99c WH |
853 | { |
854 | struct acpi_dmar_pci_path *path; | |
855 | u8 bus; | |
a7a3dad9 | 856 | int count, free = -1; |
f007e99c WH |
857 | |
858 | bus = scope->bus; | |
859 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
860 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
861 | / sizeof(struct acpi_dmar_pci_path); | |
862 | ||
863 | while (--count > 0) { | |
864 | /* | |
865 | * Access PCI directly due to the PCI | |
866 | * subsystem isn't initialized yet. | |
867 | */ | |
fa5f508f | 868 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
869 | PCI_SECONDARY_BUS); |
870 | path++; | |
871 | } | |
872 | ||
a7a3dad9 JL |
873 | for (count = 0; count < MAX_IO_APICS; count++) { |
874 | if (ir_ioapic[count].iommu == iommu && | |
875 | ir_ioapic[count].id == scope->enumeration_id) | |
876 | return 0; | |
877 | else if (ir_ioapic[count].iommu == NULL && free == -1) | |
878 | free = count; | |
879 | } | |
880 | if (free == -1) { | |
881 | pr_warn("Exceeded Max IO APICS\n"); | |
882 | return -ENOSPC; | |
883 | } | |
884 | ||
885 | ir_ioapic[free].bus = bus; | |
886 | ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); | |
887 | ir_ioapic[free].iommu = iommu; | |
888 | ir_ioapic[free].id = scope->enumeration_id; | |
889 | pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", | |
890 | scope->enumeration_id, drhd->address, iommu->seq_id); | |
891 | ||
892 | return 0; | |
f007e99c WH |
893 | } |
894 | ||
20f3097b SS |
895 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
896 | struct intel_iommu *iommu) | |
ad3ad3f6 | 897 | { |
a7a3dad9 | 898 | int ret = 0; |
ad3ad3f6 SS |
899 | struct acpi_dmar_hardware_unit *drhd; |
900 | struct acpi_dmar_device_scope *scope; | |
901 | void *start, *end; | |
902 | ||
903 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
ad3ad3f6 SS |
904 | start = (void *)(drhd + 1); |
905 | end = ((void *)drhd) + header->length; | |
906 | ||
a7a3dad9 | 907 | while (start < end && ret == 0) { |
ad3ad3f6 | 908 | scope = start; |
a7a3dad9 JL |
909 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) |
910 | ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); | |
911 | else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) | |
912 | ret = ir_parse_one_hpet_scope(scope, iommu, drhd); | |
913 | start += scope->length; | |
914 | } | |
ad3ad3f6 | 915 | |
a7a3dad9 JL |
916 | return ret; |
917 | } | |
20f3097b | 918 | |
a7a3dad9 JL |
919 | static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) |
920 | { | |
921 | int i; | |
20f3097b | 922 | |
a7a3dad9 JL |
923 | for (i = 0; i < MAX_HPET_TBS; i++) |
924 | if (ir_hpet[i].iommu == iommu) | |
925 | ir_hpet[i].iommu = NULL; | |
ad3ad3f6 | 926 | |
a7a3dad9 JL |
927 | for (i = 0; i < MAX_IO_APICS; i++) |
928 | if (ir_ioapic[i].iommu == iommu) | |
929 | ir_ioapic[i].iommu = NULL; | |
ad3ad3f6 SS |
930 | } |
931 | ||
932 | /* | |
933 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
934 | * hardware unit. | |
935 | */ | |
694835dc | 936 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
937 | { |
938 | struct dmar_drhd_unit *drhd; | |
7c919779 | 939 | struct intel_iommu *iommu; |
2f119c78 | 940 | bool ir_supported = false; |
32ab31e0 | 941 | int ioapic_idx; |
ad3ad3f6 | 942 | |
7c919779 | 943 | for_each_iommu(iommu, drhd) |
ad3ad3f6 | 944 | if (ecap_ir_support(iommu->ecap)) { |
20f3097b | 945 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
946 | return -1; |
947 | ||
2f119c78 | 948 | ir_supported = true; |
ad3ad3f6 | 949 | } |
ad3ad3f6 | 950 | |
32ab31e0 SF |
951 | if (!ir_supported) |
952 | return 0; | |
953 | ||
954 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
955 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
956 | if (!map_ioapic_to_ir(ioapic_id)) { | |
957 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
958 | "interrupt remapping will be disabled\n", | |
959 | ioapic_id); | |
960 | return -1; | |
961 | } | |
ad3ad3f6 SS |
962 | } |
963 | ||
32ab31e0 | 964 | return 1; |
ad3ad3f6 | 965 | } |
b24696bc | 966 | |
6a7885c4 | 967 | static int __init ir_dev_scope_init(void) |
c2c7286a | 968 | { |
3a5670e8 JL |
969 | int ret; |
970 | ||
95a02e97 | 971 | if (!irq_remapping_enabled) |
c2c7286a SS |
972 | return 0; |
973 | ||
3a5670e8 JL |
974 | down_write(&dmar_global_lock); |
975 | ret = dmar_dev_scope_init(); | |
976 | up_write(&dmar_global_lock); | |
977 | ||
978 | return ret; | |
c2c7286a SS |
979 | } |
980 | rootfs_initcall(ir_dev_scope_init); | |
981 | ||
95a02e97 | 982 | static void disable_irq_remapping(void) |
b24696bc FY |
983 | { |
984 | struct dmar_drhd_unit *drhd; | |
985 | struct intel_iommu *iommu = NULL; | |
986 | ||
987 | /* | |
988 | * Disable Interrupt-remapping for all the DRHD's now. | |
989 | */ | |
990 | for_each_iommu(iommu, drhd) { | |
991 | if (!ecap_ir_support(iommu->ecap)) | |
992 | continue; | |
993 | ||
95a02e97 | 994 | iommu_disable_irq_remapping(iommu); |
b24696bc FY |
995 | } |
996 | } | |
997 | ||
95a02e97 | 998 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
999 | { |
1000 | struct dmar_drhd_unit *drhd; | |
2f119c78 | 1001 | bool setup = false; |
b24696bc FY |
1002 | struct intel_iommu *iommu = NULL; |
1003 | ||
1004 | for_each_iommu(iommu, drhd) | |
1005 | if (iommu->qi) | |
1006 | dmar_reenable_qi(iommu); | |
1007 | ||
1008 | /* | |
1009 | * Setup Interrupt-remapping for all the DRHD's now. | |
1010 | */ | |
1011 | for_each_iommu(iommu, drhd) { | |
1012 | if (!ecap_ir_support(iommu->ecap)) | |
1013 | continue; | |
1014 | ||
1015 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 1016 | iommu_set_irq_remapping(iommu, eim); |
d4d1c0f3 | 1017 | iommu_enable_irq_remapping(iommu); |
2f119c78 | 1018 | setup = true; |
b24696bc FY |
1019 | } |
1020 | ||
1021 | if (!setup) | |
1022 | goto error; | |
1023 | ||
1024 | return 0; | |
1025 | ||
1026 | error: | |
1027 | /* | |
1028 | * handle error condition gracefully here! | |
1029 | */ | |
1030 | return -1; | |
1031 | } | |
1032 | ||
0c3f173a JR |
1033 | static void prepare_irte(struct irte *irte, int vector, |
1034 | unsigned int dest) | |
1035 | { | |
1036 | memset(irte, 0, sizeof(*irte)); | |
1037 | ||
1038 | irte->present = 1; | |
1039 | irte->dst_mode = apic->irq_dest_mode; | |
1040 | /* | |
1041 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
1042 | * actual level or edge trigger will be setup in the IO-APIC | |
1043 | * RTE. This will help simplify level triggered irq migration. | |
1044 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
1045 | * irq migration in the presence of interrupt-remapping. | |
1046 | */ | |
1047 | irte->trigger_mode = 0; | |
1048 | irte->dlvry_mode = apic->irq_delivery_mode; | |
1049 | irte->vector = vector; | |
1050 | irte->dest_id = IRTE_DEST(dest); | |
1051 | irte->redir_hint = 1; | |
1052 | } | |
1053 | ||
1054 | static int intel_setup_ioapic_entry(int irq, | |
1055 | struct IO_APIC_route_entry *route_entry, | |
1056 | unsigned int destination, int vector, | |
1057 | struct io_apic_irq_attr *attr) | |
1058 | { | |
1059 | int ioapic_id = mpc_ioapic_id(attr->ioapic); | |
3a5670e8 | 1060 | struct intel_iommu *iommu; |
0c3f173a JR |
1061 | struct IR_IO_APIC_route_entry *entry; |
1062 | struct irte irte; | |
1063 | int index; | |
1064 | ||
3a5670e8 JL |
1065 | down_read(&dmar_global_lock); |
1066 | iommu = map_ioapic_to_ir(ioapic_id); | |
0c3f173a JR |
1067 | if (!iommu) { |
1068 | pr_warn("No mapping iommu for ioapic %d\n", ioapic_id); | |
3a5670e8 JL |
1069 | index = -ENODEV; |
1070 | } else { | |
1071 | index = alloc_irte(iommu, irq, 1); | |
1072 | if (index < 0) { | |
1073 | pr_warn("Failed to allocate IRTE for ioapic %d\n", | |
1074 | ioapic_id); | |
1075 | index = -ENOMEM; | |
1076 | } | |
0c3f173a | 1077 | } |
3a5670e8 JL |
1078 | up_read(&dmar_global_lock); |
1079 | if (index < 0) | |
1080 | return index; | |
0c3f173a JR |
1081 | |
1082 | prepare_irte(&irte, vector, destination); | |
1083 | ||
1084 | /* Set source-id of interrupt request */ | |
1085 | set_ioapic_sid(&irte, ioapic_id); | |
1086 | ||
1087 | modify_irte(irq, &irte); | |
1088 | ||
1089 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " | |
1090 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
1091 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
1092 | "Avail:%X Vector:%02X Dest:%08X " | |
1093 | "SID:%04X SQ:%X SVT:%X)\n", | |
1094 | attr->ioapic, irte.present, irte.fpd, irte.dst_mode, | |
1095 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, | |
1096 | irte.avail, irte.vector, irte.dest_id, | |
1097 | irte.sid, irte.sq, irte.svt); | |
1098 | ||
3a5670e8 | 1099 | entry = (struct IR_IO_APIC_route_entry *)route_entry; |
0c3f173a JR |
1100 | memset(entry, 0, sizeof(*entry)); |
1101 | ||
1102 | entry->index2 = (index >> 15) & 0x1; | |
1103 | entry->zero = 0; | |
1104 | entry->format = 1; | |
1105 | entry->index = (index & 0x7fff); | |
1106 | /* | |
1107 | * IO-APIC RTE will be configured with virtual vector. | |
1108 | * irq handler will do the explicit EOI to the io-apic. | |
1109 | */ | |
1110 | entry->vector = attr->ioapic_pin; | |
1111 | entry->mask = 0; /* enable IRQ */ | |
1112 | entry->trigger = attr->trigger; | |
1113 | entry->polarity = attr->polarity; | |
1114 | ||
1115 | /* Mask level triggered irqs. | |
1116 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1117 | */ | |
1118 | if (attr->trigger) | |
1119 | entry->mask = 1; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
4c1bad6a JR |
1124 | /* |
1125 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
1126 | * | |
1127 | * For both level and edge triggered, irq migration is a simple atomic | |
1128 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
1129 | * | |
1130 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
1131 | * updated vector information), by using a virtual vector (io-apic pin number). | |
1132 | * Real vector that is used for interrupting cpu will be coming from | |
1133 | * the interrupt-remapping table entry. | |
1134 | * | |
1135 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
1136 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
1137 | */ | |
1138 | static int | |
1139 | intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
1140 | bool force) | |
1141 | { | |
91411da1 | 1142 | struct irq_cfg *cfg = irqd_cfg(data); |
4c1bad6a JR |
1143 | unsigned int dest, irq = data->irq; |
1144 | struct irte irte; | |
ff164324 | 1145 | int err; |
4c1bad6a | 1146 | |
7eb9ae07 SS |
1147 | if (!config_enabled(CONFIG_SMP)) |
1148 | return -EINVAL; | |
1149 | ||
4c1bad6a JR |
1150 | if (!cpumask_intersects(mask, cpu_online_mask)) |
1151 | return -EINVAL; | |
1152 | ||
1153 | if (get_irte(irq, &irte)) | |
1154 | return -EBUSY; | |
1155 | ||
ff164324 AG |
1156 | err = assign_irq_vector(irq, cfg, mask); |
1157 | if (err) | |
1158 | return err; | |
4c1bad6a | 1159 | |
ff164324 AG |
1160 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); |
1161 | if (err) { | |
ed88bed8 | 1162 | if (assign_irq_vector(irq, cfg, data->affinity)) |
ff164324 AG |
1163 | pr_err("Failed to recover vector for irq %d\n", irq); |
1164 | return err; | |
1165 | } | |
4c1bad6a JR |
1166 | |
1167 | irte.vector = cfg->vector; | |
1168 | irte.dest_id = IRTE_DEST(dest); | |
1169 | ||
1170 | /* | |
1171 | * Atomically updates the IRTE with the new destination, vector | |
1172 | * and flushes the interrupt entry cache. | |
1173 | */ | |
1174 | modify_irte(irq, &irte); | |
1175 | ||
1176 | /* | |
1177 | * After this point, all the interrupts will start arriving | |
1178 | * at the new destination. So, time to cleanup the previous | |
1179 | * vector allocation. | |
1180 | */ | |
1181 | if (cfg->move_in_progress) | |
1182 | send_cleanup_vector(cfg); | |
1183 | ||
1184 | cpumask_copy(data->affinity, mask); | |
1185 | return 0; | |
1186 | } | |
0c3f173a | 1187 | |
5e2b930b JR |
1188 | static void intel_compose_msi_msg(struct pci_dev *pdev, |
1189 | unsigned int irq, unsigned int dest, | |
1190 | struct msi_msg *msg, u8 hpet_id) | |
1191 | { | |
1192 | struct irq_cfg *cfg; | |
1193 | struct irte irte; | |
c558df4a | 1194 | u16 sub_handle = 0; |
5e2b930b JR |
1195 | int ir_index; |
1196 | ||
91411da1 | 1197 | cfg = irq_cfg(irq); |
5e2b930b JR |
1198 | |
1199 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
1200 | BUG_ON(ir_index == -1); | |
1201 | ||
1202 | prepare_irte(&irte, cfg->vector, dest); | |
1203 | ||
1204 | /* Set source-id of interrupt request */ | |
1205 | if (pdev) | |
1206 | set_msi_sid(&irte, pdev); | |
1207 | else | |
1208 | set_hpet_sid(&irte, hpet_id); | |
1209 | ||
1210 | modify_irte(irq, &irte); | |
1211 | ||
1212 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1213 | msg->data = sub_handle; | |
1214 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1215 | MSI_ADDR_IR_SHV | | |
1216 | MSI_ADDR_IR_INDEX1(ir_index) | | |
1217 | MSI_ADDR_IR_INDEX2(ir_index); | |
1218 | } | |
1219 | ||
1220 | /* | |
1221 | * Map the PCI dev to the corresponding remapping hardware unit | |
1222 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
1223 | * in it. | |
1224 | */ | |
1225 | static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec) | |
1226 | { | |
1227 | struct intel_iommu *iommu; | |
1228 | int index; | |
1229 | ||
3a5670e8 | 1230 | down_read(&dmar_global_lock); |
5e2b930b JR |
1231 | iommu = map_dev_to_ir(dev); |
1232 | if (!iommu) { | |
9f10e5bf | 1233 | pr_err("Unable to map PCI %s to iommu\n", pci_name(dev)); |
3a5670e8 JL |
1234 | index = -ENOENT; |
1235 | } else { | |
1236 | index = alloc_irte(iommu, irq, nvec); | |
1237 | if (index < 0) { | |
9f10e5bf | 1238 | pr_err("Unable to allocate %d IRTE for PCI %s\n", |
3a5670e8 JL |
1239 | nvec, pci_name(dev)); |
1240 | index = -ENOSPC; | |
1241 | } | |
5e2b930b | 1242 | } |
3a5670e8 | 1243 | up_read(&dmar_global_lock); |
5e2b930b | 1244 | |
5e2b930b JR |
1245 | return index; |
1246 | } | |
1247 | ||
1248 | static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
1249 | int index, int sub_handle) | |
1250 | { | |
1251 | struct intel_iommu *iommu; | |
3a5670e8 | 1252 | int ret = -ENOENT; |
5e2b930b | 1253 | |
3a5670e8 | 1254 | down_read(&dmar_global_lock); |
5e2b930b | 1255 | iommu = map_dev_to_ir(pdev); |
3a5670e8 JL |
1256 | if (iommu) { |
1257 | /* | |
1258 | * setup the mapping between the irq and the IRTE | |
1259 | * base index, the sub_handle pointing to the | |
1260 | * appropriate interrupt remap table entry. | |
1261 | */ | |
1262 | set_irte_irq(irq, iommu, index, sub_handle); | |
1263 | ret = 0; | |
1264 | } | |
1265 | up_read(&dmar_global_lock); | |
5e2b930b | 1266 | |
3a5670e8 | 1267 | return ret; |
5e2b930b JR |
1268 | } |
1269 | ||
5fc24d8c | 1270 | static int intel_alloc_hpet_msi(unsigned int irq, unsigned int id) |
5e2b930b | 1271 | { |
3a5670e8 JL |
1272 | int ret = -1; |
1273 | struct intel_iommu *iommu; | |
5e2b930b JR |
1274 | int index; |
1275 | ||
3a5670e8 JL |
1276 | down_read(&dmar_global_lock); |
1277 | iommu = map_hpet_to_ir(id); | |
1278 | if (iommu) { | |
1279 | index = alloc_irte(iommu, irq, 1); | |
1280 | if (index >= 0) | |
1281 | ret = 0; | |
1282 | } | |
1283 | up_read(&dmar_global_lock); | |
5e2b930b | 1284 | |
3a5670e8 | 1285 | return ret; |
5e2b930b JR |
1286 | } |
1287 | ||
736baef4 | 1288 | struct irq_remap_ops intel_irq_remap_ops = { |
11190302 | 1289 | .prepare = intel_prepare_irq_remapping, |
95a02e97 SS |
1290 | .enable = intel_enable_irq_remapping, |
1291 | .disable = disable_irq_remapping, | |
1292 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 1293 | .enable_faulting = enable_drhd_fault_handling, |
0c3f173a | 1294 | .setup_ioapic_entry = intel_setup_ioapic_entry, |
4c1bad6a | 1295 | .set_affinity = intel_ioapic_set_affinity, |
9d619f65 | 1296 | .free_irq = free_irte, |
5e2b930b JR |
1297 | .compose_msi_msg = intel_compose_msi_msg, |
1298 | .msi_alloc_irq = intel_msi_alloc_irq, | |
1299 | .msi_setup_irq = intel_msi_setup_irq, | |
5fc24d8c | 1300 | .alloc_hpet_msi = intel_alloc_hpet_msi, |
736baef4 | 1301 | }; |
6b197249 | 1302 | |
a7a3dad9 JL |
1303 | /* |
1304 | * Support of Interrupt Remapping Unit Hotplug | |
1305 | */ | |
1306 | static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) | |
1307 | { | |
1308 | int ret; | |
1309 | int eim = x2apic_enabled(); | |
1310 | ||
1311 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
1312 | pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", | |
1313 | iommu->reg_phys, iommu->ecap); | |
1314 | return -ENODEV; | |
1315 | } | |
1316 | ||
1317 | if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { | |
1318 | pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", | |
1319 | iommu->reg_phys); | |
1320 | return -ENODEV; | |
1321 | } | |
1322 | ||
1323 | /* TODO: check all IOAPICs are covered by IOMMU */ | |
1324 | ||
1325 | /* Setup Interrupt-remapping now. */ | |
1326 | ret = intel_setup_irq_remapping(iommu); | |
1327 | if (ret) { | |
9e4e49df JR |
1328 | pr_err("Failed to setup irq remapping for %s\n", |
1329 | iommu->name); | |
a7a3dad9 JL |
1330 | intel_teardown_irq_remapping(iommu); |
1331 | ir_remove_ioapic_hpet_scope(iommu); | |
9e4e49df | 1332 | } else { |
d4d1c0f3 | 1333 | iommu_enable_irq_remapping(iommu); |
a7a3dad9 JL |
1334 | } |
1335 | ||
1336 | return ret; | |
1337 | } | |
1338 | ||
6b197249 JL |
1339 | int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
1340 | { | |
a7a3dad9 JL |
1341 | int ret = 0; |
1342 | struct intel_iommu *iommu = dmaru->iommu; | |
1343 | ||
1344 | if (!irq_remapping_enabled) | |
1345 | return 0; | |
1346 | if (iommu == NULL) | |
1347 | return -EINVAL; | |
1348 | if (!ecap_ir_support(iommu->ecap)) | |
1349 | return 0; | |
1350 | ||
1351 | if (insert) { | |
1352 | if (!iommu->ir_table) | |
1353 | ret = dmar_ir_add(dmaru, iommu); | |
1354 | } else { | |
1355 | if (iommu->ir_table) { | |
1356 | if (!bitmap_empty(iommu->ir_table->bitmap, | |
1357 | INTR_REMAP_TABLE_ENTRIES)) { | |
1358 | ret = -EBUSY; | |
1359 | } else { | |
1360 | iommu_disable_irq_remapping(iommu); | |
1361 | intel_teardown_irq_remapping(iommu); | |
1362 | ir_remove_ioapic_hpet_scope(iommu); | |
1363 | } | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | return ret; | |
6b197249 | 1368 | } |