Commit | Line | Data |
---|---|---|
5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
ad3ad3f6 | 9 | #include <asm/io_apic.h> |
17483a1f | 10 | #include <asm/smp.h> |
6d652ea1 | 11 | #include <asm/cpu.h> |
38717946 | 12 | #include <linux/intel-iommu.h> |
46f06b72 | 13 | #include <acpi/acpi.h> |
8a8f422d | 14 | #include <asm/irq_remapping.h> |
f007e99c | 15 | #include <asm/pci-direct.h> |
5e2b930b | 16 | #include <asm/msidef.h> |
ad3ad3f6 | 17 | |
8a8f422d | 18 | #include "irq_remapping.h" |
736baef4 | 19 | |
eef93fdb JR |
20 | struct ioapic_scope { |
21 | struct intel_iommu *iommu; | |
22 | unsigned int id; | |
23 | unsigned int bus; /* PCI bus number */ | |
24 | unsigned int devfn; /* PCI devfn number */ | |
25 | }; | |
26 | ||
27 | struct hpet_scope { | |
28 | struct intel_iommu *iommu; | |
29 | u8 id; | |
30 | unsigned int bus; | |
31 | unsigned int devfn; | |
32 | }; | |
33 | ||
34 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
0c3f173a | 35 | #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) |
eef93fdb | 36 | |
ad3ad3f6 | 37 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b SS |
38 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
39 | static int ir_ioapic_num, ir_hpet_num; | |
d1423d56 | 40 | |
96f8e98b | 41 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 42 | |
694835dc JL |
43 | static int __init parse_ioapics_under_ir(void); |
44 | ||
e420dfb4 YL |
45 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
46 | { | |
dced35ae | 47 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
349d6767 | 48 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
49 | } |
50 | ||
6a7885c4 | 51 | static int get_irte(int irq, struct irte *entry) |
b6fcb33a | 52 | { |
d585d060 | 53 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 54 | unsigned long flags; |
d585d060 | 55 | int index; |
b6fcb33a | 56 | |
d585d060 | 57 | if (!entry || !irq_iommu) |
b6fcb33a SS |
58 | return -1; |
59 | ||
96f8e98b | 60 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 61 | |
e420dfb4 YL |
62 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
63 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 64 | |
96f8e98b | 65 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
66 | return 0; |
67 | } | |
68 | ||
263b5e86 | 69 | static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
b6fcb33a SS |
70 | { |
71 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 72 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
9b1b0e42 | 73 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
b6fcb33a SS |
74 | u16 index, start_index; |
75 | unsigned int mask = 0; | |
4c5502b1 | 76 | unsigned long flags; |
b6fcb33a | 77 | |
d585d060 | 78 | if (!count || !irq_iommu) |
e420dfb4 | 79 | return -1; |
e420dfb4 | 80 | |
b6fcb33a SS |
81 | /* |
82 | * start the IRTE search from index 0. | |
83 | */ | |
84 | index = start_index = 0; | |
85 | ||
86 | if (count > 1) { | |
87 | count = __roundup_pow_of_two(count); | |
88 | mask = ilog2(count); | |
89 | } | |
90 | ||
91 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
92 | printk(KERN_ERR | |
93 | "Requested mask %x exceeds the max invalidation handle" | |
94 | " mask value %Lx\n", mask, | |
95 | ecap_max_handle_mask(iommu->ecap)); | |
96 | return -1; | |
97 | } | |
98 | ||
96f8e98b | 99 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
100 | index = bitmap_find_free_region(table->bitmap, |
101 | INTR_REMAP_TABLE_ENTRIES, mask); | |
102 | if (index < 0) { | |
103 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
104 | } else { | |
105 | cfg->remapped = 1; | |
106 | irq_iommu->iommu = iommu; | |
107 | irq_iommu->irte_index = index; | |
108 | irq_iommu->sub_handle = 0; | |
109 | irq_iommu->irte_mask = mask; | |
110 | } | |
96f8e98b | 111 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
112 | |
113 | return index; | |
114 | } | |
115 | ||
704126ad | 116 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
117 | { |
118 | struct qi_desc desc; | |
119 | ||
120 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
121 | | QI_IEC_SELECTIVE; | |
122 | desc.high = 0; | |
123 | ||
704126ad | 124 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
125 | } |
126 | ||
263b5e86 | 127 | static int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
b6fcb33a | 128 | { |
d585d060 | 129 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 130 | unsigned long flags; |
d585d060 | 131 | int index; |
b6fcb33a | 132 | |
d585d060 | 133 | if (!irq_iommu) |
b6fcb33a | 134 | return -1; |
b6fcb33a | 135 | |
96f8e98b | 136 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
137 | *sub_handle = irq_iommu->sub_handle; |
138 | index = irq_iommu->irte_index; | |
96f8e98b | 139 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
140 | return index; |
141 | } | |
142 | ||
263b5e86 | 143 | static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
b6fcb33a | 144 | { |
d585d060 | 145 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
9b1b0e42 | 146 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
4c5502b1 | 147 | unsigned long flags; |
e420dfb4 | 148 | |
d585d060 | 149 | if (!irq_iommu) |
0b8f1efa | 150 | return -1; |
d585d060 | 151 | |
96f8e98b | 152 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 153 | |
9b1b0e42 | 154 | cfg->remapped = 1; |
e420dfb4 YL |
155 | irq_iommu->iommu = iommu; |
156 | irq_iommu->irte_index = index; | |
157 | irq_iommu->sub_handle = subhandle; | |
158 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 159 | |
96f8e98b | 160 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
161 | |
162 | return 0; | |
163 | } | |
164 | ||
263b5e86 | 165 | static int modify_irte(int irq, struct irte *irte_modified) |
b6fcb33a | 166 | { |
d585d060 | 167 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 168 | struct intel_iommu *iommu; |
4c5502b1 | 169 | unsigned long flags; |
d585d060 TG |
170 | struct irte *irte; |
171 | int rc, index; | |
b6fcb33a | 172 | |
d585d060 | 173 | if (!irq_iommu) |
b6fcb33a | 174 | return -1; |
d585d060 | 175 | |
96f8e98b | 176 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 177 | |
e420dfb4 | 178 | iommu = irq_iommu->iommu; |
b6fcb33a | 179 | |
e420dfb4 | 180 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
181 | irte = &iommu->ir_table->base[index]; |
182 | ||
c513b67e LT |
183 | set_64bit(&irte->low, irte_modified->low); |
184 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
185 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
186 | ||
704126ad | 187 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 188 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
189 | |
190 | return rc; | |
b6fcb33a SS |
191 | } |
192 | ||
263b5e86 | 193 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
194 | { |
195 | int i; | |
196 | ||
197 | for (i = 0; i < MAX_HPET_TBS; i++) | |
198 | if (ir_hpet[i].id == hpet_id) | |
199 | return ir_hpet[i].iommu; | |
200 | return NULL; | |
201 | } | |
202 | ||
263b5e86 | 203 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
204 | { |
205 | int i; | |
206 | ||
207 | for (i = 0; i < MAX_IO_APICS; i++) | |
208 | if (ir_ioapic[i].id == apic) | |
209 | return ir_ioapic[i].iommu; | |
210 | return NULL; | |
211 | } | |
212 | ||
263b5e86 | 213 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
214 | { |
215 | struct dmar_drhd_unit *drhd; | |
216 | ||
217 | drhd = dmar_find_matched_drhd_unit(dev); | |
218 | if (!drhd) | |
219 | return NULL; | |
220 | ||
221 | return drhd->iommu; | |
222 | } | |
223 | ||
c4658b4e WH |
224 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
225 | { | |
226 | struct irte *start, *entry, *end; | |
227 | struct intel_iommu *iommu; | |
228 | int index; | |
229 | ||
230 | if (irq_iommu->sub_handle) | |
231 | return 0; | |
232 | ||
233 | iommu = irq_iommu->iommu; | |
234 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
235 | ||
236 | start = iommu->ir_table->base + index; | |
237 | end = start + (1 << irq_iommu->irte_mask); | |
238 | ||
239 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
240 | set_64bit(&entry->low, 0); |
241 | set_64bit(&entry->high, 0); | |
c4658b4e | 242 | } |
360eb3c5 JL |
243 | bitmap_release_region(iommu->ir_table->bitmap, index, |
244 | irq_iommu->irte_mask); | |
c4658b4e WH |
245 | |
246 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
247 | } | |
248 | ||
9d619f65 | 249 | static int free_irte(int irq) |
b6fcb33a | 250 | { |
d585d060 | 251 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 252 | unsigned long flags; |
d585d060 | 253 | int rc; |
b6fcb33a | 254 | |
d585d060 | 255 | if (!irq_iommu) |
b6fcb33a | 256 | return -1; |
d585d060 | 257 | |
96f8e98b | 258 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 259 | |
c4658b4e | 260 | rc = clear_entries(irq_iommu); |
b6fcb33a | 261 | |
e420dfb4 YL |
262 | irq_iommu->iommu = NULL; |
263 | irq_iommu->irte_index = 0; | |
264 | irq_iommu->sub_handle = 0; | |
265 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 266 | |
96f8e98b | 267 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 268 | |
704126ad | 269 | return rc; |
b6fcb33a SS |
270 | } |
271 | ||
f007e99c WH |
272 | /* |
273 | * source validation type | |
274 | */ | |
275 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 276 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
277 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
278 | ||
279 | /* | |
280 | * source-id qualifier | |
281 | */ | |
282 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
283 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
284 | * the third least significant bit | |
285 | */ | |
286 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
287 | * the second and third least significant bits | |
288 | */ | |
289 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
290 | * the least three significant bits | |
291 | */ | |
292 | ||
293 | /* | |
294 | * set SVT, SQ and SID fields of irte to verify | |
295 | * source ids of interrupt requests | |
296 | */ | |
297 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
298 | unsigned int sq, unsigned int sid) | |
299 | { | |
d1423d56 CW |
300 | if (disable_sourceid_checking) |
301 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
302 | irte->svt = svt; |
303 | irte->sq = sq; | |
304 | irte->sid = sid; | |
305 | } | |
306 | ||
263b5e86 | 307 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
308 | { |
309 | int i; | |
310 | u16 sid = 0; | |
311 | ||
312 | if (!irte) | |
313 | return -1; | |
314 | ||
315 | for (i = 0; i < MAX_IO_APICS; i++) { | |
316 | if (ir_ioapic[i].id == apic) { | |
317 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
318 | break; | |
319 | } | |
320 | } | |
321 | ||
322 | if (sid == 0) { | |
323 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
324 | return -1; | |
325 | } | |
326 | ||
2fe2c602 | 327 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
263b5e86 | 332 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
333 | { |
334 | int i; | |
335 | u16 sid = 0; | |
336 | ||
337 | if (!irte) | |
338 | return -1; | |
339 | ||
340 | for (i = 0; i < MAX_HPET_TBS; i++) { | |
341 | if (ir_hpet[i].id == id) { | |
342 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; | |
343 | break; | |
344 | } | |
345 | } | |
346 | ||
347 | if (sid == 0) { | |
348 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
349 | return -1; | |
350 | } | |
351 | ||
352 | /* | |
353 | * Should really use SQ_ALL_16. Some platforms are broken. | |
354 | * While we figure out the right quirks for these broken platforms, use | |
355 | * SQ_13_IGNORE_3 for now. | |
356 | */ | |
357 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
263b5e86 | 362 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c WH |
363 | { |
364 | struct pci_dev *bridge; | |
365 | ||
366 | if (!irte || !dev) | |
367 | return -1; | |
368 | ||
369 | /* PCIe device or Root Complex integrated PCI device */ | |
5f4d91a1 | 370 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
f007e99c WH |
371 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
372 | (dev->bus->number << 8) | dev->devfn); | |
373 | return 0; | |
374 | } | |
375 | ||
376 | bridge = pci_find_upstream_pcie_bridge(dev); | |
377 | if (bridge) { | |
45e829ea | 378 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
f007e99c WH |
379 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
380 | (bridge->bus->number << 8) | dev->bus->number); | |
381 | else /* this is a legacy PCI bridge */ | |
382 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
383 | (bridge->bus->number << 8) | bridge->devfn); | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
95a02e97 | 389 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
390 | { |
391 | u64 addr; | |
c416daa9 | 392 | u32 sts; |
2ae21010 SS |
393 | unsigned long flags; |
394 | ||
395 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
396 | ||
1f5b3c3f | 397 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
398 | |
399 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
400 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
401 | ||
402 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 403 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 404 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
405 | |
406 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
407 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 408 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
409 | |
410 | /* | |
411 | * global invalidation of interrupt entry cache before enabling | |
412 | * interrupt-remapping. | |
413 | */ | |
414 | qi_global_iec(iommu); | |
415 | ||
1f5b3c3f | 416 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
417 | |
418 | /* Enable interrupt-remapping */ | |
2ae21010 | 419 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 420 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 421 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
422 | |
423 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
424 | readl, (sts & DMA_GSTS_IRES), sts); | |
425 | ||
af8d102f AL |
426 | /* |
427 | * With CFI clear in the Global Command register, we should be | |
428 | * protected from dangerous (i.e. compatibility) interrupts | |
429 | * regardless of x2apic status. Check just to be sure. | |
430 | */ | |
431 | if (sts & DMA_GSTS_CFIS) | |
432 | WARN(1, KERN_WARNING | |
433 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
434 | "you are vulnerable to IRQ injection.\n"); | |
435 | ||
1f5b3c3f | 436 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
437 | } |
438 | ||
439 | ||
95a02e97 | 440 | static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
441 | { |
442 | struct ir_table *ir_table; | |
443 | struct page *pages; | |
360eb3c5 | 444 | unsigned long *bitmap; |
2ae21010 SS |
445 | |
446 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 447 | GFP_ATOMIC); |
2ae21010 SS |
448 | |
449 | if (!iommu->ir_table) | |
450 | return -ENOMEM; | |
451 | ||
824cd75b SS |
452 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
453 | INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
454 | |
455 | if (!pages) { | |
360eb3c5 JL |
456 | pr_err("IR%d: failed to allocate pages of order %d\n", |
457 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
458 | kfree(iommu->ir_table); |
459 | return -ENOMEM; | |
460 | } | |
461 | ||
360eb3c5 JL |
462 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
463 | sizeof(long), GFP_ATOMIC); | |
464 | if (bitmap == NULL) { | |
465 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
466 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
467 | kfree(ir_table); | |
468 | return -ENOMEM; | |
469 | } | |
470 | ||
2ae21010 | 471 | ir_table->base = page_address(pages); |
360eb3c5 | 472 | ir_table->bitmap = bitmap; |
2ae21010 | 473 | |
95a02e97 | 474 | iommu_set_irq_remapping(iommu, mode); |
2ae21010 SS |
475 | return 0; |
476 | } | |
477 | ||
eba67e5d SS |
478 | /* |
479 | * Disable Interrupt Remapping. | |
480 | */ | |
95a02e97 | 481 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
482 | { |
483 | unsigned long flags; | |
484 | u32 sts; | |
485 | ||
486 | if (!ecap_ir_support(iommu->ecap)) | |
487 | return; | |
488 | ||
b24696bc FY |
489 | /* |
490 | * global invalidation of interrupt entry cache before disabling | |
491 | * interrupt-remapping. | |
492 | */ | |
493 | qi_global_iec(iommu); | |
494 | ||
1f5b3c3f | 495 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
496 | |
497 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
498 | if (!(sts & DMA_GSTS_IRES)) | |
499 | goto end; | |
500 | ||
501 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
502 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
503 | ||
504 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
505 | readl, !(sts & DMA_GSTS_IRES), sts); | |
506 | ||
507 | end: | |
1f5b3c3f | 508 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
509 | } |
510 | ||
41750d31 SS |
511 | static int __init dmar_x2apic_optout(void) |
512 | { | |
513 | struct acpi_table_dmar *dmar; | |
514 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
515 | if (!dmar || no_x2apic_optout) | |
516 | return 0; | |
517 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
518 | } | |
519 | ||
95a02e97 | 520 | static int __init intel_irq_remapping_supported(void) |
93758238 WH |
521 | { |
522 | struct dmar_drhd_unit *drhd; | |
7c919779 | 523 | struct intel_iommu *iommu; |
93758238 | 524 | |
95a02e97 | 525 | if (disable_irq_remap) |
03ea8155 | 526 | return 0; |
03bbcb2e | 527 | if (irq_remap_broken) { |
05104a4e NH |
528 | printk(KERN_WARNING |
529 | "This system BIOS has enabled interrupt remapping\n" | |
530 | "on a chipset that contains an erratum making that\n" | |
531 | "feature unstable. To maintain system stability\n" | |
532 | "interrupt remapping is being disabled. Please\n" | |
533 | "contact your BIOS vendor for an update\n"); | |
534 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
03bbcb2e NH |
535 | disable_irq_remap = 1; |
536 | return 0; | |
537 | } | |
03ea8155 | 538 | |
074835f0 YS |
539 | if (!dmar_ir_support()) |
540 | return 0; | |
541 | ||
7c919779 | 542 | for_each_iommu(iommu, drhd) |
93758238 WH |
543 | if (!ecap_ir_support(iommu->ecap)) |
544 | return 0; | |
93758238 WH |
545 | |
546 | return 1; | |
547 | } | |
548 | ||
95a02e97 | 549 | static int __init intel_enable_irq_remapping(void) |
2ae21010 SS |
550 | { |
551 | struct dmar_drhd_unit *drhd; | |
7c919779 | 552 | struct intel_iommu *iommu; |
af8d102f | 553 | bool x2apic_present; |
2ae21010 | 554 | int setup = 0; |
41750d31 | 555 | int eim = 0; |
2ae21010 | 556 | |
af8d102f AL |
557 | x2apic_present = x2apic_supported(); |
558 | ||
e936d077 YS |
559 | if (parse_ioapics_under_ir() != 1) { |
560 | printk(KERN_INFO "Not enable interrupt remapping\n"); | |
af8d102f | 561 | goto error; |
e936d077 YS |
562 | } |
563 | ||
af8d102f | 564 | if (x2apic_present) { |
b977e73a JL |
565 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); |
566 | ||
41750d31 | 567 | eim = !dmar_x2apic_optout(); |
af8d102f AL |
568 | if (!eim) |
569 | printk(KERN_WARNING | |
570 | "Your BIOS is broken and requested that x2apic be disabled.\n" | |
571 | "This will slightly decrease performance.\n" | |
572 | "Use 'intremap=no_x2apic_optout' to override BIOS request.\n"); | |
41750d31 SS |
573 | } |
574 | ||
7c919779 | 575 | for_each_iommu(iommu, drhd) { |
34aaaa94 HW |
576 | /* |
577 | * If the queued invalidation is already initialized, | |
578 | * shouldn't disable it. | |
579 | */ | |
580 | if (iommu->qi) | |
581 | continue; | |
582 | ||
1531a6a6 SS |
583 | /* |
584 | * Clear previous faults. | |
585 | */ | |
586 | dmar_fault(-1, iommu); | |
587 | ||
588 | /* | |
589 | * Disable intr remapping and queued invalidation, if already | |
590 | * enabled prior to OS handover. | |
591 | */ | |
95a02e97 | 592 | iommu_disable_irq_remapping(iommu); |
1531a6a6 SS |
593 | |
594 | dmar_disable_qi(iommu); | |
595 | } | |
596 | ||
2ae21010 SS |
597 | /* |
598 | * check for the Interrupt-remapping support | |
599 | */ | |
7c919779 | 600 | for_each_iommu(iommu, drhd) { |
2ae21010 SS |
601 | if (!ecap_ir_support(iommu->ecap)) |
602 | continue; | |
603 | ||
604 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
605 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
606 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
af8d102f | 607 | goto error; |
2ae21010 SS |
608 | } |
609 | } | |
610 | ||
611 | /* | |
612 | * Enable queued invalidation for all the DRHD's. | |
613 | */ | |
7c919779 JL |
614 | for_each_iommu(iommu, drhd) { |
615 | int ret = dmar_enable_qi(iommu); | |
2ae21010 SS |
616 | |
617 | if (ret) { | |
618 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
619 | " invalidation, ecap %Lx, ret %d\n", | |
620 | drhd->reg_base_addr, iommu->ecap, ret); | |
af8d102f | 621 | goto error; |
2ae21010 SS |
622 | } |
623 | } | |
624 | ||
625 | /* | |
626 | * Setup Interrupt-remapping for all the DRHD's now. | |
627 | */ | |
7c919779 | 628 | for_each_iommu(iommu, drhd) { |
2ae21010 SS |
629 | if (!ecap_ir_support(iommu->ecap)) |
630 | continue; | |
631 | ||
95a02e97 | 632 | if (intel_setup_irq_remapping(iommu, eim)) |
2ae21010 SS |
633 | goto error; |
634 | ||
635 | setup = 1; | |
636 | } | |
637 | ||
638 | if (!setup) | |
639 | goto error; | |
640 | ||
95a02e97 | 641 | irq_remapping_enabled = 1; |
afcc8a40 JR |
642 | |
643 | /* | |
644 | * VT-d has a different layout for IO-APIC entries when | |
645 | * interrupt remapping is enabled. So it needs a special routine | |
646 | * to print IO-APIC entries for debugging purposes too. | |
647 | */ | |
648 | x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries; | |
649 | ||
41750d31 | 650 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 651 | |
41750d31 | 652 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
653 | |
654 | error: | |
655 | /* | |
656 | * handle error condition gracefully here! | |
657 | */ | |
af8d102f AL |
658 | |
659 | if (x2apic_present) | |
d01140df | 660 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); |
af8d102f | 661 | |
2ae21010 SS |
662 | return -1; |
663 | } | |
ad3ad3f6 | 664 | |
20f3097b SS |
665 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
666 | struct intel_iommu *iommu) | |
667 | { | |
668 | struct acpi_dmar_pci_path *path; | |
669 | u8 bus; | |
670 | int count; | |
671 | ||
672 | bus = scope->bus; | |
673 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
674 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
675 | / sizeof(struct acpi_dmar_pci_path); | |
676 | ||
677 | while (--count > 0) { | |
678 | /* | |
679 | * Access PCI directly due to the PCI | |
680 | * subsystem isn't initialized yet. | |
681 | */ | |
fa5f508f | 682 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
683 | PCI_SECONDARY_BUS); |
684 | path++; | |
685 | } | |
686 | ir_hpet[ir_hpet_num].bus = bus; | |
fa5f508f | 687 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->device, path->function); |
20f3097b SS |
688 | ir_hpet[ir_hpet_num].iommu = iommu; |
689 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; | |
690 | ir_hpet_num++; | |
691 | } | |
692 | ||
f007e99c WH |
693 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
694 | struct intel_iommu *iommu) | |
695 | { | |
696 | struct acpi_dmar_pci_path *path; | |
697 | u8 bus; | |
698 | int count; | |
699 | ||
700 | bus = scope->bus; | |
701 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
702 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
703 | / sizeof(struct acpi_dmar_pci_path); | |
704 | ||
705 | while (--count > 0) { | |
706 | /* | |
707 | * Access PCI directly due to the PCI | |
708 | * subsystem isn't initialized yet. | |
709 | */ | |
fa5f508f | 710 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
711 | PCI_SECONDARY_BUS); |
712 | path++; | |
713 | } | |
714 | ||
715 | ir_ioapic[ir_ioapic_num].bus = bus; | |
fa5f508f | 716 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->device, path->function); |
f007e99c WH |
717 | ir_ioapic[ir_ioapic_num].iommu = iommu; |
718 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
719 | ir_ioapic_num++; | |
720 | } | |
721 | ||
20f3097b SS |
722 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
723 | struct intel_iommu *iommu) | |
ad3ad3f6 SS |
724 | { |
725 | struct acpi_dmar_hardware_unit *drhd; | |
726 | struct acpi_dmar_device_scope *scope; | |
727 | void *start, *end; | |
728 | ||
729 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
730 | ||
731 | start = (void *)(drhd + 1); | |
732 | end = ((void *)drhd) + header->length; | |
733 | ||
734 | while (start < end) { | |
735 | scope = start; | |
736 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
737 | if (ir_ioapic_num == MAX_IO_APICS) { | |
738 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
739 | return -1; | |
740 | } | |
741 | ||
680a7524 YL |
742 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
743 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, | |
744 | drhd->address, iommu->seq_id); | |
ad3ad3f6 | 745 | |
f007e99c | 746 | ir_parse_one_ioapic_scope(scope, iommu); |
20f3097b SS |
747 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
748 | if (ir_hpet_num == MAX_HPET_TBS) { | |
749 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); | |
750 | return -1; | |
751 | } | |
752 | ||
753 | printk(KERN_INFO "HPET id %d under DRHD base" | |
754 | " 0x%Lx\n", scope->enumeration_id, | |
755 | drhd->address); | |
756 | ||
757 | ir_parse_one_hpet_scope(scope, iommu); | |
ad3ad3f6 SS |
758 | } |
759 | start += scope->length; | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /* | |
766 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
767 | * hardware unit. | |
768 | */ | |
694835dc | 769 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
770 | { |
771 | struct dmar_drhd_unit *drhd; | |
7c919779 | 772 | struct intel_iommu *iommu; |
ad3ad3f6 | 773 | int ir_supported = 0; |
32ab31e0 | 774 | int ioapic_idx; |
ad3ad3f6 | 775 | |
7c919779 | 776 | for_each_iommu(iommu, drhd) |
ad3ad3f6 | 777 | if (ecap_ir_support(iommu->ecap)) { |
20f3097b | 778 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
779 | return -1; |
780 | ||
781 | ir_supported = 1; | |
782 | } | |
ad3ad3f6 | 783 | |
32ab31e0 SF |
784 | if (!ir_supported) |
785 | return 0; | |
786 | ||
787 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
788 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
789 | if (!map_ioapic_to_ir(ioapic_id)) { | |
790 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
791 | "interrupt remapping will be disabled\n", | |
792 | ioapic_id); | |
793 | return -1; | |
794 | } | |
ad3ad3f6 SS |
795 | } |
796 | ||
32ab31e0 | 797 | return 1; |
ad3ad3f6 | 798 | } |
b24696bc | 799 | |
6a7885c4 | 800 | static int __init ir_dev_scope_init(void) |
c2c7286a | 801 | { |
95a02e97 | 802 | if (!irq_remapping_enabled) |
c2c7286a SS |
803 | return 0; |
804 | ||
805 | return dmar_dev_scope_init(); | |
806 | } | |
807 | rootfs_initcall(ir_dev_scope_init); | |
808 | ||
95a02e97 | 809 | static void disable_irq_remapping(void) |
b24696bc FY |
810 | { |
811 | struct dmar_drhd_unit *drhd; | |
812 | struct intel_iommu *iommu = NULL; | |
813 | ||
814 | /* | |
815 | * Disable Interrupt-remapping for all the DRHD's now. | |
816 | */ | |
817 | for_each_iommu(iommu, drhd) { | |
818 | if (!ecap_ir_support(iommu->ecap)) | |
819 | continue; | |
820 | ||
95a02e97 | 821 | iommu_disable_irq_remapping(iommu); |
b24696bc FY |
822 | } |
823 | } | |
824 | ||
95a02e97 | 825 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
826 | { |
827 | struct dmar_drhd_unit *drhd; | |
828 | int setup = 0; | |
829 | struct intel_iommu *iommu = NULL; | |
830 | ||
831 | for_each_iommu(iommu, drhd) | |
832 | if (iommu->qi) | |
833 | dmar_reenable_qi(iommu); | |
834 | ||
835 | /* | |
836 | * Setup Interrupt-remapping for all the DRHD's now. | |
837 | */ | |
838 | for_each_iommu(iommu, drhd) { | |
839 | if (!ecap_ir_support(iommu->ecap)) | |
840 | continue; | |
841 | ||
842 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 843 | iommu_set_irq_remapping(iommu, eim); |
b24696bc FY |
844 | setup = 1; |
845 | } | |
846 | ||
847 | if (!setup) | |
848 | goto error; | |
849 | ||
850 | return 0; | |
851 | ||
852 | error: | |
853 | /* | |
854 | * handle error condition gracefully here! | |
855 | */ | |
856 | return -1; | |
857 | } | |
858 | ||
0c3f173a JR |
859 | static void prepare_irte(struct irte *irte, int vector, |
860 | unsigned int dest) | |
861 | { | |
862 | memset(irte, 0, sizeof(*irte)); | |
863 | ||
864 | irte->present = 1; | |
865 | irte->dst_mode = apic->irq_dest_mode; | |
866 | /* | |
867 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
868 | * actual level or edge trigger will be setup in the IO-APIC | |
869 | * RTE. This will help simplify level triggered irq migration. | |
870 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
871 | * irq migration in the presence of interrupt-remapping. | |
872 | */ | |
873 | irte->trigger_mode = 0; | |
874 | irte->dlvry_mode = apic->irq_delivery_mode; | |
875 | irte->vector = vector; | |
876 | irte->dest_id = IRTE_DEST(dest); | |
877 | irte->redir_hint = 1; | |
878 | } | |
879 | ||
880 | static int intel_setup_ioapic_entry(int irq, | |
881 | struct IO_APIC_route_entry *route_entry, | |
882 | unsigned int destination, int vector, | |
883 | struct io_apic_irq_attr *attr) | |
884 | { | |
885 | int ioapic_id = mpc_ioapic_id(attr->ioapic); | |
886 | struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id); | |
887 | struct IR_IO_APIC_route_entry *entry; | |
888 | struct irte irte; | |
889 | int index; | |
890 | ||
891 | if (!iommu) { | |
892 | pr_warn("No mapping iommu for ioapic %d\n", ioapic_id); | |
893 | return -ENODEV; | |
894 | } | |
895 | ||
896 | entry = (struct IR_IO_APIC_route_entry *)route_entry; | |
897 | ||
898 | index = alloc_irte(iommu, irq, 1); | |
899 | if (index < 0) { | |
900 | pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id); | |
901 | return -ENOMEM; | |
902 | } | |
903 | ||
904 | prepare_irte(&irte, vector, destination); | |
905 | ||
906 | /* Set source-id of interrupt request */ | |
907 | set_ioapic_sid(&irte, ioapic_id); | |
908 | ||
909 | modify_irte(irq, &irte); | |
910 | ||
911 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " | |
912 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
913 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
914 | "Avail:%X Vector:%02X Dest:%08X " | |
915 | "SID:%04X SQ:%X SVT:%X)\n", | |
916 | attr->ioapic, irte.present, irte.fpd, irte.dst_mode, | |
917 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, | |
918 | irte.avail, irte.vector, irte.dest_id, | |
919 | irte.sid, irte.sq, irte.svt); | |
920 | ||
921 | memset(entry, 0, sizeof(*entry)); | |
922 | ||
923 | entry->index2 = (index >> 15) & 0x1; | |
924 | entry->zero = 0; | |
925 | entry->format = 1; | |
926 | entry->index = (index & 0x7fff); | |
927 | /* | |
928 | * IO-APIC RTE will be configured with virtual vector. | |
929 | * irq handler will do the explicit EOI to the io-apic. | |
930 | */ | |
931 | entry->vector = attr->ioapic_pin; | |
932 | entry->mask = 0; /* enable IRQ */ | |
933 | entry->trigger = attr->trigger; | |
934 | entry->polarity = attr->polarity; | |
935 | ||
936 | /* Mask level triggered irqs. | |
937 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
938 | */ | |
939 | if (attr->trigger) | |
940 | entry->mask = 1; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
4c1bad6a JR |
945 | /* |
946 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
947 | * | |
948 | * For both level and edge triggered, irq migration is a simple atomic | |
949 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
950 | * | |
951 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
952 | * updated vector information), by using a virtual vector (io-apic pin number). | |
953 | * Real vector that is used for interrupting cpu will be coming from | |
954 | * the interrupt-remapping table entry. | |
955 | * | |
956 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
957 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
958 | */ | |
959 | static int | |
960 | intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
961 | bool force) | |
962 | { | |
963 | struct irq_cfg *cfg = data->chip_data; | |
964 | unsigned int dest, irq = data->irq; | |
965 | struct irte irte; | |
ff164324 | 966 | int err; |
4c1bad6a | 967 | |
7eb9ae07 SS |
968 | if (!config_enabled(CONFIG_SMP)) |
969 | return -EINVAL; | |
970 | ||
4c1bad6a JR |
971 | if (!cpumask_intersects(mask, cpu_online_mask)) |
972 | return -EINVAL; | |
973 | ||
974 | if (get_irte(irq, &irte)) | |
975 | return -EBUSY; | |
976 | ||
ff164324 AG |
977 | err = assign_irq_vector(irq, cfg, mask); |
978 | if (err) | |
979 | return err; | |
4c1bad6a | 980 | |
ff164324 AG |
981 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); |
982 | if (err) { | |
ed88bed8 | 983 | if (assign_irq_vector(irq, cfg, data->affinity)) |
ff164324 AG |
984 | pr_err("Failed to recover vector for irq %d\n", irq); |
985 | return err; | |
986 | } | |
4c1bad6a JR |
987 | |
988 | irte.vector = cfg->vector; | |
989 | irte.dest_id = IRTE_DEST(dest); | |
990 | ||
991 | /* | |
992 | * Atomically updates the IRTE with the new destination, vector | |
993 | * and flushes the interrupt entry cache. | |
994 | */ | |
995 | modify_irte(irq, &irte); | |
996 | ||
997 | /* | |
998 | * After this point, all the interrupts will start arriving | |
999 | * at the new destination. So, time to cleanup the previous | |
1000 | * vector allocation. | |
1001 | */ | |
1002 | if (cfg->move_in_progress) | |
1003 | send_cleanup_vector(cfg); | |
1004 | ||
1005 | cpumask_copy(data->affinity, mask); | |
1006 | return 0; | |
1007 | } | |
0c3f173a | 1008 | |
5e2b930b JR |
1009 | static void intel_compose_msi_msg(struct pci_dev *pdev, |
1010 | unsigned int irq, unsigned int dest, | |
1011 | struct msi_msg *msg, u8 hpet_id) | |
1012 | { | |
1013 | struct irq_cfg *cfg; | |
1014 | struct irte irte; | |
c558df4a | 1015 | u16 sub_handle = 0; |
5e2b930b JR |
1016 | int ir_index; |
1017 | ||
1018 | cfg = irq_get_chip_data(irq); | |
1019 | ||
1020 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
1021 | BUG_ON(ir_index == -1); | |
1022 | ||
1023 | prepare_irte(&irte, cfg->vector, dest); | |
1024 | ||
1025 | /* Set source-id of interrupt request */ | |
1026 | if (pdev) | |
1027 | set_msi_sid(&irte, pdev); | |
1028 | else | |
1029 | set_hpet_sid(&irte, hpet_id); | |
1030 | ||
1031 | modify_irte(irq, &irte); | |
1032 | ||
1033 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1034 | msg->data = sub_handle; | |
1035 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1036 | MSI_ADDR_IR_SHV | | |
1037 | MSI_ADDR_IR_INDEX1(ir_index) | | |
1038 | MSI_ADDR_IR_INDEX2(ir_index); | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * Map the PCI dev to the corresponding remapping hardware unit | |
1043 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
1044 | * in it. | |
1045 | */ | |
1046 | static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec) | |
1047 | { | |
1048 | struct intel_iommu *iommu; | |
1049 | int index; | |
1050 | ||
1051 | iommu = map_dev_to_ir(dev); | |
1052 | if (!iommu) { | |
1053 | printk(KERN_ERR | |
1054 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
1055 | return -ENOENT; | |
1056 | } | |
1057 | ||
1058 | index = alloc_irte(iommu, irq, nvec); | |
1059 | if (index < 0) { | |
1060 | printk(KERN_ERR | |
1061 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
1062 | pci_name(dev)); | |
1063 | return -ENOSPC; | |
1064 | } | |
1065 | return index; | |
1066 | } | |
1067 | ||
1068 | static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
1069 | int index, int sub_handle) | |
1070 | { | |
1071 | struct intel_iommu *iommu; | |
1072 | ||
1073 | iommu = map_dev_to_ir(pdev); | |
1074 | if (!iommu) | |
1075 | return -ENOENT; | |
1076 | /* | |
1077 | * setup the mapping between the irq and the IRTE | |
1078 | * base index, the sub_handle pointing to the | |
1079 | * appropriate interrupt remap table entry. | |
1080 | */ | |
1081 | set_irte_irq(irq, iommu, index, sub_handle); | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int intel_setup_hpet_msi(unsigned int irq, unsigned int id) | |
1087 | { | |
1088 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
1089 | int index; | |
1090 | ||
1091 | if (!iommu) | |
1092 | return -1; | |
1093 | ||
1094 | index = alloc_irte(iommu, irq, 1); | |
1095 | if (index < 0) | |
1096 | return -1; | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
736baef4 | 1101 | struct irq_remap_ops intel_irq_remap_ops = { |
95a02e97 SS |
1102 | .supported = intel_irq_remapping_supported, |
1103 | .prepare = dmar_table_init, | |
1104 | .enable = intel_enable_irq_remapping, | |
1105 | .disable = disable_irq_remapping, | |
1106 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 1107 | .enable_faulting = enable_drhd_fault_handling, |
0c3f173a | 1108 | .setup_ioapic_entry = intel_setup_ioapic_entry, |
4c1bad6a | 1109 | .set_affinity = intel_ioapic_set_affinity, |
9d619f65 | 1110 | .free_irq = free_irte, |
5e2b930b JR |
1111 | .compose_msi_msg = intel_compose_msi_msg, |
1112 | .msi_alloc_irq = intel_msi_alloc_irq, | |
1113 | .msi_setup_irq = intel_msi_setup_irq, | |
1114 | .setup_hpet_msi = intel_setup_hpet_msi, | |
736baef4 | 1115 | }; |