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41f3f513 | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
0720d1f0 SM |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | */ | |
17 | ||
18 | #ifndef MSM_IOMMU_H | |
19 | #define MSM_IOMMU_H | |
20 | ||
21 | #include <linux/interrupt.h> | |
41f3f513 | 22 | #include <linux/clk.h> |
0720d1f0 | 23 | |
08bd6839 SM |
24 | /* Sharability attributes of MSM IOMMU mappings */ |
25 | #define MSM_IOMMU_ATTR_NON_SH 0x0 | |
26 | #define MSM_IOMMU_ATTR_SH 0x4 | |
27 | ||
28 | /* Cacheability attributes of MSM IOMMU mappings */ | |
29 | #define MSM_IOMMU_ATTR_NONCACHED 0x0 | |
30 | #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 | |
31 | #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 | |
32 | #define MSM_IOMMU_ATTR_CACHED_WT 0x3 | |
33 | ||
34 | /* Mask for the cache policy attribute */ | |
35 | #define MSM_IOMMU_CP_MASK 0x03 | |
36 | ||
0720d1f0 SM |
37 | /* Maximum number of Machine IDs that we are allowing to be mapped to the same |
38 | * context bank. The number of MIDs mapped to the same CB does not affect | |
39 | * performance, but there is a practical limit on how many distinct MIDs may | |
40 | * be present. These mappings are typically determined at design time and are | |
41 | * not expected to change at run time. | |
42 | */ | |
23513c3b | 43 | #define MAX_NUM_MIDS 32 |
0720d1f0 SM |
44 | |
45 | /** | |
46 | * struct msm_iommu_dev - a single IOMMU hardware instance | |
47 | * name Human-readable name given to this IOMMU HW instance | |
a43d8c10 | 48 | * ncb Number of context banks present on this IOMMU HW instance |
0720d1f0 SM |
49 | */ |
50 | struct msm_iommu_dev { | |
51 | const char *name; | |
a43d8c10 | 52 | int ncb; |
0720d1f0 SM |
53 | }; |
54 | ||
55 | /** | |
56 | * struct msm_iommu_ctx_dev - an IOMMU context bank instance | |
57 | * name Human-readable name given to this context bank | |
58 | * num Index of this context bank within the hardware | |
59 | * mids List of Machine IDs that are to be mapped into this context | |
60 | * bank, terminated by -1. The MID is a set of signals on the | |
61 | * AXI bus that identifies the function associated with a specific | |
62 | * memory request. (See ARM spec). | |
63 | */ | |
64 | struct msm_iommu_ctx_dev { | |
65 | const char *name; | |
66 | int num; | |
67 | int mids[MAX_NUM_MIDS]; | |
68 | }; | |
69 | ||
70 | ||
71 | /** | |
72 | * struct msm_iommu_drvdata - A single IOMMU hardware instance | |
73 | * @base: IOMMU config port base address (VA) | |
a43d8c10 | 74 | * @ncb The number of contexts on this IOMMU |
0720d1f0 | 75 | * @irq: Interrupt number |
41f3f513 SM |
76 | * @clk: The bus clock for this IOMMU hardware instance |
77 | * @pclk: The clock for the IOMMU bus interconnect | |
78 | * | |
0720d1f0 SM |
79 | * A msm_iommu_drvdata holds the global driver data about a single piece |
80 | * of an IOMMU hardware instance. | |
81 | */ | |
82 | struct msm_iommu_drvdata { | |
83 | void __iomem *base; | |
84 | int irq; | |
a43d8c10 | 85 | int ncb; |
41f3f513 SM |
86 | struct clk *clk; |
87 | struct clk *pclk; | |
0720d1f0 SM |
88 | }; |
89 | ||
90 | /** | |
91 | * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance | |
92 | * @num: Hardware context number of this context | |
93 | * @pdev: Platform device associated wit this HW instance | |
94 | * @attached_elm: List element for domains to track which devices are | |
95 | * attached to them | |
96 | * | |
97 | * A msm_iommu_ctx_drvdata holds the driver data for a single context bank | |
98 | * within each IOMMU hardware instance | |
99 | */ | |
100 | struct msm_iommu_ctx_drvdata { | |
101 | int num; | |
102 | struct platform_device *pdev; | |
103 | struct list_head attached_elm; | |
104 | }; | |
105 | ||
106 | /* | |
107 | * Look up an IOMMU context device by its context name. NULL if none found. | |
108 | * Useful for testing and drivers that do not yet fully have IOMMU stuff in | |
109 | * their platform devices. | |
110 | */ | |
111 | struct device *msm_iommu_get_ctx(const char *ctx_name); | |
112 | ||
113 | /* | |
114 | * Interrupt handler for the IOMMU context fault interrupt. Hooking the | |
115 | * interrupt is not supported in the API yet, but this will print an error | |
116 | * message and dump useful IOMMU registers. | |
117 | */ | |
118 | irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id); | |
119 | ||
120 | #endif |