Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
a9dcad5e | 19 | #include <linux/platform_device.h> |
f626b52d | 20 | #include <linux/iommu.h> |
c8d35c84 | 21 | #include <linux/omap-iommu.h> |
f626b52d OBC |
22 | #include <linux/mutex.h> |
23 | #include <linux/spinlock.h> | |
ed1c7de2 | 24 | #include <linux/io.h> |
ebf7cda0 | 25 | #include <linux/pm_runtime.h> |
3c92748d FV |
26 | #include <linux/of.h> |
27 | #include <linux/of_iommu.h> | |
28 | #include <linux/of_irq.h> | |
a9dcad5e HD |
29 | |
30 | #include <asm/cacheflush.h> | |
31 | ||
2ab7c848 | 32 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 33 | |
2f7702af | 34 | #include "omap-iopgtable.h" |
ed1c7de2 | 35 | #include "omap-iommu.h" |
a9dcad5e | 36 | |
37c2836c HD |
37 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
38 | for (__i = 0; \ | |
39 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
40 | __i++) | |
41 | ||
66bc8cf3 OBC |
42 | /* bitmap of the page sizes currently supported */ |
43 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
44 | ||
f626b52d OBC |
45 | /** |
46 | * struct omap_iommu_domain - omap iommu domain | |
47 | * @pgtable: the page table | |
48 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
49 | * iommu device can be attached for now. | |
803b5277 | 50 | * @dev: Device using this domain. |
f626b52d OBC |
51 | * @lock: domain lock, should be taken when attaching/detaching |
52 | */ | |
53 | struct omap_iommu_domain { | |
54 | u32 *pgtable; | |
6c32df43 | 55 | struct omap_iommu *iommu_dev; |
803b5277 | 56 | struct device *dev; |
f626b52d OBC |
57 | spinlock_t lock; |
58 | }; | |
59 | ||
7bd9e25f IY |
60 | #define MMU_LOCK_BASE_SHIFT 10 |
61 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
62 | #define MMU_LOCK_BASE(x) \ | |
63 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
64 | ||
65 | #define MMU_LOCK_VICT_SHIFT 4 | |
66 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
67 | #define MMU_LOCK_VICT(x) \ | |
68 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
69 | ||
70 | struct iotlb_lock { | |
71 | short base; | |
72 | short vict; | |
73 | }; | |
74 | ||
a9dcad5e HD |
75 | /* accommodate the difference between omap1 and omap2/3 */ |
76 | static const struct iommu_functions *arch_iommu; | |
77 | ||
78 | static struct platform_driver omap_iommu_driver; | |
79 | static struct kmem_cache *iopte_cachep; | |
80 | ||
81 | /** | |
6c32df43 | 82 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
83 | * @ops: a pointer to architecture specific iommu functions |
84 | * | |
85 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
86 | * omap series. This interface installs such an iommu algorighm. | |
87 | **/ | |
6c32df43 | 88 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
89 | { |
90 | if (arch_iommu) | |
91 | return -EBUSY; | |
92 | ||
93 | arch_iommu = ops; | |
94 | return 0; | |
95 | } | |
6c32df43 | 96 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
97 | |
98 | /** | |
6c32df43 | 99 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
100 | * @ops: a pointer to architecture specific iommu functions |
101 | * | |
102 | * This interface uninstalls the iommu algorighm installed previously. | |
103 | **/ | |
6c32df43 | 104 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
105 | { |
106 | if (arch_iommu != ops) | |
107 | pr_err("%s: not your arch\n", __func__); | |
108 | ||
109 | arch_iommu = NULL; | |
110 | } | |
6c32df43 | 111 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
112 | |
113 | /** | |
6c32df43 | 114 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 115 | * @dev: client device |
a9dcad5e | 116 | **/ |
fabdbca8 | 117 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 118 | { |
fabdbca8 OBC |
119 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
120 | ||
a9dcad5e HD |
121 | arch_iommu->save_ctx(obj); |
122 | } | |
6c32df43 | 123 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
124 | |
125 | /** | |
6c32df43 | 126 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 127 | * @dev: client device |
a9dcad5e | 128 | **/ |
fabdbca8 | 129 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 130 | { |
fabdbca8 OBC |
131 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
132 | ||
a9dcad5e HD |
133 | arch_iommu->restore_ctx(obj); |
134 | } | |
6c32df43 | 135 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
136 | |
137 | /** | |
6c32df43 | 138 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 139 | **/ |
6c32df43 | 140 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
141 | { |
142 | return arch_iommu->version; | |
143 | } | |
6c32df43 | 144 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 145 | |
6c32df43 | 146 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
147 | { |
148 | int err; | |
72b15b6a ORL |
149 | struct platform_device *pdev = to_platform_device(obj->dev); |
150 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
a9dcad5e | 151 | |
ef4815ab MH |
152 | if (!arch_iommu) |
153 | return -ENODEV; | |
154 | ||
90e569c4 | 155 | if (pdata && pdata->deassert_reset) { |
72b15b6a ORL |
156 | err = pdata->deassert_reset(pdev, pdata->reset_name); |
157 | if (err) { | |
158 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
159 | return err; | |
160 | } | |
161 | } | |
162 | ||
ebf7cda0 | 163 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
164 | |
165 | err = arch_iommu->enable(obj); | |
166 | ||
a9dcad5e HD |
167 | return err; |
168 | } | |
169 | ||
6c32df43 | 170 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 171 | { |
72b15b6a ORL |
172 | struct platform_device *pdev = to_platform_device(obj->dev); |
173 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
174 | ||
a9dcad5e HD |
175 | arch_iommu->disable(obj); |
176 | ||
ebf7cda0 | 177 | pm_runtime_put_sync(obj->dev); |
72b15b6a | 178 | |
90e569c4 | 179 | if (pdata && pdata->assert_reset) |
72b15b6a | 180 | pdata->assert_reset(pdev, pdata->reset_name); |
a9dcad5e HD |
181 | } |
182 | ||
183 | /* | |
184 | * TLB operations | |
185 | */ | |
6c32df43 | 186 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
187 | { |
188 | BUG_ON(!cr || !e); | |
189 | ||
190 | arch_iommu->cr_to_e(cr, e); | |
191 | } | |
6c32df43 | 192 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
193 | |
194 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
195 | { | |
196 | if (!cr) | |
197 | return -EINVAL; | |
198 | ||
199 | return arch_iommu->cr_valid(cr); | |
200 | } | |
201 | ||
6c32df43 | 202 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
203 | struct iotlb_entry *e) |
204 | { | |
205 | if (!e) | |
206 | return NULL; | |
207 | ||
208 | return arch_iommu->alloc_cr(obj, e); | |
209 | } | |
210 | ||
e1f23813 | 211 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
212 | { |
213 | return arch_iommu->cr_to_virt(cr); | |
214 | } | |
a9dcad5e HD |
215 | |
216 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
217 | { | |
218 | return arch_iommu->get_pte_attr(e); | |
219 | } | |
220 | ||
6c32df43 | 221 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
222 | { |
223 | return arch_iommu->fault_isr(obj, da); | |
224 | } | |
225 | ||
6c32df43 | 226 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
227 | { |
228 | u32 val; | |
229 | ||
230 | val = iommu_read_reg(obj, MMU_LOCK); | |
231 | ||
232 | l->base = MMU_LOCK_BASE(val); | |
233 | l->vict = MMU_LOCK_VICT(val); | |
234 | ||
a9dcad5e HD |
235 | } |
236 | ||
6c32df43 | 237 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
238 | { |
239 | u32 val; | |
240 | ||
a9dcad5e HD |
241 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
242 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
243 | ||
244 | iommu_write_reg(obj, val, MMU_LOCK); | |
245 | } | |
246 | ||
6c32df43 | 247 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
248 | { |
249 | arch_iommu->tlb_read_cr(obj, cr); | |
250 | } | |
251 | ||
6c32df43 | 252 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
253 | { |
254 | arch_iommu->tlb_load_cr(obj, cr); | |
255 | ||
256 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
257 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
258 | } | |
259 | ||
260 | /** | |
261 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
262 | * @obj: target iommu | |
263 | * @cr: contents of cam and ram register | |
264 | * @buf: output buffer | |
265 | **/ | |
6c32df43 | 266 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
267 | char *buf) |
268 | { | |
269 | BUG_ON(!cr || !buf); | |
270 | ||
271 | return arch_iommu->dump_cr(obj, cr, buf); | |
272 | } | |
273 | ||
37c2836c | 274 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 275 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
276 | { |
277 | struct cr_regs cr; | |
278 | struct iotlb_lock l; | |
279 | ||
280 | iotlb_lock_get(obj, &l); | |
281 | l.vict = n; | |
282 | iotlb_lock_set(obj, &l); | |
283 | iotlb_read_cr(obj, &cr); | |
284 | ||
285 | return cr; | |
286 | } | |
287 | ||
a9dcad5e HD |
288 | /** |
289 | * load_iotlb_entry - Set an iommu tlb entry | |
290 | * @obj: target iommu | |
291 | * @e: an iommu tlb entry info | |
292 | **/ | |
5da14a47 | 293 | #ifdef PREFETCH_IOTLB |
6c32df43 | 294 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 295 | { |
a9dcad5e HD |
296 | int err = 0; |
297 | struct iotlb_lock l; | |
298 | struct cr_regs *cr; | |
299 | ||
300 | if (!obj || !obj->nr_tlb_entries || !e) | |
301 | return -EINVAL; | |
302 | ||
ebf7cda0 | 303 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 304 | |
be6d8026 KH |
305 | iotlb_lock_get(obj, &l); |
306 | if (l.base == obj->nr_tlb_entries) { | |
307 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
308 | err = -EBUSY; |
309 | goto out; | |
310 | } | |
be6d8026 | 311 | if (!e->prsvd) { |
37c2836c HD |
312 | int i; |
313 | struct cr_regs tmp; | |
be6d8026 | 314 | |
37c2836c | 315 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
316 | if (!iotlb_cr_valid(&tmp)) |
317 | break; | |
37c2836c | 318 | |
be6d8026 KH |
319 | if (i == obj->nr_tlb_entries) { |
320 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
321 | err = -EBUSY; | |
322 | goto out; | |
323 | } | |
37c2836c HD |
324 | |
325 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
326 | } else { |
327 | l.vict = l.base; | |
328 | iotlb_lock_set(obj, &l); | |
329 | } | |
a9dcad5e HD |
330 | |
331 | cr = iotlb_alloc_cr(obj, e); | |
332 | if (IS_ERR(cr)) { | |
ebf7cda0 | 333 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
334 | return PTR_ERR(cr); |
335 | } | |
336 | ||
337 | iotlb_load_cr(obj, cr); | |
338 | kfree(cr); | |
339 | ||
be6d8026 KH |
340 | if (e->prsvd) |
341 | l.base++; | |
a9dcad5e HD |
342 | /* increment victim for next tlb load */ |
343 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 344 | l.vict = l.base; |
a9dcad5e HD |
345 | iotlb_lock_set(obj, &l); |
346 | out: | |
ebf7cda0 | 347 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
348 | return err; |
349 | } | |
a9dcad5e | 350 | |
5da14a47 OBC |
351 | #else /* !PREFETCH_IOTLB */ |
352 | ||
6c32df43 | 353 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
354 | { |
355 | return 0; | |
356 | } | |
357 | ||
358 | #endif /* !PREFETCH_IOTLB */ | |
359 | ||
6c32df43 | 360 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
361 | { |
362 | return load_iotlb_entry(obj, e); | |
363 | } | |
a9dcad5e HD |
364 | |
365 | /** | |
366 | * flush_iotlb_page - Clear an iommu tlb entry | |
367 | * @obj: target iommu | |
368 | * @da: iommu device virtual address | |
369 | * | |
370 | * Clear an iommu tlb entry which includes 'da' address. | |
371 | **/ | |
6c32df43 | 372 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 373 | { |
a9dcad5e | 374 | int i; |
37c2836c | 375 | struct cr_regs cr; |
a9dcad5e | 376 | |
ebf7cda0 | 377 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 378 | |
37c2836c | 379 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
380 | u32 start; |
381 | size_t bytes; | |
382 | ||
a9dcad5e HD |
383 | if (!iotlb_cr_valid(&cr)) |
384 | continue; | |
385 | ||
386 | start = iotlb_cr_to_virt(&cr); | |
387 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
388 | ||
389 | if ((start <= da) && (da < start + bytes)) { | |
390 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
391 | __func__, start, da, bytes); | |
0fa035e5 | 392 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
393 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
394 | } | |
395 | } | |
ebf7cda0 | 396 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
397 | |
398 | if (i == obj->nr_tlb_entries) | |
399 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
400 | } | |
a9dcad5e HD |
401 | |
402 | /** | |
403 | * flush_iotlb_all - Clear all iommu tlb entries | |
404 | * @obj: target iommu | |
405 | **/ | |
6c32df43 | 406 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
407 | { |
408 | struct iotlb_lock l; | |
409 | ||
ebf7cda0 | 410 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
411 | |
412 | l.base = 0; | |
413 | l.vict = 0; | |
414 | iotlb_lock_set(obj, &l); | |
415 | ||
416 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
417 | ||
ebf7cda0 | 418 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 419 | } |
ddfa975a | 420 | |
e4efd94b | 421 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 422 | |
6c32df43 | 423 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 424 | { |
a9dcad5e HD |
425 | if (!obj || !buf) |
426 | return -EINVAL; | |
427 | ||
ebf7cda0 | 428 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 429 | |
14e0e679 | 430 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e | 431 | |
ebf7cda0 | 432 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
433 | |
434 | return bytes; | |
435 | } | |
6c32df43 | 436 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 437 | |
6c32df43 OBC |
438 | static int |
439 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
440 | { |
441 | int i; | |
37c2836c HD |
442 | struct iotlb_lock saved; |
443 | struct cr_regs tmp; | |
a9dcad5e HD |
444 | struct cr_regs *p = crs; |
445 | ||
ebf7cda0 | 446 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 447 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 448 | |
37c2836c | 449 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
450 | if (!iotlb_cr_valid(&tmp)) |
451 | continue; | |
a9dcad5e HD |
452 | *p++ = tmp; |
453 | } | |
37c2836c | 454 | |
a9dcad5e | 455 | iotlb_lock_set(obj, &saved); |
ebf7cda0 | 456 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
457 | |
458 | return p - crs; | |
459 | } | |
460 | ||
461 | /** | |
6c32df43 | 462 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
463 | * @obj: target iommu |
464 | * @buf: output buffer | |
465 | **/ | |
6c32df43 | 466 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 467 | { |
14e0e679 | 468 | int i, num; |
a9dcad5e HD |
469 | struct cr_regs *cr; |
470 | char *p = buf; | |
471 | ||
14e0e679 HD |
472 | num = bytes / sizeof(*cr); |
473 | num = min(obj->nr_tlb_entries, num); | |
474 | ||
475 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
476 | if (!cr) |
477 | return 0; | |
478 | ||
14e0e679 HD |
479 | num = __dump_tlb_entries(obj, cr, num); |
480 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
481 | p += iotlb_dump_cr(obj, cr + i, p); |
482 | kfree(cr); | |
483 | ||
484 | return p - buf; | |
485 | } | |
6c32df43 | 486 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 487 | |
6c32df43 | 488 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
489 | { |
490 | return driver_for_each_device(&omap_iommu_driver.driver, | |
491 | NULL, data, fn); | |
492 | } | |
6c32df43 | 493 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
494 | |
495 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
496 | ||
497 | /* | |
498 | * H/W pagetable operations | |
499 | */ | |
500 | static void flush_iopgd_range(u32 *first, u32 *last) | |
501 | { | |
502 | /* FIXME: L2 cache should be taken care of if it exists */ | |
503 | do { | |
504 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
505 | : : "r" (first)); | |
506 | first += L1_CACHE_BYTES / sizeof(*first); | |
507 | } while (first <= last); | |
508 | } | |
509 | ||
510 | static void flush_iopte_range(u32 *first, u32 *last) | |
511 | { | |
512 | /* FIXME: L2 cache should be taken care of if it exists */ | |
513 | do { | |
514 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
515 | : : "r" (first)); | |
516 | first += L1_CACHE_BYTES / sizeof(*first); | |
517 | } while (first <= last); | |
518 | } | |
519 | ||
520 | static void iopte_free(u32 *iopte) | |
521 | { | |
522 | /* Note: freed iopte's must be clean ready for re-use */ | |
523 | kmem_cache_free(iopte_cachep, iopte); | |
524 | } | |
525 | ||
6c32df43 | 526 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
527 | { |
528 | u32 *iopte; | |
529 | ||
530 | /* a table has already existed */ | |
531 | if (*iopgd) | |
532 | goto pte_ready; | |
533 | ||
534 | /* | |
535 | * do the allocation outside the page table lock | |
536 | */ | |
537 | spin_unlock(&obj->page_table_lock); | |
538 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
539 | spin_lock(&obj->page_table_lock); | |
540 | ||
541 | if (!*iopgd) { | |
542 | if (!iopte) | |
543 | return ERR_PTR(-ENOMEM); | |
544 | ||
545 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
546 | flush_iopgd_range(iopgd, iopgd); | |
547 | ||
548 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
549 | } else { | |
550 | /* We raced, free the reduniovant table */ | |
551 | iopte_free(iopte); | |
552 | } | |
553 | ||
554 | pte_ready: | |
555 | iopte = iopte_offset(iopgd, da); | |
556 | ||
557 | dev_vdbg(obj->dev, | |
558 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
559 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
560 | ||
561 | return iopte; | |
562 | } | |
563 | ||
6c32df43 | 564 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
565 | { |
566 | u32 *iopgd = iopgd_offset(obj, da); | |
567 | ||
4abb7617 HD |
568 | if ((da | pa) & ~IOSECTION_MASK) { |
569 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
570 | __func__, da, pa, IOSECTION_SIZE); | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
a9dcad5e HD |
574 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
575 | flush_iopgd_range(iopgd, iopgd); | |
576 | return 0; | |
577 | } | |
578 | ||
6c32df43 | 579 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
580 | { |
581 | u32 *iopgd = iopgd_offset(obj, da); | |
582 | int i; | |
583 | ||
4abb7617 HD |
584 | if ((da | pa) & ~IOSUPER_MASK) { |
585 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
586 | __func__, da, pa, IOSUPER_SIZE); | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
a9dcad5e HD |
590 | for (i = 0; i < 16; i++) |
591 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
592 | flush_iopgd_range(iopgd, iopgd + 15); | |
593 | return 0; | |
594 | } | |
595 | ||
6c32df43 | 596 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
597 | { |
598 | u32 *iopgd = iopgd_offset(obj, da); | |
599 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
600 | ||
601 | if (IS_ERR(iopte)) | |
602 | return PTR_ERR(iopte); | |
603 | ||
604 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
605 | flush_iopte_range(iopte, iopte); | |
606 | ||
607 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
608 | __func__, da, pa, iopte, *iopte); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
6c32df43 | 613 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
614 | { |
615 | u32 *iopgd = iopgd_offset(obj, da); | |
616 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
617 | int i; | |
618 | ||
4abb7617 HD |
619 | if ((da | pa) & ~IOLARGE_MASK) { |
620 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
621 | __func__, da, pa, IOLARGE_SIZE); | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
a9dcad5e HD |
625 | if (IS_ERR(iopte)) |
626 | return PTR_ERR(iopte); | |
627 | ||
628 | for (i = 0; i < 16; i++) | |
629 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
630 | flush_iopte_range(iopte, iopte + 15); | |
631 | return 0; | |
632 | } | |
633 | ||
6c32df43 OBC |
634 | static int |
635 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 636 | { |
6c32df43 | 637 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
638 | u32 prot; |
639 | int err; | |
640 | ||
641 | if (!obj || !e) | |
642 | return -EINVAL; | |
643 | ||
644 | switch (e->pgsz) { | |
645 | case MMU_CAM_PGSZ_16M: | |
646 | fn = iopgd_alloc_super; | |
647 | break; | |
648 | case MMU_CAM_PGSZ_1M: | |
649 | fn = iopgd_alloc_section; | |
650 | break; | |
651 | case MMU_CAM_PGSZ_64K: | |
652 | fn = iopte_alloc_large; | |
653 | break; | |
654 | case MMU_CAM_PGSZ_4K: | |
655 | fn = iopte_alloc_page; | |
656 | break; | |
657 | default: | |
658 | fn = NULL; | |
659 | BUG(); | |
660 | break; | |
661 | } | |
662 | ||
663 | prot = get_iopte_attr(e); | |
664 | ||
665 | spin_lock(&obj->page_table_lock); | |
666 | err = fn(obj, e->da, e->pa, prot); | |
667 | spin_unlock(&obj->page_table_lock); | |
668 | ||
669 | return err; | |
670 | } | |
671 | ||
672 | /** | |
6c32df43 | 673 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
674 | * @obj: target iommu |
675 | * @e: an iommu tlb entry info | |
676 | **/ | |
6c32df43 | 677 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
678 | { |
679 | int err; | |
680 | ||
681 | flush_iotlb_page(obj, e->da); | |
682 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 683 | if (!err) |
5da14a47 | 684 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
685 | return err; |
686 | } | |
6c32df43 | 687 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
688 | |
689 | /** | |
690 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
691 | * @obj: target iommu | |
692 | * @da: iommu device virtual address | |
693 | * @ppgd: iommu pgd entry pointer to be returned | |
694 | * @ppte: iommu pte entry pointer to be returned | |
695 | **/ | |
e1f23813 OBC |
696 | static void |
697 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
698 | { |
699 | u32 *iopgd, *iopte = NULL; | |
700 | ||
701 | iopgd = iopgd_offset(obj, da); | |
702 | if (!*iopgd) | |
703 | goto out; | |
704 | ||
a1a54456 | 705 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
706 | iopte = iopte_offset(iopgd, da); |
707 | out: | |
708 | *ppgd = iopgd; | |
709 | *ppte = iopte; | |
710 | } | |
a9dcad5e | 711 | |
6c32df43 | 712 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
713 | { |
714 | size_t bytes; | |
715 | u32 *iopgd = iopgd_offset(obj, da); | |
716 | int nent = 1; | |
717 | ||
718 | if (!*iopgd) | |
719 | return 0; | |
720 | ||
a1a54456 | 721 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
722 | int i; |
723 | u32 *iopte = iopte_offset(iopgd, da); | |
724 | ||
725 | bytes = IOPTE_SIZE; | |
726 | if (*iopte & IOPTE_LARGE) { | |
727 | nent *= 16; | |
728 | /* rewind to the 1st entry */ | |
c127c7dc | 729 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
730 | } |
731 | bytes *= nent; | |
732 | memset(iopte, 0, nent * sizeof(*iopte)); | |
733 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
734 | ||
735 | /* | |
736 | * do table walk to check if this table is necessary or not | |
737 | */ | |
738 | iopte = iopte_offset(iopgd, 0); | |
739 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
740 | if (iopte[i]) | |
741 | goto out; | |
742 | ||
743 | iopte_free(iopte); | |
744 | nent = 1; /* for the next L1 entry */ | |
745 | } else { | |
746 | bytes = IOPGD_SIZE; | |
dcc730dc | 747 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
748 | nent *= 16; |
749 | /* rewind to the 1st entry */ | |
8d33ea58 | 750 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
751 | } |
752 | bytes *= nent; | |
753 | } | |
754 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
755 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
756 | out: | |
757 | return bytes; | |
758 | } | |
759 | ||
760 | /** | |
761 | * iopgtable_clear_entry - Remove an iommu pte entry | |
762 | * @obj: target iommu | |
763 | * @da: iommu device virtual address | |
764 | **/ | |
6c32df43 | 765 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
766 | { |
767 | size_t bytes; | |
768 | ||
769 | spin_lock(&obj->page_table_lock); | |
770 | ||
771 | bytes = iopgtable_clear_entry_core(obj, da); | |
772 | flush_iotlb_page(obj, da); | |
773 | ||
774 | spin_unlock(&obj->page_table_lock); | |
775 | ||
776 | return bytes; | |
777 | } | |
a9dcad5e | 778 | |
6c32df43 | 779 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
780 | { |
781 | int i; | |
782 | ||
783 | spin_lock(&obj->page_table_lock); | |
784 | ||
785 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
786 | u32 da; | |
787 | u32 *iopgd; | |
788 | ||
789 | da = i << IOPGD_SHIFT; | |
790 | iopgd = iopgd_offset(obj, da); | |
791 | ||
792 | if (!*iopgd) | |
793 | continue; | |
794 | ||
a1a54456 | 795 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
796 | iopte_free(iopte_offset(iopgd, 0)); |
797 | ||
798 | *iopgd = 0; | |
799 | flush_iopgd_range(iopgd, iopgd); | |
800 | } | |
801 | ||
802 | flush_iotlb_all(obj); | |
803 | ||
804 | spin_unlock(&obj->page_table_lock); | |
805 | } | |
806 | ||
807 | /* | |
808 | * Device IOMMU generic operations | |
809 | */ | |
810 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
811 | { | |
d594f1f3 | 812 | u32 da, errs; |
a9dcad5e | 813 | u32 *iopgd, *iopte; |
6c32df43 | 814 | struct omap_iommu *obj = data; |
e7f10f02 | 815 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
816 | |
817 | if (!obj->refcount) | |
818 | return IRQ_NONE; | |
819 | ||
d594f1f3 | 820 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
821 | if (errs == 0) |
822 | return IRQ_HANDLED; | |
d594f1f3 DC |
823 | |
824 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 825 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
826 | return IRQ_HANDLED; |
827 | ||
37b29810 HD |
828 | iommu_disable(obj); |
829 | ||
a9dcad5e HD |
830 | iopgd = iopgd_offset(obj, da); |
831 | ||
a1a54456 | 832 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f SA |
833 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
834 | obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
835 | return IRQ_NONE; |
836 | } | |
837 | ||
838 | iopte = iopte_offset(iopgd, da); | |
839 | ||
b6c2e09f SA |
840 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
841 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); | |
a9dcad5e HD |
842 | |
843 | return IRQ_NONE; | |
844 | } | |
845 | ||
846 | static int device_match_by_alias(struct device *dev, void *data) | |
847 | { | |
6c32df43 | 848 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
849 | const char *name = data; |
850 | ||
851 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
852 | ||
853 | return strcmp(obj->name, name) == 0; | |
854 | } | |
855 | ||
856 | /** | |
f626b52d | 857 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 858 | * @name: name of target omap iommu device |
f626b52d | 859 | * @iopgd: page table |
a9dcad5e | 860 | **/ |
fabdbca8 | 861 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e | 862 | { |
7ee08b9e | 863 | int err; |
fabdbca8 OBC |
864 | struct device *dev; |
865 | struct omap_iommu *obj; | |
866 | ||
867 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
868 | (void *)name, | |
869 | device_match_by_alias); | |
870 | if (!dev) | |
7ee08b9e | 871 | return ERR_PTR(-ENODEV); |
fabdbca8 OBC |
872 | |
873 | obj = to_iommu(dev); | |
a9dcad5e | 874 | |
f626b52d | 875 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 876 | |
f626b52d OBC |
877 | /* an iommu device can only be attached once */ |
878 | if (++obj->refcount > 1) { | |
879 | dev_err(dev, "%s: already attached!\n", obj->name); | |
880 | err = -EBUSY; | |
881 | goto err_enable; | |
a9dcad5e HD |
882 | } |
883 | ||
f626b52d OBC |
884 | obj->iopgd = iopgd; |
885 | err = iommu_enable(obj); | |
886 | if (err) | |
887 | goto err_enable; | |
888 | flush_iotlb_all(obj); | |
889 | ||
7ee08b9e SA |
890 | if (!try_module_get(obj->owner)) { |
891 | err = -ENODEV; | |
a9dcad5e | 892 | goto err_module; |
7ee08b9e | 893 | } |
a9dcad5e | 894 | |
f626b52d | 895 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
896 | |
897 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
898 | return obj; | |
899 | ||
900 | err_module: | |
901 | if (obj->refcount == 1) | |
902 | iommu_disable(obj); | |
903 | err_enable: | |
904 | obj->refcount--; | |
f626b52d | 905 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
906 | return ERR_PTR(err); |
907 | } | |
a9dcad5e HD |
908 | |
909 | /** | |
f626b52d | 910 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
911 | * @obj: target iommu |
912 | **/ | |
6c32df43 | 913 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 914 | { |
acf9d467 | 915 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
916 | return; |
917 | ||
f626b52d | 918 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
919 | |
920 | if (--obj->refcount == 0) | |
921 | iommu_disable(obj); | |
922 | ||
923 | module_put(obj->owner); | |
924 | ||
f626b52d | 925 | obj->iopgd = NULL; |
d594f1f3 | 926 | |
f626b52d | 927 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 928 | |
a9dcad5e | 929 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 930 | } |
d594f1f3 | 931 | |
a9dcad5e HD |
932 | /* |
933 | * OMAP Device MMU(IOMMU) detection | |
934 | */ | |
d34d6517 | 935 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
936 | { |
937 | int err = -ENODEV; | |
a9dcad5e | 938 | int irq; |
6c32df43 | 939 | struct omap_iommu *obj; |
a9dcad5e HD |
940 | struct resource *res; |
941 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
3c92748d | 942 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 943 | |
f129b3df | 944 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
945 | if (!obj) |
946 | return -ENOMEM; | |
947 | ||
3c92748d FV |
948 | if (of) { |
949 | obj->name = dev_name(&pdev->dev); | |
950 | obj->nr_tlb_entries = 32; | |
951 | err = of_property_read_u32(of, "ti,#tlb-entries", | |
952 | &obj->nr_tlb_entries); | |
953 | if (err && err != -EINVAL) | |
954 | return err; | |
955 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
956 | return -EINVAL; | |
957 | /* | |
958 | * da_start and da_end are needed for omap-iovmm, so hardcode | |
959 | * these values as used by OMAP3 ISP - the only user for | |
960 | * omap-iovmm | |
961 | */ | |
962 | obj->da_start = 0; | |
963 | obj->da_end = 0xfffff000; | |
b148d5fb SA |
964 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) |
965 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d FV |
966 | } else { |
967 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
968 | obj->name = pdata->name; | |
969 | obj->da_start = pdata->da_start; | |
970 | obj->da_end = pdata->da_end; | |
971 | } | |
972 | if (obj->da_end <= obj->da_start) | |
973 | return -EINVAL; | |
974 | ||
a9dcad5e HD |
975 | obj->dev = &pdev->dev; |
976 | obj->ctx = (void *)obj + sizeof(*obj); | |
977 | ||
f626b52d | 978 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
979 | mutex_init(&obj->mmap_lock); |
980 | spin_lock_init(&obj->page_table_lock); | |
981 | INIT_LIST_HEAD(&obj->mmap); | |
982 | ||
983 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
984 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
985 | if (IS_ERR(obj->regbase)) | |
986 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 987 | |
a9dcad5e | 988 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
989 | if (irq < 0) |
990 | return -ENODEV; | |
991 | ||
992 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
993 | dev_name(obj->dev), obj); | |
a9dcad5e | 994 | if (err < 0) |
f129b3df | 995 | return err; |
a9dcad5e HD |
996 | platform_set_drvdata(pdev, obj); |
997 | ||
ebf7cda0 ORL |
998 | pm_runtime_irq_safe(obj->dev); |
999 | pm_runtime_enable(obj->dev); | |
1000 | ||
a9dcad5e HD |
1001 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
1002 | return 0; | |
a9dcad5e HD |
1003 | } |
1004 | ||
d34d6517 | 1005 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 1006 | { |
6c32df43 | 1007 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 1008 | |
a9dcad5e | 1009 | iopgtable_clear_entry_all(obj); |
a9dcad5e | 1010 | |
ebf7cda0 ORL |
1011 | pm_runtime_disable(obj->dev); |
1012 | ||
a9dcad5e | 1013 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
1014 | return 0; |
1015 | } | |
1016 | ||
3c92748d FV |
1017 | static struct of_device_id omap_iommu_of_match[] = { |
1018 | { .compatible = "ti,omap2-iommu" }, | |
1019 | { .compatible = "ti,omap4-iommu" }, | |
1020 | { .compatible = "ti,dra7-iommu" }, | |
1021 | {}, | |
1022 | }; | |
1023 | MODULE_DEVICE_TABLE(of, omap_iommu_of_match); | |
1024 | ||
a9dcad5e HD |
1025 | static struct platform_driver omap_iommu_driver = { |
1026 | .probe = omap_iommu_probe, | |
d34d6517 | 1027 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1028 | .driver = { |
1029 | .name = "omap-iommu", | |
3c92748d | 1030 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1031 | }, |
1032 | }; | |
1033 | ||
1034 | static void iopte_cachep_ctor(void *iopte) | |
1035 | { | |
1036 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1037 | } | |
1038 | ||
ed1c7de2 TL |
1039 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
1040 | u32 flags) | |
1041 | { | |
1042 | memset(e, 0, sizeof(*e)); | |
1043 | ||
1044 | e->da = da; | |
1045 | e->pa = pa; | |
1046 | e->valid = 1; | |
1047 | /* FIXME: add OMAP1 support */ | |
1048 | e->pgsz = flags & MMU_CAM_PGSZ_MASK; | |
1049 | e->endian = flags & MMU_RAM_ENDIAN_MASK; | |
1050 | e->elsz = flags & MMU_RAM_ELSZ_MASK; | |
1051 | e->mixed = flags & MMU_RAM_MIXED_MASK; | |
1052 | ||
1053 | return iopgsz_to_bytes(e->pgsz); | |
1054 | } | |
1055 | ||
f626b52d | 1056 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1057 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1058 | { |
1059 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1060 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1061 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1062 | struct iotlb_entry e; |
1063 | int omap_pgsz; | |
1064 | u32 ret, flags; | |
1065 | ||
1066 | /* we only support mapping a single iommu page for now */ | |
1067 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1068 | if (omap_pgsz < 0) { | |
1069 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1070 | return -EINVAL; | |
1071 | } | |
1072 | ||
1073 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1074 | ||
1075 | flags = omap_pgsz | prot; | |
1076 | ||
1077 | iotlb_init_entry(&e, da, pa, flags); | |
1078 | ||
6c32df43 | 1079 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1080 | if (ret) |
6c32df43 | 1081 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1082 | |
b4550d41 | 1083 | return ret; |
f626b52d OBC |
1084 | } |
1085 | ||
5009065d OBC |
1086 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1087 | size_t size) | |
f626b52d OBC |
1088 | { |
1089 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1090 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1091 | struct device *dev = oiommu->dev; |
f626b52d | 1092 | |
5009065d | 1093 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1094 | |
5009065d | 1095 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1096 | } |
1097 | ||
1098 | static int | |
1099 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1100 | { | |
1101 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1102 | struct omap_iommu *oiommu; |
fabdbca8 | 1103 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1104 | int ret = 0; |
1105 | ||
1106 | spin_lock(&omap_domain->lock); | |
1107 | ||
1108 | /* only a single device is supported per domain for now */ | |
1109 | if (omap_domain->iommu_dev) { | |
1110 | dev_err(dev, "iommu domain is already attached\n"); | |
1111 | ret = -EBUSY; | |
1112 | goto out; | |
1113 | } | |
1114 | ||
1115 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1116 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1117 | if (IS_ERR(oiommu)) { |
1118 | ret = PTR_ERR(oiommu); | |
1119 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1120 | goto out; | |
1121 | } | |
1122 | ||
fabdbca8 | 1123 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1124 | omap_domain->dev = dev; |
e7f10f02 | 1125 | oiommu->domain = domain; |
f626b52d OBC |
1126 | |
1127 | out: | |
1128 | spin_unlock(&omap_domain->lock); | |
1129 | return ret; | |
1130 | } | |
1131 | ||
803b5277 ORL |
1132 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1133 | struct device *dev) | |
f626b52d | 1134 | { |
fabdbca8 | 1135 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1136 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1137 | |
1138 | /* only a single device is supported per domain for now */ | |
1139 | if (omap_domain->iommu_dev != oiommu) { | |
1140 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1141 | return; |
f626b52d OBC |
1142 | } |
1143 | ||
1144 | iopgtable_clear_entry_all(oiommu); | |
1145 | ||
1146 | omap_iommu_detach(oiommu); | |
1147 | ||
fabdbca8 | 1148 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1149 | omap_domain->dev = NULL; |
1150 | } | |
f626b52d | 1151 | |
803b5277 ORL |
1152 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1153 | struct device *dev) | |
1154 | { | |
1155 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1156 | ||
1157 | spin_lock(&omap_domain->lock); | |
1158 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1159 | spin_unlock(&omap_domain->lock); |
1160 | } | |
1161 | ||
1162 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1163 | { | |
1164 | struct omap_iommu_domain *omap_domain; | |
1165 | ||
1166 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1167 | if (!omap_domain) { | |
1168 | pr_err("kzalloc failed\n"); | |
1169 | goto out; | |
1170 | } | |
1171 | ||
1172 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1173 | if (!omap_domain->pgtable) { | |
1174 | pr_err("kzalloc failed\n"); | |
1175 | goto fail_nomem; | |
1176 | } | |
1177 | ||
1178 | /* | |
1179 | * should never fail, but please keep this around to ensure | |
1180 | * we keep the hardware happy | |
1181 | */ | |
1182 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1183 | ||
1184 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1185 | spin_lock_init(&omap_domain->lock); | |
1186 | ||
1187 | domain->priv = omap_domain; | |
1188 | ||
2c6edb0c JR |
1189 | domain->geometry.aperture_start = 0; |
1190 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1191 | domain->geometry.force_aperture = true; | |
1192 | ||
f626b52d OBC |
1193 | return 0; |
1194 | ||
1195 | fail_nomem: | |
1196 | kfree(omap_domain); | |
1197 | out: | |
1198 | return -ENOMEM; | |
1199 | } | |
1200 | ||
f626b52d OBC |
1201 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1202 | { | |
1203 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1204 | ||
1205 | domain->priv = NULL; | |
1206 | ||
803b5277 ORL |
1207 | /* |
1208 | * An iommu device is still attached | |
1209 | * (currently, only one device can be attached) ? | |
1210 | */ | |
1211 | if (omap_domain->iommu_dev) | |
1212 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1213 | ||
f626b52d OBC |
1214 | kfree(omap_domain->pgtable); |
1215 | kfree(omap_domain); | |
1216 | } | |
1217 | ||
1218 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 1219 | dma_addr_t da) |
f626b52d OBC |
1220 | { |
1221 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1222 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1223 | struct device *dev = oiommu->dev; |
1224 | u32 *pgd, *pte; | |
1225 | phys_addr_t ret = 0; | |
1226 | ||
1227 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1228 | ||
1229 | if (pte) { | |
1230 | if (iopte_is_small(*pte)) | |
1231 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1232 | else if (iopte_is_large(*pte)) | |
1233 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1234 | else | |
2abfcfbc SA |
1235 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
1236 | (unsigned long long)da); | |
f626b52d OBC |
1237 | } else { |
1238 | if (iopgd_is_section(*pgd)) | |
1239 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1240 | else if (iopgd_is_super(*pgd)) | |
1241 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1242 | else | |
2abfcfbc SA |
1243 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
1244 | (unsigned long long)da); | |
f626b52d OBC |
1245 | } |
1246 | ||
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1251 | unsigned long cap) | |
1252 | { | |
1253 | return 0; | |
1254 | } | |
1255 | ||
07a02030 LP |
1256 | static int omap_iommu_add_device(struct device *dev) |
1257 | { | |
1258 | struct omap_iommu_arch_data *arch_data; | |
1259 | struct device_node *np; | |
1260 | ||
1261 | /* | |
1262 | * Allocate the archdata iommu structure for DT-based devices. | |
1263 | * | |
1264 | * TODO: Simplify this when removing non-DT support completely from the | |
1265 | * IOMMU users. | |
1266 | */ | |
1267 | if (!dev->of_node) | |
1268 | return 0; | |
1269 | ||
1270 | np = of_parse_phandle(dev->of_node, "iommus", 0); | |
1271 | if (!np) | |
1272 | return 0; | |
1273 | ||
1274 | arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); | |
1275 | if (!arch_data) { | |
1276 | of_node_put(np); | |
1277 | return -ENOMEM; | |
1278 | } | |
1279 | ||
1280 | arch_data->name = kstrdup(dev_name(dev), GFP_KERNEL); | |
1281 | dev->archdata.iommu = arch_data; | |
1282 | ||
1283 | of_node_put(np); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | static void omap_iommu_remove_device(struct device *dev) | |
1289 | { | |
1290 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1291 | ||
1292 | if (!dev->of_node || !arch_data) | |
1293 | return; | |
1294 | ||
1295 | kfree(arch_data->name); | |
1296 | kfree(arch_data); | |
1297 | } | |
1298 | ||
f626b52d OBC |
1299 | static struct iommu_ops omap_iommu_ops = { |
1300 | .domain_init = omap_iommu_domain_init, | |
1301 | .domain_destroy = omap_iommu_domain_destroy, | |
1302 | .attach_dev = omap_iommu_attach_dev, | |
1303 | .detach_dev = omap_iommu_detach_dev, | |
1304 | .map = omap_iommu_map, | |
1305 | .unmap = omap_iommu_unmap, | |
1306 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1307 | .domain_has_cap = omap_iommu_domain_has_cap, | |
07a02030 LP |
1308 | .add_device = omap_iommu_add_device, |
1309 | .remove_device = omap_iommu_remove_device, | |
66bc8cf3 | 1310 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1311 | }; |
1312 | ||
a9dcad5e HD |
1313 | static int __init omap_iommu_init(void) |
1314 | { | |
1315 | struct kmem_cache *p; | |
1316 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1317 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1318 | ||
1319 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1320 | iopte_cachep_ctor); | |
1321 | if (!p) | |
1322 | return -ENOMEM; | |
1323 | iopte_cachep = p; | |
1324 | ||
a65bc64f | 1325 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1326 | |
a9dcad5e HD |
1327 | return platform_driver_register(&omap_iommu_driver); |
1328 | } | |
435792d9 OBC |
1329 | /* must be ready before omap3isp is probed */ |
1330 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1331 | |
1332 | static void __exit omap_iommu_exit(void) | |
1333 | { | |
1334 | kmem_cache_destroy(iopte_cachep); | |
1335 | ||
1336 | platform_driver_unregister(&omap_iommu_driver); | |
1337 | } | |
1338 | module_exit(omap_iommu_exit); | |
1339 | ||
1340 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1341 | MODULE_ALIAS("platform:omap-iommu"); | |
1342 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1343 | MODULE_LICENSE("GPL v2"); |