Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
a9dcad5e | 19 | #include <linux/platform_device.h> |
f626b52d | 20 | #include <linux/iommu.h> |
c8d35c84 | 21 | #include <linux/omap-iommu.h> |
f626b52d OBC |
22 | #include <linux/mutex.h> |
23 | #include <linux/spinlock.h> | |
ed1c7de2 | 24 | #include <linux/io.h> |
ebf7cda0 | 25 | #include <linux/pm_runtime.h> |
3c92748d FV |
26 | #include <linux/of.h> |
27 | #include <linux/of_iommu.h> | |
28 | #include <linux/of_irq.h> | |
7d682774 | 29 | #include <linux/of_platform.h> |
a9dcad5e HD |
30 | |
31 | #include <asm/cacheflush.h> | |
32 | ||
2ab7c848 | 33 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 34 | |
2f7702af | 35 | #include "omap-iopgtable.h" |
ed1c7de2 | 36 | #include "omap-iommu.h" |
a9dcad5e | 37 | |
5acc97db SA |
38 | #define to_iommu(dev) \ |
39 | ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))) | |
40 | ||
37c2836c HD |
41 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
42 | for (__i = 0; \ | |
43 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
44 | __i++) | |
45 | ||
66bc8cf3 OBC |
46 | /* bitmap of the page sizes currently supported */ |
47 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
48 | ||
f626b52d OBC |
49 | /** |
50 | * struct omap_iommu_domain - omap iommu domain | |
51 | * @pgtable: the page table | |
52 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
53 | * iommu device can be attached for now. | |
803b5277 | 54 | * @dev: Device using this domain. |
f626b52d OBC |
55 | * @lock: domain lock, should be taken when attaching/detaching |
56 | */ | |
57 | struct omap_iommu_domain { | |
58 | u32 *pgtable; | |
6c32df43 | 59 | struct omap_iommu *iommu_dev; |
803b5277 | 60 | struct device *dev; |
f626b52d OBC |
61 | spinlock_t lock; |
62 | }; | |
63 | ||
7bd9e25f IY |
64 | #define MMU_LOCK_BASE_SHIFT 10 |
65 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
66 | #define MMU_LOCK_BASE(x) \ | |
67 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
68 | ||
69 | #define MMU_LOCK_VICT_SHIFT 4 | |
70 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
71 | #define MMU_LOCK_VICT(x) \ | |
72 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
73 | ||
74 | struct iotlb_lock { | |
75 | short base; | |
76 | short vict; | |
77 | }; | |
78 | ||
a9dcad5e HD |
79 | static struct platform_driver omap_iommu_driver; |
80 | static struct kmem_cache *iopte_cachep; | |
81 | ||
a9dcad5e | 82 | /** |
6c32df43 | 83 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 84 | * @dev: client device |
a9dcad5e | 85 | **/ |
fabdbca8 | 86 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 87 | { |
fabdbca8 | 88 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
bd4396f0 SA |
89 | u32 *p = obj->ctx; |
90 | int i; | |
fabdbca8 | 91 | |
bd4396f0 SA |
92 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { |
93 | p[i] = iommu_read_reg(obj, i * sizeof(u32)); | |
94 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
95 | } | |
a9dcad5e | 96 | } |
6c32df43 | 97 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
98 | |
99 | /** | |
6c32df43 | 100 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 101 | * @dev: client device |
a9dcad5e | 102 | **/ |
fabdbca8 | 103 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 104 | { |
fabdbca8 | 105 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
bd4396f0 SA |
106 | u32 *p = obj->ctx; |
107 | int i; | |
fabdbca8 | 108 | |
bd4396f0 SA |
109 | for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { |
110 | iommu_write_reg(obj, p[i], i * sizeof(u32)); | |
111 | dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); | |
112 | } | |
a9dcad5e | 113 | } |
6c32df43 | 114 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e | 115 | |
bd4396f0 SA |
116 | static void __iommu_set_twl(struct omap_iommu *obj, bool on) |
117 | { | |
118 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
119 | ||
120 | if (on) | |
121 | iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); | |
122 | else | |
123 | iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); | |
124 | ||
125 | l &= ~MMU_CNTL_MASK; | |
126 | if (on) | |
127 | l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); | |
128 | else | |
129 | l |= (MMU_CNTL_MMU_EN); | |
130 | ||
131 | iommu_write_reg(obj, l, MMU_CNTL); | |
132 | } | |
133 | ||
134 | static int omap2_iommu_enable(struct omap_iommu *obj) | |
135 | { | |
136 | u32 l, pa; | |
137 | ||
138 | if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) | |
139 | return -EINVAL; | |
140 | ||
141 | pa = virt_to_phys(obj->iopgd); | |
142 | if (!IS_ALIGNED(pa, SZ_16K)) | |
143 | return -EINVAL; | |
144 | ||
145 | l = iommu_read_reg(obj, MMU_REVISION); | |
146 | dev_info(obj->dev, "%s: version %d.%d\n", obj->name, | |
147 | (l >> 4) & 0xf, l & 0xf); | |
148 | ||
149 | iommu_write_reg(obj, pa, MMU_TTB); | |
150 | ||
151 | if (obj->has_bus_err_back) | |
152 | iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); | |
153 | ||
154 | __iommu_set_twl(obj, true); | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static void omap2_iommu_disable(struct omap_iommu *obj) | |
160 | { | |
161 | u32 l = iommu_read_reg(obj, MMU_CNTL); | |
162 | ||
163 | l &= ~MMU_CNTL_MASK; | |
164 | iommu_write_reg(obj, l, MMU_CNTL); | |
165 | ||
166 | dev_dbg(obj->dev, "%s is shutting down\n", obj->name); | |
167 | } | |
168 | ||
6c32df43 | 169 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
170 | { |
171 | int err; | |
72b15b6a ORL |
172 | struct platform_device *pdev = to_platform_device(obj->dev); |
173 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
a9dcad5e | 174 | |
90e569c4 | 175 | if (pdata && pdata->deassert_reset) { |
72b15b6a ORL |
176 | err = pdata->deassert_reset(pdev, pdata->reset_name); |
177 | if (err) { | |
178 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
179 | return err; | |
180 | } | |
181 | } | |
182 | ||
ebf7cda0 | 183 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 184 | |
bd4396f0 | 185 | err = omap2_iommu_enable(obj); |
a9dcad5e | 186 | |
a9dcad5e HD |
187 | return err; |
188 | } | |
189 | ||
6c32df43 | 190 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 191 | { |
72b15b6a ORL |
192 | struct platform_device *pdev = to_platform_device(obj->dev); |
193 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
194 | ||
bd4396f0 | 195 | omap2_iommu_disable(obj); |
a9dcad5e | 196 | |
ebf7cda0 | 197 | pm_runtime_put_sync(obj->dev); |
72b15b6a | 198 | |
90e569c4 | 199 | if (pdata && pdata->assert_reset) |
72b15b6a | 200 | pdata->assert_reset(pdev, pdata->reset_name); |
a9dcad5e HD |
201 | } |
202 | ||
203 | /* | |
204 | * TLB operations | |
205 | */ | |
6c32df43 | 206 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
207 | { |
208 | BUG_ON(!cr || !e); | |
209 | ||
bd4396f0 SA |
210 | e->da = cr->cam & MMU_CAM_VATAG_MASK; |
211 | e->pa = cr->ram & MMU_RAM_PADDR_MASK; | |
212 | e->valid = cr->cam & MMU_CAM_V; | |
213 | e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; | |
214 | e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; | |
215 | e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; | |
216 | e->mixed = cr->ram & MMU_RAM_MIXED; | |
a9dcad5e | 217 | } |
6c32df43 | 218 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
219 | |
220 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
221 | { | |
222 | if (!cr) | |
223 | return -EINVAL; | |
224 | ||
bd4396f0 | 225 | return cr->cam & MMU_CAM_V; |
a9dcad5e HD |
226 | } |
227 | ||
e1f23813 | 228 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e | 229 | { |
bd4396f0 SA |
230 | u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; |
231 | u32 mask = get_cam_va_mask(cr->cam & page_size); | |
232 | ||
233 | return cr->cam & mask; | |
a9dcad5e | 234 | } |
a9dcad5e HD |
235 | |
236 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
237 | { | |
bd4396f0 SA |
238 | u32 attr; |
239 | ||
240 | attr = e->mixed << 5; | |
241 | attr |= e->endian; | |
242 | attr |= e->elsz >> 3; | |
243 | attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) || | |
244 | (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6); | |
245 | return attr; | |
a9dcad5e HD |
246 | } |
247 | ||
6c32df43 | 248 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e | 249 | { |
bd4396f0 SA |
250 | u32 status, fault_addr; |
251 | ||
252 | status = iommu_read_reg(obj, MMU_IRQSTATUS); | |
253 | status &= MMU_IRQ_MASK; | |
254 | if (!status) { | |
255 | *da = 0; | |
256 | return 0; | |
257 | } | |
258 | ||
259 | fault_addr = iommu_read_reg(obj, MMU_FAULT_AD); | |
260 | *da = fault_addr; | |
261 | ||
262 | iommu_write_reg(obj, status, MMU_IRQSTATUS); | |
263 | ||
264 | return status; | |
a9dcad5e HD |
265 | } |
266 | ||
6c32df43 | 267 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
268 | { |
269 | u32 val; | |
270 | ||
271 | val = iommu_read_reg(obj, MMU_LOCK); | |
272 | ||
273 | l->base = MMU_LOCK_BASE(val); | |
274 | l->vict = MMU_LOCK_VICT(val); | |
275 | ||
a9dcad5e HD |
276 | } |
277 | ||
6c32df43 | 278 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
279 | { |
280 | u32 val; | |
281 | ||
a9dcad5e HD |
282 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
283 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
284 | ||
285 | iommu_write_reg(obj, val, MMU_LOCK); | |
286 | } | |
287 | ||
6c32df43 | 288 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 289 | { |
bd4396f0 SA |
290 | cr->cam = iommu_read_reg(obj, MMU_READ_CAM); |
291 | cr->ram = iommu_read_reg(obj, MMU_READ_RAM); | |
a9dcad5e HD |
292 | } |
293 | ||
6c32df43 | 294 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e | 295 | { |
bd4396f0 SA |
296 | iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); |
297 | iommu_write_reg(obj, cr->ram, MMU_RAM); | |
a9dcad5e HD |
298 | |
299 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
300 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
301 | } | |
302 | ||
37c2836c | 303 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 304 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
305 | { |
306 | struct cr_regs cr; | |
307 | struct iotlb_lock l; | |
308 | ||
309 | iotlb_lock_get(obj, &l); | |
310 | l.vict = n; | |
311 | iotlb_lock_set(obj, &l); | |
312 | iotlb_read_cr(obj, &cr); | |
313 | ||
314 | return cr; | |
315 | } | |
316 | ||
bd4396f0 SA |
317 | #ifdef PREFETCH_IOTLB |
318 | static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, | |
319 | struct iotlb_entry *e) | |
320 | { | |
321 | struct cr_regs *cr; | |
322 | ||
323 | if (!e) | |
324 | return NULL; | |
325 | ||
326 | if (e->da & ~(get_cam_va_mask(e->pgsz))) { | |
327 | dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, | |
328 | e->da); | |
329 | return ERR_PTR(-EINVAL); | |
330 | } | |
331 | ||
332 | cr = kmalloc(sizeof(*cr), GFP_KERNEL); | |
333 | if (!cr) | |
334 | return ERR_PTR(-ENOMEM); | |
335 | ||
336 | cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; | |
337 | cr->ram = e->pa | e->endian | e->elsz | e->mixed; | |
338 | ||
339 | return cr; | |
340 | } | |
341 | ||
a9dcad5e HD |
342 | /** |
343 | * load_iotlb_entry - Set an iommu tlb entry | |
344 | * @obj: target iommu | |
345 | * @e: an iommu tlb entry info | |
346 | **/ | |
6c32df43 | 347 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 348 | { |
a9dcad5e HD |
349 | int err = 0; |
350 | struct iotlb_lock l; | |
351 | struct cr_regs *cr; | |
352 | ||
353 | if (!obj || !obj->nr_tlb_entries || !e) | |
354 | return -EINVAL; | |
355 | ||
ebf7cda0 | 356 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 357 | |
be6d8026 KH |
358 | iotlb_lock_get(obj, &l); |
359 | if (l.base == obj->nr_tlb_entries) { | |
360 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
361 | err = -EBUSY; |
362 | goto out; | |
363 | } | |
be6d8026 | 364 | if (!e->prsvd) { |
37c2836c HD |
365 | int i; |
366 | struct cr_regs tmp; | |
be6d8026 | 367 | |
37c2836c | 368 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
369 | if (!iotlb_cr_valid(&tmp)) |
370 | break; | |
37c2836c | 371 | |
be6d8026 KH |
372 | if (i == obj->nr_tlb_entries) { |
373 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
374 | err = -EBUSY; | |
375 | goto out; | |
376 | } | |
37c2836c HD |
377 | |
378 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
379 | } else { |
380 | l.vict = l.base; | |
381 | iotlb_lock_set(obj, &l); | |
382 | } | |
a9dcad5e HD |
383 | |
384 | cr = iotlb_alloc_cr(obj, e); | |
385 | if (IS_ERR(cr)) { | |
ebf7cda0 | 386 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
387 | return PTR_ERR(cr); |
388 | } | |
389 | ||
390 | iotlb_load_cr(obj, cr); | |
391 | kfree(cr); | |
392 | ||
be6d8026 KH |
393 | if (e->prsvd) |
394 | l.base++; | |
a9dcad5e HD |
395 | /* increment victim for next tlb load */ |
396 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 397 | l.vict = l.base; |
a9dcad5e HD |
398 | iotlb_lock_set(obj, &l); |
399 | out: | |
ebf7cda0 | 400 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
401 | return err; |
402 | } | |
a9dcad5e | 403 | |
5da14a47 OBC |
404 | #else /* !PREFETCH_IOTLB */ |
405 | ||
6c32df43 | 406 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
407 | { |
408 | return 0; | |
409 | } | |
410 | ||
411 | #endif /* !PREFETCH_IOTLB */ | |
412 | ||
6c32df43 | 413 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
414 | { |
415 | return load_iotlb_entry(obj, e); | |
416 | } | |
a9dcad5e HD |
417 | |
418 | /** | |
419 | * flush_iotlb_page - Clear an iommu tlb entry | |
420 | * @obj: target iommu | |
421 | * @da: iommu device virtual address | |
422 | * | |
423 | * Clear an iommu tlb entry which includes 'da' address. | |
424 | **/ | |
6c32df43 | 425 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 426 | { |
a9dcad5e | 427 | int i; |
37c2836c | 428 | struct cr_regs cr; |
a9dcad5e | 429 | |
ebf7cda0 | 430 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 431 | |
37c2836c | 432 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
433 | u32 start; |
434 | size_t bytes; | |
435 | ||
a9dcad5e HD |
436 | if (!iotlb_cr_valid(&cr)) |
437 | continue; | |
438 | ||
439 | start = iotlb_cr_to_virt(&cr); | |
440 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
441 | ||
442 | if ((start <= da) && (da < start + bytes)) { | |
443 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
444 | __func__, start, da, bytes); | |
0fa035e5 | 445 | iotlb_load_cr(obj, &cr); |
a9dcad5e | 446 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
f7129a0e | 447 | break; |
a9dcad5e HD |
448 | } |
449 | } | |
ebf7cda0 | 450 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
451 | |
452 | if (i == obj->nr_tlb_entries) | |
453 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
454 | } | |
a9dcad5e HD |
455 | |
456 | /** | |
457 | * flush_iotlb_all - Clear all iommu tlb entries | |
458 | * @obj: target iommu | |
459 | **/ | |
6c32df43 | 460 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
461 | { |
462 | struct iotlb_lock l; | |
463 | ||
ebf7cda0 | 464 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
465 | |
466 | l.base = 0; | |
467 | l.vict = 0; | |
468 | iotlb_lock_set(obj, &l); | |
469 | ||
470 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
471 | ||
ebf7cda0 | 472 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 473 | } |
ddfa975a | 474 | |
e4efd94b | 475 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 476 | |
bd4396f0 SA |
477 | #define pr_reg(name) \ |
478 | do { \ | |
479 | ssize_t bytes; \ | |
480 | const char *str = "%20s: %08x\n"; \ | |
481 | const int maxcol = 32; \ | |
482 | bytes = snprintf(p, maxcol, str, __stringify(name), \ | |
483 | iommu_read_reg(obj, MMU_##name)); \ | |
484 | p += bytes; \ | |
485 | len -= bytes; \ | |
486 | if (len < maxcol) \ | |
487 | goto out; \ | |
488 | } while (0) | |
489 | ||
490 | static ssize_t | |
491 | omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len) | |
492 | { | |
493 | char *p = buf; | |
494 | ||
495 | pr_reg(REVISION); | |
496 | pr_reg(IRQSTATUS); | |
497 | pr_reg(IRQENABLE); | |
498 | pr_reg(WALKING_ST); | |
499 | pr_reg(CNTL); | |
500 | pr_reg(FAULT_AD); | |
501 | pr_reg(TTB); | |
502 | pr_reg(LOCK); | |
503 | pr_reg(LD_TLB); | |
504 | pr_reg(CAM); | |
505 | pr_reg(RAM); | |
506 | pr_reg(GFLUSH); | |
507 | pr_reg(FLUSH_ENTRY); | |
508 | pr_reg(READ_CAM); | |
509 | pr_reg(READ_RAM); | |
510 | pr_reg(EMU_FAULT_AD); | |
511 | out: | |
512 | return p - buf; | |
513 | } | |
514 | ||
6c32df43 | 515 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 516 | { |
a9dcad5e HD |
517 | if (!obj || !buf) |
518 | return -EINVAL; | |
519 | ||
ebf7cda0 | 520 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 521 | |
bd4396f0 | 522 | bytes = omap2_iommu_dump_ctx(obj, buf, bytes); |
a9dcad5e | 523 | |
ebf7cda0 | 524 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
525 | |
526 | return bytes; | |
527 | } | |
6c32df43 | 528 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 529 | |
6c32df43 OBC |
530 | static int |
531 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
532 | { |
533 | int i; | |
37c2836c HD |
534 | struct iotlb_lock saved; |
535 | struct cr_regs tmp; | |
a9dcad5e HD |
536 | struct cr_regs *p = crs; |
537 | ||
ebf7cda0 | 538 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 539 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 540 | |
37c2836c | 541 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
542 | if (!iotlb_cr_valid(&tmp)) |
543 | continue; | |
a9dcad5e HD |
544 | *p++ = tmp; |
545 | } | |
37c2836c | 546 | |
a9dcad5e | 547 | iotlb_lock_set(obj, &saved); |
ebf7cda0 | 548 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
549 | |
550 | return p - crs; | |
551 | } | |
552 | ||
bd4396f0 SA |
553 | /** |
554 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
555 | * @obj: target iommu | |
556 | * @cr: contents of cam and ram register | |
557 | * @buf: output buffer | |
558 | **/ | |
559 | static ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, | |
560 | char *buf) | |
561 | { | |
562 | char *p = buf; | |
563 | ||
564 | /* FIXME: Need more detail analysis of cam/ram */ | |
565 | p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, | |
566 | (cr->cam & MMU_CAM_P) ? 1 : 0); | |
567 | ||
568 | return p - buf; | |
569 | } | |
570 | ||
a9dcad5e | 571 | /** |
6c32df43 | 572 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
573 | * @obj: target iommu |
574 | * @buf: output buffer | |
575 | **/ | |
6c32df43 | 576 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 577 | { |
14e0e679 | 578 | int i, num; |
a9dcad5e HD |
579 | struct cr_regs *cr; |
580 | char *p = buf; | |
581 | ||
14e0e679 HD |
582 | num = bytes / sizeof(*cr); |
583 | num = min(obj->nr_tlb_entries, num); | |
584 | ||
585 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
586 | if (!cr) |
587 | return 0; | |
588 | ||
14e0e679 HD |
589 | num = __dump_tlb_entries(obj, cr, num); |
590 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
591 | p += iotlb_dump_cr(obj, cr + i, p); |
592 | kfree(cr); | |
593 | ||
594 | return p - buf; | |
595 | } | |
6c32df43 | 596 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 597 | |
6c32df43 | 598 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
599 | { |
600 | return driver_for_each_device(&omap_iommu_driver.driver, | |
601 | NULL, data, fn); | |
602 | } | |
6c32df43 | 603 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
604 | |
605 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
606 | ||
607 | /* | |
608 | * H/W pagetable operations | |
609 | */ | |
610 | static void flush_iopgd_range(u32 *first, u32 *last) | |
611 | { | |
612 | /* FIXME: L2 cache should be taken care of if it exists */ | |
613 | do { | |
614 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
615 | : : "r" (first)); | |
616 | first += L1_CACHE_BYTES / sizeof(*first); | |
617 | } while (first <= last); | |
618 | } | |
619 | ||
620 | static void flush_iopte_range(u32 *first, u32 *last) | |
621 | { | |
622 | /* FIXME: L2 cache should be taken care of if it exists */ | |
623 | do { | |
624 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
625 | : : "r" (first)); | |
626 | first += L1_CACHE_BYTES / sizeof(*first); | |
627 | } while (first <= last); | |
628 | } | |
629 | ||
630 | static void iopte_free(u32 *iopte) | |
631 | { | |
632 | /* Note: freed iopte's must be clean ready for re-use */ | |
e28045ab ZZ |
633 | if (iopte) |
634 | kmem_cache_free(iopte_cachep, iopte); | |
a9dcad5e HD |
635 | } |
636 | ||
6c32df43 | 637 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
638 | { |
639 | u32 *iopte; | |
640 | ||
641 | /* a table has already existed */ | |
642 | if (*iopgd) | |
643 | goto pte_ready; | |
644 | ||
645 | /* | |
646 | * do the allocation outside the page table lock | |
647 | */ | |
648 | spin_unlock(&obj->page_table_lock); | |
649 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
650 | spin_lock(&obj->page_table_lock); | |
651 | ||
652 | if (!*iopgd) { | |
653 | if (!iopte) | |
654 | return ERR_PTR(-ENOMEM); | |
655 | ||
656 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
657 | flush_iopgd_range(iopgd, iopgd); | |
658 | ||
659 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
660 | } else { | |
661 | /* We raced, free the reduniovant table */ | |
662 | iopte_free(iopte); | |
663 | } | |
664 | ||
665 | pte_ready: | |
666 | iopte = iopte_offset(iopgd, da); | |
667 | ||
668 | dev_vdbg(obj->dev, | |
669 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
670 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
671 | ||
672 | return iopte; | |
673 | } | |
674 | ||
6c32df43 | 675 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
676 | { |
677 | u32 *iopgd = iopgd_offset(obj, da); | |
678 | ||
4abb7617 HD |
679 | if ((da | pa) & ~IOSECTION_MASK) { |
680 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
681 | __func__, da, pa, IOSECTION_SIZE); | |
682 | return -EINVAL; | |
683 | } | |
684 | ||
a9dcad5e HD |
685 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
686 | flush_iopgd_range(iopgd, iopgd); | |
687 | return 0; | |
688 | } | |
689 | ||
6c32df43 | 690 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
691 | { |
692 | u32 *iopgd = iopgd_offset(obj, da); | |
693 | int i; | |
694 | ||
4abb7617 HD |
695 | if ((da | pa) & ~IOSUPER_MASK) { |
696 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
697 | __func__, da, pa, IOSUPER_SIZE); | |
698 | return -EINVAL; | |
699 | } | |
700 | ||
a9dcad5e HD |
701 | for (i = 0; i < 16; i++) |
702 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
703 | flush_iopgd_range(iopgd, iopgd + 15); | |
704 | return 0; | |
705 | } | |
706 | ||
6c32df43 | 707 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
708 | { |
709 | u32 *iopgd = iopgd_offset(obj, da); | |
710 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
711 | ||
712 | if (IS_ERR(iopte)) | |
713 | return PTR_ERR(iopte); | |
714 | ||
715 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
716 | flush_iopte_range(iopte, iopte); | |
717 | ||
718 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
719 | __func__, da, pa, iopte, *iopte); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
6c32df43 | 724 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
725 | { |
726 | u32 *iopgd = iopgd_offset(obj, da); | |
727 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
728 | int i; | |
729 | ||
4abb7617 HD |
730 | if ((da | pa) & ~IOLARGE_MASK) { |
731 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
732 | __func__, da, pa, IOLARGE_SIZE); | |
733 | return -EINVAL; | |
734 | } | |
735 | ||
a9dcad5e HD |
736 | if (IS_ERR(iopte)) |
737 | return PTR_ERR(iopte); | |
738 | ||
739 | for (i = 0; i < 16; i++) | |
740 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
741 | flush_iopte_range(iopte, iopte + 15); | |
742 | return 0; | |
743 | } | |
744 | ||
6c32df43 OBC |
745 | static int |
746 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 747 | { |
6c32df43 | 748 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
749 | u32 prot; |
750 | int err; | |
751 | ||
752 | if (!obj || !e) | |
753 | return -EINVAL; | |
754 | ||
755 | switch (e->pgsz) { | |
756 | case MMU_CAM_PGSZ_16M: | |
757 | fn = iopgd_alloc_super; | |
758 | break; | |
759 | case MMU_CAM_PGSZ_1M: | |
760 | fn = iopgd_alloc_section; | |
761 | break; | |
762 | case MMU_CAM_PGSZ_64K: | |
763 | fn = iopte_alloc_large; | |
764 | break; | |
765 | case MMU_CAM_PGSZ_4K: | |
766 | fn = iopte_alloc_page; | |
767 | break; | |
768 | default: | |
769 | fn = NULL; | |
770 | BUG(); | |
771 | break; | |
772 | } | |
773 | ||
774 | prot = get_iopte_attr(e); | |
775 | ||
776 | spin_lock(&obj->page_table_lock); | |
777 | err = fn(obj, e->da, e->pa, prot); | |
778 | spin_unlock(&obj->page_table_lock); | |
779 | ||
780 | return err; | |
781 | } | |
782 | ||
783 | /** | |
6c32df43 | 784 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
785 | * @obj: target iommu |
786 | * @e: an iommu tlb entry info | |
787 | **/ | |
6c32df43 | 788 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
789 | { |
790 | int err; | |
791 | ||
792 | flush_iotlb_page(obj, e->da); | |
793 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 794 | if (!err) |
5da14a47 | 795 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
796 | return err; |
797 | } | |
6c32df43 | 798 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
799 | |
800 | /** | |
801 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
802 | * @obj: target iommu | |
803 | * @da: iommu device virtual address | |
804 | * @ppgd: iommu pgd entry pointer to be returned | |
805 | * @ppte: iommu pte entry pointer to be returned | |
806 | **/ | |
e1f23813 OBC |
807 | static void |
808 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
809 | { |
810 | u32 *iopgd, *iopte = NULL; | |
811 | ||
812 | iopgd = iopgd_offset(obj, da); | |
813 | if (!*iopgd) | |
814 | goto out; | |
815 | ||
a1a54456 | 816 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
817 | iopte = iopte_offset(iopgd, da); |
818 | out: | |
819 | *ppgd = iopgd; | |
820 | *ppte = iopte; | |
821 | } | |
a9dcad5e | 822 | |
6c32df43 | 823 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
824 | { |
825 | size_t bytes; | |
826 | u32 *iopgd = iopgd_offset(obj, da); | |
827 | int nent = 1; | |
828 | ||
829 | if (!*iopgd) | |
830 | return 0; | |
831 | ||
a1a54456 | 832 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
833 | int i; |
834 | u32 *iopte = iopte_offset(iopgd, da); | |
835 | ||
836 | bytes = IOPTE_SIZE; | |
837 | if (*iopte & IOPTE_LARGE) { | |
838 | nent *= 16; | |
839 | /* rewind to the 1st entry */ | |
c127c7dc | 840 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
841 | } |
842 | bytes *= nent; | |
843 | memset(iopte, 0, nent * sizeof(*iopte)); | |
844 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
845 | ||
846 | /* | |
847 | * do table walk to check if this table is necessary or not | |
848 | */ | |
849 | iopte = iopte_offset(iopgd, 0); | |
850 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
851 | if (iopte[i]) | |
852 | goto out; | |
853 | ||
854 | iopte_free(iopte); | |
855 | nent = 1; /* for the next L1 entry */ | |
856 | } else { | |
857 | bytes = IOPGD_SIZE; | |
dcc730dc | 858 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
859 | nent *= 16; |
860 | /* rewind to the 1st entry */ | |
8d33ea58 | 861 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
862 | } |
863 | bytes *= nent; | |
864 | } | |
865 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
866 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
867 | out: | |
868 | return bytes; | |
869 | } | |
870 | ||
871 | /** | |
872 | * iopgtable_clear_entry - Remove an iommu pte entry | |
873 | * @obj: target iommu | |
874 | * @da: iommu device virtual address | |
875 | **/ | |
6c32df43 | 876 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
877 | { |
878 | size_t bytes; | |
879 | ||
880 | spin_lock(&obj->page_table_lock); | |
881 | ||
882 | bytes = iopgtable_clear_entry_core(obj, da); | |
883 | flush_iotlb_page(obj, da); | |
884 | ||
885 | spin_unlock(&obj->page_table_lock); | |
886 | ||
887 | return bytes; | |
888 | } | |
a9dcad5e | 889 | |
6c32df43 | 890 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
891 | { |
892 | int i; | |
893 | ||
894 | spin_lock(&obj->page_table_lock); | |
895 | ||
896 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
897 | u32 da; | |
898 | u32 *iopgd; | |
899 | ||
900 | da = i << IOPGD_SHIFT; | |
901 | iopgd = iopgd_offset(obj, da); | |
902 | ||
903 | if (!*iopgd) | |
904 | continue; | |
905 | ||
a1a54456 | 906 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
907 | iopte_free(iopte_offset(iopgd, 0)); |
908 | ||
909 | *iopgd = 0; | |
910 | flush_iopgd_range(iopgd, iopgd); | |
911 | } | |
912 | ||
913 | flush_iotlb_all(obj); | |
914 | ||
915 | spin_unlock(&obj->page_table_lock); | |
916 | } | |
917 | ||
918 | /* | |
919 | * Device IOMMU generic operations | |
920 | */ | |
921 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
922 | { | |
d594f1f3 | 923 | u32 da, errs; |
a9dcad5e | 924 | u32 *iopgd, *iopte; |
6c32df43 | 925 | struct omap_iommu *obj = data; |
e7f10f02 | 926 | struct iommu_domain *domain = obj->domain; |
2088ecba | 927 | struct omap_iommu_domain *omap_domain = domain->priv; |
a9dcad5e | 928 | |
2088ecba | 929 | if (!omap_domain->iommu_dev) |
a9dcad5e HD |
930 | return IRQ_NONE; |
931 | ||
d594f1f3 | 932 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
933 | if (errs == 0) |
934 | return IRQ_HANDLED; | |
d594f1f3 DC |
935 | |
936 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 937 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
938 | return IRQ_HANDLED; |
939 | ||
37b29810 HD |
940 | iommu_disable(obj); |
941 | ||
a9dcad5e HD |
942 | iopgd = iopgd_offset(obj, da); |
943 | ||
a1a54456 | 944 | if (!iopgd_is_table(*iopgd)) { |
b6c2e09f SA |
945 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n", |
946 | obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
947 | return IRQ_NONE; |
948 | } | |
949 | ||
950 | iopte = iopte_offset(iopgd, da); | |
951 | ||
b6c2e09f SA |
952 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n", |
953 | obj->name, errs, da, iopgd, *iopgd, iopte, *iopte); | |
a9dcad5e HD |
954 | |
955 | return IRQ_NONE; | |
956 | } | |
957 | ||
958 | static int device_match_by_alias(struct device *dev, void *data) | |
959 | { | |
6c32df43 | 960 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
961 | const char *name = data; |
962 | ||
963 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
964 | ||
965 | return strcmp(obj->name, name) == 0; | |
966 | } | |
967 | ||
968 | /** | |
f626b52d | 969 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 970 | * @name: name of target omap iommu device |
f626b52d | 971 | * @iopgd: page table |
a9dcad5e | 972 | **/ |
fabdbca8 | 973 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e | 974 | { |
7ee08b9e | 975 | int err; |
fabdbca8 OBC |
976 | struct device *dev; |
977 | struct omap_iommu *obj; | |
978 | ||
979 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
980 | (void *)name, | |
981 | device_match_by_alias); | |
982 | if (!dev) | |
7ee08b9e | 983 | return ERR_PTR(-ENODEV); |
fabdbca8 OBC |
984 | |
985 | obj = to_iommu(dev); | |
a9dcad5e | 986 | |
f626b52d | 987 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 988 | |
f626b52d OBC |
989 | obj->iopgd = iopgd; |
990 | err = iommu_enable(obj); | |
991 | if (err) | |
992 | goto err_enable; | |
993 | flush_iotlb_all(obj); | |
994 | ||
f626b52d | 995 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
996 | |
997 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
998 | return obj; | |
999 | ||
a9dcad5e | 1000 | err_enable: |
f626b52d | 1001 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
1002 | return ERR_PTR(err); |
1003 | } | |
a9dcad5e HD |
1004 | |
1005 | /** | |
f626b52d | 1006 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
1007 | * @obj: target iommu |
1008 | **/ | |
6c32df43 | 1009 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 1010 | { |
acf9d467 | 1011 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
1012 | return; |
1013 | ||
f626b52d | 1014 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 1015 | |
2088ecba | 1016 | iommu_disable(obj); |
f626b52d | 1017 | obj->iopgd = NULL; |
d594f1f3 | 1018 | |
f626b52d | 1019 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 1020 | |
a9dcad5e | 1021 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 1022 | } |
d594f1f3 | 1023 | |
a9dcad5e HD |
1024 | /* |
1025 | * OMAP Device MMU(IOMMU) detection | |
1026 | */ | |
d34d6517 | 1027 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
1028 | { |
1029 | int err = -ENODEV; | |
a9dcad5e | 1030 | int irq; |
6c32df43 | 1031 | struct omap_iommu *obj; |
a9dcad5e HD |
1032 | struct resource *res; |
1033 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
3c92748d | 1034 | struct device_node *of = pdev->dev.of_node; |
a9dcad5e | 1035 | |
f129b3df | 1036 | obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
a9dcad5e HD |
1037 | if (!obj) |
1038 | return -ENOMEM; | |
1039 | ||
3c92748d FV |
1040 | if (of) { |
1041 | obj->name = dev_name(&pdev->dev); | |
1042 | obj->nr_tlb_entries = 32; | |
1043 | err = of_property_read_u32(of, "ti,#tlb-entries", | |
1044 | &obj->nr_tlb_entries); | |
1045 | if (err && err != -EINVAL) | |
1046 | return err; | |
1047 | if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8) | |
1048 | return -EINVAL; | |
b148d5fb SA |
1049 | if (of_find_property(of, "ti,iommu-bus-err-back", NULL)) |
1050 | obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN; | |
3c92748d FV |
1051 | } else { |
1052 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
1053 | obj->name = pdata->name; | |
3c92748d | 1054 | } |
3c92748d | 1055 | |
a9dcad5e HD |
1056 | obj->dev = &pdev->dev; |
1057 | obj->ctx = (void *)obj + sizeof(*obj); | |
1058 | ||
f626b52d | 1059 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e | 1060 | spin_lock_init(&obj->page_table_lock); |
a9dcad5e HD |
1061 | |
1062 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f129b3df SA |
1063 | obj->regbase = devm_ioremap_resource(obj->dev, res); |
1064 | if (IS_ERR(obj->regbase)) | |
1065 | return PTR_ERR(obj->regbase); | |
da4a0f76 | 1066 | |
a9dcad5e | 1067 | irq = platform_get_irq(pdev, 0); |
f129b3df SA |
1068 | if (irq < 0) |
1069 | return -ENODEV; | |
1070 | ||
1071 | err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED, | |
1072 | dev_name(obj->dev), obj); | |
a9dcad5e | 1073 | if (err < 0) |
f129b3df | 1074 | return err; |
a9dcad5e HD |
1075 | platform_set_drvdata(pdev, obj); |
1076 | ||
ebf7cda0 ORL |
1077 | pm_runtime_irq_safe(obj->dev); |
1078 | pm_runtime_enable(obj->dev); | |
1079 | ||
a9dcad5e HD |
1080 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
1081 | return 0; | |
a9dcad5e HD |
1082 | } |
1083 | ||
d34d6517 | 1084 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e | 1085 | { |
6c32df43 | 1086 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e | 1087 | |
a9dcad5e | 1088 | iopgtable_clear_entry_all(obj); |
a9dcad5e | 1089 | |
ebf7cda0 ORL |
1090 | pm_runtime_disable(obj->dev); |
1091 | ||
a9dcad5e | 1092 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
a9dcad5e HD |
1093 | return 0; |
1094 | } | |
1095 | ||
d943b0ff | 1096 | static const struct of_device_id omap_iommu_of_match[] = { |
3c92748d FV |
1097 | { .compatible = "ti,omap2-iommu" }, |
1098 | { .compatible = "ti,omap4-iommu" }, | |
1099 | { .compatible = "ti,dra7-iommu" }, | |
1100 | {}, | |
1101 | }; | |
1102 | MODULE_DEVICE_TABLE(of, omap_iommu_of_match); | |
1103 | ||
a9dcad5e HD |
1104 | static struct platform_driver omap_iommu_driver = { |
1105 | .probe = omap_iommu_probe, | |
d34d6517 | 1106 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1107 | .driver = { |
1108 | .name = "omap-iommu", | |
3c92748d | 1109 | .of_match_table = of_match_ptr(omap_iommu_of_match), |
a9dcad5e HD |
1110 | }, |
1111 | }; | |
1112 | ||
1113 | static void iopte_cachep_ctor(void *iopte) | |
1114 | { | |
1115 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1116 | } | |
1117 | ||
286f600b | 1118 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz) |
ed1c7de2 TL |
1119 | { |
1120 | memset(e, 0, sizeof(*e)); | |
1121 | ||
1122 | e->da = da; | |
1123 | e->pa = pa; | |
d760e3e0 | 1124 | e->valid = MMU_CAM_V; |
286f600b LP |
1125 | e->pgsz = pgsz; |
1126 | e->endian = MMU_RAM_ENDIAN_LITTLE; | |
1127 | e->elsz = MMU_RAM_ELSZ_8; | |
1128 | e->mixed = 0; | |
ed1c7de2 TL |
1129 | |
1130 | return iopgsz_to_bytes(e->pgsz); | |
1131 | } | |
1132 | ||
f626b52d | 1133 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1134 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1135 | { |
1136 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1137 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1138 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1139 | struct iotlb_entry e; |
1140 | int omap_pgsz; | |
286f600b | 1141 | u32 ret; |
f626b52d | 1142 | |
f626b52d OBC |
1143 | omap_pgsz = bytes_to_iopgsz(bytes); |
1144 | if (omap_pgsz < 0) { | |
1145 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
1149 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1150 | ||
286f600b | 1151 | iotlb_init_entry(&e, da, pa, omap_pgsz); |
f626b52d | 1152 | |
6c32df43 | 1153 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1154 | if (ret) |
6c32df43 | 1155 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1156 | |
b4550d41 | 1157 | return ret; |
f626b52d OBC |
1158 | } |
1159 | ||
5009065d OBC |
1160 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1161 | size_t size) | |
f626b52d OBC |
1162 | { |
1163 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1164 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1165 | struct device *dev = oiommu->dev; |
f626b52d | 1166 | |
5009065d | 1167 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1168 | |
5009065d | 1169 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1170 | } |
1171 | ||
1172 | static int | |
1173 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1174 | { | |
1175 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1176 | struct omap_iommu *oiommu; |
fabdbca8 | 1177 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1178 | int ret = 0; |
1179 | ||
e3f595b9 SA |
1180 | if (!arch_data || !arch_data->name) { |
1181 | dev_err(dev, "device doesn't have an associated iommu\n"); | |
1182 | return -EINVAL; | |
1183 | } | |
1184 | ||
f626b52d OBC |
1185 | spin_lock(&omap_domain->lock); |
1186 | ||
1187 | /* only a single device is supported per domain for now */ | |
1188 | if (omap_domain->iommu_dev) { | |
1189 | dev_err(dev, "iommu domain is already attached\n"); | |
1190 | ret = -EBUSY; | |
1191 | goto out; | |
1192 | } | |
1193 | ||
1194 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1195 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1196 | if (IS_ERR(oiommu)) { |
1197 | ret = PTR_ERR(oiommu); | |
1198 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1199 | goto out; | |
1200 | } | |
1201 | ||
fabdbca8 | 1202 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1203 | omap_domain->dev = dev; |
e7f10f02 | 1204 | oiommu->domain = domain; |
f626b52d OBC |
1205 | |
1206 | out: | |
1207 | spin_unlock(&omap_domain->lock); | |
1208 | return ret; | |
1209 | } | |
1210 | ||
803b5277 ORL |
1211 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1212 | struct device *dev) | |
f626b52d | 1213 | { |
fabdbca8 | 1214 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1215 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1216 | |
1217 | /* only a single device is supported per domain for now */ | |
1218 | if (omap_domain->iommu_dev != oiommu) { | |
1219 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1220 | return; |
f626b52d OBC |
1221 | } |
1222 | ||
1223 | iopgtable_clear_entry_all(oiommu); | |
1224 | ||
1225 | omap_iommu_detach(oiommu); | |
1226 | ||
fabdbca8 | 1227 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1228 | omap_domain->dev = NULL; |
1229 | } | |
f626b52d | 1230 | |
803b5277 ORL |
1231 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1232 | struct device *dev) | |
1233 | { | |
1234 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1235 | ||
1236 | spin_lock(&omap_domain->lock); | |
1237 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1238 | spin_unlock(&omap_domain->lock); |
1239 | } | |
1240 | ||
1241 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1242 | { | |
1243 | struct omap_iommu_domain *omap_domain; | |
1244 | ||
1245 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1246 | if (!omap_domain) { | |
1247 | pr_err("kzalloc failed\n"); | |
1248 | goto out; | |
1249 | } | |
1250 | ||
1251 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1252 | if (!omap_domain->pgtable) { | |
1253 | pr_err("kzalloc failed\n"); | |
1254 | goto fail_nomem; | |
1255 | } | |
1256 | ||
1257 | /* | |
1258 | * should never fail, but please keep this around to ensure | |
1259 | * we keep the hardware happy | |
1260 | */ | |
1261 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1262 | ||
1263 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1264 | spin_lock_init(&omap_domain->lock); | |
1265 | ||
1266 | domain->priv = omap_domain; | |
1267 | ||
2c6edb0c JR |
1268 | domain->geometry.aperture_start = 0; |
1269 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1270 | domain->geometry.force_aperture = true; | |
1271 | ||
f626b52d OBC |
1272 | return 0; |
1273 | ||
1274 | fail_nomem: | |
1275 | kfree(omap_domain); | |
1276 | out: | |
1277 | return -ENOMEM; | |
1278 | } | |
1279 | ||
f626b52d OBC |
1280 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1281 | { | |
1282 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1283 | ||
1284 | domain->priv = NULL; | |
1285 | ||
803b5277 ORL |
1286 | /* |
1287 | * An iommu device is still attached | |
1288 | * (currently, only one device can be attached) ? | |
1289 | */ | |
1290 | if (omap_domain->iommu_dev) | |
1291 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1292 | ||
f626b52d OBC |
1293 | kfree(omap_domain->pgtable); |
1294 | kfree(omap_domain); | |
1295 | } | |
1296 | ||
1297 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 1298 | dma_addr_t da) |
f626b52d OBC |
1299 | { |
1300 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1301 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1302 | struct device *dev = oiommu->dev; |
1303 | u32 *pgd, *pte; | |
1304 | phys_addr_t ret = 0; | |
1305 | ||
1306 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1307 | ||
1308 | if (pte) { | |
1309 | if (iopte_is_small(*pte)) | |
1310 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1311 | else if (iopte_is_large(*pte)) | |
1312 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1313 | else | |
2abfcfbc SA |
1314 | dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte, |
1315 | (unsigned long long)da); | |
f626b52d OBC |
1316 | } else { |
1317 | if (iopgd_is_section(*pgd)) | |
1318 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1319 | else if (iopgd_is_super(*pgd)) | |
1320 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1321 | else | |
2abfcfbc SA |
1322 | dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd, |
1323 | (unsigned long long)da); | |
f626b52d OBC |
1324 | } |
1325 | ||
1326 | return ret; | |
1327 | } | |
1328 | ||
07a02030 LP |
1329 | static int omap_iommu_add_device(struct device *dev) |
1330 | { | |
1331 | struct omap_iommu_arch_data *arch_data; | |
1332 | struct device_node *np; | |
7d682774 | 1333 | struct platform_device *pdev; |
07a02030 LP |
1334 | |
1335 | /* | |
1336 | * Allocate the archdata iommu structure for DT-based devices. | |
1337 | * | |
1338 | * TODO: Simplify this when removing non-DT support completely from the | |
1339 | * IOMMU users. | |
1340 | */ | |
1341 | if (!dev->of_node) | |
1342 | return 0; | |
1343 | ||
1344 | np = of_parse_phandle(dev->of_node, "iommus", 0); | |
1345 | if (!np) | |
1346 | return 0; | |
1347 | ||
7d682774 SA |
1348 | pdev = of_find_device_by_node(np); |
1349 | if (WARN_ON(!pdev)) { | |
1350 | of_node_put(np); | |
1351 | return -EINVAL; | |
1352 | } | |
1353 | ||
07a02030 LP |
1354 | arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL); |
1355 | if (!arch_data) { | |
1356 | of_node_put(np); | |
1357 | return -ENOMEM; | |
1358 | } | |
1359 | ||
7d682774 | 1360 | arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL); |
07a02030 LP |
1361 | dev->archdata.iommu = arch_data; |
1362 | ||
1363 | of_node_put(np); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static void omap_iommu_remove_device(struct device *dev) | |
1369 | { | |
1370 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
1371 | ||
1372 | if (!dev->of_node || !arch_data) | |
1373 | return; | |
1374 | ||
1375 | kfree(arch_data->name); | |
1376 | kfree(arch_data); | |
1377 | } | |
1378 | ||
b22f6434 | 1379 | static const struct iommu_ops omap_iommu_ops = { |
f626b52d OBC |
1380 | .domain_init = omap_iommu_domain_init, |
1381 | .domain_destroy = omap_iommu_domain_destroy, | |
1382 | .attach_dev = omap_iommu_attach_dev, | |
1383 | .detach_dev = omap_iommu_detach_dev, | |
1384 | .map = omap_iommu_map, | |
1385 | .unmap = omap_iommu_unmap, | |
1386 | .iova_to_phys = omap_iommu_iova_to_phys, | |
07a02030 LP |
1387 | .add_device = omap_iommu_add_device, |
1388 | .remove_device = omap_iommu_remove_device, | |
66bc8cf3 | 1389 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1390 | }; |
1391 | ||
a9dcad5e HD |
1392 | static int __init omap_iommu_init(void) |
1393 | { | |
1394 | struct kmem_cache *p; | |
1395 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1396 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1397 | ||
1398 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1399 | iopte_cachep_ctor); | |
1400 | if (!p) | |
1401 | return -ENOMEM; | |
1402 | iopte_cachep = p; | |
1403 | ||
a65bc64f | 1404 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1405 | |
a9dcad5e HD |
1406 | return platform_driver_register(&omap_iommu_driver); |
1407 | } | |
435792d9 OBC |
1408 | /* must be ready before omap3isp is probed */ |
1409 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1410 | |
1411 | static void __exit omap_iommu_exit(void) | |
1412 | { | |
1413 | kmem_cache_destroy(iopte_cachep); | |
1414 | ||
1415 | platform_driver_unregister(&omap_iommu_driver); | |
1416 | } | |
1417 | module_exit(omap_iommu_exit); | |
1418 | ||
1419 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1420 | MODULE_ALIAS("platform:omap-iommu"); | |
1421 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1422 | MODULE_LICENSE("GPL v2"); |