Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
f626b52d OBC |
21 | #include <linux/iommu.h> |
22 | #include <linux/mutex.h> | |
23 | #include <linux/spinlock.h> | |
a9dcad5e HD |
24 | |
25 | #include <asm/cacheflush.h> | |
26 | ||
ce491cf8 | 27 | #include <plat/iommu.h> |
a9dcad5e | 28 | |
fcf3a6ef | 29 | #include <plat/iopgtable.h> |
a9dcad5e | 30 | |
37c2836c HD |
31 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
32 | for (__i = 0; \ | |
33 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
34 | __i++) | |
35 | ||
66bc8cf3 OBC |
36 | /* bitmap of the page sizes currently supported */ |
37 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
38 | ||
f626b52d OBC |
39 | /** |
40 | * struct omap_iommu_domain - omap iommu domain | |
41 | * @pgtable: the page table | |
42 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
43 | * iommu device can be attached for now. | |
44 | * @lock: domain lock, should be taken when attaching/detaching | |
45 | */ | |
46 | struct omap_iommu_domain { | |
47 | u32 *pgtable; | |
6c32df43 | 48 | struct omap_iommu *iommu_dev; |
f626b52d OBC |
49 | spinlock_t lock; |
50 | }; | |
51 | ||
a9dcad5e HD |
52 | /* accommodate the difference between omap1 and omap2/3 */ |
53 | static const struct iommu_functions *arch_iommu; | |
54 | ||
55 | static struct platform_driver omap_iommu_driver; | |
56 | static struct kmem_cache *iopte_cachep; | |
57 | ||
58 | /** | |
6c32df43 | 59 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
60 | * @ops: a pointer to architecture specific iommu functions |
61 | * | |
62 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
63 | * omap series. This interface installs such an iommu algorighm. | |
64 | **/ | |
6c32df43 | 65 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
66 | { |
67 | if (arch_iommu) | |
68 | return -EBUSY; | |
69 | ||
70 | arch_iommu = ops; | |
71 | return 0; | |
72 | } | |
6c32df43 | 73 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
74 | |
75 | /** | |
6c32df43 | 76 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
77 | * @ops: a pointer to architecture specific iommu functions |
78 | * | |
79 | * This interface uninstalls the iommu algorighm installed previously. | |
80 | **/ | |
6c32df43 | 81 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
82 | { |
83 | if (arch_iommu != ops) | |
84 | pr_err("%s: not your arch\n", __func__); | |
85 | ||
86 | arch_iommu = NULL; | |
87 | } | |
6c32df43 | 88 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
89 | |
90 | /** | |
6c32df43 | 91 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
a9dcad5e HD |
92 | * @obj: target iommu |
93 | **/ | |
6c32df43 | 94 | void omap_iommu_save_ctx(struct omap_iommu *obj) |
a9dcad5e HD |
95 | { |
96 | arch_iommu->save_ctx(obj); | |
97 | } | |
6c32df43 | 98 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
99 | |
100 | /** | |
6c32df43 | 101 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
a9dcad5e HD |
102 | * @obj: target iommu |
103 | **/ | |
6c32df43 | 104 | void omap_iommu_restore_ctx(struct omap_iommu *obj) |
a9dcad5e HD |
105 | { |
106 | arch_iommu->restore_ctx(obj); | |
107 | } | |
6c32df43 | 108 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
109 | |
110 | /** | |
6c32df43 | 111 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 112 | **/ |
6c32df43 | 113 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
114 | { |
115 | return arch_iommu->version; | |
116 | } | |
6c32df43 | 117 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 118 | |
6c32df43 | 119 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
120 | { |
121 | int err; | |
122 | ||
123 | if (!obj) | |
124 | return -EINVAL; | |
125 | ||
ef4815ab MH |
126 | if (!arch_iommu) |
127 | return -ENODEV; | |
128 | ||
a9dcad5e HD |
129 | clk_enable(obj->clk); |
130 | ||
131 | err = arch_iommu->enable(obj); | |
132 | ||
133 | clk_disable(obj->clk); | |
134 | return err; | |
135 | } | |
136 | ||
6c32df43 | 137 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e HD |
138 | { |
139 | if (!obj) | |
140 | return; | |
141 | ||
142 | clk_enable(obj->clk); | |
143 | ||
144 | arch_iommu->disable(obj); | |
145 | ||
146 | clk_disable(obj->clk); | |
147 | } | |
148 | ||
149 | /* | |
150 | * TLB operations | |
151 | */ | |
6c32df43 | 152 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
153 | { |
154 | BUG_ON(!cr || !e); | |
155 | ||
156 | arch_iommu->cr_to_e(cr, e); | |
157 | } | |
6c32df43 | 158 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
159 | |
160 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
161 | { | |
162 | if (!cr) | |
163 | return -EINVAL; | |
164 | ||
165 | return arch_iommu->cr_valid(cr); | |
166 | } | |
167 | ||
6c32df43 | 168 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
169 | struct iotlb_entry *e) |
170 | { | |
171 | if (!e) | |
172 | return NULL; | |
173 | ||
174 | return arch_iommu->alloc_cr(obj, e); | |
175 | } | |
176 | ||
e1f23813 | 177 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
178 | { |
179 | return arch_iommu->cr_to_virt(cr); | |
180 | } | |
a9dcad5e HD |
181 | |
182 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
183 | { | |
184 | return arch_iommu->get_pte_attr(e); | |
185 | } | |
186 | ||
6c32df43 | 187 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
188 | { |
189 | return arch_iommu->fault_isr(obj, da); | |
190 | } | |
191 | ||
6c32df43 | 192 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
193 | { |
194 | u32 val; | |
195 | ||
196 | val = iommu_read_reg(obj, MMU_LOCK); | |
197 | ||
198 | l->base = MMU_LOCK_BASE(val); | |
199 | l->vict = MMU_LOCK_VICT(val); | |
200 | ||
a9dcad5e HD |
201 | } |
202 | ||
6c32df43 | 203 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
204 | { |
205 | u32 val; | |
206 | ||
a9dcad5e HD |
207 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
208 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
209 | ||
210 | iommu_write_reg(obj, val, MMU_LOCK); | |
211 | } | |
212 | ||
6c32df43 | 213 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
214 | { |
215 | arch_iommu->tlb_read_cr(obj, cr); | |
216 | } | |
217 | ||
6c32df43 | 218 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
219 | { |
220 | arch_iommu->tlb_load_cr(obj, cr); | |
221 | ||
222 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
223 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
224 | } | |
225 | ||
226 | /** | |
227 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
228 | * @obj: target iommu | |
229 | * @cr: contents of cam and ram register | |
230 | * @buf: output buffer | |
231 | **/ | |
6c32df43 | 232 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
233 | char *buf) |
234 | { | |
235 | BUG_ON(!cr || !buf); | |
236 | ||
237 | return arch_iommu->dump_cr(obj, cr, buf); | |
238 | } | |
239 | ||
37c2836c | 240 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 241 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
242 | { |
243 | struct cr_regs cr; | |
244 | struct iotlb_lock l; | |
245 | ||
246 | iotlb_lock_get(obj, &l); | |
247 | l.vict = n; | |
248 | iotlb_lock_set(obj, &l); | |
249 | iotlb_read_cr(obj, &cr); | |
250 | ||
251 | return cr; | |
252 | } | |
253 | ||
a9dcad5e HD |
254 | /** |
255 | * load_iotlb_entry - Set an iommu tlb entry | |
256 | * @obj: target iommu | |
257 | * @e: an iommu tlb entry info | |
258 | **/ | |
5da14a47 | 259 | #ifdef PREFETCH_IOTLB |
6c32df43 | 260 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 261 | { |
a9dcad5e HD |
262 | int err = 0; |
263 | struct iotlb_lock l; | |
264 | struct cr_regs *cr; | |
265 | ||
266 | if (!obj || !obj->nr_tlb_entries || !e) | |
267 | return -EINVAL; | |
268 | ||
269 | clk_enable(obj->clk); | |
270 | ||
be6d8026 KH |
271 | iotlb_lock_get(obj, &l); |
272 | if (l.base == obj->nr_tlb_entries) { | |
273 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
274 | err = -EBUSY; |
275 | goto out; | |
276 | } | |
be6d8026 | 277 | if (!e->prsvd) { |
37c2836c HD |
278 | int i; |
279 | struct cr_regs tmp; | |
be6d8026 | 280 | |
37c2836c | 281 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
282 | if (!iotlb_cr_valid(&tmp)) |
283 | break; | |
37c2836c | 284 | |
be6d8026 KH |
285 | if (i == obj->nr_tlb_entries) { |
286 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
287 | err = -EBUSY; | |
288 | goto out; | |
289 | } | |
37c2836c HD |
290 | |
291 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
292 | } else { |
293 | l.vict = l.base; | |
294 | iotlb_lock_set(obj, &l); | |
295 | } | |
a9dcad5e HD |
296 | |
297 | cr = iotlb_alloc_cr(obj, e); | |
298 | if (IS_ERR(cr)) { | |
299 | clk_disable(obj->clk); | |
300 | return PTR_ERR(cr); | |
301 | } | |
302 | ||
303 | iotlb_load_cr(obj, cr); | |
304 | kfree(cr); | |
305 | ||
be6d8026 KH |
306 | if (e->prsvd) |
307 | l.base++; | |
a9dcad5e HD |
308 | /* increment victim for next tlb load */ |
309 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 310 | l.vict = l.base; |
a9dcad5e HD |
311 | iotlb_lock_set(obj, &l); |
312 | out: | |
313 | clk_disable(obj->clk); | |
314 | return err; | |
315 | } | |
a9dcad5e | 316 | |
5da14a47 OBC |
317 | #else /* !PREFETCH_IOTLB */ |
318 | ||
6c32df43 | 319 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
320 | { |
321 | return 0; | |
322 | } | |
323 | ||
324 | #endif /* !PREFETCH_IOTLB */ | |
325 | ||
6c32df43 | 326 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
327 | { |
328 | return load_iotlb_entry(obj, e); | |
329 | } | |
a9dcad5e HD |
330 | |
331 | /** | |
332 | * flush_iotlb_page - Clear an iommu tlb entry | |
333 | * @obj: target iommu | |
334 | * @da: iommu device virtual address | |
335 | * | |
336 | * Clear an iommu tlb entry which includes 'da' address. | |
337 | **/ | |
6c32df43 | 338 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 339 | { |
a9dcad5e | 340 | int i; |
37c2836c | 341 | struct cr_regs cr; |
a9dcad5e HD |
342 | |
343 | clk_enable(obj->clk); | |
344 | ||
37c2836c | 345 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
346 | u32 start; |
347 | size_t bytes; | |
348 | ||
a9dcad5e HD |
349 | if (!iotlb_cr_valid(&cr)) |
350 | continue; | |
351 | ||
352 | start = iotlb_cr_to_virt(&cr); | |
353 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
354 | ||
355 | if ((start <= da) && (da < start + bytes)) { | |
356 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
357 | __func__, start, da, bytes); | |
0fa035e5 | 358 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
359 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
360 | } | |
361 | } | |
362 | clk_disable(obj->clk); | |
363 | ||
364 | if (i == obj->nr_tlb_entries) | |
365 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
366 | } | |
a9dcad5e HD |
367 | |
368 | /** | |
369 | * flush_iotlb_all - Clear all iommu tlb entries | |
370 | * @obj: target iommu | |
371 | **/ | |
6c32df43 | 372 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
373 | { |
374 | struct iotlb_lock l; | |
375 | ||
376 | clk_enable(obj->clk); | |
377 | ||
378 | l.base = 0; | |
379 | l.vict = 0; | |
380 | iotlb_lock_set(obj, &l); | |
381 | ||
382 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
383 | ||
384 | clk_disable(obj->clk); | |
385 | } | |
ddfa975a | 386 | |
e4efd94b | 387 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 388 | |
6c32df43 | 389 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 390 | { |
a9dcad5e HD |
391 | if (!obj || !buf) |
392 | return -EINVAL; | |
393 | ||
394 | clk_enable(obj->clk); | |
395 | ||
14e0e679 | 396 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
397 | |
398 | clk_disable(obj->clk); | |
399 | ||
400 | return bytes; | |
401 | } | |
6c32df43 | 402 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 403 | |
6c32df43 OBC |
404 | static int |
405 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
406 | { |
407 | int i; | |
37c2836c HD |
408 | struct iotlb_lock saved; |
409 | struct cr_regs tmp; | |
a9dcad5e HD |
410 | struct cr_regs *p = crs; |
411 | ||
412 | clk_enable(obj->clk); | |
a9dcad5e | 413 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 414 | |
37c2836c | 415 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
416 | if (!iotlb_cr_valid(&tmp)) |
417 | continue; | |
a9dcad5e HD |
418 | *p++ = tmp; |
419 | } | |
37c2836c | 420 | |
a9dcad5e HD |
421 | iotlb_lock_set(obj, &saved); |
422 | clk_disable(obj->clk); | |
423 | ||
424 | return p - crs; | |
425 | } | |
426 | ||
427 | /** | |
6c32df43 | 428 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
429 | * @obj: target iommu |
430 | * @buf: output buffer | |
431 | **/ | |
6c32df43 | 432 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 433 | { |
14e0e679 | 434 | int i, num; |
a9dcad5e HD |
435 | struct cr_regs *cr; |
436 | char *p = buf; | |
437 | ||
14e0e679 HD |
438 | num = bytes / sizeof(*cr); |
439 | num = min(obj->nr_tlb_entries, num); | |
440 | ||
441 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
442 | if (!cr) |
443 | return 0; | |
444 | ||
14e0e679 HD |
445 | num = __dump_tlb_entries(obj, cr, num); |
446 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
447 | p += iotlb_dump_cr(obj, cr + i, p); |
448 | kfree(cr); | |
449 | ||
450 | return p - buf; | |
451 | } | |
6c32df43 | 452 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 453 | |
6c32df43 | 454 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
455 | { |
456 | return driver_for_each_device(&omap_iommu_driver.driver, | |
457 | NULL, data, fn); | |
458 | } | |
6c32df43 | 459 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
460 | |
461 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
462 | ||
463 | /* | |
464 | * H/W pagetable operations | |
465 | */ | |
466 | static void flush_iopgd_range(u32 *first, u32 *last) | |
467 | { | |
468 | /* FIXME: L2 cache should be taken care of if it exists */ | |
469 | do { | |
470 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
471 | : : "r" (first)); | |
472 | first += L1_CACHE_BYTES / sizeof(*first); | |
473 | } while (first <= last); | |
474 | } | |
475 | ||
476 | static void flush_iopte_range(u32 *first, u32 *last) | |
477 | { | |
478 | /* FIXME: L2 cache should be taken care of if it exists */ | |
479 | do { | |
480 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
481 | : : "r" (first)); | |
482 | first += L1_CACHE_BYTES / sizeof(*first); | |
483 | } while (first <= last); | |
484 | } | |
485 | ||
486 | static void iopte_free(u32 *iopte) | |
487 | { | |
488 | /* Note: freed iopte's must be clean ready for re-use */ | |
489 | kmem_cache_free(iopte_cachep, iopte); | |
490 | } | |
491 | ||
6c32df43 | 492 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
493 | { |
494 | u32 *iopte; | |
495 | ||
496 | /* a table has already existed */ | |
497 | if (*iopgd) | |
498 | goto pte_ready; | |
499 | ||
500 | /* | |
501 | * do the allocation outside the page table lock | |
502 | */ | |
503 | spin_unlock(&obj->page_table_lock); | |
504 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
505 | spin_lock(&obj->page_table_lock); | |
506 | ||
507 | if (!*iopgd) { | |
508 | if (!iopte) | |
509 | return ERR_PTR(-ENOMEM); | |
510 | ||
511 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
512 | flush_iopgd_range(iopgd, iopgd); | |
513 | ||
514 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
515 | } else { | |
516 | /* We raced, free the reduniovant table */ | |
517 | iopte_free(iopte); | |
518 | } | |
519 | ||
520 | pte_ready: | |
521 | iopte = iopte_offset(iopgd, da); | |
522 | ||
523 | dev_vdbg(obj->dev, | |
524 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
525 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
526 | ||
527 | return iopte; | |
528 | } | |
529 | ||
6c32df43 | 530 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
531 | { |
532 | u32 *iopgd = iopgd_offset(obj, da); | |
533 | ||
4abb7617 HD |
534 | if ((da | pa) & ~IOSECTION_MASK) { |
535 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
536 | __func__, da, pa, IOSECTION_SIZE); | |
537 | return -EINVAL; | |
538 | } | |
539 | ||
a9dcad5e HD |
540 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
541 | flush_iopgd_range(iopgd, iopgd); | |
542 | return 0; | |
543 | } | |
544 | ||
6c32df43 | 545 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
546 | { |
547 | u32 *iopgd = iopgd_offset(obj, da); | |
548 | int i; | |
549 | ||
4abb7617 HD |
550 | if ((da | pa) & ~IOSUPER_MASK) { |
551 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
552 | __func__, da, pa, IOSUPER_SIZE); | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
a9dcad5e HD |
556 | for (i = 0; i < 16; i++) |
557 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
558 | flush_iopgd_range(iopgd, iopgd + 15); | |
559 | return 0; | |
560 | } | |
561 | ||
6c32df43 | 562 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
563 | { |
564 | u32 *iopgd = iopgd_offset(obj, da); | |
565 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
566 | ||
567 | if (IS_ERR(iopte)) | |
568 | return PTR_ERR(iopte); | |
569 | ||
570 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
571 | flush_iopte_range(iopte, iopte); | |
572 | ||
573 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
574 | __func__, da, pa, iopte, *iopte); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
6c32df43 | 579 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
580 | { |
581 | u32 *iopgd = iopgd_offset(obj, da); | |
582 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
583 | int i; | |
584 | ||
4abb7617 HD |
585 | if ((da | pa) & ~IOLARGE_MASK) { |
586 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
587 | __func__, da, pa, IOLARGE_SIZE); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
a9dcad5e HD |
591 | if (IS_ERR(iopte)) |
592 | return PTR_ERR(iopte); | |
593 | ||
594 | for (i = 0; i < 16; i++) | |
595 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
596 | flush_iopte_range(iopte, iopte + 15); | |
597 | return 0; | |
598 | } | |
599 | ||
6c32df43 OBC |
600 | static int |
601 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 602 | { |
6c32df43 | 603 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
604 | u32 prot; |
605 | int err; | |
606 | ||
607 | if (!obj || !e) | |
608 | return -EINVAL; | |
609 | ||
610 | switch (e->pgsz) { | |
611 | case MMU_CAM_PGSZ_16M: | |
612 | fn = iopgd_alloc_super; | |
613 | break; | |
614 | case MMU_CAM_PGSZ_1M: | |
615 | fn = iopgd_alloc_section; | |
616 | break; | |
617 | case MMU_CAM_PGSZ_64K: | |
618 | fn = iopte_alloc_large; | |
619 | break; | |
620 | case MMU_CAM_PGSZ_4K: | |
621 | fn = iopte_alloc_page; | |
622 | break; | |
623 | default: | |
624 | fn = NULL; | |
625 | BUG(); | |
626 | break; | |
627 | } | |
628 | ||
629 | prot = get_iopte_attr(e); | |
630 | ||
631 | spin_lock(&obj->page_table_lock); | |
632 | err = fn(obj, e->da, e->pa, prot); | |
633 | spin_unlock(&obj->page_table_lock); | |
634 | ||
635 | return err; | |
636 | } | |
637 | ||
638 | /** | |
6c32df43 | 639 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
640 | * @obj: target iommu |
641 | * @e: an iommu tlb entry info | |
642 | **/ | |
6c32df43 | 643 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
644 | { |
645 | int err; | |
646 | ||
647 | flush_iotlb_page(obj, e->da); | |
648 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 649 | if (!err) |
5da14a47 | 650 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
651 | return err; |
652 | } | |
6c32df43 | 653 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
654 | |
655 | /** | |
656 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
657 | * @obj: target iommu | |
658 | * @da: iommu device virtual address | |
659 | * @ppgd: iommu pgd entry pointer to be returned | |
660 | * @ppte: iommu pte entry pointer to be returned | |
661 | **/ | |
e1f23813 OBC |
662 | static void |
663 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
664 | { |
665 | u32 *iopgd, *iopte = NULL; | |
666 | ||
667 | iopgd = iopgd_offset(obj, da); | |
668 | if (!*iopgd) | |
669 | goto out; | |
670 | ||
a1a54456 | 671 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
672 | iopte = iopte_offset(iopgd, da); |
673 | out: | |
674 | *ppgd = iopgd; | |
675 | *ppte = iopte; | |
676 | } | |
a9dcad5e | 677 | |
6c32df43 | 678 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
679 | { |
680 | size_t bytes; | |
681 | u32 *iopgd = iopgd_offset(obj, da); | |
682 | int nent = 1; | |
683 | ||
684 | if (!*iopgd) | |
685 | return 0; | |
686 | ||
a1a54456 | 687 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
688 | int i; |
689 | u32 *iopte = iopte_offset(iopgd, da); | |
690 | ||
691 | bytes = IOPTE_SIZE; | |
692 | if (*iopte & IOPTE_LARGE) { | |
693 | nent *= 16; | |
694 | /* rewind to the 1st entry */ | |
c127c7dc | 695 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
696 | } |
697 | bytes *= nent; | |
698 | memset(iopte, 0, nent * sizeof(*iopte)); | |
699 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
700 | ||
701 | /* | |
702 | * do table walk to check if this table is necessary or not | |
703 | */ | |
704 | iopte = iopte_offset(iopgd, 0); | |
705 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
706 | if (iopte[i]) | |
707 | goto out; | |
708 | ||
709 | iopte_free(iopte); | |
710 | nent = 1; /* for the next L1 entry */ | |
711 | } else { | |
712 | bytes = IOPGD_SIZE; | |
dcc730dc | 713 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
714 | nent *= 16; |
715 | /* rewind to the 1st entry */ | |
8d33ea58 | 716 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
717 | } |
718 | bytes *= nent; | |
719 | } | |
720 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
721 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
722 | out: | |
723 | return bytes; | |
724 | } | |
725 | ||
726 | /** | |
727 | * iopgtable_clear_entry - Remove an iommu pte entry | |
728 | * @obj: target iommu | |
729 | * @da: iommu device virtual address | |
730 | **/ | |
6c32df43 | 731 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
732 | { |
733 | size_t bytes; | |
734 | ||
735 | spin_lock(&obj->page_table_lock); | |
736 | ||
737 | bytes = iopgtable_clear_entry_core(obj, da); | |
738 | flush_iotlb_page(obj, da); | |
739 | ||
740 | spin_unlock(&obj->page_table_lock); | |
741 | ||
742 | return bytes; | |
743 | } | |
a9dcad5e | 744 | |
6c32df43 | 745 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
746 | { |
747 | int i; | |
748 | ||
749 | spin_lock(&obj->page_table_lock); | |
750 | ||
751 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
752 | u32 da; | |
753 | u32 *iopgd; | |
754 | ||
755 | da = i << IOPGD_SHIFT; | |
756 | iopgd = iopgd_offset(obj, da); | |
757 | ||
758 | if (!*iopgd) | |
759 | continue; | |
760 | ||
a1a54456 | 761 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
762 | iopte_free(iopte_offset(iopgd, 0)); |
763 | ||
764 | *iopgd = 0; | |
765 | flush_iopgd_range(iopgd, iopgd); | |
766 | } | |
767 | ||
768 | flush_iotlb_all(obj); | |
769 | ||
770 | spin_unlock(&obj->page_table_lock); | |
771 | } | |
772 | ||
773 | /* | |
774 | * Device IOMMU generic operations | |
775 | */ | |
776 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
777 | { | |
d594f1f3 | 778 | u32 da, errs; |
a9dcad5e | 779 | u32 *iopgd, *iopte; |
6c32df43 | 780 | struct omap_iommu *obj = data; |
e7f10f02 | 781 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
782 | |
783 | if (!obj->refcount) | |
784 | return IRQ_NONE; | |
785 | ||
a9dcad5e | 786 | clk_enable(obj->clk); |
d594f1f3 | 787 | errs = iommu_report_fault(obj, &da); |
a9dcad5e | 788 | clk_disable(obj->clk); |
c56b2ddd LP |
789 | if (errs == 0) |
790 | return IRQ_HANDLED; | |
d594f1f3 DC |
791 | |
792 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 793 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
794 | return IRQ_HANDLED; |
795 | ||
37b29810 HD |
796 | iommu_disable(obj); |
797 | ||
a9dcad5e HD |
798 | iopgd = iopgd_offset(obj, da); |
799 | ||
a1a54456 | 800 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
801 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
802 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
803 | return IRQ_NONE; |
804 | } | |
805 | ||
806 | iopte = iopte_offset(iopgd, da); | |
807 | ||
d594f1f3 DC |
808 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
809 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
810 | iopte, *iopte); | |
a9dcad5e HD |
811 | |
812 | return IRQ_NONE; | |
813 | } | |
814 | ||
815 | static int device_match_by_alias(struct device *dev, void *data) | |
816 | { | |
6c32df43 | 817 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
818 | const char *name = data; |
819 | ||
820 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
821 | ||
822 | return strcmp(obj->name, name) == 0; | |
823 | } | |
824 | ||
c7f4ab26 | 825 | /** |
f626b52d OBC |
826 | * omap_find_iommu_device() - find an omap iommu device by name |
827 | * @name: name of the iommu device | |
828 | * | |
829 | * The generic iommu API requires the caller to provide the device | |
830 | * he wishes to attach to a certain iommu domain. | |
831 | * | |
832 | * Drivers generally should not bother with this as it should just | |
833 | * be taken care of by the DMA-API using dev_archdata. | |
834 | * | |
835 | * This function is provided as an interim solution until the latter | |
836 | * materializes, and omap3isp is fully migrated to the DMA-API. | |
837 | */ | |
838 | struct device *omap_find_iommu_device(const char *name) | |
c7f4ab26 | 839 | { |
f626b52d OBC |
840 | return driver_find_device(&omap_iommu_driver.driver, NULL, |
841 | (void *)name, | |
842 | device_match_by_alias); | |
c7f4ab26 | 843 | } |
f626b52d | 844 | EXPORT_SYMBOL_GPL(omap_find_iommu_device); |
c7f4ab26 | 845 | |
a9dcad5e | 846 | /** |
f626b52d OBC |
847 | * omap_iommu_attach() - attach iommu device to an iommu domain |
848 | * @dev: target omap iommu device | |
849 | * @iopgd: page table | |
a9dcad5e | 850 | **/ |
6c32df43 | 851 | static struct omap_iommu *omap_iommu_attach(struct device *dev, u32 *iopgd) |
a9dcad5e HD |
852 | { |
853 | int err = -ENOMEM; | |
6c32df43 | 854 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e | 855 | |
f626b52d | 856 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 857 | |
f626b52d OBC |
858 | /* an iommu device can only be attached once */ |
859 | if (++obj->refcount > 1) { | |
860 | dev_err(dev, "%s: already attached!\n", obj->name); | |
861 | err = -EBUSY; | |
862 | goto err_enable; | |
a9dcad5e HD |
863 | } |
864 | ||
f626b52d OBC |
865 | obj->iopgd = iopgd; |
866 | err = iommu_enable(obj); | |
867 | if (err) | |
868 | goto err_enable; | |
869 | flush_iotlb_all(obj); | |
870 | ||
a9dcad5e HD |
871 | if (!try_module_get(obj->owner)) |
872 | goto err_module; | |
873 | ||
f626b52d | 874 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
875 | |
876 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
877 | return obj; | |
878 | ||
879 | err_module: | |
880 | if (obj->refcount == 1) | |
881 | iommu_disable(obj); | |
882 | err_enable: | |
883 | obj->refcount--; | |
f626b52d | 884 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
885 | return ERR_PTR(err); |
886 | } | |
a9dcad5e HD |
887 | |
888 | /** | |
f626b52d | 889 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
890 | * @obj: target iommu |
891 | **/ | |
6c32df43 | 892 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 893 | { |
acf9d467 | 894 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
895 | return; |
896 | ||
f626b52d | 897 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
898 | |
899 | if (--obj->refcount == 0) | |
900 | iommu_disable(obj); | |
901 | ||
902 | module_put(obj->owner); | |
903 | ||
f626b52d | 904 | obj->iopgd = NULL; |
d594f1f3 | 905 | |
f626b52d | 906 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 907 | |
a9dcad5e | 908 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 909 | } |
d594f1f3 | 910 | |
a9dcad5e HD |
911 | /* |
912 | * OMAP Device MMU(IOMMU) detection | |
913 | */ | |
914 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
915 | { | |
916 | int err = -ENODEV; | |
a9dcad5e | 917 | int irq; |
6c32df43 | 918 | struct omap_iommu *obj; |
a9dcad5e HD |
919 | struct resource *res; |
920 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
921 | ||
922 | if (pdev->num_resources != 2) | |
923 | return -EINVAL; | |
924 | ||
925 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
926 | if (!obj) | |
927 | return -ENOMEM; | |
928 | ||
929 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
930 | if (IS_ERR(obj->clk)) | |
931 | goto err_clk; | |
932 | ||
933 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
934 | obj->name = pdata->name; | |
935 | obj->dev = &pdev->dev; | |
936 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
937 | obj->da_start = pdata->da_start; |
938 | obj->da_end = pdata->da_end; | |
a9dcad5e | 939 | |
f626b52d | 940 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
941 | mutex_init(&obj->mmap_lock); |
942 | spin_lock_init(&obj->page_table_lock); | |
943 | INIT_LIST_HEAD(&obj->mmap); | |
944 | ||
945 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
946 | if (!res) { | |
947 | err = -ENODEV; | |
948 | goto err_mem; | |
949 | } | |
a9dcad5e HD |
950 | |
951 | res = request_mem_region(res->start, resource_size(res), | |
952 | dev_name(&pdev->dev)); | |
953 | if (!res) { | |
954 | err = -EIO; | |
955 | goto err_mem; | |
956 | } | |
957 | ||
da4a0f76 AK |
958 | obj->regbase = ioremap(res->start, resource_size(res)); |
959 | if (!obj->regbase) { | |
960 | err = -ENOMEM; | |
961 | goto err_ioremap; | |
962 | } | |
963 | ||
a9dcad5e HD |
964 | irq = platform_get_irq(pdev, 0); |
965 | if (irq < 0) { | |
966 | err = -ENODEV; | |
967 | goto err_irq; | |
968 | } | |
969 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
970 | dev_name(&pdev->dev), obj); | |
971 | if (err < 0) | |
972 | goto err_irq; | |
973 | platform_set_drvdata(pdev, obj); | |
974 | ||
a9dcad5e HD |
975 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
976 | return 0; | |
977 | ||
a9dcad5e | 978 | err_irq: |
a9dcad5e | 979 | iounmap(obj->regbase); |
da4a0f76 AK |
980 | err_ioremap: |
981 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e HD |
982 | err_mem: |
983 | clk_put(obj->clk); | |
984 | err_clk: | |
985 | kfree(obj); | |
986 | return err; | |
987 | } | |
988 | ||
989 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
990 | { | |
991 | int irq; | |
992 | struct resource *res; | |
6c32df43 | 993 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
994 | |
995 | platform_set_drvdata(pdev, NULL); | |
996 | ||
997 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
998 | |
999 | irq = platform_get_irq(pdev, 0); | |
1000 | free_irq(irq, obj); | |
1001 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1002 | release_mem_region(res->start, resource_size(res)); | |
1003 | iounmap(obj->regbase); | |
1004 | ||
1005 | clk_put(obj->clk); | |
1006 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1007 | kfree(obj); | |
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | static struct platform_driver omap_iommu_driver = { | |
1012 | .probe = omap_iommu_probe, | |
1013 | .remove = __devexit_p(omap_iommu_remove), | |
1014 | .driver = { | |
1015 | .name = "omap-iommu", | |
1016 | }, | |
1017 | }; | |
1018 | ||
1019 | static void iopte_cachep_ctor(void *iopte) | |
1020 | { | |
1021 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1022 | } | |
1023 | ||
f626b52d | 1024 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1025 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1026 | { |
1027 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1028 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1029 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1030 | struct iotlb_entry e; |
1031 | int omap_pgsz; | |
1032 | u32 ret, flags; | |
1033 | ||
1034 | /* we only support mapping a single iommu page for now */ | |
1035 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1036 | if (omap_pgsz < 0) { | |
1037 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
1041 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1042 | ||
1043 | flags = omap_pgsz | prot; | |
1044 | ||
1045 | iotlb_init_entry(&e, da, pa, flags); | |
1046 | ||
6c32df43 | 1047 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1048 | if (ret) |
6c32df43 | 1049 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1050 | |
b4550d41 | 1051 | return ret; |
f626b52d OBC |
1052 | } |
1053 | ||
5009065d OBC |
1054 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1055 | size_t size) | |
f626b52d OBC |
1056 | { |
1057 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1058 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1059 | struct device *dev = oiommu->dev; |
f626b52d | 1060 | |
5009065d | 1061 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1062 | |
5009065d | 1063 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1064 | } |
1065 | ||
1066 | static int | |
1067 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1068 | { | |
1069 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1070 | struct omap_iommu *oiommu; |
f626b52d OBC |
1071 | int ret = 0; |
1072 | ||
1073 | spin_lock(&omap_domain->lock); | |
1074 | ||
1075 | /* only a single device is supported per domain for now */ | |
1076 | if (omap_domain->iommu_dev) { | |
1077 | dev_err(dev, "iommu domain is already attached\n"); | |
1078 | ret = -EBUSY; | |
1079 | goto out; | |
1080 | } | |
1081 | ||
1082 | /* get a handle to and enable the omap iommu */ | |
1083 | oiommu = omap_iommu_attach(dev, omap_domain->pgtable); | |
1084 | if (IS_ERR(oiommu)) { | |
1085 | ret = PTR_ERR(oiommu); | |
1086 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1087 | goto out; | |
1088 | } | |
1089 | ||
1090 | omap_domain->iommu_dev = oiommu; | |
e7f10f02 | 1091 | oiommu->domain = domain; |
f626b52d OBC |
1092 | |
1093 | out: | |
1094 | spin_unlock(&omap_domain->lock); | |
1095 | return ret; | |
1096 | } | |
1097 | ||
1098 | static void omap_iommu_detach_dev(struct iommu_domain *domain, | |
1099 | struct device *dev) | |
1100 | { | |
1101 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1102 | struct omap_iommu *oiommu = to_iommu(dev); |
f626b52d OBC |
1103 | |
1104 | spin_lock(&omap_domain->lock); | |
1105 | ||
1106 | /* only a single device is supported per domain for now */ | |
1107 | if (omap_domain->iommu_dev != oiommu) { | |
1108 | dev_err(dev, "invalid iommu device\n"); | |
1109 | goto out; | |
1110 | } | |
1111 | ||
1112 | iopgtable_clear_entry_all(oiommu); | |
1113 | ||
1114 | omap_iommu_detach(oiommu); | |
1115 | ||
1116 | omap_domain->iommu_dev = NULL; | |
1117 | ||
1118 | out: | |
1119 | spin_unlock(&omap_domain->lock); | |
1120 | } | |
1121 | ||
1122 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1123 | { | |
1124 | struct omap_iommu_domain *omap_domain; | |
1125 | ||
1126 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1127 | if (!omap_domain) { | |
1128 | pr_err("kzalloc failed\n"); | |
1129 | goto out; | |
1130 | } | |
1131 | ||
1132 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1133 | if (!omap_domain->pgtable) { | |
1134 | pr_err("kzalloc failed\n"); | |
1135 | goto fail_nomem; | |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * should never fail, but please keep this around to ensure | |
1140 | * we keep the hardware happy | |
1141 | */ | |
1142 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1143 | ||
1144 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1145 | spin_lock_init(&omap_domain->lock); | |
1146 | ||
1147 | domain->priv = omap_domain; | |
1148 | ||
1149 | return 0; | |
1150 | ||
1151 | fail_nomem: | |
1152 | kfree(omap_domain); | |
1153 | out: | |
1154 | return -ENOMEM; | |
1155 | } | |
1156 | ||
1157 | /* assume device was already detached */ | |
1158 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) | |
1159 | { | |
1160 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1161 | ||
1162 | domain->priv = NULL; | |
1163 | ||
1164 | kfree(omap_domain->pgtable); | |
1165 | kfree(omap_domain); | |
1166 | } | |
1167 | ||
1168 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
1169 | unsigned long da) | |
1170 | { | |
1171 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1172 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1173 | struct device *dev = oiommu->dev; |
1174 | u32 *pgd, *pte; | |
1175 | phys_addr_t ret = 0; | |
1176 | ||
1177 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1178 | ||
1179 | if (pte) { | |
1180 | if (iopte_is_small(*pte)) | |
1181 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1182 | else if (iopte_is_large(*pte)) | |
1183 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1184 | else | |
1185 | dev_err(dev, "bogus pte 0x%x", *pte); | |
1186 | } else { | |
1187 | if (iopgd_is_section(*pgd)) | |
1188 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1189 | else if (iopgd_is_super(*pgd)) | |
1190 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1191 | else | |
1192 | dev_err(dev, "bogus pgd 0x%x", *pgd); | |
1193 | } | |
1194 | ||
1195 | return ret; | |
1196 | } | |
1197 | ||
1198 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1199 | unsigned long cap) | |
1200 | { | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static struct iommu_ops omap_iommu_ops = { | |
1205 | .domain_init = omap_iommu_domain_init, | |
1206 | .domain_destroy = omap_iommu_domain_destroy, | |
1207 | .attach_dev = omap_iommu_attach_dev, | |
1208 | .detach_dev = omap_iommu_detach_dev, | |
1209 | .map = omap_iommu_map, | |
1210 | .unmap = omap_iommu_unmap, | |
1211 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1212 | .domain_has_cap = omap_iommu_domain_has_cap, | |
66bc8cf3 | 1213 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1214 | }; |
1215 | ||
a9dcad5e HD |
1216 | static int __init omap_iommu_init(void) |
1217 | { | |
1218 | struct kmem_cache *p; | |
1219 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1220 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1221 | ||
1222 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1223 | iopte_cachep_ctor); | |
1224 | if (!p) | |
1225 | return -ENOMEM; | |
1226 | iopte_cachep = p; | |
1227 | ||
a65bc64f | 1228 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1229 | |
a9dcad5e HD |
1230 | return platform_driver_register(&omap_iommu_driver); |
1231 | } | |
1232 | module_init(omap_iommu_init); | |
1233 | ||
1234 | static void __exit omap_iommu_exit(void) | |
1235 | { | |
1236 | kmem_cache_destroy(iopte_cachep); | |
1237 | ||
1238 | platform_driver_unregister(&omap_iommu_driver); | |
1239 | } | |
1240 | module_exit(omap_iommu_exit); | |
1241 | ||
1242 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1243 | MODULE_ALIAS("platform:omap-iommu"); | |
1244 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1245 | MODULE_LICENSE("GPL v2"); |