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ed1c7de2 TL |
1 | /* |
2 | * omap iommu: main structures | |
3 | * | |
4 | * Copyright (C) 2008-2009 Nokia Corporation | |
5 | * | |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
533b40cc SA |
13 | #ifndef _OMAP_IOMMU_H |
14 | #define _OMAP_IOMMU_H | |
15 | ||
eb642a3f SA |
16 | #include <linux/bitops.h> |
17 | ||
69c2c196 SA |
18 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
19 | for (__i = 0; \ | |
20 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
21 | __i++) | |
22 | ||
ed1c7de2 TL |
23 | struct iotlb_entry { |
24 | u32 da; | |
25 | u32 pa; | |
26 | u32 pgsz, prsvd, valid; | |
dc308f9f | 27 | u32 endian, elsz, mixed; |
ed1c7de2 TL |
28 | }; |
29 | ||
30 | struct omap_iommu { | |
31 | const char *name; | |
ed1c7de2 | 32 | void __iomem *regbase; |
3ca9299e | 33 | struct regmap *syscfg; |
ed1c7de2 | 34 | struct device *dev; |
ed1c7de2 | 35 | struct iommu_domain *domain; |
61c75352 | 36 | struct dentry *debug_dir; |
ed1c7de2 | 37 | |
ed1c7de2 TL |
38 | spinlock_t iommu_lock; /* global for this whole object */ |
39 | ||
40 | /* | |
41 | * We don't change iopgd for a situation like pgd for a task, | |
42 | * but share it globally for each iommu. | |
43 | */ | |
44 | u32 *iopgd; | |
45 | spinlock_t page_table_lock; /* protect iopgd */ | |
46 | ||
47 | int nr_tlb_entries; | |
48 | ||
ed1c7de2 | 49 | void *ctx; /* iommu context: registres saved area */ |
b148d5fb SA |
50 | |
51 | int has_bus_err_back; | |
3ca9299e | 52 | u32 id; |
ed1c7de2 TL |
53 | }; |
54 | ||
55 | struct cr_regs { | |
dc308f9f SA |
56 | u32 cam; |
57 | u32 ram; | |
ed1c7de2 TL |
58 | }; |
59 | ||
69c2c196 SA |
60 | struct iotlb_lock { |
61 | short base; | |
62 | short vict; | |
63 | }; | |
64 | ||
ed1c7de2 TL |
65 | /** |
66 | * dev_to_omap_iommu() - retrieves an omap iommu object from a user device | |
67 | * @dev: iommu client device | |
68 | */ | |
69 | static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) | |
70 | { | |
71 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; | |
72 | ||
73 | return arch_data->iommu_dev; | |
74 | } | |
ed1c7de2 | 75 | |
ed1c7de2 TL |
76 | /* |
77 | * MMU Register offsets | |
78 | */ | |
79 | #define MMU_REVISION 0x00 | |
ed1c7de2 TL |
80 | #define MMU_IRQSTATUS 0x18 |
81 | #define MMU_IRQENABLE 0x1c | |
82 | #define MMU_WALKING_ST 0x40 | |
83 | #define MMU_CNTL 0x44 | |
84 | #define MMU_FAULT_AD 0x48 | |
85 | #define MMU_TTB 0x4c | |
86 | #define MMU_LOCK 0x50 | |
87 | #define MMU_LD_TLB 0x54 | |
88 | #define MMU_CAM 0x58 | |
89 | #define MMU_RAM 0x5c | |
90 | #define MMU_GFLUSH 0x60 | |
91 | #define MMU_FLUSH_ENTRY 0x64 | |
92 | #define MMU_READ_CAM 0x68 | |
93 | #define MMU_READ_RAM 0x6c | |
94 | #define MMU_EMU_FAULT_AD 0x70 | |
b148d5fb | 95 | #define MMU_GP_REG 0x88 |
ed1c7de2 TL |
96 | |
97 | #define MMU_REG_SIZE 256 | |
98 | ||
99 | /* | |
100 | * MMU Register bit definitions | |
101 | */ | |
bd4396f0 | 102 | /* IRQSTATUS & IRQENABLE */ |
eb642a3f SA |
103 | #define MMU_IRQ_MULTIHITFAULT BIT(4) |
104 | #define MMU_IRQ_TABLEWALKFAULT BIT(3) | |
105 | #define MMU_IRQ_EMUMISS BIT(2) | |
106 | #define MMU_IRQ_TRANSLATIONFAULT BIT(1) | |
107 | #define MMU_IRQ_TLBMISS BIT(0) | |
bd4396f0 SA |
108 | |
109 | #define __MMU_IRQ_FAULT \ | |
110 | (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) | |
111 | #define MMU_IRQ_MASK \ | |
112 | (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) | |
113 | #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) | |
114 | #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) | |
115 | ||
116 | /* MMU_CNTL */ | |
117 | #define MMU_CNTL_SHIFT 1 | |
118 | #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) | |
eb642a3f SA |
119 | #define MMU_CNTL_EML_TLB BIT(3) |
120 | #define MMU_CNTL_TWL_EN BIT(2) | |
121 | #define MMU_CNTL_MMU_EN BIT(1) | |
bd4396f0 SA |
122 | |
123 | /* CAM */ | |
ed1c7de2 TL |
124 | #define MMU_CAM_VATAG_SHIFT 12 |
125 | #define MMU_CAM_VATAG_MASK \ | |
126 | ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) | |
eb642a3f SA |
127 | #define MMU_CAM_P BIT(3) |
128 | #define MMU_CAM_V BIT(2) | |
ed1c7de2 TL |
129 | #define MMU_CAM_PGSZ_MASK 3 |
130 | #define MMU_CAM_PGSZ_1M (0 << 0) | |
131 | #define MMU_CAM_PGSZ_64K (1 << 0) | |
132 | #define MMU_CAM_PGSZ_4K (2 << 0) | |
133 | #define MMU_CAM_PGSZ_16M (3 << 0) | |
134 | ||
bd4396f0 | 135 | /* RAM */ |
ed1c7de2 TL |
136 | #define MMU_RAM_PADDR_SHIFT 12 |
137 | #define MMU_RAM_PADDR_MASK \ | |
138 | ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) | |
139 | ||
baaa7b5d | 140 | #define MMU_RAM_ENDIAN_SHIFT 9 |
eb642a3f | 141 | #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT) |
baaa7b5d | 142 | #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) |
eb642a3f | 143 | #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT) |
ed1c7de2 | 144 | |
baaa7b5d | 145 | #define MMU_RAM_ELSZ_SHIFT 7 |
ed1c7de2 TL |
146 | #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) |
147 | #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) | |
148 | #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) | |
149 | #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) | |
150 | #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) | |
151 | #define MMU_RAM_MIXED_SHIFT 6 | |
eb642a3f | 152 | #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT) |
ed1c7de2 TL |
153 | #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK |
154 | ||
b148d5fb SA |
155 | #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 |
156 | ||
bd4396f0 SA |
157 | #define get_cam_va_mask(pgsz) \ |
158 | (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ | |
159 | ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ | |
160 | ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ | |
161 | ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) | |
162 | ||
3ca9299e SA |
163 | /* |
164 | * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP) | |
165 | */ | |
166 | #define DSP_SYS_REVISION 0x00 | |
167 | #define DSP_SYS_MMU_CONFIG 0x18 | |
168 | #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4 | |
169 | ||
ed1c7de2 TL |
170 | /* |
171 | * utilities for super page(16MB, 1MB, 64KB and 4KB) | |
172 | */ | |
173 | ||
174 | #define iopgsz_max(bytes) \ | |
175 | (((bytes) >= SZ_16M) ? SZ_16M : \ | |
176 | ((bytes) >= SZ_1M) ? SZ_1M : \ | |
177 | ((bytes) >= SZ_64K) ? SZ_64K : \ | |
178 | ((bytes) >= SZ_4K) ? SZ_4K : 0) | |
179 | ||
180 | #define bytes_to_iopgsz(bytes) \ | |
181 | (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ | |
182 | ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ | |
183 | ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ | |
184 | ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) | |
185 | ||
186 | #define iopgsz_to_bytes(iopgsz) \ | |
187 | (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ | |
188 | ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ | |
189 | ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ | |
190 | ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) | |
191 | ||
192 | #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) | |
193 | ||
194 | /* | |
195 | * global functions | |
196 | */ | |
ed1c7de2 | 197 | |
69c2c196 SA |
198 | struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n); |
199 | void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l); | |
200 | void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l); | |
201 | ||
202 | #ifdef CONFIG_OMAP_IOMMU_DEBUG | |
61c75352 SA |
203 | void omap_iommu_debugfs_init(void); |
204 | void omap_iommu_debugfs_exit(void); | |
205 | ||
206 | void omap_iommu_debugfs_add(struct omap_iommu *obj); | |
207 | void omap_iommu_debugfs_remove(struct omap_iommu *obj); | |
208 | #else | |
209 | static inline void omap_iommu_debugfs_init(void) { } | |
210 | static inline void omap_iommu_debugfs_exit(void) { } | |
211 | ||
212 | static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { } | |
213 | static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { } | |
214 | #endif | |
215 | ||
ed1c7de2 TL |
216 | /* |
217 | * register accessors | |
218 | */ | |
219 | static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) | |
220 | { | |
221 | return __raw_readl(obj->regbase + offs); | |
222 | } | |
223 | ||
224 | static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) | |
225 | { | |
226 | __raw_writel(val, obj->regbase + offs); | |
227 | } | |
533b40cc | 228 | |
69c2c196 SA |
229 | static inline int iotlb_cr_valid(struct cr_regs *cr) |
230 | { | |
231 | if (!cr) | |
232 | return -EINVAL; | |
233 | ||
234 | return cr->cam & MMU_CAM_V; | |
235 | } | |
236 | ||
533b40cc | 237 | #endif /* _OMAP_IOMMU_H */ |