[deliverable/linux.git] / drivers / iommu / omap-iommu2.c

/*
 * omap iommu: omap2/3 architecture specific functions
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
 *		Paul Mundt and Toshihiro Kobayashi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/omap-iommu.h>
#include <linux/slab.h>
#include <linux/stringify.h>
#include <linux/platform_data/iommu-omap.h>

#include "omap-iommu.h"

/*
 * omap2 architecture specific register bit definitions
 */
/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
#define MMU_IRQ_EMUMISS		(1 << 2)
#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
#define MMU_IRQ_TLBMISS		(1 << 0)

#define __MMU_IRQ_FAULT		\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
#define MMU_IRQ_MASK		\
	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	(1 << 3)
#define MMU_CNTL_TWL_EN		(1 << 2)
#define MMU_CNTL_MMU_EN		(1 << 1)

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)

static void __iommu_set_twl(struct omap_iommu *obj, bool on)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	if (on)
		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	else
		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);

	l &= ~MMU_CNTL_MASK;
	if (on)
		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
	else
		l |= (MMU_CNTL_MMU_EN);

	iommu_write_reg(obj, l, MMU_CNTL);
}


static int omap2_iommu_enable(struct omap_iommu *obj)
{
	u32 l, pa;

	if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
		return -EINVAL;

	pa = virt_to_phys(obj->iopgd);
	if (!IS_ALIGNED(pa, SZ_16K))
		return -EINVAL;

	l = iommu_read_reg(obj, MMU_REVISION);
	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
		 (l >> 4) & 0xf, l & 0xf);

	iommu_write_reg(obj, pa, MMU_TTB);

	if (obj->has_bus_err_back)
		iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);

	__iommu_set_twl(obj, true);

	return 0;
}

static void omap2_iommu_disable(struct omap_iommu *obj)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	l &= ~MMU_CNTL_MASK;
	iommu_write_reg(obj, l, MMU_CNTL);

	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
}

static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
{
	__iommu_set_twl(obj, false);
}

static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
{
	u32 stat, da;

	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	stat &= MMU_IRQ_MASK;
	if (!stat) {
		*ra = 0;
		return 0;
	}

	da = iommu_read_reg(obj, MMU_FAULT_AD);
	*ra = da;

	iommu_write_reg(obj, stat, MMU_IRQSTATUS);

	return stat;
}

static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
{
	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
}

static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
{
	iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
	iommu_write_reg(obj, cr->ram, MMU_RAM);
}

static u32 omap2_cr_to_virt(struct cr_regs *cr)
{
	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	u32 mask = get_cam_va_mask(cr->cam & page_size);

	return cr->cam & mask;
}

static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
						struct iotlb_entry *e)
{
	struct cr_regs *cr;

	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
		dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
			e->da);
		return ERR_PTR(-EINVAL);
	}

	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	if (!cr)
		return ERR_PTR(-ENOMEM);

	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
	cr->ram = e->pa | e->endian | e->elsz | e->mixed;

	return cr;
}

static inline int omap2_cr_valid(struct cr_regs *cr)
{
	return cr->cam & MMU_CAM_V;
}

static u32 omap2_get_pte_attr(struct iotlb_entry *e)
{
	u32 attr;

	attr = e->mixed << 5;
	attr |= e->endian;
	attr |= e->elsz >> 3;
	attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
			(e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
	return attr;
}

static ssize_t
omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
{
	char *p = buf;

	/* FIXME: Need more detail analysis of cam/ram */
	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
					(cr->cam & MMU_CAM_P) ? 1 : 0);

	return p - buf;
}

#define pr_reg(name)							\
	do {								\
		ssize_t bytes;						\
		const char *str = "%20s: %08x\n";			\
		const int maxcol = 32;					\
		bytes = snprintf(p, maxcol, str, __stringify(name),	\
				 iommu_read_reg(obj, MMU_##name));	\
		p += bytes;						\
		len -= bytes;						\
		if (len < maxcol)					\
			goto out;					\
	} while (0)

static ssize_t
omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
{
	char *p = buf;

	pr_reg(REVISION);
	pr_reg(IRQSTATUS);
	pr_reg(IRQENABLE);
	pr_reg(WALKING_ST);
	pr_reg(CNTL);
	pr_reg(FAULT_AD);
	pr_reg(TTB);
	pr_reg(LOCK);
	pr_reg(LD_TLB);
	pr_reg(CAM);
	pr_reg(RAM);
	pr_reg(GFLUSH);
	pr_reg(FLUSH_ENTRY);
	pr_reg(READ_CAM);
	pr_reg(READ_RAM);
	pr_reg(EMU_FAULT_AD);
out:
	return p - buf;
}

static void omap2_iommu_save_ctx(struct omap_iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		p[i] = iommu_read_reg(obj, i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}
}

static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		iommu_write_reg(obj, p[i], i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}
}

static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
{
	e->da		= cr->cam & MMU_CAM_VATAG_MASK;
	e->pa		= cr->ram & MMU_RAM_PADDR_MASK;
	e->valid	= cr->cam & MMU_CAM_V;
	e->pgsz		= cr->cam & MMU_CAM_PGSZ_MASK;
	e->endian	= cr->ram & MMU_RAM_ENDIAN_MASK;
	e->elsz		= cr->ram & MMU_RAM_ELSZ_MASK;
	e->mixed	= cr->ram & MMU_RAM_MIXED;
}

static const struct iommu_functions omap2_iommu_ops = {
	.enable		= omap2_iommu_enable,
	.disable	= omap2_iommu_disable,
	.set_twl	= omap2_iommu_set_twl,
	.fault_isr	= omap2_iommu_fault_isr,

	.tlb_read_cr	= omap2_tlb_read_cr,
	.tlb_load_cr	= omap2_tlb_load_cr,

	.cr_to_e	= omap2_cr_to_e,
	.cr_to_virt	= omap2_cr_to_virt,
	.alloc_cr	= omap2_alloc_cr,
	.cr_valid	= omap2_cr_valid,
	.dump_cr	= omap2_dump_cr,

	.get_pte_attr	= omap2_get_pte_attr,

	.save_ctx	= omap2_iommu_save_ctx,
	.restore_ctx	= omap2_iommu_restore_ctx,
	.dump_ctx	= omap2_iommu_dump_ctx,
};

static int __init omap2_iommu_init(void)
{
	return omap_install_iommu_arch(&omap2_iommu_ops);
}
module_init(omap2_iommu_init);

static void __exit omap2_iommu_exit(void)
{
	omap_uninstall_iommu_arch(&omap2_iommu_ops);
}
module_exit(omap2_iommu_exit);

MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bcb5733 HD	1	/*
	2	* omap iommu: omap2/3 architecture specific functions
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
	7	* Paul Mundt and Toshihiro Kobayashi
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/err.h>
	15	#include <linux/device.h>
ed1c7de2	16	#include <linux/io.h>
2bcb5733 HD	17	#include <linux/jiffies.h>
2bcb5733 HD	18	#include <linux/module.h>
c8d35c84	19	#include <linux/omap-iommu.h>
5a0e3ad6	20	#include <linux/slab.h>
2bcb5733	21	#include <linux/stringify.h>
2ab7c848	22	#include <linux/platform_data/iommu-omap.h>
2bcb5733	23
ed1c7de2	24	#include "omap-iommu.h"
2bcb5733 HD	25
	26	/*
	27	* omap2 architecture specific register bit definitions
	28	*/
2bcb5733 HD	29	/* IRQSTATUS & IRQENABLE */
	30	#define MMU_IRQ_MULTIHITFAULT (1 << 4)
	31	#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
	32	#define MMU_IRQ_EMUMISS (1 << 2)
	33	#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
	34	#define MMU_IRQ_TLBMISS (1 << 0)
993dd17e KH	35
	36	#define __MMU_IRQ_FAULT \
	37	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_EMUMISS \| MMU_IRQ_TRANSLATIONFAULT)
	38	#define MMU_IRQ_MASK \
	39	(__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_TLBMISS)
	40	#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT)
	41	#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TLBMISS)
2bcb5733 HD	42
	43	/* MMU_CNTL */
	44	#define MMU_CNTL_SHIFT 1
	45	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
	46	#define MMU_CNTL_EML_TLB (1 << 3)
	47	#define MMU_CNTL_TWL_EN (1 << 2)
	48	#define MMU_CNTL_MMU_EN (1 << 1)
	49
	50	#define get_cam_va_mask(pgsz) \
	51	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	52	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	53	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	54	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	55
6c32df43	56	static void __iommu_set_twl(struct omap_iommu *obj, bool on)
ddfa975a KH	57	{
	58	u32 l = iommu_read_reg(obj, MMU_CNTL);
	59
	60	if (on)
	61	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	62	else
	63	iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
	64
	65	l &= ~MMU_CNTL_MASK;
	66	if (on)
	67	l \|= (MMU_CNTL_MMU_EN \| MMU_CNTL_TWL_EN);
	68	else
	69	l \|= (MMU_CNTL_MMU_EN);
	70
	71	iommu_write_reg(obj, l, MMU_CNTL);
	72	}
	73
	74
6c32df43	75	static int omap2_iommu_enable(struct omap_iommu *obj)
2bcb5733 HD	76	{
2bcb5733 HD	77	u32 l, pa;
2bcb5733 HD	78
	79	if (!obj->iopgd \|\| !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
	80	return -EINVAL;
	81
	82	pa = virt_to_phys(obj->iopgd);
	83	if (!IS_ALIGNED(pa, SZ_16K))
	84	return -EINVAL;
	85
2bcb5733 HD	86	l = iommu_read_reg(obj, MMU_REVISION);
	87	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
	88	(l >> 4) & 0xf, l & 0xf);
	89
2bcb5733 HD	90	iommu_write_reg(obj, pa, MMU_TTB);
2bcb5733 HD	91
b148d5fb SA	92	if (obj->has_bus_err_back)
	93	iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
	94
ddfa975a	95	__iommu_set_twl(obj, true);
2bcb5733 HD	96
	97	return 0;
	98	}
	99
6c32df43	100	static void omap2_iommu_disable(struct omap_iommu *obj)
2bcb5733 HD	101	{
	102	u32 l = iommu_read_reg(obj, MMU_CNTL);
	103
	104	l &= ~MMU_CNTL_MASK;
	105	iommu_write_reg(obj, l, MMU_CNTL);
2bcb5733 HD	106
	107	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
	108	}
	109
6c32df43	110	static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
ddfa975a KH	111	{
	112	__iommu_set_twl(obj, false);
	113	}
	114
6c32df43	115	static u32 omap2_iommu_fault_isr(struct omap_iommu obj, u32 ra)
2bcb5733	116	{
2bcb5733	117	u32 stat, da;
2bcb5733 HD	118
	119	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	120	stat &= MMU_IRQ_MASK;
d594f1f3 DC	121	if (!stat) {
d594f1f3 DC	122	*ra = 0;
2bcb5733	123	return 0;
d594f1f3	124	}
2bcb5733 HD	125
	126	da = iommu_read_reg(obj, MMU_FAULT_AD);
	127	*ra = da;
	128
2bcb5733	129	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
37b29810	130
124262a2	131	return stat;
2bcb5733 HD	132	}
2bcb5733 HD	133
6c32df43	134	static void omap2_tlb_read_cr(struct omap_iommu obj, struct cr_regs cr)
2bcb5733 HD	135	{
	136	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	137	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
	138	}
	139
6c32df43	140	static void omap2_tlb_load_cr(struct omap_iommu obj, struct cr_regs cr)
2bcb5733 HD	141	{
	142	iommu_write_reg(obj, cr->cam \| MMU_CAM_V, MMU_CAM);
	143	iommu_write_reg(obj, cr->ram, MMU_RAM);
	144	}
	145
	146	static u32 omap2_cr_to_virt(struct cr_regs *cr)
	147	{
	148	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	149	u32 mask = get_cam_va_mask(cr->cam & page_size);
	150
	151	return cr->cam & mask;
	152	}
	153
6c32df43 OBC	154	static struct cr_regs omap2_alloc_cr(struct omap_iommu obj,
6c32df43 OBC	155	struct iotlb_entry *e)
2bcb5733 HD	156	{
	157	struct cr_regs *cr;
	158
	159	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
	160	dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
	161	e->da);
	162	return ERR_PTR(-EINVAL);
	163	}
	164
	165	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	166	if (!cr)
	167	return ERR_PTR(-ENOMEM);
	168
77bc5abb	169	cr->cam = (e->da & MMU_CAM_VATAG_MASK) \| e->prsvd \| e->pgsz \| e->valid;
2bcb5733 HD	170	cr->ram = e->pa \| e->endian \| e->elsz \| e->mixed;
	171
	172	return cr;
	173	}
	174
	175	static inline int omap2_cr_valid(struct cr_regs *cr)
	176	{
	177	return cr->cam & MMU_CAM_V;
	178	}
	179
	180	static u32 omap2_get_pte_attr(struct iotlb_entry *e)
	181	{
	182	u32 attr;
	183
	184	attr = e->mixed << 5;
	185	attr \|= e->endian;
	186	attr \|= e->elsz >> 3;
7e20b6f3 SA	187	attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) \|\|
7e20b6f3 SA	188	(e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
2bcb5733 HD	189	return attr;
	190	}
	191
6c32df43 OBC	192	static ssize_t
6c32df43 OBC	193	omap2_dump_cr(struct omap_iommu obj, struct cr_regs cr, char *buf)
2bcb5733 HD	194	{
	195	char *p = buf;
	196
	197	/* FIXME: Need more detail analysis of cam/ram */
be6d8026 KH	198	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
be6d8026 KH	199	(cr->cam & MMU_CAM_P) ? 1 : 0);
2bcb5733 HD	200
	201	return p - buf;
	202	}
	203
	204	#define pr_reg(name) \
14e0e679 HD	205	do { \
	206	ssize_t bytes; \
	207	const char *str = "%20s: %08x\n"; \
	208	const int maxcol = 32; \
	209	bytes = snprintf(p, maxcol, str, __stringify(name), \
	210	iommu_read_reg(obj, MMU_##name)); \
	211	p += bytes; \
	212	len -= bytes; \
	213	if (len < maxcol) \
	214	goto out; \
	215	} while (0)
	216
6c32df43 OBC	217	static ssize_t
6c32df43 OBC	218	omap2_iommu_dump_ctx(struct omap_iommu obj, char buf, ssize_t len)
2bcb5733 HD	219	{
	220	char *p = buf;
	221
	222	pr_reg(REVISION);
2bcb5733 HD	223	pr_reg(IRQSTATUS);
	224	pr_reg(IRQENABLE);
	225	pr_reg(WALKING_ST);
	226	pr_reg(CNTL);
	227	pr_reg(FAULT_AD);
	228	pr_reg(TTB);
	229	pr_reg(LOCK);
	230	pr_reg(LD_TLB);
	231	pr_reg(CAM);
	232	pr_reg(RAM);
	233	pr_reg(GFLUSH);
	234	pr_reg(FLUSH_ENTRY);
	235	pr_reg(READ_CAM);
	236	pr_reg(READ_RAM);
	237	pr_reg(EMU_FAULT_AD);
14e0e679	238	out:
2bcb5733 HD	239	return p - buf;
	240	}
	241
6c32df43	242	static void omap2_iommu_save_ctx(struct omap_iommu *obj)
2bcb5733 HD	243	{
	244	int i;
	245	u32 *p = obj->ctx;
	246
	247	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	248	p[i] = iommu_read_reg(obj, i * sizeof(u32));
	249	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	250	}
2bcb5733 HD	251	}
2bcb5733 HD	252
6c32df43	253	static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
2bcb5733 HD	254	{
	255	int i;
	256	u32 *p = obj->ctx;
	257
	258	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	259	iommu_write_reg(obj, p[i], i * sizeof(u32));
	260	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	261	}
2bcb5733 HD	262	}
	263
	264	static void omap2_cr_to_e(struct cr_regs cr, struct iotlb_entry e)
	265	{
	266	e->da = cr->cam & MMU_CAM_VATAG_MASK;
	267	e->pa = cr->ram & MMU_RAM_PADDR_MASK;
	268	e->valid = cr->cam & MMU_CAM_V;
	269	e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
	270	e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
	271	e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
	272	e->mixed = cr->ram & MMU_RAM_MIXED;
	273	}
	274
	275	static const struct iommu_functions omap2_iommu_ops = {
2bcb5733 HD	276	.enable = omap2_iommu_enable,
2bcb5733 HD	277	.disable = omap2_iommu_disable,
ddfa975a	278	.set_twl = omap2_iommu_set_twl,
2bcb5733 HD	279	.fault_isr = omap2_iommu_fault_isr,
	280
	281	.tlb_read_cr = omap2_tlb_read_cr,
	282	.tlb_load_cr = omap2_tlb_load_cr,
	283
	284	.cr_to_e = omap2_cr_to_e,
	285	.cr_to_virt = omap2_cr_to_virt,
	286	.alloc_cr = omap2_alloc_cr,
	287	.cr_valid = omap2_cr_valid,
	288	.dump_cr = omap2_dump_cr,
	289
	290	.get_pte_attr = omap2_get_pte_attr,
	291
	292	.save_ctx = omap2_iommu_save_ctx,
	293	.restore_ctx = omap2_iommu_restore_ctx,
	294	.dump_ctx = omap2_iommu_dump_ctx,
	295	};
	296
	297	static int __init omap2_iommu_init(void)
	298	{
6c32df43	299	return omap_install_iommu_arch(&omap2_iommu_ops);
2bcb5733 HD	300	}
	301	module_init(omap2_iommu_init);
	302
	303	static void __exit omap2_iommu_exit(void)
	304	{
6c32df43	305	omap_uninstall_iommu_arch(&omap2_iommu_ops);
2bcb5733 HD	306	}
	307	module_exit(omap2_iommu_exit);
	308
	309	MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
	310	MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
	311	MODULE_LICENSE("GPL v2");