[deliverable/linux.git] / drivers / iommu / omap-iommu2.c

/*
 * omap iommu: omap2/3 architecture specific functions
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
 *		Paul Mundt and Toshihiro Kobayashi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/omap-iommu.h>
#include <linux/slab.h>
#include <linux/stringify.h>

#include <plat/iommu.h>
#include "omap-iommu.h"

/*
 * omap2 architecture specific register bit definitions
 */
#define IOMMU_ARCH_VERSION	0x00000011

/* SYSCONF */
#define MMU_SYS_IDLE_SHIFT	3
#define MMU_SYS_IDLE_FORCE	(0 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_NONE	(1 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_SMART	(2 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_MASK	(3 << MMU_SYS_IDLE_SHIFT)

#define MMU_SYS_SOFTRESET	(1 << 1)
#define MMU_SYS_AUTOIDLE	1

/* SYSSTATUS */
#define MMU_SYS_RESETDONE	1

/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
#define MMU_IRQ_EMUMISS		(1 << 2)
#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
#define MMU_IRQ_TLBMISS		(1 << 0)

#define __MMU_IRQ_FAULT		\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
#define MMU_IRQ_MASK		\
	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	(1 << 3)
#define MMU_CNTL_TWL_EN		(1 << 2)
#define MMU_CNTL_MMU_EN		(1 << 1)

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)


static void __iommu_set_twl(struct omap_iommu *obj, bool on)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	if (on)
		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	else
		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);

	l &= ~MMU_CNTL_MASK;
	if (on)
		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
	else
		l |= (MMU_CNTL_MMU_EN);

	iommu_write_reg(obj, l, MMU_CNTL);
}


static int omap2_iommu_enable(struct omap_iommu *obj)
{
	u32 l, pa;
	unsigned long timeout;

	if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
		return -EINVAL;

	pa = virt_to_phys(obj->iopgd);
	if (!IS_ALIGNED(pa, SZ_16K))
		return -EINVAL;

	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);

	timeout = jiffies + msecs_to_jiffies(20);
	do {
		l = iommu_read_reg(obj, MMU_SYSSTATUS);
		if (l & MMU_SYS_RESETDONE)
			break;
	} while (!time_after(jiffies, timeout));

	if (!(l & MMU_SYS_RESETDONE)) {
		dev_err(obj->dev, "can't take mmu out of reset\n");
		return -ENODEV;
	}

	l = iommu_read_reg(obj, MMU_REVISION);
	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
		 (l >> 4) & 0xf, l & 0xf);

	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	l &= ~MMU_SYS_IDLE_MASK;
	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
	iommu_write_reg(obj, l, MMU_SYSCONFIG);

	iommu_write_reg(obj, pa, MMU_TTB);

	__iommu_set_twl(obj, true);

	return 0;
}

static void omap2_iommu_disable(struct omap_iommu *obj)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	l &= ~MMU_CNTL_MASK;
	iommu_write_reg(obj, l, MMU_CNTL);
	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);

	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
}

static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
{
	__iommu_set_twl(obj, false);
}

static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
{
	u32 stat, da;
	u32 errs = 0;

	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	stat &= MMU_IRQ_MASK;
	if (!stat) {
		*ra = 0;
		return 0;
	}

	da = iommu_read_reg(obj, MMU_FAULT_AD);
	*ra = da;

	if (stat & MMU_IRQ_TLBMISS)
		errs |= OMAP_IOMMU_ERR_TLB_MISS;
	if (stat & MMU_IRQ_TRANSLATIONFAULT)
		errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
	if (stat & MMU_IRQ_EMUMISS)
		errs |= OMAP_IOMMU_ERR_EMU_MISS;
	if (stat & MMU_IRQ_TABLEWALKFAULT)
		errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
	if (stat & MMU_IRQ_MULTIHITFAULT)
		errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
	iommu_write_reg(obj, stat, MMU_IRQSTATUS);

	return errs;
}

static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
{
	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
}

static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
{
	iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
	iommu_write_reg(obj, cr->ram, MMU_RAM);
}

static u32 omap2_cr_to_virt(struct cr_regs *cr)
{
	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	u32 mask = get_cam_va_mask(cr->cam & page_size);

	return cr->cam & mask;
}

static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
						struct iotlb_entry *e)
{
	struct cr_regs *cr;

	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
		dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
			e->da);
		return ERR_PTR(-EINVAL);
	}

	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	if (!cr)
		return ERR_PTR(-ENOMEM);

	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
	cr->ram = e->pa | e->endian | e->elsz | e->mixed;

	return cr;
}

static inline int omap2_cr_valid(struct cr_regs *cr)
{
	return cr->cam & MMU_CAM_V;
}

static u32 omap2_get_pte_attr(struct iotlb_entry *e)
{
	u32 attr;

	attr = e->mixed << 5;
	attr |= e->endian;
	attr |= e->elsz >> 3;
	attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
			(e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
	return attr;
}

static ssize_t
omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
{
	char *p = buf;

	/* FIXME: Need more detail analysis of cam/ram */
	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
					(cr->cam & MMU_CAM_P) ? 1 : 0);

	return p - buf;
}

#define pr_reg(name)							\
	do {								\
		ssize_t bytes;						\
		const char *str = "%20s: %08x\n";			\
		const int maxcol = 32;					\
		bytes = snprintf(p, maxcol, str, __stringify(name),	\
				 iommu_read_reg(obj, MMU_##name));	\
		p += bytes;						\
		len -= bytes;						\
		if (len < maxcol)					\
			goto out;					\
	} while (0)

static ssize_t
omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
{
	char *p = buf;

	pr_reg(REVISION);
	pr_reg(SYSCONFIG);
	pr_reg(SYSSTATUS);
	pr_reg(IRQSTATUS);
	pr_reg(IRQENABLE);
	pr_reg(WALKING_ST);
	pr_reg(CNTL);
	pr_reg(FAULT_AD);
	pr_reg(TTB);
	pr_reg(LOCK);
	pr_reg(LD_TLB);
	pr_reg(CAM);
	pr_reg(RAM);
	pr_reg(GFLUSH);
	pr_reg(FLUSH_ENTRY);
	pr_reg(READ_CAM);
	pr_reg(READ_RAM);
	pr_reg(EMU_FAULT_AD);
out:
	return p - buf;
}

static void omap2_iommu_save_ctx(struct omap_iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		p[i] = iommu_read_reg(obj, i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		iommu_write_reg(obj, p[i], i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
{
	e->da		= cr->cam & MMU_CAM_VATAG_MASK;
	e->pa		= cr->ram & MMU_RAM_PADDR_MASK;
	e->valid	= cr->cam & MMU_CAM_V;
	e->pgsz		= cr->cam & MMU_CAM_PGSZ_MASK;
	e->endian	= cr->ram & MMU_RAM_ENDIAN_MASK;
	e->elsz		= cr->ram & MMU_RAM_ELSZ_MASK;
	e->mixed	= cr->ram & MMU_RAM_MIXED;
}

static const struct iommu_functions omap2_iommu_ops = {
	.version	= IOMMU_ARCH_VERSION,

	.enable		= omap2_iommu_enable,
	.disable	= omap2_iommu_disable,
	.set_twl	= omap2_iommu_set_twl,
	.fault_isr	= omap2_iommu_fault_isr,

	.tlb_read_cr	= omap2_tlb_read_cr,
	.tlb_load_cr	= omap2_tlb_load_cr,

	.cr_to_e	= omap2_cr_to_e,
	.cr_to_virt	= omap2_cr_to_virt,
	.alloc_cr	= omap2_alloc_cr,
	.cr_valid	= omap2_cr_valid,
	.dump_cr	= omap2_dump_cr,

	.get_pte_attr	= omap2_get_pte_attr,

	.save_ctx	= omap2_iommu_save_ctx,
	.restore_ctx	= omap2_iommu_restore_ctx,
	.dump_ctx	= omap2_iommu_dump_ctx,
};

static int __init omap2_iommu_init(void)
{
	return omap_install_iommu_arch(&omap2_iommu_ops);
}
module_init(omap2_iommu_init);

static void __exit omap2_iommu_exit(void)
{
	omap_uninstall_iommu_arch(&omap2_iommu_ops);
}
module_exit(omap2_iommu_exit);

MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bcb5733 HD	1	/*
	2	* omap iommu: omap2/3 architecture specific functions
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
	7	* Paul Mundt and Toshihiro Kobayashi
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/err.h>
	15	#include <linux/device.h>
ed1c7de2	16	#include <linux/io.h>
2bcb5733 HD	17	#include <linux/jiffies.h>
2bcb5733 HD	18	#include <linux/module.h>
c8d35c84	19	#include <linux/omap-iommu.h>
5a0e3ad6	20	#include <linux/slab.h>
2bcb5733 HD	21	#include <linux/stringify.h>
2bcb5733 HD	22
ce491cf8	23	#include <plat/iommu.h>
ed1c7de2	24	#include "omap-iommu.h"
2bcb5733 HD	25
	26	/*
	27	* omap2 architecture specific register bit definitions
	28	*/
	29	#define IOMMU_ARCH_VERSION 0x00000011
	30
	31	/* SYSCONF */
	32	#define MMU_SYS_IDLE_SHIFT 3
	33	#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
	34	#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
	35	#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
	36	#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
	37
	38	#define MMU_SYS_SOFTRESET (1 << 1)
	39	#define MMU_SYS_AUTOIDLE 1
	40
	41	/* SYSSTATUS */
	42	#define MMU_SYS_RESETDONE 1
	43
	44	/* IRQSTATUS & IRQENABLE */
	45	#define MMU_IRQ_MULTIHITFAULT (1 << 4)
	46	#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
	47	#define MMU_IRQ_EMUMISS (1 << 2)
	48	#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
	49	#define MMU_IRQ_TLBMISS (1 << 0)
993dd17e KH	50
	51	#define __MMU_IRQ_FAULT \
	52	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_EMUMISS \| MMU_IRQ_TRANSLATIONFAULT)
	53	#define MMU_IRQ_MASK \
	54	(__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_TLBMISS)
	55	#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT)
	56	#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TLBMISS)
2bcb5733 HD	57
	58	/* MMU_CNTL */
	59	#define MMU_CNTL_SHIFT 1
	60	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
	61	#define MMU_CNTL_EML_TLB (1 << 3)
	62	#define MMU_CNTL_TWL_EN (1 << 2)
	63	#define MMU_CNTL_MMU_EN (1 << 1)
	64
	65	#define get_cam_va_mask(pgsz) \
	66	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	67	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	68	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	69	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	70
ddfa975a	71
6c32df43	72	static void __iommu_set_twl(struct omap_iommu *obj, bool on)
ddfa975a KH	73	{
	74	u32 l = iommu_read_reg(obj, MMU_CNTL);
	75
	76	if (on)
	77	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	78	else
	79	iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
	80
	81	l &= ~MMU_CNTL_MASK;
	82	if (on)
	83	l \|= (MMU_CNTL_MMU_EN \| MMU_CNTL_TWL_EN);
	84	else
	85	l \|= (MMU_CNTL_MMU_EN);
	86
	87	iommu_write_reg(obj, l, MMU_CNTL);
	88	}
	89
	90
6c32df43	91	static int omap2_iommu_enable(struct omap_iommu *obj)
2bcb5733 HD	92	{
	93	u32 l, pa;
	94	unsigned long timeout;
	95
	96	if (!obj->iopgd \|\| !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
	97	return -EINVAL;
	98
	99	pa = virt_to_phys(obj->iopgd);
	100	if (!IS_ALIGNED(pa, SZ_16K))
	101	return -EINVAL;
	102
	103	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
	104
	105	timeout = jiffies + msecs_to_jiffies(20);
	106	do {
	107	l = iommu_read_reg(obj, MMU_SYSSTATUS);
	108	if (l & MMU_SYS_RESETDONE)
	109	break;
055c49d2	110	} while (!time_after(jiffies, timeout));
2bcb5733 HD	111
	112	if (!(l & MMU_SYS_RESETDONE)) {
	113	dev_err(obj->dev, "can't take mmu out of reset\n");
	114	return -ENODEV;
	115	}
	116
	117	l = iommu_read_reg(obj, MMU_REVISION);
	118	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
	119	(l >> 4) & 0xf, l & 0xf);
	120
	121	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	122	l &= ~MMU_SYS_IDLE_MASK;
	123	l \|= (MMU_SYS_IDLE_SMART \| MMU_SYS_AUTOIDLE);
	124	iommu_write_reg(obj, l, MMU_SYSCONFIG);
	125
2bcb5733 HD	126	iommu_write_reg(obj, pa, MMU_TTB);
2bcb5733 HD	127
ddfa975a	128	__iommu_set_twl(obj, true);
2bcb5733 HD	129
	130	return 0;
	131	}
	132
6c32df43	133	static void omap2_iommu_disable(struct omap_iommu *obj)
2bcb5733 HD	134	{
	135	u32 l = iommu_read_reg(obj, MMU_CNTL);
	136
	137	l &= ~MMU_CNTL_MASK;
	138	iommu_write_reg(obj, l, MMU_CNTL);
	139	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
	140
	141	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
	142	}
	143
6c32df43	144	static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
ddfa975a KH	145	{
	146	__iommu_set_twl(obj, false);
	147	}
	148
6c32df43	149	static u32 omap2_iommu_fault_isr(struct omap_iommu obj, u32 ra)
2bcb5733	150	{
2bcb5733	151	u32 stat, da;
d594f1f3	152	u32 errs = 0;
2bcb5733 HD	153
	154	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	155	stat &= MMU_IRQ_MASK;
d594f1f3 DC	156	if (!stat) {
d594f1f3 DC	157	*ra = 0;
2bcb5733	158	return 0;
d594f1f3	159	}
2bcb5733 HD	160
	161	da = iommu_read_reg(obj, MMU_FAULT_AD);
	162	*ra = da;
	163
d594f1f3 DC	164	if (stat & MMU_IRQ_TLBMISS)
	165	errs \|= OMAP_IOMMU_ERR_TLB_MISS;
	166	if (stat & MMU_IRQ_TRANSLATIONFAULT)
	167	errs \|= OMAP_IOMMU_ERR_TRANS_FAULT;
	168	if (stat & MMU_IRQ_EMUMISS)
	169	errs \|= OMAP_IOMMU_ERR_EMU_MISS;
	170	if (stat & MMU_IRQ_TABLEWALKFAULT)
	171	errs \|= OMAP_IOMMU_ERR_TBLWALK_FAULT;
	172	if (stat & MMU_IRQ_MULTIHITFAULT)
	173	errs \|= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
2bcb5733	174	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
37b29810	175
d594f1f3	176	return errs;
2bcb5733 HD	177	}
2bcb5733 HD	178
6c32df43	179	static void omap2_tlb_read_cr(struct omap_iommu obj, struct cr_regs cr)
2bcb5733 HD	180	{
	181	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	182	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
	183	}
	184
6c32df43	185	static void omap2_tlb_load_cr(struct omap_iommu obj, struct cr_regs cr)
2bcb5733 HD	186	{
	187	iommu_write_reg(obj, cr->cam \| MMU_CAM_V, MMU_CAM);
	188	iommu_write_reg(obj, cr->ram, MMU_RAM);
	189	}
	190
	191	static u32 omap2_cr_to_virt(struct cr_regs *cr)
	192	{
	193	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	194	u32 mask = get_cam_va_mask(cr->cam & page_size);
	195
	196	return cr->cam & mask;
	197	}
	198
6c32df43 OBC	199	static struct cr_regs omap2_alloc_cr(struct omap_iommu obj,
6c32df43 OBC	200	struct iotlb_entry *e)
2bcb5733 HD	201	{
	202	struct cr_regs *cr;
	203
	204	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
	205	dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
	206	e->da);
	207	return ERR_PTR(-EINVAL);
	208	}
	209
	210	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	211	if (!cr)
	212	return ERR_PTR(-ENOMEM);
	213
77bc5abb	214	cr->cam = (e->da & MMU_CAM_VATAG_MASK) \| e->prsvd \| e->pgsz \| e->valid;
2bcb5733 HD	215	cr->ram = e->pa \| e->endian \| e->elsz \| e->mixed;
	216
	217	return cr;
	218	}
	219
	220	static inline int omap2_cr_valid(struct cr_regs *cr)
	221	{
	222	return cr->cam & MMU_CAM_V;
	223	}
	224
	225	static u32 omap2_get_pte_attr(struct iotlb_entry *e)
	226	{
	227	u32 attr;
	228
	229	attr = e->mixed << 5;
	230	attr \|= e->endian;
	231	attr \|= e->elsz >> 3;
7e20b6f3 SA	232	attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) \|\|
7e20b6f3 SA	233	(e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
2bcb5733 HD	234	return attr;
	235	}
	236
6c32df43 OBC	237	static ssize_t
6c32df43 OBC	238	omap2_dump_cr(struct omap_iommu obj, struct cr_regs cr, char *buf)
2bcb5733 HD	239	{
	240	char *p = buf;
	241
	242	/* FIXME: Need more detail analysis of cam/ram */
be6d8026 KH	243	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
be6d8026 KH	244	(cr->cam & MMU_CAM_P) ? 1 : 0);
2bcb5733 HD	245
	246	return p - buf;
	247	}
	248
	249	#define pr_reg(name) \
14e0e679 HD	250	do { \
	251	ssize_t bytes; \
	252	const char *str = "%20s: %08x\n"; \
	253	const int maxcol = 32; \
	254	bytes = snprintf(p, maxcol, str, __stringify(name), \
	255	iommu_read_reg(obj, MMU_##name)); \
	256	p += bytes; \
	257	len -= bytes; \
	258	if (len < maxcol) \
	259	goto out; \
	260	} while (0)
	261
6c32df43 OBC	262	static ssize_t
6c32df43 OBC	263	omap2_iommu_dump_ctx(struct omap_iommu obj, char buf, ssize_t len)
2bcb5733 HD	264	{
	265	char *p = buf;
	266
	267	pr_reg(REVISION);
	268	pr_reg(SYSCONFIG);
	269	pr_reg(SYSSTATUS);
	270	pr_reg(IRQSTATUS);
	271	pr_reg(IRQENABLE);
	272	pr_reg(WALKING_ST);
	273	pr_reg(CNTL);
	274	pr_reg(FAULT_AD);
	275	pr_reg(TTB);
	276	pr_reg(LOCK);
	277	pr_reg(LD_TLB);
	278	pr_reg(CAM);
	279	pr_reg(RAM);
	280	pr_reg(GFLUSH);
	281	pr_reg(FLUSH_ENTRY);
	282	pr_reg(READ_CAM);
	283	pr_reg(READ_RAM);
	284	pr_reg(EMU_FAULT_AD);
14e0e679	285	out:
2bcb5733 HD	286	return p - buf;
	287	}
	288
6c32df43	289	static void omap2_iommu_save_ctx(struct omap_iommu *obj)
2bcb5733 HD	290	{
	291	int i;
	292	u32 *p = obj->ctx;
	293
	294	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	295	p[i] = iommu_read_reg(obj, i * sizeof(u32));
	296	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	297	}
	298
	299	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	300	}
	301
6c32df43	302	static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
2bcb5733 HD	303	{
	304	int i;
	305	u32 *p = obj->ctx;
	306
	307	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	308	iommu_write_reg(obj, p[i], i * sizeof(u32));
	309	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	310	}
	311
	312	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	313	}
	314
	315	static void omap2_cr_to_e(struct cr_regs cr, struct iotlb_entry e)
	316	{
	317	e->da = cr->cam & MMU_CAM_VATAG_MASK;
	318	e->pa = cr->ram & MMU_RAM_PADDR_MASK;
	319	e->valid = cr->cam & MMU_CAM_V;
	320	e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
	321	e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
	322	e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
	323	e->mixed = cr->ram & MMU_RAM_MIXED;
	324	}
	325
	326	static const struct iommu_functions omap2_iommu_ops = {
	327	.version = IOMMU_ARCH_VERSION,
	328
	329	.enable = omap2_iommu_enable,
	330	.disable = omap2_iommu_disable,
ddfa975a	331	.set_twl = omap2_iommu_set_twl,
2bcb5733 HD	332	.fault_isr = omap2_iommu_fault_isr,
	333
	334	.tlb_read_cr = omap2_tlb_read_cr,
	335	.tlb_load_cr = omap2_tlb_load_cr,
	336
	337	.cr_to_e = omap2_cr_to_e,
	338	.cr_to_virt = omap2_cr_to_virt,
	339	.alloc_cr = omap2_alloc_cr,
	340	.cr_valid = omap2_cr_valid,
	341	.dump_cr = omap2_dump_cr,
	342
	343	.get_pte_attr = omap2_get_pte_attr,
	344
	345	.save_ctx = omap2_iommu_save_ctx,
	346	.restore_ctx = omap2_iommu_restore_ctx,
	347	.dump_ctx = omap2_iommu_dump_ctx,
	348	};
	349
	350	static int __init omap2_iommu_init(void)
	351	{
6c32df43	352	return omap_install_iommu_arch(&omap2_iommu_ops);
2bcb5733 HD	353	}
	354	module_init(omap2_iommu_init);
	355
	356	static void __exit omap2_iommu_exit(void)
	357	{
6c32df43	358	omap_uninstall_iommu_arch(&omap2_iommu_ops);
2bcb5733 HD	359	}
	360	module_exit(omap2_iommu_exit);
	361
	362	MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
	363	MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
	364	MODULE_LICENSE("GPL v2");