Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
d1313e78 | 10 | #include <linux/debugfs.h> |
bc5e6dea | 11 | #include <linux/err.h> |
7a31f6f4 | 12 | #include <linux/iommu.h> |
89184651 | 13 | #include <linux/kernel.h> |
0760e8fa | 14 | #include <linux/of.h> |
89184651 TR |
15 | #include <linux/of_device.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
89184651 TR |
22 | struct tegra_smmu { |
23 | void __iomem *regs; | |
24 | struct device *dev; | |
e6bc5933 | 25 | |
89184651 TR |
26 | struct tegra_mc *mc; |
27 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 28 | |
804cb54c | 29 | unsigned long pfn_mask; |
11cec15b | 30 | unsigned long tlb_mask; |
804cb54c | 31 | |
89184651 TR |
32 | unsigned long *asids; |
33 | struct mutex lock; | |
39abf8aa | 34 | |
89184651 | 35 | struct list_head list; |
d1313e78 TR |
36 | |
37 | struct dentry *debugfs; | |
7a31f6f4 | 38 | }; |
7a31f6f4 | 39 | |
89184651 | 40 | struct tegra_smmu_as { |
d5f1a81c | 41 | struct iommu_domain domain; |
89184651 TR |
42 | struct tegra_smmu *smmu; |
43 | unsigned int use_count; | |
32924c76 | 44 | u32 *count; |
853520fa | 45 | struct page **pts; |
89184651 | 46 | struct page *pd; |
e3c97196 | 47 | dma_addr_t pd_dma; |
89184651 TR |
48 | unsigned id; |
49 | u32 attr; | |
7a31f6f4 HD |
50 | }; |
51 | ||
d5f1a81c JR |
52 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
53 | { | |
54 | return container_of(dom, struct tegra_smmu_as, domain); | |
55 | } | |
56 | ||
89184651 TR |
57 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
58 | unsigned long offset) | |
59 | { | |
60 | writel(value, smmu->regs + offset); | |
61 | } | |
7a31f6f4 | 62 | |
89184651 TR |
63 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
64 | { | |
65 | return readl(smmu->regs + offset); | |
66 | } | |
5a2c937a | 67 | |
89184651 TR |
68 | #define SMMU_CONFIG 0x010 |
69 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 70 | |
89184651 TR |
71 | #define SMMU_TLB_CONFIG 0x14 |
72 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
73 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
11cec15b TR |
74 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ |
75 | ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask) | |
0760e8fa | 76 | |
89184651 TR |
77 | #define SMMU_PTC_CONFIG 0x18 |
78 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
79 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
80 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 81 | |
89184651 TR |
82 | #define SMMU_PTB_ASID 0x01c |
83 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 84 | |
89184651 | 85 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 86 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 87 | |
e3c97196 | 88 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 89 | |
89184651 TR |
90 | #define SMMU_TLB_FLUSH 0x030 |
91 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
92 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
93 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
94 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
95 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
96 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
97 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
98 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
99 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 100 | |
89184651 TR |
101 | #define SMMU_PTC_FLUSH 0x034 |
102 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
103 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 104 | |
89184651 TR |
105 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
106 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 107 | |
89184651 TR |
108 | /* per-SWGROUP SMMU_*_ASID register */ |
109 | #define SMMU_ASID_ENABLE (1 << 31) | |
110 | #define SMMU_ASID_MASK 0x7f | |
111 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 112 | |
89184651 TR |
113 | /* page table definitions */ |
114 | #define SMMU_NUM_PDE 1024 | |
115 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 116 | |
89184651 TR |
117 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
118 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 119 | |
89184651 TR |
120 | #define SMMU_PDE_SHIFT 22 |
121 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 122 | |
89184651 TR |
123 | #define SMMU_PD_READABLE (1 << 31) |
124 | #define SMMU_PD_WRITABLE (1 << 30) | |
125 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 126 | |
89184651 TR |
127 | #define SMMU_PDE_READABLE (1 << 31) |
128 | #define SMMU_PDE_WRITABLE (1 << 30) | |
129 | #define SMMU_PDE_NONSECURE (1 << 29) | |
130 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 131 | |
89184651 TR |
132 | #define SMMU_PTE_READABLE (1 << 31) |
133 | #define SMMU_PTE_WRITABLE (1 << 30) | |
134 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 135 | |
89184651 TR |
136 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
137 | SMMU_PDE_NONSECURE) | |
138 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
139 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 140 | |
34d35f8c RK |
141 | static unsigned int iova_pd_index(unsigned long iova) |
142 | { | |
143 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
144 | } | |
145 | ||
146 | static unsigned int iova_pt_index(unsigned long iova) | |
147 | { | |
148 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
149 | } | |
150 | ||
e3c97196 | 151 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 152 | { |
e3c97196 RK |
153 | addr >>= 12; |
154 | return (addr & smmu->pfn_mask) == addr; | |
155 | } | |
4b3c7d10 | 156 | |
e3c97196 RK |
157 | static dma_addr_t smmu_pde_to_dma(u32 pde) |
158 | { | |
159 | return pde << 12; | |
4b3c7d10 RK |
160 | } |
161 | ||
b8fe0382 RK |
162 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
163 | { | |
164 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
165 | } | |
166 | ||
e3c97196 | 167 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 168 | unsigned long offset) |
7a31f6f4 | 169 | { |
89184651 TR |
170 | u32 value; |
171 | ||
b8fe0382 | 172 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 173 | |
b8fe0382 | 174 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
175 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
176 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 177 | #else |
b8fe0382 | 178 | value = 0; |
89184651 | 179 | #endif |
b8fe0382 | 180 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 181 | } |
89184651 | 182 | |
e3c97196 | 183 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 184 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
185 | } |
186 | ||
89184651 | 187 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 188 | { |
89184651 | 189 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
190 | } |
191 | ||
89184651 TR |
192 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
193 | unsigned long asid) | |
7a31f6f4 | 194 | { |
89184651 | 195 | u32 value; |
7a31f6f4 | 196 | |
89184651 TR |
197 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
198 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
199 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
200 | } |
201 | ||
89184651 TR |
202 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
203 | unsigned long asid, | |
204 | unsigned long iova) | |
7a31f6f4 | 205 | { |
89184651 | 206 | u32 value; |
7a31f6f4 | 207 | |
89184651 TR |
208 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
209 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
210 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
211 | } |
212 | ||
89184651 TR |
213 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
214 | unsigned long asid, | |
215 | unsigned long iova) | |
7a31f6f4 | 216 | { |
89184651 | 217 | u32 value; |
7a31f6f4 | 218 | |
89184651 TR |
219 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
220 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
221 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
222 | } |
223 | ||
89184651 | 224 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 225 | { |
89184651 | 226 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
227 | } |
228 | ||
89184651 | 229 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 230 | { |
89184651 | 231 | unsigned long id; |
7a31f6f4 | 232 | |
89184651 | 233 | mutex_lock(&smmu->lock); |
7a31f6f4 | 234 | |
89184651 TR |
235 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
236 | if (id >= smmu->soc->num_asids) { | |
237 | mutex_unlock(&smmu->lock); | |
238 | return -ENOSPC; | |
7a31f6f4 | 239 | } |
7a31f6f4 | 240 | |
89184651 TR |
241 | set_bit(id, smmu->asids); |
242 | *idp = id; | |
243 | ||
244 | mutex_unlock(&smmu->lock); | |
245 | return 0; | |
7a31f6f4 HD |
246 | } |
247 | ||
89184651 | 248 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 249 | { |
89184651 TR |
250 | mutex_lock(&smmu->lock); |
251 | clear_bit(id, smmu->asids); | |
252 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 253 | } |
89184651 TR |
254 | |
255 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 256 | { |
89184651 | 257 | return false; |
7a31f6f4 | 258 | } |
7a31f6f4 | 259 | |
d5f1a81c | 260 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 261 | { |
89184651 | 262 | struct tegra_smmu_as *as; |
7a31f6f4 | 263 | |
d5f1a81c JR |
264 | if (type != IOMMU_DOMAIN_UNMANAGED) |
265 | return NULL; | |
266 | ||
89184651 TR |
267 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
268 | if (!as) | |
d5f1a81c | 269 | return NULL; |
7a31f6f4 | 270 | |
89184651 | 271 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 272 | |
707917cb | 273 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
274 | if (!as->pd) { |
275 | kfree(as); | |
d5f1a81c | 276 | return NULL; |
7a31f6f4 | 277 | } |
9e971a03 | 278 | |
32924c76 | 279 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
280 | if (!as->count) { |
281 | __free_page(as->pd); | |
282 | kfree(as); | |
d5f1a81c | 283 | return NULL; |
7a31f6f4 | 284 | } |
9e971a03 | 285 | |
853520fa RK |
286 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
287 | if (!as->pts) { | |
32924c76 | 288 | kfree(as->count); |
853520fa RK |
289 | __free_page(as->pd); |
290 | kfree(as); | |
291 | return NULL; | |
292 | } | |
293 | ||
471d9144 | 294 | /* setup aperture */ |
7f65ef01 JR |
295 | as->domain.geometry.aperture_start = 0; |
296 | as->domain.geometry.aperture_end = 0xffffffff; | |
297 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 298 | |
d5f1a81c | 299 | return &as->domain; |
7a31f6f4 HD |
300 | } |
301 | ||
d5f1a81c | 302 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 303 | { |
d5f1a81c | 304 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 305 | |
89184651 | 306 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 307 | |
89184651 | 308 | kfree(as); |
7a31f6f4 HD |
309 | } |
310 | ||
89184651 TR |
311 | static const struct tegra_smmu_swgroup * |
312 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 313 | { |
89184651 TR |
314 | const struct tegra_smmu_swgroup *group = NULL; |
315 | unsigned int i; | |
7a31f6f4 | 316 | |
89184651 TR |
317 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
318 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
319 | group = &smmu->soc->swgroups[i]; | |
320 | break; | |
321 | } | |
322 | } | |
7a31f6f4 | 323 | |
89184651 | 324 | return group; |
7a31f6f4 HD |
325 | } |
326 | ||
89184651 TR |
327 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
328 | unsigned int asid) | |
7a31f6f4 | 329 | { |
89184651 TR |
330 | const struct tegra_smmu_swgroup *group; |
331 | unsigned int i; | |
332 | u32 value; | |
7a31f6f4 | 333 | |
89184651 TR |
334 | for (i = 0; i < smmu->soc->num_clients; i++) { |
335 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 336 | |
89184651 TR |
337 | if (client->swgroup != swgroup) |
338 | continue; | |
7a31f6f4 | 339 | |
89184651 TR |
340 | value = smmu_readl(smmu, client->smmu.reg); |
341 | value |= BIT(client->smmu.bit); | |
342 | smmu_writel(smmu, value, client->smmu.reg); | |
343 | } | |
7a31f6f4 | 344 | |
89184651 TR |
345 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
346 | if (group) { | |
347 | value = smmu_readl(smmu, group->reg); | |
348 | value &= ~SMMU_ASID_MASK; | |
349 | value |= SMMU_ASID_VALUE(asid); | |
350 | value |= SMMU_ASID_ENABLE; | |
351 | smmu_writel(smmu, value, group->reg); | |
352 | } | |
7a31f6f4 HD |
353 | } |
354 | ||
89184651 TR |
355 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
356 | unsigned int asid) | |
7a31f6f4 | 357 | { |
89184651 TR |
358 | const struct tegra_smmu_swgroup *group; |
359 | unsigned int i; | |
360 | u32 value; | |
7a31f6f4 | 361 | |
89184651 TR |
362 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
363 | if (group) { | |
364 | value = smmu_readl(smmu, group->reg); | |
365 | value &= ~SMMU_ASID_MASK; | |
366 | value |= SMMU_ASID_VALUE(asid); | |
367 | value &= ~SMMU_ASID_ENABLE; | |
368 | smmu_writel(smmu, value, group->reg); | |
369 | } | |
7a31f6f4 | 370 | |
89184651 TR |
371 | for (i = 0; i < smmu->soc->num_clients; i++) { |
372 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 373 | |
89184651 TR |
374 | if (client->swgroup != swgroup) |
375 | continue; | |
7a31f6f4 | 376 | |
89184651 TR |
377 | value = smmu_readl(smmu, client->smmu.reg); |
378 | value &= ~BIT(client->smmu.bit); | |
379 | smmu_writel(smmu, value, client->smmu.reg); | |
380 | } | |
7a31f6f4 HD |
381 | } |
382 | ||
89184651 TR |
383 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
384 | struct tegra_smmu_as *as) | |
7a31f6f4 | 385 | { |
89184651 | 386 | u32 value; |
7a31f6f4 HD |
387 | int err; |
388 | ||
89184651 TR |
389 | if (as->use_count > 0) { |
390 | as->use_count++; | |
391 | return 0; | |
7a31f6f4 | 392 | } |
7a31f6f4 | 393 | |
e3c97196 RK |
394 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
395 | DMA_TO_DEVICE); | |
396 | if (dma_mapping_error(smmu->dev, as->pd_dma)) | |
397 | return -ENOMEM; | |
398 | ||
399 | /* We can't handle 64-bit DMA addresses */ | |
400 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
401 | err = -ENOMEM; | |
402 | goto err_unmap; | |
403 | } | |
404 | ||
89184651 TR |
405 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
406 | if (err < 0) | |
e3c97196 | 407 | goto err_unmap; |
7a31f6f4 | 408 | |
e3c97196 | 409 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 410 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 411 | |
89184651 | 412 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 413 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
414 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
415 | smmu_flush(smmu); | |
7a31f6f4 | 416 | |
89184651 TR |
417 | as->smmu = smmu; |
418 | as->use_count++; | |
7a31f6f4 | 419 | |
89184651 | 420 | return 0; |
e3c97196 RK |
421 | |
422 | err_unmap: | |
423 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
424 | return err; | |
7a31f6f4 HD |
425 | } |
426 | ||
89184651 TR |
427 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
428 | struct tegra_smmu_as *as) | |
7a31f6f4 | 429 | { |
89184651 TR |
430 | if (--as->use_count > 0) |
431 | return; | |
432 | ||
433 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
434 | |
435 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
436 | ||
89184651 | 437 | as->smmu = NULL; |
7a31f6f4 HD |
438 | } |
439 | ||
89184651 TR |
440 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
441 | struct device *dev) | |
7a31f6f4 | 442 | { |
89184651 | 443 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 444 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
445 | struct device_node *np = dev->of_node; |
446 | struct of_phandle_args args; | |
447 | unsigned int index = 0; | |
448 | int err = 0; | |
7a31f6f4 | 449 | |
89184651 TR |
450 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
451 | &args)) { | |
452 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 453 | |
89184651 TR |
454 | if (args.np != smmu->dev->of_node) { |
455 | of_node_put(args.np); | |
d2453b2c | 456 | continue; |
89184651 | 457 | } |
d2453b2c | 458 | |
89184651 | 459 | of_node_put(args.np); |
d2453b2c | 460 | |
89184651 TR |
461 | err = tegra_smmu_as_prepare(smmu, as); |
462 | if (err < 0) | |
463 | return err; | |
464 | ||
465 | tegra_smmu_enable(smmu, swgroup, as->id); | |
466 | index++; | |
7a31f6f4 | 467 | } |
7a31f6f4 | 468 | |
89184651 TR |
469 | if (index == 0) |
470 | return -ENODEV; | |
7a31f6f4 | 471 | |
89184651 TR |
472 | return 0; |
473 | } | |
7a31f6f4 | 474 | |
89184651 TR |
475 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
476 | { | |
d5f1a81c | 477 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
478 | struct device_node *np = dev->of_node; |
479 | struct tegra_smmu *smmu = as->smmu; | |
480 | struct of_phandle_args args; | |
481 | unsigned int index = 0; | |
7a31f6f4 | 482 | |
89184651 TR |
483 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
484 | &args)) { | |
485 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 486 | |
89184651 TR |
487 | if (args.np != smmu->dev->of_node) { |
488 | of_node_put(args.np); | |
489 | continue; | |
490 | } | |
23349902 | 491 | |
89184651 | 492 | of_node_put(args.np); |
7a31f6f4 | 493 | |
89184651 TR |
494 | tegra_smmu_disable(smmu, swgroup, as->id); |
495 | tegra_smmu_as_unprepare(smmu, as); | |
496 | index++; | |
497 | } | |
7a31f6f4 HD |
498 | } |
499 | ||
4080e99b RK |
500 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
501 | u32 value) | |
502 | { | |
503 | unsigned int pd_index = iova_pd_index(iova); | |
504 | struct tegra_smmu *smmu = as->smmu; | |
505 | u32 *pd = page_address(as->pd); | |
506 | unsigned long offset = pd_index * sizeof(*pd); | |
507 | ||
508 | /* Set the page directory entry first */ | |
509 | pd[pd_index] = value; | |
510 | ||
511 | /* The flush the page directory entry from caches */ | |
512 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
513 | sizeof(*pd), DMA_TO_DEVICE); | |
514 | ||
515 | /* And flush the iommu */ | |
516 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
517 | smmu_flush_tlb_section(smmu, as->id, iova); | |
518 | smmu_flush(smmu); | |
519 | } | |
520 | ||
0b42c7c1 RK |
521 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
522 | { | |
523 | u32 *pt = page_address(pt_page); | |
524 | ||
525 | return pt + iova_pt_index(iova); | |
526 | } | |
527 | ||
528 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 529 | dma_addr_t *dmap) |
0b42c7c1 RK |
530 | { |
531 | unsigned int pd_index = iova_pd_index(iova); | |
532 | struct page *pt_page; | |
e3c97196 | 533 | u32 *pd; |
0b42c7c1 | 534 | |
853520fa RK |
535 | pt_page = as->pts[pd_index]; |
536 | if (!pt_page) | |
0b42c7c1 RK |
537 | return NULL; |
538 | ||
e3c97196 RK |
539 | pd = page_address(as->pd); |
540 | *dmap = smmu_pde_to_dma(pd[pd_index]); | |
0b42c7c1 RK |
541 | |
542 | return tegra_smmu_pte_offset(pt_page, iova); | |
543 | } | |
544 | ||
89184651 | 545 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
e3c97196 | 546 | dma_addr_t *dmap) |
7a31f6f4 | 547 | { |
34d35f8c | 548 | unsigned int pde = iova_pd_index(iova); |
89184651 | 549 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 550 | |
853520fa | 551 | if (!as->pts[pde]) { |
e3c97196 RK |
552 | struct page *page; |
553 | dma_addr_t dma; | |
554 | ||
707917cb | 555 | page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
556 | if (!page) |
557 | return NULL; | |
7a31f6f4 | 558 | |
e3c97196 RK |
559 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
560 | DMA_TO_DEVICE); | |
561 | if (dma_mapping_error(smmu->dev, dma)) { | |
562 | __free_page(page); | |
563 | return NULL; | |
564 | } | |
565 | ||
566 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
567 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
568 | DMA_TO_DEVICE); | |
569 | __free_page(page); | |
570 | return NULL; | |
571 | } | |
572 | ||
853520fa RK |
573 | as->pts[pde] = page; |
574 | ||
4080e99b RK |
575 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
576 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
577 | |
578 | *dmap = dma; | |
89184651 | 579 | } else { |
4080e99b RK |
580 | u32 *pd = page_address(as->pd); |
581 | ||
e3c97196 | 582 | *dmap = smmu_pde_to_dma(pd[pde]); |
7a31f6f4 HD |
583 | } |
584 | ||
7ffc6f06 RK |
585 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
586 | } | |
0b42c7c1 | 587 | |
7ffc6f06 RK |
588 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
589 | { | |
590 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 591 | |
7ffc6f06 | 592 | as->count[pd_index]++; |
89184651 | 593 | } |
39abf8aa | 594 | |
b98e34f0 | 595 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 596 | { |
34d35f8c | 597 | unsigned int pde = iova_pd_index(iova); |
853520fa | 598 | struct page *page = as->pts[pde]; |
39abf8aa | 599 | |
89184651 TR |
600 | /* |
601 | * When no entries in this page table are used anymore, return the | |
602 | * memory page to the system. | |
603 | */ | |
32924c76 | 604 | if (--as->count[pde] == 0) { |
4080e99b RK |
605 | struct tegra_smmu *smmu = as->smmu; |
606 | u32 *pd = page_address(as->pd); | |
e3c97196 | 607 | dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]); |
39abf8aa | 608 | |
4080e99b | 609 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 610 | |
e3c97196 | 611 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 612 | __free_page(page); |
853520fa | 613 | as->pts[pde] = NULL; |
39abf8aa | 614 | } |
39abf8aa HD |
615 | } |
616 | ||
8482ee5e | 617 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 618 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
619 | { |
620 | struct tegra_smmu *smmu = as->smmu; | |
621 | unsigned long offset = offset_in_page(pte); | |
622 | ||
623 | *pte = val; | |
624 | ||
e3c97196 RK |
625 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
626 | 4, DMA_TO_DEVICE); | |
627 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
628 | smmu_flush_tlb_group(smmu, as->id, iova); |
629 | smmu_flush(smmu); | |
630 | } | |
631 | ||
89184651 TR |
632 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
633 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 634 | { |
d5f1a81c | 635 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 636 | dma_addr_t pte_dma; |
89184651 | 637 | u32 *pte; |
39abf8aa | 638 | |
e3c97196 | 639 | pte = as_get_pte(as, iova, &pte_dma); |
89184651 TR |
640 | if (!pte) |
641 | return -ENOMEM; | |
39abf8aa | 642 | |
7ffc6f06 RK |
643 | /* If we aren't overwriting a pre-existing entry, increment use */ |
644 | if (*pte == 0) | |
645 | tegra_smmu_pte_get_use(as, iova); | |
646 | ||
e3c97196 | 647 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
8482ee5e | 648 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); |
39abf8aa | 649 | |
39abf8aa HD |
650 | return 0; |
651 | } | |
652 | ||
89184651 TR |
653 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
654 | size_t size) | |
39abf8aa | 655 | { |
d5f1a81c | 656 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 657 | dma_addr_t pte_dma; |
89184651 | 658 | u32 *pte; |
39abf8aa | 659 | |
e3c97196 | 660 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 661 | if (!pte || !*pte) |
89184651 | 662 | return 0; |
39abf8aa | 663 | |
e3c97196 | 664 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
665 | tegra_smmu_pte_put_use(as, iova); |
666 | ||
89184651 | 667 | return size; |
39abf8aa HD |
668 | } |
669 | ||
89184651 TR |
670 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
671 | dma_addr_t iova) | |
39abf8aa | 672 | { |
d5f1a81c | 673 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 674 | unsigned long pfn; |
e3c97196 | 675 | dma_addr_t pte_dma; |
89184651 | 676 | u32 *pte; |
39abf8aa | 677 | |
e3c97196 | 678 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
679 | if (!pte || !*pte) |
680 | return 0; | |
681 | ||
804cb54c | 682 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 683 | |
89184651 | 684 | return PFN_PHYS(pfn); |
39abf8aa HD |
685 | } |
686 | ||
89184651 | 687 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 688 | { |
89184651 TR |
689 | struct platform_device *pdev; |
690 | struct tegra_mc *mc; | |
7a31f6f4 | 691 | |
89184651 TR |
692 | pdev = of_find_device_by_node(np); |
693 | if (!pdev) | |
694 | return NULL; | |
695 | ||
696 | mc = platform_get_drvdata(pdev); | |
697 | if (!mc) | |
698 | return NULL; | |
699 | ||
700 | return mc->smmu; | |
7a31f6f4 HD |
701 | } |
702 | ||
89184651 | 703 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 704 | { |
89184651 TR |
705 | struct device_node *np = dev->of_node; |
706 | struct of_phandle_args args; | |
707 | unsigned int index = 0; | |
7a31f6f4 | 708 | |
89184651 TR |
709 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
710 | &args) == 0) { | |
711 | struct tegra_smmu *smmu; | |
712 | ||
713 | smmu = tegra_smmu_find(args.np); | |
714 | if (smmu) { | |
715 | /* | |
716 | * Only a single IOMMU master interface is currently | |
717 | * supported by the Linux kernel, so abort after the | |
718 | * first match. | |
719 | */ | |
720 | dev->archdata.iommu = smmu; | |
721 | break; | |
722 | } | |
723 | ||
724 | index++; | |
725 | } | |
726 | ||
727 | return 0; | |
7a31f6f4 HD |
728 | } |
729 | ||
89184651 | 730 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 731 | { |
89184651 TR |
732 | dev->archdata.iommu = NULL; |
733 | } | |
7a31f6f4 | 734 | |
89184651 TR |
735 | static const struct iommu_ops tegra_smmu_ops = { |
736 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
737 | .domain_alloc = tegra_smmu_domain_alloc, |
738 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
739 | .attach_dev = tegra_smmu_attach_dev, |
740 | .detach_dev = tegra_smmu_detach_dev, | |
741 | .add_device = tegra_smmu_add_device, | |
742 | .remove_device = tegra_smmu_remove_device, | |
743 | .map = tegra_smmu_map, | |
744 | .unmap = tegra_smmu_unmap, | |
745 | .map_sg = default_iommu_map_sg, | |
746 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 747 | |
89184651 TR |
748 | .pgsize_bitmap = SZ_4K, |
749 | }; | |
7a31f6f4 | 750 | |
89184651 TR |
751 | static void tegra_smmu_ahb_enable(void) |
752 | { | |
753 | static const struct of_device_id ahb_match[] = { | |
754 | { .compatible = "nvidia,tegra30-ahb", }, | |
755 | { } | |
756 | }; | |
757 | struct device_node *ahb; | |
7a31f6f4 | 758 | |
89184651 TR |
759 | ahb = of_find_matching_node(NULL, ahb_match); |
760 | if (ahb) { | |
761 | tegra_ahb_enable_smmu(ahb); | |
762 | of_node_put(ahb); | |
7a31f6f4 | 763 | } |
89184651 | 764 | } |
7a31f6f4 | 765 | |
d1313e78 TR |
766 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
767 | { | |
768 | struct tegra_smmu *smmu = s->private; | |
769 | unsigned int i; | |
770 | u32 value; | |
771 | ||
772 | seq_printf(s, "swgroup enabled ASID\n"); | |
773 | seq_printf(s, "------------------------\n"); | |
774 | ||
775 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
776 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
777 | const char *status; | |
778 | unsigned int asid; | |
779 | ||
780 | value = smmu_readl(smmu, group->reg); | |
781 | ||
782 | if (value & SMMU_ASID_ENABLE) | |
783 | status = "yes"; | |
784 | else | |
785 | status = "no"; | |
786 | ||
787 | asid = value & SMMU_ASID_MASK; | |
788 | ||
789 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
790 | asid); | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) | |
797 | { | |
798 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); | |
799 | } | |
800 | ||
801 | static const struct file_operations tegra_smmu_swgroups_fops = { | |
802 | .open = tegra_smmu_swgroups_open, | |
803 | .read = seq_read, | |
804 | .llseek = seq_lseek, | |
805 | .release = single_release, | |
806 | }; | |
807 | ||
808 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
809 | { | |
810 | struct tegra_smmu *smmu = s->private; | |
811 | unsigned int i; | |
812 | u32 value; | |
813 | ||
814 | seq_printf(s, "client enabled\n"); | |
815 | seq_printf(s, "--------------------\n"); | |
816 | ||
817 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
818 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
819 | const char *status; | |
820 | ||
821 | value = smmu_readl(smmu, client->smmu.reg); | |
822 | ||
823 | if (value & BIT(client->smmu.bit)) | |
824 | status = "yes"; | |
825 | else | |
826 | status = "no"; | |
827 | ||
828 | seq_printf(s, "%-12s %s\n", client->name, status); | |
829 | } | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) | |
835 | { | |
836 | return single_open(file, tegra_smmu_clients_show, inode->i_private); | |
837 | } | |
838 | ||
839 | static const struct file_operations tegra_smmu_clients_fops = { | |
840 | .open = tegra_smmu_clients_open, | |
841 | .read = seq_read, | |
842 | .llseek = seq_lseek, | |
843 | .release = single_release, | |
844 | }; | |
845 | ||
846 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
847 | { | |
848 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
849 | if (!smmu->debugfs) | |
850 | return; | |
851 | ||
852 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
853 | &tegra_smmu_swgroups_fops); | |
854 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
855 | &tegra_smmu_clients_fops); | |
856 | } | |
857 | ||
858 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
859 | { | |
860 | debugfs_remove_recursive(smmu->debugfs); | |
861 | } | |
862 | ||
89184651 TR |
863 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
864 | const struct tegra_smmu_soc *soc, | |
865 | struct tegra_mc *mc) | |
866 | { | |
867 | struct tegra_smmu *smmu; | |
868 | size_t size; | |
869 | u32 value; | |
870 | int err; | |
7a31f6f4 | 871 | |
89184651 TR |
872 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
873 | if (!soc) | |
874 | return NULL; | |
0760e8fa | 875 | |
89184651 TR |
876 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
877 | if (!smmu) | |
878 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 879 | |
89184651 TR |
880 | /* |
881 | * This is a bit of a hack. Ideally we'd want to simply return this | |
882 | * value. However the IOMMU registration process will attempt to add | |
883 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
884 | * not to rely on global variables to track the IOMMU instance, we | |
885 | * set it here so that it can be looked up from the .add_device() | |
886 | * callback via the IOMMU device's .drvdata field. | |
887 | */ | |
888 | mc->smmu = smmu; | |
0760e8fa | 889 | |
89184651 | 890 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 891 | |
89184651 TR |
892 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
893 | if (!smmu->asids) | |
894 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 895 | |
89184651 | 896 | mutex_init(&smmu->lock); |
7a31f6f4 | 897 | |
89184651 TR |
898 | smmu->regs = mc->regs; |
899 | smmu->soc = soc; | |
900 | smmu->dev = dev; | |
901 | smmu->mc = mc; | |
7a31f6f4 | 902 | |
804cb54c TR |
903 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
904 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
905 | mc->soc->num_address_bits, smmu->pfn_mask); | |
11cec15b TR |
906 | smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1; |
907 | dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, | |
908 | smmu->tlb_mask); | |
804cb54c | 909 | |
89184651 | 910 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 911 | |
89184651 TR |
912 | if (soc->supports_request_limit) |
913 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 914 | |
89184651 | 915 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 916 | |
89184651 | 917 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
11cec15b | 918 | SMMU_TLB_CONFIG_ACTIVE_LINES(smmu); |
7a31f6f4 | 919 | |
89184651 TR |
920 | if (soc->supports_round_robin_arbitration) |
921 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 922 | |
89184651 | 923 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 924 | |
b8fe0382 | 925 | smmu_flush_ptc_all(smmu); |
89184651 TR |
926 | smmu_flush_tlb(smmu); |
927 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
928 | smmu_flush(smmu); | |
929 | ||
930 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 931 | |
89184651 TR |
932 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
933 | if (err < 0) | |
934 | return ERR_PTR(err); | |
7a31f6f4 | 935 | |
d1313e78 TR |
936 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
937 | tegra_smmu_debugfs_init(smmu); | |
938 | ||
89184651 TR |
939 | return smmu; |
940 | } | |
d1313e78 TR |
941 | |
942 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
943 | { | |
944 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
945 | tegra_smmu_debugfs_exit(smmu); | |
946 | } |