Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
d1313e78 | 10 | #include <linux/debugfs.h> |
bc5e6dea | 11 | #include <linux/err.h> |
7a31f6f4 | 12 | #include <linux/iommu.h> |
89184651 | 13 | #include <linux/kernel.h> |
0760e8fa | 14 | #include <linux/of.h> |
89184651 TR |
15 | #include <linux/of_device.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
89184651 TR |
22 | struct tegra_smmu { |
23 | void __iomem *regs; | |
24 | struct device *dev; | |
e6bc5933 | 25 | |
89184651 TR |
26 | struct tegra_mc *mc; |
27 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 28 | |
804cb54c TR |
29 | unsigned long pfn_mask; |
30 | ||
89184651 TR |
31 | unsigned long *asids; |
32 | struct mutex lock; | |
39abf8aa | 33 | |
89184651 | 34 | struct list_head list; |
d1313e78 TR |
35 | |
36 | struct dentry *debugfs; | |
7a31f6f4 | 37 | }; |
7a31f6f4 | 38 | |
89184651 | 39 | struct tegra_smmu_as { |
d5f1a81c | 40 | struct iommu_domain domain; |
89184651 TR |
41 | struct tegra_smmu *smmu; |
42 | unsigned int use_count; | |
43 | struct page *count; | |
44 | struct page *pd; | |
45 | unsigned id; | |
46 | u32 attr; | |
7a31f6f4 HD |
47 | }; |
48 | ||
d5f1a81c JR |
49 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
50 | { | |
51 | return container_of(dom, struct tegra_smmu_as, domain); | |
52 | } | |
53 | ||
89184651 TR |
54 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
55 | unsigned long offset) | |
56 | { | |
57 | writel(value, smmu->regs + offset); | |
58 | } | |
7a31f6f4 | 59 | |
89184651 TR |
60 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
61 | { | |
62 | return readl(smmu->regs + offset); | |
63 | } | |
5a2c937a | 64 | |
89184651 TR |
65 | #define SMMU_CONFIG 0x010 |
66 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 67 | |
89184651 TR |
68 | #define SMMU_TLB_CONFIG 0x14 |
69 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
70 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
71 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) | |
0760e8fa | 72 | |
89184651 TR |
73 | #define SMMU_PTC_CONFIG 0x18 |
74 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
75 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
76 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 77 | |
89184651 TR |
78 | #define SMMU_PTB_ASID 0x01c |
79 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 80 | |
89184651 TR |
81 | #define SMMU_PTB_DATA 0x020 |
82 | #define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr)) | |
7a31f6f4 | 83 | |
89184651 | 84 | #define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 85 | |
89184651 TR |
86 | #define SMMU_TLB_FLUSH 0x030 |
87 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
88 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
89 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
90 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
91 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
92 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
93 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
94 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
95 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 96 | |
89184651 TR |
97 | #define SMMU_PTC_FLUSH 0x034 |
98 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
99 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 100 | |
89184651 TR |
101 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
102 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 103 | |
89184651 TR |
104 | /* per-SWGROUP SMMU_*_ASID register */ |
105 | #define SMMU_ASID_ENABLE (1 << 31) | |
106 | #define SMMU_ASID_MASK 0x7f | |
107 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 108 | |
89184651 TR |
109 | /* page table definitions */ |
110 | #define SMMU_NUM_PDE 1024 | |
111 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 112 | |
89184651 TR |
113 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
114 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 115 | |
89184651 TR |
116 | #define SMMU_PDE_SHIFT 22 |
117 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 118 | |
89184651 TR |
119 | #define SMMU_PD_READABLE (1 << 31) |
120 | #define SMMU_PD_WRITABLE (1 << 30) | |
121 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 122 | |
89184651 TR |
123 | #define SMMU_PDE_READABLE (1 << 31) |
124 | #define SMMU_PDE_WRITABLE (1 << 30) | |
125 | #define SMMU_PDE_NONSECURE (1 << 29) | |
126 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 127 | |
89184651 TR |
128 | #define SMMU_PTE_READABLE (1 << 31) |
129 | #define SMMU_PTE_WRITABLE (1 << 30) | |
130 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 131 | |
89184651 TR |
132 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
133 | SMMU_PDE_NONSECURE) | |
134 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
135 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 136 | |
89184651 TR |
137 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, |
138 | unsigned long offset) | |
7a31f6f4 | 139 | { |
89184651 TR |
140 | phys_addr_t phys = page ? page_to_phys(page) : 0; |
141 | u32 value; | |
142 | ||
143 | if (page) { | |
144 | offset &= ~(smmu->mc->soc->atom_size - 1); | |
145 | ||
146 | if (smmu->mc->soc->num_address_bits > 32) { | |
147 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
148 | value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
149 | #else | |
150 | value = 0; | |
151 | #endif | |
152 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); | |
7a31f6f4 | 153 | } |
7a31f6f4 | 154 | |
89184651 TR |
155 | value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
156 | } else { | |
157 | value = SMMU_PTC_FLUSH_TYPE_ALL; | |
7a31f6f4 | 158 | } |
89184651 TR |
159 | |
160 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); | |
7a31f6f4 HD |
161 | } |
162 | ||
89184651 | 163 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 164 | { |
89184651 | 165 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
166 | } |
167 | ||
89184651 TR |
168 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
169 | unsigned long asid) | |
7a31f6f4 | 170 | { |
89184651 | 171 | u32 value; |
7a31f6f4 | 172 | |
89184651 TR |
173 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
174 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
175 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
176 | } |
177 | ||
89184651 TR |
178 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
179 | unsigned long asid, | |
180 | unsigned long iova) | |
7a31f6f4 | 181 | { |
89184651 | 182 | u32 value; |
7a31f6f4 | 183 | |
89184651 TR |
184 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
185 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
186 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
187 | } |
188 | ||
89184651 TR |
189 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
190 | unsigned long asid, | |
191 | unsigned long iova) | |
7a31f6f4 | 192 | { |
89184651 | 193 | u32 value; |
7a31f6f4 | 194 | |
89184651 TR |
195 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
196 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
197 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
198 | } |
199 | ||
89184651 | 200 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 201 | { |
89184651 | 202 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
203 | } |
204 | ||
89184651 | 205 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 206 | { |
89184651 | 207 | unsigned long id; |
7a31f6f4 | 208 | |
89184651 | 209 | mutex_lock(&smmu->lock); |
7a31f6f4 | 210 | |
89184651 TR |
211 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
212 | if (id >= smmu->soc->num_asids) { | |
213 | mutex_unlock(&smmu->lock); | |
214 | return -ENOSPC; | |
7a31f6f4 | 215 | } |
7a31f6f4 | 216 | |
89184651 TR |
217 | set_bit(id, smmu->asids); |
218 | *idp = id; | |
219 | ||
220 | mutex_unlock(&smmu->lock); | |
221 | return 0; | |
7a31f6f4 HD |
222 | } |
223 | ||
89184651 | 224 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 225 | { |
89184651 TR |
226 | mutex_lock(&smmu->lock); |
227 | clear_bit(id, smmu->asids); | |
228 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 229 | } |
89184651 TR |
230 | |
231 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 232 | { |
89184651 | 233 | return false; |
7a31f6f4 | 234 | } |
7a31f6f4 | 235 | |
d5f1a81c | 236 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 237 | { |
89184651 TR |
238 | struct tegra_smmu_as *as; |
239 | unsigned int i; | |
240 | uint32_t *pd; | |
7a31f6f4 | 241 | |
d5f1a81c JR |
242 | if (type != IOMMU_DOMAIN_UNMANAGED) |
243 | return NULL; | |
244 | ||
89184651 TR |
245 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
246 | if (!as) | |
d5f1a81c | 247 | return NULL; |
7a31f6f4 | 248 | |
89184651 | 249 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 250 | |
89184651 TR |
251 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
252 | if (!as->pd) { | |
253 | kfree(as); | |
d5f1a81c | 254 | return NULL; |
7a31f6f4 | 255 | } |
9e971a03 | 256 | |
89184651 TR |
257 | as->count = alloc_page(GFP_KERNEL); |
258 | if (!as->count) { | |
259 | __free_page(as->pd); | |
260 | kfree(as); | |
d5f1a81c | 261 | return NULL; |
7a31f6f4 | 262 | } |
9e971a03 | 263 | |
89184651 TR |
264 | /* clear PDEs */ |
265 | pd = page_address(as->pd); | |
266 | SetPageReserved(as->pd); | |
9e971a03 | 267 | |
89184651 TR |
268 | for (i = 0; i < SMMU_NUM_PDE; i++) |
269 | pd[i] = 0; | |
7a31f6f4 | 270 | |
89184651 TR |
271 | /* clear PDE usage counters */ |
272 | pd = page_address(as->count); | |
273 | SetPageReserved(as->count); | |
7a31f6f4 | 274 | |
89184651 TR |
275 | for (i = 0; i < SMMU_NUM_PDE; i++) |
276 | pd[i] = 0; | |
9e971a03 | 277 | |
471d9144 | 278 | /* setup aperture */ |
7f65ef01 JR |
279 | as->domain.geometry.aperture_start = 0; |
280 | as->domain.geometry.aperture_end = 0xffffffff; | |
281 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 282 | |
d5f1a81c | 283 | return &as->domain; |
7a31f6f4 HD |
284 | } |
285 | ||
d5f1a81c | 286 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 287 | { |
d5f1a81c | 288 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 289 | |
89184651 TR |
290 | /* TODO: free page directory and page tables */ |
291 | ClearPageReserved(as->pd); | |
7a31f6f4 | 292 | |
89184651 | 293 | kfree(as); |
7a31f6f4 HD |
294 | } |
295 | ||
89184651 TR |
296 | static const struct tegra_smmu_swgroup * |
297 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 298 | { |
89184651 TR |
299 | const struct tegra_smmu_swgroup *group = NULL; |
300 | unsigned int i; | |
7a31f6f4 | 301 | |
89184651 TR |
302 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
303 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
304 | group = &smmu->soc->swgroups[i]; | |
305 | break; | |
306 | } | |
307 | } | |
7a31f6f4 | 308 | |
89184651 | 309 | return group; |
7a31f6f4 HD |
310 | } |
311 | ||
89184651 TR |
312 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
313 | unsigned int asid) | |
7a31f6f4 | 314 | { |
89184651 TR |
315 | const struct tegra_smmu_swgroup *group; |
316 | unsigned int i; | |
317 | u32 value; | |
7a31f6f4 | 318 | |
89184651 TR |
319 | for (i = 0; i < smmu->soc->num_clients; i++) { |
320 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 321 | |
89184651 TR |
322 | if (client->swgroup != swgroup) |
323 | continue; | |
7a31f6f4 | 324 | |
89184651 TR |
325 | value = smmu_readl(smmu, client->smmu.reg); |
326 | value |= BIT(client->smmu.bit); | |
327 | smmu_writel(smmu, value, client->smmu.reg); | |
328 | } | |
7a31f6f4 | 329 | |
89184651 TR |
330 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
331 | if (group) { | |
332 | value = smmu_readl(smmu, group->reg); | |
333 | value &= ~SMMU_ASID_MASK; | |
334 | value |= SMMU_ASID_VALUE(asid); | |
335 | value |= SMMU_ASID_ENABLE; | |
336 | smmu_writel(smmu, value, group->reg); | |
337 | } | |
7a31f6f4 HD |
338 | } |
339 | ||
89184651 TR |
340 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
341 | unsigned int asid) | |
7a31f6f4 | 342 | { |
89184651 TR |
343 | const struct tegra_smmu_swgroup *group; |
344 | unsigned int i; | |
345 | u32 value; | |
7a31f6f4 | 346 | |
89184651 TR |
347 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
348 | if (group) { | |
349 | value = smmu_readl(smmu, group->reg); | |
350 | value &= ~SMMU_ASID_MASK; | |
351 | value |= SMMU_ASID_VALUE(asid); | |
352 | value &= ~SMMU_ASID_ENABLE; | |
353 | smmu_writel(smmu, value, group->reg); | |
354 | } | |
7a31f6f4 | 355 | |
89184651 TR |
356 | for (i = 0; i < smmu->soc->num_clients; i++) { |
357 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 358 | |
89184651 TR |
359 | if (client->swgroup != swgroup) |
360 | continue; | |
7a31f6f4 | 361 | |
89184651 TR |
362 | value = smmu_readl(smmu, client->smmu.reg); |
363 | value &= ~BIT(client->smmu.bit); | |
364 | smmu_writel(smmu, value, client->smmu.reg); | |
365 | } | |
7a31f6f4 HD |
366 | } |
367 | ||
89184651 TR |
368 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
369 | struct tegra_smmu_as *as) | |
7a31f6f4 | 370 | { |
89184651 | 371 | u32 value; |
7a31f6f4 HD |
372 | int err; |
373 | ||
89184651 TR |
374 | if (as->use_count > 0) { |
375 | as->use_count++; | |
376 | return 0; | |
7a31f6f4 | 377 | } |
7a31f6f4 | 378 | |
89184651 TR |
379 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
380 | if (err < 0) | |
381 | return err; | |
7a31f6f4 | 382 | |
89184651 TR |
383 | smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD); |
384 | smmu_flush_ptc(smmu, as->pd, 0); | |
385 | smmu_flush_tlb_asid(smmu, as->id); | |
7a31f6f4 | 386 | |
89184651 TR |
387 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
388 | value = SMMU_PTB_DATA_VALUE(as->pd, as->attr); | |
389 | smmu_writel(smmu, value, SMMU_PTB_DATA); | |
390 | smmu_flush(smmu); | |
7a31f6f4 | 391 | |
89184651 TR |
392 | as->smmu = smmu; |
393 | as->use_count++; | |
7a31f6f4 | 394 | |
89184651 | 395 | return 0; |
7a31f6f4 HD |
396 | } |
397 | ||
89184651 TR |
398 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
399 | struct tegra_smmu_as *as) | |
7a31f6f4 | 400 | { |
89184651 TR |
401 | if (--as->use_count > 0) |
402 | return; | |
403 | ||
404 | tegra_smmu_free_asid(smmu, as->id); | |
405 | as->smmu = NULL; | |
7a31f6f4 HD |
406 | } |
407 | ||
89184651 TR |
408 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
409 | struct device *dev) | |
7a31f6f4 | 410 | { |
89184651 | 411 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 412 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
413 | struct device_node *np = dev->of_node; |
414 | struct of_phandle_args args; | |
415 | unsigned int index = 0; | |
416 | int err = 0; | |
7a31f6f4 | 417 | |
89184651 TR |
418 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
419 | &args)) { | |
420 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 421 | |
89184651 TR |
422 | if (args.np != smmu->dev->of_node) { |
423 | of_node_put(args.np); | |
d2453b2c | 424 | continue; |
89184651 | 425 | } |
d2453b2c | 426 | |
89184651 | 427 | of_node_put(args.np); |
d2453b2c | 428 | |
89184651 TR |
429 | err = tegra_smmu_as_prepare(smmu, as); |
430 | if (err < 0) | |
431 | return err; | |
432 | ||
433 | tegra_smmu_enable(smmu, swgroup, as->id); | |
434 | index++; | |
7a31f6f4 | 435 | } |
7a31f6f4 | 436 | |
89184651 TR |
437 | if (index == 0) |
438 | return -ENODEV; | |
7a31f6f4 | 439 | |
89184651 TR |
440 | return 0; |
441 | } | |
7a31f6f4 | 442 | |
89184651 TR |
443 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
444 | { | |
d5f1a81c | 445 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
446 | struct device_node *np = dev->of_node; |
447 | struct tegra_smmu *smmu = as->smmu; | |
448 | struct of_phandle_args args; | |
449 | unsigned int index = 0; | |
7a31f6f4 | 450 | |
89184651 TR |
451 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
452 | &args)) { | |
453 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 454 | |
89184651 TR |
455 | if (args.np != smmu->dev->of_node) { |
456 | of_node_put(args.np); | |
457 | continue; | |
458 | } | |
23349902 | 459 | |
89184651 | 460 | of_node_put(args.np); |
7a31f6f4 | 461 | |
89184651 TR |
462 | tegra_smmu_disable(smmu, swgroup, as->id); |
463 | tegra_smmu_as_unprepare(smmu, as); | |
464 | index++; | |
465 | } | |
7a31f6f4 HD |
466 | } |
467 | ||
89184651 TR |
468 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
469 | struct page **pagep) | |
7a31f6f4 | 470 | { |
89184651 TR |
471 | u32 *pd = page_address(as->pd), *pt, *count; |
472 | u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff; | |
473 | u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff; | |
474 | struct tegra_smmu *smmu = as->smmu; | |
475 | struct page *page; | |
476 | unsigned int i; | |
477 | ||
478 | if (pd[pde] == 0) { | |
479 | page = alloc_page(GFP_KERNEL | __GFP_DMA); | |
480 | if (!page) | |
481 | return NULL; | |
7a31f6f4 | 482 | |
89184651 TR |
483 | pt = page_address(page); |
484 | SetPageReserved(page); | |
7a31f6f4 | 485 | |
89184651 TR |
486 | for (i = 0; i < SMMU_NUM_PTE; i++) |
487 | pt[i] = 0; | |
7a31f6f4 | 488 | |
89184651 | 489 | smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT); |
7a31f6f4 | 490 | |
89184651 | 491 | pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
7a31f6f4 | 492 | |
89184651 TR |
493 | smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4); |
494 | smmu_flush_ptc(smmu, as->pd, pde << 2); | |
495 | smmu_flush_tlb_section(smmu, as->id, iova); | |
496 | smmu_flush(smmu); | |
497 | } else { | |
804cb54c | 498 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
89184651 | 499 | pt = page_address(page); |
7a31f6f4 HD |
500 | } |
501 | ||
89184651 | 502 | *pagep = page; |
7a31f6f4 | 503 | |
89184651 TR |
504 | /* Keep track of entries in this page table. */ |
505 | count = page_address(as->count); | |
506 | if (pt[pte] == 0) | |
507 | count[pde]++; | |
7a31f6f4 | 508 | |
89184651 TR |
509 | return &pt[pte]; |
510 | } | |
39abf8aa | 511 | |
89184651 | 512 | static void as_put_pte(struct tegra_smmu_as *as, dma_addr_t iova) |
39abf8aa | 513 | { |
89184651 TR |
514 | u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff; |
515 | u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff; | |
516 | u32 *count = page_address(as->count); | |
517 | u32 *pd = page_address(as->pd), *pt; | |
518 | struct page *page; | |
39abf8aa | 519 | |
804cb54c | 520 | page = pfn_to_page(pd[pde] & as->smmu->pfn_mask); |
89184651 | 521 | pt = page_address(page); |
39abf8aa | 522 | |
89184651 TR |
523 | /* |
524 | * When no entries in this page table are used anymore, return the | |
525 | * memory page to the system. | |
526 | */ | |
527 | if (pt[pte] != 0) { | |
528 | if (--count[pde] == 0) { | |
529 | ClearPageReserved(page); | |
530 | __free_page(page); | |
531 | pd[pde] = 0; | |
532 | } | |
39abf8aa | 533 | |
89184651 | 534 | pt[pte] = 0; |
39abf8aa | 535 | } |
39abf8aa HD |
536 | } |
537 | ||
89184651 TR |
538 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
539 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 540 | { |
d5f1a81c | 541 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
542 | struct tegra_smmu *smmu = as->smmu; |
543 | unsigned long offset; | |
544 | struct page *page; | |
545 | u32 *pte; | |
39abf8aa | 546 | |
89184651 TR |
547 | pte = as_get_pte(as, iova, &page); |
548 | if (!pte) | |
549 | return -ENOMEM; | |
39abf8aa | 550 | |
89184651 TR |
551 | *pte = __phys_to_pfn(paddr) | SMMU_PTE_ATTR; |
552 | offset = offset_in_page(pte); | |
39abf8aa | 553 | |
89184651 TR |
554 | smmu->soc->ops->flush_dcache(page, offset, 4); |
555 | smmu_flush_ptc(smmu, page, offset); | |
556 | smmu_flush_tlb_group(smmu, as->id, iova); | |
557 | smmu_flush(smmu); | |
39abf8aa | 558 | |
39abf8aa HD |
559 | return 0; |
560 | } | |
561 | ||
89184651 TR |
562 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
563 | size_t size) | |
39abf8aa | 564 | { |
d5f1a81c | 565 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
566 | struct tegra_smmu *smmu = as->smmu; |
567 | unsigned long offset; | |
568 | struct page *page; | |
569 | u32 *pte; | |
39abf8aa | 570 | |
89184651 TR |
571 | pte = as_get_pte(as, iova, &page); |
572 | if (!pte) | |
573 | return 0; | |
39abf8aa | 574 | |
89184651 TR |
575 | offset = offset_in_page(pte); |
576 | as_put_pte(as, iova); | |
577 | ||
578 | smmu->soc->ops->flush_dcache(page, offset, 4); | |
579 | smmu_flush_ptc(smmu, page, offset); | |
580 | smmu_flush_tlb_group(smmu, as->id, iova); | |
581 | smmu_flush(smmu); | |
582 | ||
583 | return size; | |
39abf8aa HD |
584 | } |
585 | ||
89184651 TR |
586 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
587 | dma_addr_t iova) | |
39abf8aa | 588 | { |
d5f1a81c | 589 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
590 | struct page *page; |
591 | unsigned long pfn; | |
592 | u32 *pte; | |
39abf8aa | 593 | |
89184651 | 594 | pte = as_get_pte(as, iova, &page); |
804cb54c | 595 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 596 | |
89184651 | 597 | return PFN_PHYS(pfn); |
39abf8aa HD |
598 | } |
599 | ||
89184651 | 600 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 601 | { |
89184651 TR |
602 | struct platform_device *pdev; |
603 | struct tegra_mc *mc; | |
7a31f6f4 | 604 | |
89184651 TR |
605 | pdev = of_find_device_by_node(np); |
606 | if (!pdev) | |
607 | return NULL; | |
608 | ||
609 | mc = platform_get_drvdata(pdev); | |
610 | if (!mc) | |
611 | return NULL; | |
612 | ||
613 | return mc->smmu; | |
7a31f6f4 HD |
614 | } |
615 | ||
89184651 | 616 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 617 | { |
89184651 TR |
618 | struct device_node *np = dev->of_node; |
619 | struct of_phandle_args args; | |
620 | unsigned int index = 0; | |
7a31f6f4 | 621 | |
89184651 TR |
622 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
623 | &args) == 0) { | |
624 | struct tegra_smmu *smmu; | |
625 | ||
626 | smmu = tegra_smmu_find(args.np); | |
627 | if (smmu) { | |
628 | /* | |
629 | * Only a single IOMMU master interface is currently | |
630 | * supported by the Linux kernel, so abort after the | |
631 | * first match. | |
632 | */ | |
633 | dev->archdata.iommu = smmu; | |
634 | break; | |
635 | } | |
636 | ||
637 | index++; | |
638 | } | |
639 | ||
640 | return 0; | |
7a31f6f4 HD |
641 | } |
642 | ||
89184651 | 643 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 644 | { |
89184651 TR |
645 | dev->archdata.iommu = NULL; |
646 | } | |
7a31f6f4 | 647 | |
89184651 TR |
648 | static const struct iommu_ops tegra_smmu_ops = { |
649 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
650 | .domain_alloc = tegra_smmu_domain_alloc, |
651 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
652 | .attach_dev = tegra_smmu_attach_dev, |
653 | .detach_dev = tegra_smmu_detach_dev, | |
654 | .add_device = tegra_smmu_add_device, | |
655 | .remove_device = tegra_smmu_remove_device, | |
656 | .map = tegra_smmu_map, | |
657 | .unmap = tegra_smmu_unmap, | |
658 | .map_sg = default_iommu_map_sg, | |
659 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 660 | |
89184651 TR |
661 | .pgsize_bitmap = SZ_4K, |
662 | }; | |
7a31f6f4 | 663 | |
89184651 TR |
664 | static void tegra_smmu_ahb_enable(void) |
665 | { | |
666 | static const struct of_device_id ahb_match[] = { | |
667 | { .compatible = "nvidia,tegra30-ahb", }, | |
668 | { } | |
669 | }; | |
670 | struct device_node *ahb; | |
7a31f6f4 | 671 | |
89184651 TR |
672 | ahb = of_find_matching_node(NULL, ahb_match); |
673 | if (ahb) { | |
674 | tegra_ahb_enable_smmu(ahb); | |
675 | of_node_put(ahb); | |
7a31f6f4 | 676 | } |
89184651 | 677 | } |
7a31f6f4 | 678 | |
d1313e78 TR |
679 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
680 | { | |
681 | struct tegra_smmu *smmu = s->private; | |
682 | unsigned int i; | |
683 | u32 value; | |
684 | ||
685 | seq_printf(s, "swgroup enabled ASID\n"); | |
686 | seq_printf(s, "------------------------\n"); | |
687 | ||
688 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
689 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
690 | const char *status; | |
691 | unsigned int asid; | |
692 | ||
693 | value = smmu_readl(smmu, group->reg); | |
694 | ||
695 | if (value & SMMU_ASID_ENABLE) | |
696 | status = "yes"; | |
697 | else | |
698 | status = "no"; | |
699 | ||
700 | asid = value & SMMU_ASID_MASK; | |
701 | ||
702 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
703 | asid); | |
704 | } | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) | |
710 | { | |
711 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); | |
712 | } | |
713 | ||
714 | static const struct file_operations tegra_smmu_swgroups_fops = { | |
715 | .open = tegra_smmu_swgroups_open, | |
716 | .read = seq_read, | |
717 | .llseek = seq_lseek, | |
718 | .release = single_release, | |
719 | }; | |
720 | ||
721 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
722 | { | |
723 | struct tegra_smmu *smmu = s->private; | |
724 | unsigned int i; | |
725 | u32 value; | |
726 | ||
727 | seq_printf(s, "client enabled\n"); | |
728 | seq_printf(s, "--------------------\n"); | |
729 | ||
730 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
731 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
732 | const char *status; | |
733 | ||
734 | value = smmu_readl(smmu, client->smmu.reg); | |
735 | ||
736 | if (value & BIT(client->smmu.bit)) | |
737 | status = "yes"; | |
738 | else | |
739 | status = "no"; | |
740 | ||
741 | seq_printf(s, "%-12s %s\n", client->name, status); | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) | |
748 | { | |
749 | return single_open(file, tegra_smmu_clients_show, inode->i_private); | |
750 | } | |
751 | ||
752 | static const struct file_operations tegra_smmu_clients_fops = { | |
753 | .open = tegra_smmu_clients_open, | |
754 | .read = seq_read, | |
755 | .llseek = seq_lseek, | |
756 | .release = single_release, | |
757 | }; | |
758 | ||
759 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
760 | { | |
761 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
762 | if (!smmu->debugfs) | |
763 | return; | |
764 | ||
765 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
766 | &tegra_smmu_swgroups_fops); | |
767 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
768 | &tegra_smmu_clients_fops); | |
769 | } | |
770 | ||
771 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
772 | { | |
773 | debugfs_remove_recursive(smmu->debugfs); | |
774 | } | |
775 | ||
89184651 TR |
776 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
777 | const struct tegra_smmu_soc *soc, | |
778 | struct tegra_mc *mc) | |
779 | { | |
780 | struct tegra_smmu *smmu; | |
781 | size_t size; | |
782 | u32 value; | |
783 | int err; | |
7a31f6f4 | 784 | |
89184651 TR |
785 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
786 | if (!soc) | |
787 | return NULL; | |
0760e8fa | 788 | |
89184651 TR |
789 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
790 | if (!smmu) | |
791 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 792 | |
89184651 TR |
793 | /* |
794 | * This is a bit of a hack. Ideally we'd want to simply return this | |
795 | * value. However the IOMMU registration process will attempt to add | |
796 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
797 | * not to rely on global variables to track the IOMMU instance, we | |
798 | * set it here so that it can be looked up from the .add_device() | |
799 | * callback via the IOMMU device's .drvdata field. | |
800 | */ | |
801 | mc->smmu = smmu; | |
0760e8fa | 802 | |
89184651 | 803 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 804 | |
89184651 TR |
805 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
806 | if (!smmu->asids) | |
807 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 808 | |
89184651 | 809 | mutex_init(&smmu->lock); |
7a31f6f4 | 810 | |
89184651 TR |
811 | smmu->regs = mc->regs; |
812 | smmu->soc = soc; | |
813 | smmu->dev = dev; | |
814 | smmu->mc = mc; | |
7a31f6f4 | 815 | |
804cb54c TR |
816 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
817 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
818 | mc->soc->num_address_bits, smmu->pfn_mask); | |
819 | ||
89184651 | 820 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 821 | |
89184651 TR |
822 | if (soc->supports_request_limit) |
823 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 824 | |
89184651 | 825 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 826 | |
89184651 TR |
827 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
828 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); | |
7a31f6f4 | 829 | |
89184651 TR |
830 | if (soc->supports_round_robin_arbitration) |
831 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 832 | |
89184651 | 833 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 834 | |
89184651 TR |
835 | smmu_flush_ptc(smmu, NULL, 0); |
836 | smmu_flush_tlb(smmu); | |
837 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
838 | smmu_flush(smmu); | |
839 | ||
840 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 841 | |
89184651 TR |
842 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
843 | if (err < 0) | |
844 | return ERR_PTR(err); | |
7a31f6f4 | 845 | |
d1313e78 TR |
846 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
847 | tegra_smmu_debugfs_init(smmu); | |
848 | ||
89184651 TR |
849 | return smmu; |
850 | } | |
d1313e78 TR |
851 | |
852 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
853 | { | |
854 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
855 | tegra_smmu_debugfs_exit(smmu); | |
856 | } |