Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
bc5e6dea | 10 | #include <linux/err.h> |
7a31f6f4 | 11 | #include <linux/iommu.h> |
89184651 | 12 | #include <linux/kernel.h> |
0760e8fa | 13 | #include <linux/of.h> |
89184651 TR |
14 | #include <linux/of_device.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/slab.h> | |
306a7f91 TR |
17 | |
18 | #include <soc/tegra/ahb.h> | |
89184651 | 19 | #include <soc/tegra/mc.h> |
7a31f6f4 | 20 | |
89184651 TR |
21 | struct tegra_smmu { |
22 | void __iomem *regs; | |
23 | struct device *dev; | |
e6bc5933 | 24 | |
89184651 TR |
25 | struct tegra_mc *mc; |
26 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 27 | |
804cb54c TR |
28 | unsigned long pfn_mask; |
29 | ||
89184651 TR |
30 | unsigned long *asids; |
31 | struct mutex lock; | |
39abf8aa | 32 | |
89184651 | 33 | struct list_head list; |
7a31f6f4 | 34 | }; |
7a31f6f4 | 35 | |
89184651 | 36 | struct tegra_smmu_as { |
d5f1a81c | 37 | struct iommu_domain domain; |
89184651 TR |
38 | struct tegra_smmu *smmu; |
39 | unsigned int use_count; | |
40 | struct page *count; | |
41 | struct page *pd; | |
42 | unsigned id; | |
43 | u32 attr; | |
7a31f6f4 HD |
44 | }; |
45 | ||
d5f1a81c JR |
46 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
47 | { | |
48 | return container_of(dom, struct tegra_smmu_as, domain); | |
49 | } | |
50 | ||
89184651 TR |
51 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
52 | unsigned long offset) | |
53 | { | |
54 | writel(value, smmu->regs + offset); | |
55 | } | |
7a31f6f4 | 56 | |
89184651 TR |
57 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
58 | { | |
59 | return readl(smmu->regs + offset); | |
60 | } | |
5a2c937a | 61 | |
89184651 TR |
62 | #define SMMU_CONFIG 0x010 |
63 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 64 | |
89184651 TR |
65 | #define SMMU_TLB_CONFIG 0x14 |
66 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
67 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
68 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) | |
0760e8fa | 69 | |
89184651 TR |
70 | #define SMMU_PTC_CONFIG 0x18 |
71 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
72 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
73 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 74 | |
89184651 TR |
75 | #define SMMU_PTB_ASID 0x01c |
76 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 77 | |
89184651 TR |
78 | #define SMMU_PTB_DATA 0x020 |
79 | #define SMMU_PTB_DATA_VALUE(page, attr) (page_to_phys(page) >> 12 | (attr)) | |
7a31f6f4 | 80 | |
89184651 | 81 | #define SMMU_MK_PDE(page, attr) (page_to_phys(page) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 82 | |
89184651 TR |
83 | #define SMMU_TLB_FLUSH 0x030 |
84 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
85 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
86 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
87 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
88 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
89 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
90 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
91 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
92 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 93 | |
89184651 TR |
94 | #define SMMU_PTC_FLUSH 0x034 |
95 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
96 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 97 | |
89184651 TR |
98 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
99 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 100 | |
89184651 TR |
101 | /* per-SWGROUP SMMU_*_ASID register */ |
102 | #define SMMU_ASID_ENABLE (1 << 31) | |
103 | #define SMMU_ASID_MASK 0x7f | |
104 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 105 | |
89184651 TR |
106 | /* page table definitions */ |
107 | #define SMMU_NUM_PDE 1024 | |
108 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 109 | |
89184651 TR |
110 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
111 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 112 | |
89184651 TR |
113 | #define SMMU_PDE_SHIFT 22 |
114 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 115 | |
89184651 TR |
116 | #define SMMU_PD_READABLE (1 << 31) |
117 | #define SMMU_PD_WRITABLE (1 << 30) | |
118 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 119 | |
89184651 TR |
120 | #define SMMU_PDE_READABLE (1 << 31) |
121 | #define SMMU_PDE_WRITABLE (1 << 30) | |
122 | #define SMMU_PDE_NONSECURE (1 << 29) | |
123 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 124 | |
89184651 TR |
125 | #define SMMU_PTE_READABLE (1 << 31) |
126 | #define SMMU_PTE_WRITABLE (1 << 30) | |
127 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 128 | |
89184651 TR |
129 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
130 | SMMU_PDE_NONSECURE) | |
131 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
132 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 133 | |
89184651 TR |
134 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, |
135 | unsigned long offset) | |
7a31f6f4 | 136 | { |
89184651 TR |
137 | phys_addr_t phys = page ? page_to_phys(page) : 0; |
138 | u32 value; | |
139 | ||
140 | if (page) { | |
141 | offset &= ~(smmu->mc->soc->atom_size - 1); | |
142 | ||
143 | if (smmu->mc->soc->num_address_bits > 32) { | |
144 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
145 | value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
146 | #else | |
147 | value = 0; | |
148 | #endif | |
149 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); | |
7a31f6f4 | 150 | } |
7a31f6f4 | 151 | |
89184651 TR |
152 | value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
153 | } else { | |
154 | value = SMMU_PTC_FLUSH_TYPE_ALL; | |
7a31f6f4 | 155 | } |
89184651 TR |
156 | |
157 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); | |
7a31f6f4 HD |
158 | } |
159 | ||
89184651 | 160 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 161 | { |
89184651 | 162 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
163 | } |
164 | ||
89184651 TR |
165 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
166 | unsigned long asid) | |
7a31f6f4 | 167 | { |
89184651 | 168 | u32 value; |
7a31f6f4 | 169 | |
89184651 TR |
170 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
171 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
172 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
173 | } |
174 | ||
89184651 TR |
175 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
176 | unsigned long asid, | |
177 | unsigned long iova) | |
7a31f6f4 | 178 | { |
89184651 | 179 | u32 value; |
7a31f6f4 | 180 | |
89184651 TR |
181 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
182 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
183 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
184 | } |
185 | ||
89184651 TR |
186 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
187 | unsigned long asid, | |
188 | unsigned long iova) | |
7a31f6f4 | 189 | { |
89184651 | 190 | u32 value; |
7a31f6f4 | 191 | |
89184651 TR |
192 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
193 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
194 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
195 | } |
196 | ||
89184651 | 197 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 198 | { |
89184651 | 199 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
200 | } |
201 | ||
89184651 | 202 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 203 | { |
89184651 | 204 | unsigned long id; |
7a31f6f4 | 205 | |
89184651 | 206 | mutex_lock(&smmu->lock); |
7a31f6f4 | 207 | |
89184651 TR |
208 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
209 | if (id >= smmu->soc->num_asids) { | |
210 | mutex_unlock(&smmu->lock); | |
211 | return -ENOSPC; | |
7a31f6f4 | 212 | } |
7a31f6f4 | 213 | |
89184651 TR |
214 | set_bit(id, smmu->asids); |
215 | *idp = id; | |
216 | ||
217 | mutex_unlock(&smmu->lock); | |
218 | return 0; | |
7a31f6f4 HD |
219 | } |
220 | ||
89184651 | 221 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 222 | { |
89184651 TR |
223 | mutex_lock(&smmu->lock); |
224 | clear_bit(id, smmu->asids); | |
225 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 226 | } |
89184651 TR |
227 | |
228 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 229 | { |
89184651 | 230 | return false; |
7a31f6f4 | 231 | } |
7a31f6f4 | 232 | |
d5f1a81c | 233 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 234 | { |
89184651 TR |
235 | struct tegra_smmu_as *as; |
236 | unsigned int i; | |
237 | uint32_t *pd; | |
7a31f6f4 | 238 | |
d5f1a81c JR |
239 | if (type != IOMMU_DOMAIN_UNMANAGED) |
240 | return NULL; | |
241 | ||
89184651 TR |
242 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
243 | if (!as) | |
d5f1a81c | 244 | return NULL; |
7a31f6f4 | 245 | |
89184651 | 246 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 247 | |
89184651 TR |
248 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA); |
249 | if (!as->pd) { | |
250 | kfree(as); | |
d5f1a81c | 251 | return NULL; |
7a31f6f4 | 252 | } |
9e971a03 | 253 | |
89184651 TR |
254 | as->count = alloc_page(GFP_KERNEL); |
255 | if (!as->count) { | |
256 | __free_page(as->pd); | |
257 | kfree(as); | |
d5f1a81c | 258 | return NULL; |
7a31f6f4 | 259 | } |
9e971a03 | 260 | |
89184651 TR |
261 | /* clear PDEs */ |
262 | pd = page_address(as->pd); | |
263 | SetPageReserved(as->pd); | |
9e971a03 | 264 | |
89184651 TR |
265 | for (i = 0; i < SMMU_NUM_PDE; i++) |
266 | pd[i] = 0; | |
7a31f6f4 | 267 | |
89184651 TR |
268 | /* clear PDE usage counters */ |
269 | pd = page_address(as->count); | |
270 | SetPageReserved(as->count); | |
7a31f6f4 | 271 | |
89184651 TR |
272 | for (i = 0; i < SMMU_NUM_PDE; i++) |
273 | pd[i] = 0; | |
9e971a03 | 274 | |
471d9144 | 275 | /* setup aperture */ |
7f65ef01 JR |
276 | as->domain.geometry.aperture_start = 0; |
277 | as->domain.geometry.aperture_end = 0xffffffff; | |
278 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 279 | |
d5f1a81c | 280 | return &as->domain; |
7a31f6f4 HD |
281 | } |
282 | ||
d5f1a81c | 283 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 284 | { |
d5f1a81c | 285 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 286 | |
89184651 TR |
287 | /* TODO: free page directory and page tables */ |
288 | ClearPageReserved(as->pd); | |
7a31f6f4 | 289 | |
89184651 | 290 | kfree(as); |
7a31f6f4 HD |
291 | } |
292 | ||
89184651 TR |
293 | static const struct tegra_smmu_swgroup * |
294 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 295 | { |
89184651 TR |
296 | const struct tegra_smmu_swgroup *group = NULL; |
297 | unsigned int i; | |
7a31f6f4 | 298 | |
89184651 TR |
299 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
300 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
301 | group = &smmu->soc->swgroups[i]; | |
302 | break; | |
303 | } | |
304 | } | |
7a31f6f4 | 305 | |
89184651 | 306 | return group; |
7a31f6f4 HD |
307 | } |
308 | ||
89184651 TR |
309 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
310 | unsigned int asid) | |
7a31f6f4 | 311 | { |
89184651 TR |
312 | const struct tegra_smmu_swgroup *group; |
313 | unsigned int i; | |
314 | u32 value; | |
7a31f6f4 | 315 | |
89184651 TR |
316 | for (i = 0; i < smmu->soc->num_clients; i++) { |
317 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 318 | |
89184651 TR |
319 | if (client->swgroup != swgroup) |
320 | continue; | |
7a31f6f4 | 321 | |
89184651 TR |
322 | value = smmu_readl(smmu, client->smmu.reg); |
323 | value |= BIT(client->smmu.bit); | |
324 | smmu_writel(smmu, value, client->smmu.reg); | |
325 | } | |
7a31f6f4 | 326 | |
89184651 TR |
327 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
328 | if (group) { | |
329 | value = smmu_readl(smmu, group->reg); | |
330 | value &= ~SMMU_ASID_MASK; | |
331 | value |= SMMU_ASID_VALUE(asid); | |
332 | value |= SMMU_ASID_ENABLE; | |
333 | smmu_writel(smmu, value, group->reg); | |
334 | } | |
7a31f6f4 HD |
335 | } |
336 | ||
89184651 TR |
337 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
338 | unsigned int asid) | |
7a31f6f4 | 339 | { |
89184651 TR |
340 | const struct tegra_smmu_swgroup *group; |
341 | unsigned int i; | |
342 | u32 value; | |
7a31f6f4 | 343 | |
89184651 TR |
344 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
345 | if (group) { | |
346 | value = smmu_readl(smmu, group->reg); | |
347 | value &= ~SMMU_ASID_MASK; | |
348 | value |= SMMU_ASID_VALUE(asid); | |
349 | value &= ~SMMU_ASID_ENABLE; | |
350 | smmu_writel(smmu, value, group->reg); | |
351 | } | |
7a31f6f4 | 352 | |
89184651 TR |
353 | for (i = 0; i < smmu->soc->num_clients; i++) { |
354 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 355 | |
89184651 TR |
356 | if (client->swgroup != swgroup) |
357 | continue; | |
7a31f6f4 | 358 | |
89184651 TR |
359 | value = smmu_readl(smmu, client->smmu.reg); |
360 | value &= ~BIT(client->smmu.bit); | |
361 | smmu_writel(smmu, value, client->smmu.reg); | |
362 | } | |
7a31f6f4 HD |
363 | } |
364 | ||
89184651 TR |
365 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
366 | struct tegra_smmu_as *as) | |
7a31f6f4 | 367 | { |
89184651 | 368 | u32 value; |
7a31f6f4 HD |
369 | int err; |
370 | ||
89184651 TR |
371 | if (as->use_count > 0) { |
372 | as->use_count++; | |
373 | return 0; | |
7a31f6f4 | 374 | } |
7a31f6f4 | 375 | |
89184651 TR |
376 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
377 | if (err < 0) | |
378 | return err; | |
7a31f6f4 | 379 | |
89184651 TR |
380 | smmu->soc->ops->flush_dcache(as->pd, 0, SMMU_SIZE_PD); |
381 | smmu_flush_ptc(smmu, as->pd, 0); | |
382 | smmu_flush_tlb_asid(smmu, as->id); | |
7a31f6f4 | 383 | |
89184651 TR |
384 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
385 | value = SMMU_PTB_DATA_VALUE(as->pd, as->attr); | |
386 | smmu_writel(smmu, value, SMMU_PTB_DATA); | |
387 | smmu_flush(smmu); | |
7a31f6f4 | 388 | |
89184651 TR |
389 | as->smmu = smmu; |
390 | as->use_count++; | |
7a31f6f4 | 391 | |
89184651 | 392 | return 0; |
7a31f6f4 HD |
393 | } |
394 | ||
89184651 TR |
395 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
396 | struct tegra_smmu_as *as) | |
7a31f6f4 | 397 | { |
89184651 TR |
398 | if (--as->use_count > 0) |
399 | return; | |
400 | ||
401 | tegra_smmu_free_asid(smmu, as->id); | |
402 | as->smmu = NULL; | |
7a31f6f4 HD |
403 | } |
404 | ||
89184651 TR |
405 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
406 | struct device *dev) | |
7a31f6f4 | 407 | { |
89184651 | 408 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 409 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
410 | struct device_node *np = dev->of_node; |
411 | struct of_phandle_args args; | |
412 | unsigned int index = 0; | |
413 | int err = 0; | |
7a31f6f4 | 414 | |
89184651 TR |
415 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
416 | &args)) { | |
417 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 418 | |
89184651 TR |
419 | if (args.np != smmu->dev->of_node) { |
420 | of_node_put(args.np); | |
d2453b2c | 421 | continue; |
89184651 | 422 | } |
d2453b2c | 423 | |
89184651 | 424 | of_node_put(args.np); |
d2453b2c | 425 | |
89184651 TR |
426 | err = tegra_smmu_as_prepare(smmu, as); |
427 | if (err < 0) | |
428 | return err; | |
429 | ||
430 | tegra_smmu_enable(smmu, swgroup, as->id); | |
431 | index++; | |
7a31f6f4 | 432 | } |
7a31f6f4 | 433 | |
89184651 TR |
434 | if (index == 0) |
435 | return -ENODEV; | |
7a31f6f4 | 436 | |
89184651 TR |
437 | return 0; |
438 | } | |
7a31f6f4 | 439 | |
89184651 TR |
440 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
441 | { | |
d5f1a81c | 442 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
443 | struct device_node *np = dev->of_node; |
444 | struct tegra_smmu *smmu = as->smmu; | |
445 | struct of_phandle_args args; | |
446 | unsigned int index = 0; | |
7a31f6f4 | 447 | |
89184651 TR |
448 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
449 | &args)) { | |
450 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 451 | |
89184651 TR |
452 | if (args.np != smmu->dev->of_node) { |
453 | of_node_put(args.np); | |
454 | continue; | |
455 | } | |
23349902 | 456 | |
89184651 | 457 | of_node_put(args.np); |
7a31f6f4 | 458 | |
89184651 TR |
459 | tegra_smmu_disable(smmu, swgroup, as->id); |
460 | tegra_smmu_as_unprepare(smmu, as); | |
461 | index++; | |
462 | } | |
7a31f6f4 HD |
463 | } |
464 | ||
89184651 TR |
465 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
466 | struct page **pagep) | |
7a31f6f4 | 467 | { |
89184651 TR |
468 | u32 *pd = page_address(as->pd), *pt, *count; |
469 | u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff; | |
470 | u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff; | |
471 | struct tegra_smmu *smmu = as->smmu; | |
472 | struct page *page; | |
473 | unsigned int i; | |
474 | ||
475 | if (pd[pde] == 0) { | |
476 | page = alloc_page(GFP_KERNEL | __GFP_DMA); | |
477 | if (!page) | |
478 | return NULL; | |
7a31f6f4 | 479 | |
89184651 TR |
480 | pt = page_address(page); |
481 | SetPageReserved(page); | |
7a31f6f4 | 482 | |
89184651 TR |
483 | for (i = 0; i < SMMU_NUM_PTE; i++) |
484 | pt[i] = 0; | |
7a31f6f4 | 485 | |
89184651 | 486 | smmu->soc->ops->flush_dcache(page, 0, SMMU_SIZE_PT); |
7a31f6f4 | 487 | |
89184651 | 488 | pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT); |
7a31f6f4 | 489 | |
89184651 TR |
490 | smmu->soc->ops->flush_dcache(as->pd, pde << 2, 4); |
491 | smmu_flush_ptc(smmu, as->pd, pde << 2); | |
492 | smmu_flush_tlb_section(smmu, as->id, iova); | |
493 | smmu_flush(smmu); | |
494 | } else { | |
804cb54c | 495 | page = pfn_to_page(pd[pde] & smmu->pfn_mask); |
89184651 | 496 | pt = page_address(page); |
7a31f6f4 HD |
497 | } |
498 | ||
89184651 | 499 | *pagep = page; |
7a31f6f4 | 500 | |
89184651 TR |
501 | /* Keep track of entries in this page table. */ |
502 | count = page_address(as->count); | |
503 | if (pt[pte] == 0) | |
504 | count[pde]++; | |
7a31f6f4 | 505 | |
89184651 TR |
506 | return &pt[pte]; |
507 | } | |
39abf8aa | 508 | |
89184651 | 509 | static void as_put_pte(struct tegra_smmu_as *as, dma_addr_t iova) |
39abf8aa | 510 | { |
89184651 TR |
511 | u32 pde = (iova >> SMMU_PDE_SHIFT) & 0x3ff; |
512 | u32 pte = (iova >> SMMU_PTE_SHIFT) & 0x3ff; | |
513 | u32 *count = page_address(as->count); | |
514 | u32 *pd = page_address(as->pd), *pt; | |
515 | struct page *page; | |
39abf8aa | 516 | |
804cb54c | 517 | page = pfn_to_page(pd[pde] & as->smmu->pfn_mask); |
89184651 | 518 | pt = page_address(page); |
39abf8aa | 519 | |
89184651 TR |
520 | /* |
521 | * When no entries in this page table are used anymore, return the | |
522 | * memory page to the system. | |
523 | */ | |
524 | if (pt[pte] != 0) { | |
525 | if (--count[pde] == 0) { | |
526 | ClearPageReserved(page); | |
527 | __free_page(page); | |
528 | pd[pde] = 0; | |
529 | } | |
39abf8aa | 530 | |
89184651 | 531 | pt[pte] = 0; |
39abf8aa | 532 | } |
39abf8aa HD |
533 | } |
534 | ||
89184651 TR |
535 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
536 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 537 | { |
d5f1a81c | 538 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
539 | struct tegra_smmu *smmu = as->smmu; |
540 | unsigned long offset; | |
541 | struct page *page; | |
542 | u32 *pte; | |
39abf8aa | 543 | |
89184651 TR |
544 | pte = as_get_pte(as, iova, &page); |
545 | if (!pte) | |
546 | return -ENOMEM; | |
39abf8aa | 547 | |
89184651 TR |
548 | *pte = __phys_to_pfn(paddr) | SMMU_PTE_ATTR; |
549 | offset = offset_in_page(pte); | |
39abf8aa | 550 | |
89184651 TR |
551 | smmu->soc->ops->flush_dcache(page, offset, 4); |
552 | smmu_flush_ptc(smmu, page, offset); | |
553 | smmu_flush_tlb_group(smmu, as->id, iova); | |
554 | smmu_flush(smmu); | |
39abf8aa | 555 | |
39abf8aa HD |
556 | return 0; |
557 | } | |
558 | ||
89184651 TR |
559 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
560 | size_t size) | |
39abf8aa | 561 | { |
d5f1a81c | 562 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
563 | struct tegra_smmu *smmu = as->smmu; |
564 | unsigned long offset; | |
565 | struct page *page; | |
566 | u32 *pte; | |
39abf8aa | 567 | |
89184651 TR |
568 | pte = as_get_pte(as, iova, &page); |
569 | if (!pte) | |
570 | return 0; | |
39abf8aa | 571 | |
89184651 TR |
572 | offset = offset_in_page(pte); |
573 | as_put_pte(as, iova); | |
574 | ||
575 | smmu->soc->ops->flush_dcache(page, offset, 4); | |
576 | smmu_flush_ptc(smmu, page, offset); | |
577 | smmu_flush_tlb_group(smmu, as->id, iova); | |
578 | smmu_flush(smmu); | |
579 | ||
580 | return size; | |
39abf8aa HD |
581 | } |
582 | ||
89184651 TR |
583 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
584 | dma_addr_t iova) | |
39abf8aa | 585 | { |
d5f1a81c | 586 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
587 | struct page *page; |
588 | unsigned long pfn; | |
589 | u32 *pte; | |
39abf8aa | 590 | |
89184651 | 591 | pte = as_get_pte(as, iova, &page); |
804cb54c | 592 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 593 | |
89184651 | 594 | return PFN_PHYS(pfn); |
39abf8aa HD |
595 | } |
596 | ||
89184651 | 597 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 598 | { |
89184651 TR |
599 | struct platform_device *pdev; |
600 | struct tegra_mc *mc; | |
7a31f6f4 | 601 | |
89184651 TR |
602 | pdev = of_find_device_by_node(np); |
603 | if (!pdev) | |
604 | return NULL; | |
605 | ||
606 | mc = platform_get_drvdata(pdev); | |
607 | if (!mc) | |
608 | return NULL; | |
609 | ||
610 | return mc->smmu; | |
7a31f6f4 HD |
611 | } |
612 | ||
89184651 | 613 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 614 | { |
89184651 TR |
615 | struct device_node *np = dev->of_node; |
616 | struct of_phandle_args args; | |
617 | unsigned int index = 0; | |
7a31f6f4 | 618 | |
89184651 TR |
619 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
620 | &args) == 0) { | |
621 | struct tegra_smmu *smmu; | |
622 | ||
623 | smmu = tegra_smmu_find(args.np); | |
624 | if (smmu) { | |
625 | /* | |
626 | * Only a single IOMMU master interface is currently | |
627 | * supported by the Linux kernel, so abort after the | |
628 | * first match. | |
629 | */ | |
630 | dev->archdata.iommu = smmu; | |
631 | break; | |
632 | } | |
633 | ||
634 | index++; | |
635 | } | |
636 | ||
637 | return 0; | |
7a31f6f4 HD |
638 | } |
639 | ||
89184651 | 640 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 641 | { |
89184651 TR |
642 | dev->archdata.iommu = NULL; |
643 | } | |
7a31f6f4 | 644 | |
89184651 TR |
645 | static const struct iommu_ops tegra_smmu_ops = { |
646 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
647 | .domain_alloc = tegra_smmu_domain_alloc, |
648 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
649 | .attach_dev = tegra_smmu_attach_dev, |
650 | .detach_dev = tegra_smmu_detach_dev, | |
651 | .add_device = tegra_smmu_add_device, | |
652 | .remove_device = tegra_smmu_remove_device, | |
653 | .map = tegra_smmu_map, | |
654 | .unmap = tegra_smmu_unmap, | |
655 | .map_sg = default_iommu_map_sg, | |
656 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 657 | |
89184651 TR |
658 | .pgsize_bitmap = SZ_4K, |
659 | }; | |
7a31f6f4 | 660 | |
89184651 TR |
661 | static void tegra_smmu_ahb_enable(void) |
662 | { | |
663 | static const struct of_device_id ahb_match[] = { | |
664 | { .compatible = "nvidia,tegra30-ahb", }, | |
665 | { } | |
666 | }; | |
667 | struct device_node *ahb; | |
7a31f6f4 | 668 | |
89184651 TR |
669 | ahb = of_find_matching_node(NULL, ahb_match); |
670 | if (ahb) { | |
671 | tegra_ahb_enable_smmu(ahb); | |
672 | of_node_put(ahb); | |
7a31f6f4 | 673 | } |
89184651 | 674 | } |
7a31f6f4 | 675 | |
89184651 TR |
676 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
677 | const struct tegra_smmu_soc *soc, | |
678 | struct tegra_mc *mc) | |
679 | { | |
680 | struct tegra_smmu *smmu; | |
681 | size_t size; | |
682 | u32 value; | |
683 | int err; | |
7a31f6f4 | 684 | |
89184651 TR |
685 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
686 | if (!soc) | |
687 | return NULL; | |
0760e8fa | 688 | |
89184651 TR |
689 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
690 | if (!smmu) | |
691 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 692 | |
89184651 TR |
693 | /* |
694 | * This is a bit of a hack. Ideally we'd want to simply return this | |
695 | * value. However the IOMMU registration process will attempt to add | |
696 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
697 | * not to rely on global variables to track the IOMMU instance, we | |
698 | * set it here so that it can be looked up from the .add_device() | |
699 | * callback via the IOMMU device's .drvdata field. | |
700 | */ | |
701 | mc->smmu = smmu; | |
0760e8fa | 702 | |
89184651 | 703 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 704 | |
89184651 TR |
705 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
706 | if (!smmu->asids) | |
707 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 708 | |
89184651 | 709 | mutex_init(&smmu->lock); |
7a31f6f4 | 710 | |
89184651 TR |
711 | smmu->regs = mc->regs; |
712 | smmu->soc = soc; | |
713 | smmu->dev = dev; | |
714 | smmu->mc = mc; | |
7a31f6f4 | 715 | |
804cb54c TR |
716 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
717 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
718 | mc->soc->num_address_bits, smmu->pfn_mask); | |
719 | ||
89184651 | 720 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 721 | |
89184651 TR |
722 | if (soc->supports_request_limit) |
723 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 724 | |
89184651 | 725 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 726 | |
89184651 TR |
727 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
728 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); | |
7a31f6f4 | 729 | |
89184651 TR |
730 | if (soc->supports_round_robin_arbitration) |
731 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 732 | |
89184651 | 733 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 734 | |
89184651 TR |
735 | smmu_flush_ptc(smmu, NULL, 0); |
736 | smmu_flush_tlb(smmu); | |
737 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
738 | smmu_flush(smmu); | |
739 | ||
740 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 741 | |
89184651 TR |
742 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
743 | if (err < 0) | |
744 | return ERR_PTR(err); | |
7a31f6f4 | 745 | |
89184651 TR |
746 | return smmu; |
747 | } |