Commit | Line | Data |
---|---|---|
7a31f6f4 | 1 | /* |
89184651 | 2 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 | 3 | * |
89184651 TR |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7a31f6f4 HD |
7 | */ |
8 | ||
804cb54c | 9 | #include <linux/bitops.h> |
d1313e78 | 10 | #include <linux/debugfs.h> |
bc5e6dea | 11 | #include <linux/err.h> |
7a31f6f4 | 12 | #include <linux/iommu.h> |
89184651 | 13 | #include <linux/kernel.h> |
0760e8fa | 14 | #include <linux/of.h> |
89184651 TR |
15 | #include <linux/of_device.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
89184651 TR |
22 | struct tegra_smmu { |
23 | void __iomem *regs; | |
24 | struct device *dev; | |
e6bc5933 | 25 | |
89184651 TR |
26 | struct tegra_mc *mc; |
27 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 28 | |
804cb54c TR |
29 | unsigned long pfn_mask; |
30 | ||
89184651 TR |
31 | unsigned long *asids; |
32 | struct mutex lock; | |
39abf8aa | 33 | |
89184651 | 34 | struct list_head list; |
d1313e78 TR |
35 | |
36 | struct dentry *debugfs; | |
7a31f6f4 | 37 | }; |
7a31f6f4 | 38 | |
89184651 | 39 | struct tegra_smmu_as { |
d5f1a81c | 40 | struct iommu_domain domain; |
89184651 TR |
41 | struct tegra_smmu *smmu; |
42 | unsigned int use_count; | |
32924c76 | 43 | u32 *count; |
853520fa | 44 | struct page **pts; |
89184651 | 45 | struct page *pd; |
e3c97196 | 46 | dma_addr_t pd_dma; |
89184651 TR |
47 | unsigned id; |
48 | u32 attr; | |
7a31f6f4 HD |
49 | }; |
50 | ||
d5f1a81c JR |
51 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
52 | { | |
53 | return container_of(dom, struct tegra_smmu_as, domain); | |
54 | } | |
55 | ||
89184651 TR |
56 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
57 | unsigned long offset) | |
58 | { | |
59 | writel(value, smmu->regs + offset); | |
60 | } | |
7a31f6f4 | 61 | |
89184651 TR |
62 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
63 | { | |
64 | return readl(smmu->regs + offset); | |
65 | } | |
5a2c937a | 66 | |
89184651 TR |
67 | #define SMMU_CONFIG 0x010 |
68 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 69 | |
89184651 TR |
70 | #define SMMU_TLB_CONFIG 0x14 |
71 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
72 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
73 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(x) ((x) & 0x3f) | |
0760e8fa | 74 | |
89184651 TR |
75 | #define SMMU_PTC_CONFIG 0x18 |
76 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
77 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
78 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 79 | |
89184651 TR |
80 | #define SMMU_PTB_ASID 0x01c |
81 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 82 | |
89184651 | 83 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 84 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 85 | |
e3c97196 | 86 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 87 | |
89184651 TR |
88 | #define SMMU_TLB_FLUSH 0x030 |
89 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
90 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
91 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
92 | #define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) | |
93 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ | |
94 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
95 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
96 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
97 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 98 | |
89184651 TR |
99 | #define SMMU_PTC_FLUSH 0x034 |
100 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
101 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 102 | |
89184651 TR |
103 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
104 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 105 | |
89184651 TR |
106 | /* per-SWGROUP SMMU_*_ASID register */ |
107 | #define SMMU_ASID_ENABLE (1 << 31) | |
108 | #define SMMU_ASID_MASK 0x7f | |
109 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 110 | |
89184651 TR |
111 | /* page table definitions */ |
112 | #define SMMU_NUM_PDE 1024 | |
113 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 114 | |
89184651 TR |
115 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
116 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 117 | |
89184651 TR |
118 | #define SMMU_PDE_SHIFT 22 |
119 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 120 | |
89184651 TR |
121 | #define SMMU_PD_READABLE (1 << 31) |
122 | #define SMMU_PD_WRITABLE (1 << 30) | |
123 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 124 | |
89184651 TR |
125 | #define SMMU_PDE_READABLE (1 << 31) |
126 | #define SMMU_PDE_WRITABLE (1 << 30) | |
127 | #define SMMU_PDE_NONSECURE (1 << 29) | |
128 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 129 | |
89184651 TR |
130 | #define SMMU_PTE_READABLE (1 << 31) |
131 | #define SMMU_PTE_WRITABLE (1 << 30) | |
132 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 133 | |
89184651 TR |
134 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
135 | SMMU_PDE_NONSECURE) | |
136 | #define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ | |
137 | SMMU_PTE_NONSECURE) | |
7a31f6f4 | 138 | |
34d35f8c RK |
139 | static unsigned int iova_pd_index(unsigned long iova) |
140 | { | |
141 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
142 | } | |
143 | ||
144 | static unsigned int iova_pt_index(unsigned long iova) | |
145 | { | |
146 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
147 | } | |
148 | ||
e3c97196 | 149 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 150 | { |
e3c97196 RK |
151 | addr >>= 12; |
152 | return (addr & smmu->pfn_mask) == addr; | |
153 | } | |
4b3c7d10 | 154 | |
e3c97196 RK |
155 | static dma_addr_t smmu_pde_to_dma(u32 pde) |
156 | { | |
157 | return pde << 12; | |
4b3c7d10 RK |
158 | } |
159 | ||
b8fe0382 RK |
160 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
161 | { | |
162 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
163 | } | |
164 | ||
e3c97196 | 165 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 166 | unsigned long offset) |
7a31f6f4 | 167 | { |
89184651 TR |
168 | u32 value; |
169 | ||
b8fe0382 | 170 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 171 | |
b8fe0382 | 172 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
173 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
174 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 175 | #else |
b8fe0382 | 176 | value = 0; |
89184651 | 177 | #endif |
b8fe0382 | 178 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 179 | } |
89184651 | 180 | |
e3c97196 | 181 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 182 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
183 | } |
184 | ||
89184651 | 185 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 186 | { |
89184651 | 187 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
188 | } |
189 | ||
89184651 TR |
190 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
191 | unsigned long asid) | |
7a31f6f4 | 192 | { |
89184651 | 193 | u32 value; |
7a31f6f4 | 194 | |
89184651 TR |
195 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
196 | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
197 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
198 | } |
199 | ||
89184651 TR |
200 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
201 | unsigned long asid, | |
202 | unsigned long iova) | |
7a31f6f4 | 203 | { |
89184651 | 204 | u32 value; |
7a31f6f4 | 205 | |
89184651 TR |
206 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
207 | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
208 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
209 | } |
210 | ||
89184651 TR |
211 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
212 | unsigned long asid, | |
213 | unsigned long iova) | |
7a31f6f4 | 214 | { |
89184651 | 215 | u32 value; |
7a31f6f4 | 216 | |
89184651 TR |
217 | value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) | |
218 | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
219 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); | |
7a31f6f4 HD |
220 | } |
221 | ||
89184651 | 222 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 223 | { |
89184651 | 224 | smmu_readl(smmu, SMMU_CONFIG); |
7a31f6f4 HD |
225 | } |
226 | ||
89184651 | 227 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 228 | { |
89184651 | 229 | unsigned long id; |
7a31f6f4 | 230 | |
89184651 | 231 | mutex_lock(&smmu->lock); |
7a31f6f4 | 232 | |
89184651 TR |
233 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
234 | if (id >= smmu->soc->num_asids) { | |
235 | mutex_unlock(&smmu->lock); | |
236 | return -ENOSPC; | |
7a31f6f4 | 237 | } |
7a31f6f4 | 238 | |
89184651 TR |
239 | set_bit(id, smmu->asids); |
240 | *idp = id; | |
241 | ||
242 | mutex_unlock(&smmu->lock); | |
243 | return 0; | |
7a31f6f4 HD |
244 | } |
245 | ||
89184651 | 246 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 247 | { |
89184651 TR |
248 | mutex_lock(&smmu->lock); |
249 | clear_bit(id, smmu->asids); | |
250 | mutex_unlock(&smmu->lock); | |
7a31f6f4 | 251 | } |
89184651 TR |
252 | |
253 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 254 | { |
89184651 | 255 | return false; |
7a31f6f4 | 256 | } |
7a31f6f4 | 257 | |
d5f1a81c | 258 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 259 | { |
89184651 | 260 | struct tegra_smmu_as *as; |
7a31f6f4 | 261 | |
d5f1a81c JR |
262 | if (type != IOMMU_DOMAIN_UNMANAGED) |
263 | return NULL; | |
264 | ||
89184651 TR |
265 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
266 | if (!as) | |
d5f1a81c | 267 | return NULL; |
7a31f6f4 | 268 | |
89184651 | 269 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 270 | |
707917cb | 271 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
272 | if (!as->pd) { |
273 | kfree(as); | |
d5f1a81c | 274 | return NULL; |
7a31f6f4 | 275 | } |
9e971a03 | 276 | |
32924c76 | 277 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
278 | if (!as->count) { |
279 | __free_page(as->pd); | |
280 | kfree(as); | |
d5f1a81c | 281 | return NULL; |
7a31f6f4 | 282 | } |
9e971a03 | 283 | |
853520fa RK |
284 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
285 | if (!as->pts) { | |
32924c76 | 286 | kfree(as->count); |
853520fa RK |
287 | __free_page(as->pd); |
288 | kfree(as); | |
289 | return NULL; | |
290 | } | |
291 | ||
471d9144 | 292 | /* setup aperture */ |
7f65ef01 JR |
293 | as->domain.geometry.aperture_start = 0; |
294 | as->domain.geometry.aperture_end = 0xffffffff; | |
295 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 296 | |
d5f1a81c | 297 | return &as->domain; |
7a31f6f4 HD |
298 | } |
299 | ||
d5f1a81c | 300 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 301 | { |
d5f1a81c | 302 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 303 | |
89184651 | 304 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 305 | |
89184651 | 306 | kfree(as); |
7a31f6f4 HD |
307 | } |
308 | ||
89184651 TR |
309 | static const struct tegra_smmu_swgroup * |
310 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 311 | { |
89184651 TR |
312 | const struct tegra_smmu_swgroup *group = NULL; |
313 | unsigned int i; | |
7a31f6f4 | 314 | |
89184651 TR |
315 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
316 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
317 | group = &smmu->soc->swgroups[i]; | |
318 | break; | |
319 | } | |
320 | } | |
7a31f6f4 | 321 | |
89184651 | 322 | return group; |
7a31f6f4 HD |
323 | } |
324 | ||
89184651 TR |
325 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
326 | unsigned int asid) | |
7a31f6f4 | 327 | { |
89184651 TR |
328 | const struct tegra_smmu_swgroup *group; |
329 | unsigned int i; | |
330 | u32 value; | |
7a31f6f4 | 331 | |
89184651 TR |
332 | for (i = 0; i < smmu->soc->num_clients; i++) { |
333 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 334 | |
89184651 TR |
335 | if (client->swgroup != swgroup) |
336 | continue; | |
7a31f6f4 | 337 | |
89184651 TR |
338 | value = smmu_readl(smmu, client->smmu.reg); |
339 | value |= BIT(client->smmu.bit); | |
340 | smmu_writel(smmu, value, client->smmu.reg); | |
341 | } | |
7a31f6f4 | 342 | |
89184651 TR |
343 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
344 | if (group) { | |
345 | value = smmu_readl(smmu, group->reg); | |
346 | value &= ~SMMU_ASID_MASK; | |
347 | value |= SMMU_ASID_VALUE(asid); | |
348 | value |= SMMU_ASID_ENABLE; | |
349 | smmu_writel(smmu, value, group->reg); | |
350 | } | |
7a31f6f4 HD |
351 | } |
352 | ||
89184651 TR |
353 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
354 | unsigned int asid) | |
7a31f6f4 | 355 | { |
89184651 TR |
356 | const struct tegra_smmu_swgroup *group; |
357 | unsigned int i; | |
358 | u32 value; | |
7a31f6f4 | 359 | |
89184651 TR |
360 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
361 | if (group) { | |
362 | value = smmu_readl(smmu, group->reg); | |
363 | value &= ~SMMU_ASID_MASK; | |
364 | value |= SMMU_ASID_VALUE(asid); | |
365 | value &= ~SMMU_ASID_ENABLE; | |
366 | smmu_writel(smmu, value, group->reg); | |
367 | } | |
7a31f6f4 | 368 | |
89184651 TR |
369 | for (i = 0; i < smmu->soc->num_clients; i++) { |
370 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 371 | |
89184651 TR |
372 | if (client->swgroup != swgroup) |
373 | continue; | |
7a31f6f4 | 374 | |
89184651 TR |
375 | value = smmu_readl(smmu, client->smmu.reg); |
376 | value &= ~BIT(client->smmu.bit); | |
377 | smmu_writel(smmu, value, client->smmu.reg); | |
378 | } | |
7a31f6f4 HD |
379 | } |
380 | ||
89184651 TR |
381 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
382 | struct tegra_smmu_as *as) | |
7a31f6f4 | 383 | { |
89184651 | 384 | u32 value; |
7a31f6f4 HD |
385 | int err; |
386 | ||
89184651 TR |
387 | if (as->use_count > 0) { |
388 | as->use_count++; | |
389 | return 0; | |
7a31f6f4 | 390 | } |
7a31f6f4 | 391 | |
e3c97196 RK |
392 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
393 | DMA_TO_DEVICE); | |
394 | if (dma_mapping_error(smmu->dev, as->pd_dma)) | |
395 | return -ENOMEM; | |
396 | ||
397 | /* We can't handle 64-bit DMA addresses */ | |
398 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
399 | err = -ENOMEM; | |
400 | goto err_unmap; | |
401 | } | |
402 | ||
89184651 TR |
403 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
404 | if (err < 0) | |
e3c97196 | 405 | goto err_unmap; |
7a31f6f4 | 406 | |
e3c97196 | 407 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 408 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 409 | |
89184651 | 410 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 411 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
412 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
413 | smmu_flush(smmu); | |
7a31f6f4 | 414 | |
89184651 TR |
415 | as->smmu = smmu; |
416 | as->use_count++; | |
7a31f6f4 | 417 | |
89184651 | 418 | return 0; |
e3c97196 RK |
419 | |
420 | err_unmap: | |
421 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
422 | return err; | |
7a31f6f4 HD |
423 | } |
424 | ||
89184651 TR |
425 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
426 | struct tegra_smmu_as *as) | |
7a31f6f4 | 427 | { |
89184651 TR |
428 | if (--as->use_count > 0) |
429 | return; | |
430 | ||
431 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
432 | |
433 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
434 | ||
89184651 | 435 | as->smmu = NULL; |
7a31f6f4 HD |
436 | } |
437 | ||
89184651 TR |
438 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
439 | struct device *dev) | |
7a31f6f4 | 440 | { |
89184651 | 441 | struct tegra_smmu *smmu = dev->archdata.iommu; |
d5f1a81c | 442 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
443 | struct device_node *np = dev->of_node; |
444 | struct of_phandle_args args; | |
445 | unsigned int index = 0; | |
446 | int err = 0; | |
7a31f6f4 | 447 | |
89184651 TR |
448 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
449 | &args)) { | |
450 | unsigned int swgroup = args.args[0]; | |
d2453b2c | 451 | |
89184651 TR |
452 | if (args.np != smmu->dev->of_node) { |
453 | of_node_put(args.np); | |
d2453b2c | 454 | continue; |
89184651 | 455 | } |
d2453b2c | 456 | |
89184651 | 457 | of_node_put(args.np); |
d2453b2c | 458 | |
89184651 TR |
459 | err = tegra_smmu_as_prepare(smmu, as); |
460 | if (err < 0) | |
461 | return err; | |
462 | ||
463 | tegra_smmu_enable(smmu, swgroup, as->id); | |
464 | index++; | |
7a31f6f4 | 465 | } |
7a31f6f4 | 466 | |
89184651 TR |
467 | if (index == 0) |
468 | return -ENODEV; | |
7a31f6f4 | 469 | |
89184651 TR |
470 | return 0; |
471 | } | |
7a31f6f4 | 472 | |
89184651 TR |
473 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
474 | { | |
d5f1a81c | 475 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 TR |
476 | struct device_node *np = dev->of_node; |
477 | struct tegra_smmu *smmu = as->smmu; | |
478 | struct of_phandle_args args; | |
479 | unsigned int index = 0; | |
7a31f6f4 | 480 | |
89184651 TR |
481 | while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
482 | &args)) { | |
483 | unsigned int swgroup = args.args[0]; | |
7a31f6f4 | 484 | |
89184651 TR |
485 | if (args.np != smmu->dev->of_node) { |
486 | of_node_put(args.np); | |
487 | continue; | |
488 | } | |
23349902 | 489 | |
89184651 | 490 | of_node_put(args.np); |
7a31f6f4 | 491 | |
89184651 TR |
492 | tegra_smmu_disable(smmu, swgroup, as->id); |
493 | tegra_smmu_as_unprepare(smmu, as); | |
494 | index++; | |
495 | } | |
7a31f6f4 HD |
496 | } |
497 | ||
4080e99b RK |
498 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
499 | u32 value) | |
500 | { | |
501 | unsigned int pd_index = iova_pd_index(iova); | |
502 | struct tegra_smmu *smmu = as->smmu; | |
503 | u32 *pd = page_address(as->pd); | |
504 | unsigned long offset = pd_index * sizeof(*pd); | |
505 | ||
506 | /* Set the page directory entry first */ | |
507 | pd[pd_index] = value; | |
508 | ||
509 | /* The flush the page directory entry from caches */ | |
510 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
511 | sizeof(*pd), DMA_TO_DEVICE); | |
512 | ||
513 | /* And flush the iommu */ | |
514 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
515 | smmu_flush_tlb_section(smmu, as->id, iova); | |
516 | smmu_flush(smmu); | |
517 | } | |
518 | ||
0b42c7c1 RK |
519 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
520 | { | |
521 | u32 *pt = page_address(pt_page); | |
522 | ||
523 | return pt + iova_pt_index(iova); | |
524 | } | |
525 | ||
526 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 527 | dma_addr_t *dmap) |
0b42c7c1 RK |
528 | { |
529 | unsigned int pd_index = iova_pd_index(iova); | |
530 | struct page *pt_page; | |
e3c97196 | 531 | u32 *pd; |
0b42c7c1 | 532 | |
853520fa RK |
533 | pt_page = as->pts[pd_index]; |
534 | if (!pt_page) | |
0b42c7c1 RK |
535 | return NULL; |
536 | ||
e3c97196 RK |
537 | pd = page_address(as->pd); |
538 | *dmap = smmu_pde_to_dma(pd[pd_index]); | |
0b42c7c1 RK |
539 | |
540 | return tegra_smmu_pte_offset(pt_page, iova); | |
541 | } | |
542 | ||
89184651 | 543 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
e3c97196 | 544 | dma_addr_t *dmap) |
7a31f6f4 | 545 | { |
34d35f8c | 546 | unsigned int pde = iova_pd_index(iova); |
89184651 | 547 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 548 | |
853520fa | 549 | if (!as->pts[pde]) { |
e3c97196 RK |
550 | struct page *page; |
551 | dma_addr_t dma; | |
552 | ||
707917cb | 553 | page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
554 | if (!page) |
555 | return NULL; | |
7a31f6f4 | 556 | |
e3c97196 RK |
557 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
558 | DMA_TO_DEVICE); | |
559 | if (dma_mapping_error(smmu->dev, dma)) { | |
560 | __free_page(page); | |
561 | return NULL; | |
562 | } | |
563 | ||
564 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
565 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
566 | DMA_TO_DEVICE); | |
567 | __free_page(page); | |
568 | return NULL; | |
569 | } | |
570 | ||
853520fa RK |
571 | as->pts[pde] = page; |
572 | ||
4080e99b RK |
573 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
574 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
575 | |
576 | *dmap = dma; | |
89184651 | 577 | } else { |
4080e99b RK |
578 | u32 *pd = page_address(as->pd); |
579 | ||
e3c97196 | 580 | *dmap = smmu_pde_to_dma(pd[pde]); |
7a31f6f4 HD |
581 | } |
582 | ||
7ffc6f06 RK |
583 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
584 | } | |
0b42c7c1 | 585 | |
7ffc6f06 RK |
586 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
587 | { | |
588 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 589 | |
7ffc6f06 | 590 | as->count[pd_index]++; |
89184651 | 591 | } |
39abf8aa | 592 | |
b98e34f0 | 593 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 594 | { |
34d35f8c | 595 | unsigned int pde = iova_pd_index(iova); |
853520fa | 596 | struct page *page = as->pts[pde]; |
39abf8aa | 597 | |
89184651 TR |
598 | /* |
599 | * When no entries in this page table are used anymore, return the | |
600 | * memory page to the system. | |
601 | */ | |
32924c76 | 602 | if (--as->count[pde] == 0) { |
4080e99b RK |
603 | struct tegra_smmu *smmu = as->smmu; |
604 | u32 *pd = page_address(as->pd); | |
e3c97196 | 605 | dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]); |
39abf8aa | 606 | |
4080e99b | 607 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 608 | |
e3c97196 | 609 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 610 | __free_page(page); |
853520fa | 611 | as->pts[pde] = NULL; |
39abf8aa | 612 | } |
39abf8aa HD |
613 | } |
614 | ||
8482ee5e | 615 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 616 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
617 | { |
618 | struct tegra_smmu *smmu = as->smmu; | |
619 | unsigned long offset = offset_in_page(pte); | |
620 | ||
621 | *pte = val; | |
622 | ||
e3c97196 RK |
623 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
624 | 4, DMA_TO_DEVICE); | |
625 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
626 | smmu_flush_tlb_group(smmu, as->id, iova); |
627 | smmu_flush(smmu); | |
628 | } | |
629 | ||
89184651 TR |
630 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
631 | phys_addr_t paddr, size_t size, int prot) | |
39abf8aa | 632 | { |
d5f1a81c | 633 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 634 | dma_addr_t pte_dma; |
89184651 | 635 | u32 *pte; |
39abf8aa | 636 | |
e3c97196 | 637 | pte = as_get_pte(as, iova, &pte_dma); |
89184651 TR |
638 | if (!pte) |
639 | return -ENOMEM; | |
39abf8aa | 640 | |
7ffc6f06 RK |
641 | /* If we aren't overwriting a pre-existing entry, increment use */ |
642 | if (*pte == 0) | |
643 | tegra_smmu_pte_get_use(as, iova); | |
644 | ||
e3c97196 | 645 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
8482ee5e | 646 | __phys_to_pfn(paddr) | SMMU_PTE_ATTR); |
39abf8aa | 647 | |
39abf8aa HD |
648 | return 0; |
649 | } | |
650 | ||
89184651 TR |
651 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
652 | size_t size) | |
39abf8aa | 653 | { |
d5f1a81c | 654 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 655 | dma_addr_t pte_dma; |
89184651 | 656 | u32 *pte; |
39abf8aa | 657 | |
e3c97196 | 658 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 659 | if (!pte || !*pte) |
89184651 | 660 | return 0; |
39abf8aa | 661 | |
e3c97196 | 662 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
663 | tegra_smmu_pte_put_use(as, iova); |
664 | ||
89184651 | 665 | return size; |
39abf8aa HD |
666 | } |
667 | ||
89184651 TR |
668 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
669 | dma_addr_t iova) | |
39abf8aa | 670 | { |
d5f1a81c | 671 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 672 | unsigned long pfn; |
e3c97196 | 673 | dma_addr_t pte_dma; |
89184651 | 674 | u32 *pte; |
39abf8aa | 675 | |
e3c97196 | 676 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
677 | if (!pte || !*pte) |
678 | return 0; | |
679 | ||
804cb54c | 680 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 681 | |
89184651 | 682 | return PFN_PHYS(pfn); |
39abf8aa HD |
683 | } |
684 | ||
89184651 | 685 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
7a31f6f4 | 686 | { |
89184651 TR |
687 | struct platform_device *pdev; |
688 | struct tegra_mc *mc; | |
7a31f6f4 | 689 | |
89184651 TR |
690 | pdev = of_find_device_by_node(np); |
691 | if (!pdev) | |
692 | return NULL; | |
693 | ||
694 | mc = platform_get_drvdata(pdev); | |
695 | if (!mc) | |
696 | return NULL; | |
697 | ||
698 | return mc->smmu; | |
7a31f6f4 HD |
699 | } |
700 | ||
89184651 | 701 | static int tegra_smmu_add_device(struct device *dev) |
7a31f6f4 | 702 | { |
89184651 TR |
703 | struct device_node *np = dev->of_node; |
704 | struct of_phandle_args args; | |
705 | unsigned int index = 0; | |
7a31f6f4 | 706 | |
89184651 TR |
707 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, |
708 | &args) == 0) { | |
709 | struct tegra_smmu *smmu; | |
710 | ||
711 | smmu = tegra_smmu_find(args.np); | |
712 | if (smmu) { | |
713 | /* | |
714 | * Only a single IOMMU master interface is currently | |
715 | * supported by the Linux kernel, so abort after the | |
716 | * first match. | |
717 | */ | |
718 | dev->archdata.iommu = smmu; | |
719 | break; | |
720 | } | |
721 | ||
722 | index++; | |
723 | } | |
724 | ||
725 | return 0; | |
7a31f6f4 HD |
726 | } |
727 | ||
89184651 | 728 | static void tegra_smmu_remove_device(struct device *dev) |
7a31f6f4 | 729 | { |
89184651 TR |
730 | dev->archdata.iommu = NULL; |
731 | } | |
7a31f6f4 | 732 | |
89184651 TR |
733 | static const struct iommu_ops tegra_smmu_ops = { |
734 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
735 | .domain_alloc = tegra_smmu_domain_alloc, |
736 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
737 | .attach_dev = tegra_smmu_attach_dev, |
738 | .detach_dev = tegra_smmu_detach_dev, | |
739 | .add_device = tegra_smmu_add_device, | |
740 | .remove_device = tegra_smmu_remove_device, | |
741 | .map = tegra_smmu_map, | |
742 | .unmap = tegra_smmu_unmap, | |
743 | .map_sg = default_iommu_map_sg, | |
744 | .iova_to_phys = tegra_smmu_iova_to_phys, | |
7a31f6f4 | 745 | |
89184651 TR |
746 | .pgsize_bitmap = SZ_4K, |
747 | }; | |
7a31f6f4 | 748 | |
89184651 TR |
749 | static void tegra_smmu_ahb_enable(void) |
750 | { | |
751 | static const struct of_device_id ahb_match[] = { | |
752 | { .compatible = "nvidia,tegra30-ahb", }, | |
753 | { } | |
754 | }; | |
755 | struct device_node *ahb; | |
7a31f6f4 | 756 | |
89184651 TR |
757 | ahb = of_find_matching_node(NULL, ahb_match); |
758 | if (ahb) { | |
759 | tegra_ahb_enable_smmu(ahb); | |
760 | of_node_put(ahb); | |
7a31f6f4 | 761 | } |
89184651 | 762 | } |
7a31f6f4 | 763 | |
d1313e78 TR |
764 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
765 | { | |
766 | struct tegra_smmu *smmu = s->private; | |
767 | unsigned int i; | |
768 | u32 value; | |
769 | ||
770 | seq_printf(s, "swgroup enabled ASID\n"); | |
771 | seq_printf(s, "------------------------\n"); | |
772 | ||
773 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
774 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
775 | const char *status; | |
776 | unsigned int asid; | |
777 | ||
778 | value = smmu_readl(smmu, group->reg); | |
779 | ||
780 | if (value & SMMU_ASID_ENABLE) | |
781 | status = "yes"; | |
782 | else | |
783 | status = "no"; | |
784 | ||
785 | asid = value & SMMU_ASID_MASK; | |
786 | ||
787 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
788 | asid); | |
789 | } | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
794 | static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file) | |
795 | { | |
796 | return single_open(file, tegra_smmu_swgroups_show, inode->i_private); | |
797 | } | |
798 | ||
799 | static const struct file_operations tegra_smmu_swgroups_fops = { | |
800 | .open = tegra_smmu_swgroups_open, | |
801 | .read = seq_read, | |
802 | .llseek = seq_lseek, | |
803 | .release = single_release, | |
804 | }; | |
805 | ||
806 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
807 | { | |
808 | struct tegra_smmu *smmu = s->private; | |
809 | unsigned int i; | |
810 | u32 value; | |
811 | ||
812 | seq_printf(s, "client enabled\n"); | |
813 | seq_printf(s, "--------------------\n"); | |
814 | ||
815 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
816 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
817 | const char *status; | |
818 | ||
819 | value = smmu_readl(smmu, client->smmu.reg); | |
820 | ||
821 | if (value & BIT(client->smmu.bit)) | |
822 | status = "yes"; | |
823 | else | |
824 | status = "no"; | |
825 | ||
826 | seq_printf(s, "%-12s %s\n", client->name, status); | |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static int tegra_smmu_clients_open(struct inode *inode, struct file *file) | |
833 | { | |
834 | return single_open(file, tegra_smmu_clients_show, inode->i_private); | |
835 | } | |
836 | ||
837 | static const struct file_operations tegra_smmu_clients_fops = { | |
838 | .open = tegra_smmu_clients_open, | |
839 | .read = seq_read, | |
840 | .llseek = seq_lseek, | |
841 | .release = single_release, | |
842 | }; | |
843 | ||
844 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
845 | { | |
846 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
847 | if (!smmu->debugfs) | |
848 | return; | |
849 | ||
850 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
851 | &tegra_smmu_swgroups_fops); | |
852 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
853 | &tegra_smmu_clients_fops); | |
854 | } | |
855 | ||
856 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
857 | { | |
858 | debugfs_remove_recursive(smmu->debugfs); | |
859 | } | |
860 | ||
89184651 TR |
861 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
862 | const struct tegra_smmu_soc *soc, | |
863 | struct tegra_mc *mc) | |
864 | { | |
865 | struct tegra_smmu *smmu; | |
866 | size_t size; | |
867 | u32 value; | |
868 | int err; | |
7a31f6f4 | 869 | |
89184651 TR |
870 | /* This can happen on Tegra20 which doesn't have an SMMU */ |
871 | if (!soc) | |
872 | return NULL; | |
0760e8fa | 873 | |
89184651 TR |
874 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
875 | if (!smmu) | |
876 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 877 | |
89184651 TR |
878 | /* |
879 | * This is a bit of a hack. Ideally we'd want to simply return this | |
880 | * value. However the IOMMU registration process will attempt to add | |
881 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
882 | * not to rely on global variables to track the IOMMU instance, we | |
883 | * set it here so that it can be looked up from the .add_device() | |
884 | * callback via the IOMMU device's .drvdata field. | |
885 | */ | |
886 | mc->smmu = smmu; | |
0760e8fa | 887 | |
89184651 | 888 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 889 | |
89184651 TR |
890 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
891 | if (!smmu->asids) | |
892 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 893 | |
89184651 | 894 | mutex_init(&smmu->lock); |
7a31f6f4 | 895 | |
89184651 TR |
896 | smmu->regs = mc->regs; |
897 | smmu->soc = soc; | |
898 | smmu->dev = dev; | |
899 | smmu->mc = mc; | |
7a31f6f4 | 900 | |
804cb54c TR |
901 | smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; |
902 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", | |
903 | mc->soc->num_address_bits, smmu->pfn_mask); | |
904 | ||
89184651 | 905 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 906 | |
89184651 TR |
907 | if (soc->supports_request_limit) |
908 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 909 | |
89184651 | 910 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 911 | |
89184651 TR |
912 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
913 | SMMU_TLB_CONFIG_ACTIVE_LINES(0x20); | |
7a31f6f4 | 914 | |
89184651 TR |
915 | if (soc->supports_round_robin_arbitration) |
916 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 917 | |
89184651 | 918 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 919 | |
b8fe0382 | 920 | smmu_flush_ptc_all(smmu); |
89184651 TR |
921 | smmu_flush_tlb(smmu); |
922 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
923 | smmu_flush(smmu); | |
924 | ||
925 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 926 | |
89184651 TR |
927 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
928 | if (err < 0) | |
929 | return ERR_PTR(err); | |
7a31f6f4 | 930 | |
d1313e78 TR |
931 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
932 | tegra_smmu_debugfs_init(smmu); | |
933 | ||
89184651 TR |
934 | return smmu; |
935 | } | |
d1313e78 TR |
936 | |
937 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
938 | { | |
939 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
940 | tegra_smmu_debugfs_exit(smmu); | |
941 | } |