[deliverable/linux.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config BRCMSTB_L2_IRQ
	bool
	depends on ARM
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select IRQ_DOMAIN

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select IRQ_DOMAIN

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
	8	select MULTI_IRQ_HANDLER
	9
	10	config GIC_NON_BANKED
	11	bool
	12
021f6537 MZ	13	config ARM_GIC_V3
	14	bool
	15	select IRQ_DOMAIN
	16	select MULTI_IRQ_HANDLER
	17
292ec080 UKK	18	config ARM_NVIC
	19	bool
	20	select IRQ_DOMAIN
	21	select GENERIC_IRQ_CHIP
	22
44430ec0 RH	23	config ARM_VIC
	24	bool
	25	select IRQ_DOMAIN
	26	select MULTI_IRQ_HANDLER
	27
	28	config ARM_VIC_NR
	29	int
	30	default 4 if ARCH_S5PV210
44430ec0 RH	31	default 2
	32	depends on ARM_VIC
	33	help
	34	The maximum number of VICs available in the system, for
	35	power management.
	36
b1479ebb BB	37	config ATMEL_AIC_IRQ
	38	bool
	39	select GENERIC_IRQ_CHIP
	40	select IRQ_DOMAIN
	41	select MULTI_IRQ_HANDLER
	42	select SPARSE_IRQ
	43
	44	config ATMEL_AIC5_IRQ
	45	bool
	46	select GENERIC_IRQ_CHIP
	47	select IRQ_DOMAIN
	48	select MULTI_IRQ_HANDLER
	49	select SPARSE_IRQ
	50
7f646e92 FF	51	config BRCMSTB_L2_IRQ
	52	bool
	53	depends on ARM
	54	select GENERIC_IRQ_CHIP
	55	select IRQ_DOMAIN
	56
350d71b9 SH	57	config DW_APB_ICTL
	58	bool
	59	select IRQ_DOMAIN
	60
b6ef9161 JH	61	config IMGPDC_IRQ
	62	bool
	63	select GENERIC_IRQ_CHIP
	64	select IRQ_DOMAIN
	65
afc98d90 AS	66	config CLPS711X_IRQCHIP
	67	bool
	68	depends on ARCH_CLPS711X
	69	select IRQ_DOMAIN
	70	select MULTI_IRQ_HANDLER
	71	select SPARSE_IRQ
	72	default y
	73
4db8e6d2 SK	74	config OR1K_PIC
	75	bool
	76	select IRQ_DOMAIN
	77
9dbd90f1 SH	78	config ORION_IRQCHIP
	79	bool
	80	select IRQ_DOMAIN
	81	select MULTI_IRQ_HANDLER
	82
44358048 MD	83	config RENESAS_INTC_IRQPIN
	84	bool
	85	select IRQ_DOMAIN
	86
fbc83b7f MD	87	config RENESAS_IRQC
	88	bool
	89	select IRQ_DOMAIN
	90
b06eb017 CR	91	config TB10X_IRQC
	92	bool
	93	select IRQ_DOMAIN
	94	select GENERIC_IRQ_CHIP
	95
2389d501 LW	96	config VERSATILE_FPGA_IRQ
	97	bool
	98	select IRQ_DOMAIN
	99
	100	config VERSATILE_FPGA_IRQ_NR
	101	int
	102	default 4
	103	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	104
	105	config XTENSA_MX
	106	bool
	107	select IRQ_DOMAIN
96ca848e S	108
	109	config IRQ_CROSSBAR
	110	bool
	111	help
	112	Support for a CROSSBAR ip that preceeds the main interrupt controller.
	113	The primary irqchip invokes the crossbar's callback which inturn allocates
	114	a free irq and configures the IP. Thus the peripheral interrupts are
	115	routed to one of the free irqchip interrupt lines.