[deliverable/linux.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER

config ARM_GIC_V2M
	bool
	depends on ARM_GIC
	depends on PCI && PCI_MSI
	select PCI_MSI_IRQ_DOMAIN

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY

config ARM_GIC_V3_ITS
	bool
	select PCI_MSI_IRQ_DOMAIN

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select IRQ_DOMAIN

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select MIPS_CM
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44 RH	9	select MULTI_IRQ_HANDLER
81243e44 RH	10
853a33ce SS	11	config ARM_GIC_V2M
	12	bool
	13	depends on ARM_GIC
	14	depends on PCI && PCI_MSI
	15	select PCI_MSI_IRQ_DOMAIN
	16
81243e44 RH	17	config GIC_NON_BANKED
	18	bool
	19
021f6537 MZ	20	config ARM_GIC_V3
	21	bool
	22	select IRQ_DOMAIN
	23	select MULTI_IRQ_HANDLER
443acc4f	24	select IRQ_DOMAIN_HIERARCHY
021f6537	25
19812729 MZ	26	config ARM_GIC_V3_ITS
	27	bool
	28	select PCI_MSI_IRQ_DOMAIN
021f6537	29
292ec080 UKK	30	config ARM_NVIC
	31	bool
	32	select IRQ_DOMAIN
	33	select GENERIC_IRQ_CHIP
	34
44430ec0 RH	35	config ARM_VIC
	36	bool
	37	select IRQ_DOMAIN
	38	select MULTI_IRQ_HANDLER
	39
	40	config ARM_VIC_NR
	41	int
	42	default 4 if ARCH_S5PV210
44430ec0 RH	43	default 2
	44	depends on ARM_VIC
	45	help
	46	The maximum number of VICs available in the system, for
	47	power management.
	48
b1479ebb BB	49	config ATMEL_AIC_IRQ
	50	bool
	51	select GENERIC_IRQ_CHIP
	52	select IRQ_DOMAIN
	53	select MULTI_IRQ_HANDLER
	54	select SPARSE_IRQ
	55
	56	config ATMEL_AIC5_IRQ
	57	bool
	58	select GENERIC_IRQ_CHIP
	59	select IRQ_DOMAIN
	60	select MULTI_IRQ_HANDLER
	61	select SPARSE_IRQ
	62
a4fcbb86 KC	63	config BCM7120_L2_IRQ
	64	bool
	65	select GENERIC_IRQ_CHIP
	66	select IRQ_DOMAIN
	67
7f646e92 FF	68	config BRCMSTB_L2_IRQ
7f646e92 FF	69	bool
7f646e92 FF	70	select GENERIC_IRQ_CHIP
	71	select IRQ_DOMAIN
	72
350d71b9 SH	73	config DW_APB_ICTL
350d71b9 SH	74	bool
e1588490	75	select GENERIC_IRQ_CHIP
350d71b9 SH	76	select IRQ_DOMAIN
350d71b9 SH	77
b6ef9161 JH	78	config IMGPDC_IRQ
	79	bool
	80	select GENERIC_IRQ_CHIP
	81	select IRQ_DOMAIN
	82
afc98d90 AS	83	config CLPS711X_IRQCHIP
	84	bool
	85	depends on ARCH_CLPS711X
	86	select IRQ_DOMAIN
	87	select MULTI_IRQ_HANDLER
	88	select SPARSE_IRQ
	89	default y
	90
4db8e6d2 SK	91	config OR1K_PIC
	92	bool
	93	select IRQ_DOMAIN
	94
8598066c FB	95	config OMAP_IRQCHIP
	96	bool
	97	select GENERIC_IRQ_CHIP
	98	select IRQ_DOMAIN
	99
9dbd90f1 SH	100	config ORION_IRQCHIP
	101	bool
	102	select IRQ_DOMAIN
	103	select MULTI_IRQ_HANDLER
	104
44358048 MD	105	config RENESAS_INTC_IRQPIN
	106	bool
	107	select IRQ_DOMAIN
	108
fbc83b7f MD	109	config RENESAS_IRQC
	110	bool
	111	select IRQ_DOMAIN
	112
b06eb017 CR	113	config TB10X_IRQC
	114	bool
	115	select IRQ_DOMAIN
	116	select GENERIC_IRQ_CHIP
	117
2389d501 LW	118	config VERSATILE_FPGA_IRQ
	119	bool
	120	select IRQ_DOMAIN
	121
	122	config VERSATILE_FPGA_IRQ_NR
	123	int
	124	default 4
	125	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	126
	127	config XTENSA_MX
	128	bool
	129	select IRQ_DOMAIN
96ca848e S	130
	131	config IRQ_CROSSBAR
	132	bool
	133	help
f54619f2	134	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	135	The primary irqchip invokes the crossbar's callback which inturn allocates
	136	a free irq and configures the IP. Thus the peripheral interrupts are
	137	routed to one of the free irqchip interrupt lines.
89323f8c GS	138
	139	config KEYSTONE_IRQ
	140	tristate "Keystone 2 IRQ controller IP"
	141	depends on ARCH_KEYSTONE
	142	help
	143	Support for Texas Instruments Keystone 2 IRQ controller IP which
	144	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	145
	146	config MIPS_GIC
	147	bool
	148	select MIPS_CM