[deliverable/linux.git] / drivers / irqchip / exynos-combiner.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Combiner irqchip for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/mach/irq.h>

#include <plat/cpu.h>

#include "irqchip.h"

#define COMBINER_ENABLE_SET	0x0
#define COMBINER_ENABLE_CLEAR	0x4
#define COMBINER_INT_STATUS	0xC

#define IRQ_IN_COMBINER		8

static DEFINE_SPINLOCK(irq_controller_lock);

struct combiner_chip_data {
	unsigned int irq_offset;
	unsigned int irq_mask;
	void __iomem *base;
	unsigned int parent_irq;
};

static struct irq_domain *combiner_irq_domain;

static inline void __iomem *combiner_base(struct irq_data *data)
{
	struct combiner_chip_data *combiner_data =
		irq_data_get_irq_chip_data(data);

	return combiner_data->base;
}

static void combiner_mask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}

static void combiner_unmask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->hwirq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}

static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned int cascade_irq, combiner_irq;
	unsigned long status;

	chained_irq_enter(chip, desc);

	spin_lock(&irq_controller_lock);
	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	spin_unlock(&irq_controller_lock);
	status &= chip_data->irq_mask;

	if (status == 0)
		goto out;

	combiner_irq = __ffs(status);

	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
	if (unlikely(cascade_irq >= NR_IRQS))
		do_bad_IRQ(cascade_irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	chained_irq_exit(chip, desc);
}

#ifdef CONFIG_SMP
static int combiner_set_affinity(struct irq_data *d,
				 const struct cpumask *mask_val, bool force)
{
	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);

	if (chip && chip->irq_set_affinity)
		return chip->irq_set_affinity(data, mask_val, force);
	else
		return -EINVAL;
}
#endif

static struct irq_chip combiner_chip = {
	.name			= "COMBINER",
	.irq_mask		= combiner_mask_irq,
	.irq_unmask		= combiner_unmask_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	= combiner_set_affinity,
#endif
};

static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
					unsigned int irq)
{
	if (irq_set_handler_data(irq, combiner_data) != 0)
		BUG();
	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}

static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
				     unsigned int combiner_nr,
				     void __iomem *base, unsigned int irq)
{
	combiner_data->base = base;
	combiner_data->irq_offset = irq_find_mapping(
		combiner_irq_domain, combiner_nr * IRQ_IN_COMBINER);
	combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
	combiner_data->parent_irq = irq;

	/* Disable all interrupts */
	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
}

#ifdef CONFIG_OF
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	if (d->of_node != controller)
		return -EINVAL;

	if (intsize < 2)
		return -EINVAL;

	*out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
	*out_type = 0;

	return 0;
}
#else
static int combiner_irq_domain_xlate(struct irq_domain *d,
				     struct device_node *controller,
				     const u32 *intspec, unsigned int intsize,
				     unsigned long *out_hwirq,
				     unsigned int *out_type)
{
	return -EINVAL;
}
#endif

static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
				   irq_hw_number_t hw)
{
	struct combiner_chip_data *combiner_data = d->host_data;

	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

static struct irq_domain_ops combiner_irq_domain_ops = {
	.xlate	= combiner_irq_domain_xlate,
	.map	= combiner_irq_domain_map,
};

static unsigned int exynos4x12_combiner_extra_irq(int group)
{
	switch (group) {
	case 16:
		return IRQ_SPI(107);
	case 17:
		return IRQ_SPI(108);
	case 18:
		return IRQ_SPI(48);
	case 19:
		return IRQ_SPI(42);
	default:
		return 0;
	}
}

void __init combiner_init(void __iomem *combiner_base,
			  struct device_node *np,
			  unsigned int max_nr)
{
	int i, irq, irq_base;
	unsigned int nr_irq;
	struct combiner_chip_data *combiner_data;

	nr_irq = max_nr * IRQ_IN_COMBINER;

	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
	if (IS_ERR_VALUE(irq_base)) {
		irq_base = COMBINER_IRQ(0, 0);
		pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
	}

	combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
	if (!combiner_data) {
		pr_warning("%s: could not allocate combiner data\n", __func__);
		return;
	}

	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
				&combiner_irq_domain_ops, combiner_data);
	if (WARN_ON(!combiner_irq_domain)) {
		pr_warning("%s: irq domain init failed\n", __func__);
		return;
	}

	for (i = 0; i < max_nr; i++) {
		if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
			irq = IRQ_SPI(i);
		else
			irq = exynos4x12_combiner_extra_irq(i);
#ifdef CONFIG_OF
		if (np)
			irq = irq_of_parse_and_map(np, i);
#endif
		combiner_init_one(&combiner_data[i], i,
				  combiner_base + (i >> 2) * 0x10, irq);
		combiner_cascade_irq(&combiner_data[i], irq);
	}
}

#ifdef CONFIG_OF
static int __init combiner_of_init(struct device_node *np,
				   struct device_node *parent)
{
	void __iomem *combiner_base;
	unsigned int max_nr = 20;

	combiner_base = of_iomap(np, 0);
	if (!combiner_base) {
		pr_err("%s: failed to map combiner registers\n", __func__);
		return -ENXIO;
	}

	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
		pr_info("%s: number of combiners not specified, "
			"setting default as %d.\n",
			__func__, max_nr);
	}

	combiner_init(combiner_base, np, max_nr);

	return 0;
}
IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
		combiner_of_init);
#endif
Commit	Line	Data
a900e5d9 RH	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Combiner irqchip for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/err.h>
	12	#include <linux/export.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
d34f03d4	15	#include <linux/slab.h>
a900e5d9 RH	16	#include <linux/irqdomain.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
	19	#include <asm/mach/irq.h>
	20
	21	#include <plat/cpu.h>
	22
	23	#include "irqchip.h"
	24
	25	#define COMBINER_ENABLE_SET 0x0
	26	#define COMBINER_ENABLE_CLEAR 0x4
	27	#define COMBINER_INT_STATUS 0xC
	28
6761dcfe AB	29	#define IRQ_IN_COMBINER 8
6761dcfe AB	30
a900e5d9 RH	31	static DEFINE_SPINLOCK(irq_controller_lock);
	32
	33	struct combiner_chip_data {
	34	unsigned int irq_offset;
	35	unsigned int irq_mask;
	36	void __iomem *base;
df7ef462	37	unsigned int parent_irq;
a900e5d9 RH	38	};
	39
	40	static struct irq_domain *combiner_irq_domain;
a900e5d9 RH	41
	42	static inline void __iomem combiner_base(struct irq_data data)
	43	{
	44	struct combiner_chip_data *combiner_data =
	45	irq_data_get_irq_chip_data(data);
	46
	47	return combiner_data->base;
	48	}
	49
	50	static void combiner_mask_irq(struct irq_data *data)
	51	{
	52	u32 mask = 1 << (data->hwirq % 32);
	53
	54	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
	55	}
	56
	57	static void combiner_unmask_irq(struct irq_data *data)
	58	{
	59	u32 mask = 1 << (data->hwirq % 32);
	60
	61	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
	62	}
	63
	64	static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
	65	{
	66	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	67	struct irq_chip *chip = irq_get_chip(irq);
	68	unsigned int cascade_irq, combiner_irq;
	69	unsigned long status;
	70
	71	chained_irq_enter(chip, desc);
	72
	73	spin_lock(&irq_controller_lock);
	74	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	75	spin_unlock(&irq_controller_lock);
	76	status &= chip_data->irq_mask;
	77
	78	if (status == 0)
	79	goto out;
	80
	81	combiner_irq = __ffs(status);
	82
	83	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
	84	if (unlikely(cascade_irq >= NR_IRQS))
	85	do_bad_IRQ(cascade_irq, desc);
	86	else
	87	generic_handle_irq(cascade_irq);
	88
	89	out:
	90	chained_irq_exit(chip, desc);
	91	}
	92
df7ef462 CP	93	#ifdef CONFIG_SMP
	94	static int combiner_set_affinity(struct irq_data *d,
	95	const struct cpumask *mask_val, bool force)
	96	{
	97	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
	98	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
	99	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
	100
	101	if (chip && chip->irq_set_affinity)
	102	return chip->irq_set_affinity(data, mask_val, force);
	103	else
	104	return -EINVAL;
	105	}
	106	#endif
	107
a900e5d9	108	static struct irq_chip combiner_chip = {
df7ef462 CP	109	.name = "COMBINER",
	110	.irq_mask = combiner_mask_irq,
	111	.irq_unmask = combiner_unmask_irq,
	112	#ifdef CONFIG_SMP
	113	.irq_set_affinity = combiner_set_affinity,
	114	#endif
a900e5d9 RH	115	};
a900e5d9 RH	116
d34f03d4	117	static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
4e164dc5 CP	118	unsigned int irq)
4e164dc5 CP	119	{
d34f03d4	120	if (irq_set_handler_data(irq, combiner_data) != 0)
a900e5d9 RH	121	BUG();
	122	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
	123	}
	124
d34f03d4 AB	125	static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
d34f03d4 AB	126	unsigned int combiner_nr,
df7ef462	127	void __iomem *base, unsigned int irq)
a900e5d9	128	{
d34f03d4 AB	129	combiner_data->base = base;
d34f03d4 AB	130	combiner_data->irq_offset = irq_find_mapping(
6761dcfe	131	combiner_irq_domain, combiner_nr * IRQ_IN_COMBINER);
d34f03d4 AB	132	combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
d34f03d4 AB	133	combiner_data->parent_irq = irq;
a900e5d9 RH	134
a900e5d9 RH	135	/* Disable all interrupts */
d34f03d4	136	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
a900e5d9 RH	137	}
	138
	139	#ifdef CONFIG_OF
	140	static int combiner_irq_domain_xlate(struct irq_domain *d,
	141	struct device_node *controller,
	142	const u32 *intspec, unsigned int intsize,
	143	unsigned long *out_hwirq,
	144	unsigned int *out_type)
	145	{
	146	if (d->of_node != controller)
	147	return -EINVAL;
	148
	149	if (intsize < 2)
	150	return -EINVAL;
	151
6761dcfe	152	out_hwirq = intspec[0] IRQ_IN_COMBINER + intspec[1];
a900e5d9 RH	153	*out_type = 0;
	154
	155	return 0;
	156	}
	157	#else
	158	static int combiner_irq_domain_xlate(struct irq_domain *d,
	159	struct device_node *controller,
	160	const u32 *intspec, unsigned int intsize,
	161	unsigned long *out_hwirq,
	162	unsigned int *out_type)
	163	{
	164	return -EINVAL;
	165	}
	166	#endif
	167
	168	static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
	169	irq_hw_number_t hw)
	170	{
d34f03d4 AB	171	struct combiner_chip_data *combiner_data = d->host_data;
d34f03d4 AB	172
a900e5d9 RH	173	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
	174	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
	175	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	176
	177	return 0;
	178	}
	179
	180	static struct irq_domain_ops combiner_irq_domain_ops = {
	181	.xlate = combiner_irq_domain_xlate,
	182	.map = combiner_irq_domain_map,
	183	};
	184
4e164dc5 CP	185	static unsigned int exynos4x12_combiner_extra_irq(int group)
	186	{
	187	switch (group) {
	188	case 16:
	189	return IRQ_SPI(107);
	190	case 17:
	191	return IRQ_SPI(108);
	192	case 18:
	193	return IRQ_SPI(48);
	194	case 19:
	195	return IRQ_SPI(42);
	196	default:
	197	return 0;
	198	}
	199	}
	200
a900e5d9	201	void __init combiner_init(void __iomem *combiner_base,
6761dcfe AB	202	struct device_node *np,
6761dcfe AB	203	unsigned int max_nr)
a900e5d9 RH	204	{
a900e5d9 RH	205	int i, irq, irq_base;
6761dcfe	206	unsigned int nr_irq;
d34f03d4	207	struct combiner_chip_data *combiner_data;
a900e5d9	208
6761dcfe	209	nr_irq = max_nr * IRQ_IN_COMBINER;
a900e5d9 RH	210
	211	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
	212	if (IS_ERR_VALUE(irq_base)) {
	213	irq_base = COMBINER_IRQ(0, 0);
	214	pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
	215	}
	216
d34f03d4 AB	217	combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
	218	if (!combiner_data) {
	219	pr_warning("%s: could not allocate combiner data\n", __func__);
	220	return;
	221	}
	222
a900e5d9	223	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
d34f03d4	224	&combiner_irq_domain_ops, combiner_data);
a900e5d9 RH	225	if (WARN_ON(!combiner_irq_domain)) {
	226	pr_warning("%s: irq domain init failed\n", __func__);
	227	return;
	228	}
	229
	230	for (i = 0; i < max_nr; i++) {
4e164dc5 CP	231	if (i < EXYNOS4210_MAX_COMBINER_NR \|\| soc_is_exynos5250())
	232	irq = IRQ_SPI(i);
	233	else
	234	irq = exynos4x12_combiner_extra_irq(i);
a900e5d9 RH	235	#ifdef CONFIG_OF
	236	if (np)
	237	irq = irq_of_parse_and_map(np, i);
	238	#endif
d34f03d4 AB	239	combiner_init_one(&combiner_data[i], i,
	240	combiner_base + (i >> 2) * 0x10, irq);
	241	combiner_cascade_irq(&combiner_data[i], irq);
a900e5d9 RH	242	}
	243	}
	244
	245	#ifdef CONFIG_OF
	246	static int __init combiner_of_init(struct device_node *np,
	247	struct device_node *parent)
	248	{
	249	void __iomem *combiner_base;
6761dcfe	250	unsigned int max_nr = 20;
a900e5d9 RH	251
	252	combiner_base = of_iomap(np, 0);
	253	if (!combiner_base) {
	254	pr_err("%s: failed to map combiner registers\n", __func__);
	255	return -ENXIO;
	256	}
	257
6761dcfe AB	258	if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
	259	pr_info("%s: number of combiners not specified, "
	260	"setting default as %d.\n",
	261	__func__, max_nr);
	262	}
	263
	264	combiner_init(combiner_base, np, max_nr);
a900e5d9 RH	265
	266	return 0;
	267	}
	268	IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
	269	combiner_of_init);
	270	#endif