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9ae6f740 TP |
1 | /* |
2 | * Marvell Armada 370 and Armada XP SoC IRQ handling | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * Ben Dooks <ben.dooks@codethink.co.uk> | |
10 | * | |
11 | * This file is licensed under the terms of the GNU General Public | |
12 | * License version 2. This program is licensed "as is" without any | |
13 | * warranty of any kind, whether express or implied. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/interrupt.h> | |
41a83e06 | 21 | #include <linux/irqchip.h> |
bc69b8ad | 22 | #include <linux/irqchip/chained_irq.h> |
d7df84b3 | 23 | #include <linux/cpu.h> |
9ae6f740 TP |
24 | #include <linux/io.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
31f614ed | 27 | #include <linux/of_pci.h> |
9ae6f740 | 28 | #include <linux/irqdomain.h> |
31f614ed | 29 | #include <linux/slab.h> |
0f077eb5 | 30 | #include <linux/syscore_ops.h> |
31f614ed | 31 | #include <linux/msi.h> |
9ae6f740 TP |
32 | #include <asm/mach/arch.h> |
33 | #include <asm/exception.h> | |
344e873e | 34 | #include <asm/smp_plat.h> |
9339d432 TP |
35 | #include <asm/mach/irq.h> |
36 | ||
9ae6f740 TP |
37 | /* Interrupt Controller Registers Map */ |
38 | #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) | |
39 | #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) | |
28da06df MR |
40 | #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) |
41 | #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) | |
9ae6f740 | 42 | |
f3e16ccd | 43 | #define ARMADA_370_XP_INT_CONTROL (0x00) |
9ae6f740 TP |
44 | #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) |
45 | #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) | |
3202bf01 | 46 | #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) |
8cc3cfc5 | 47 | #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF |
758e8366 | 48 | #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) |
9ae6f740 TP |
49 | |
50 | #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) | |
bc69b8ad | 51 | #define ARMADA_375_PPI_CAUSE (0x10) |
9ae6f740 | 52 | |
344e873e GC |
53 | #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) |
54 | #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) | |
55 | #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) | |
56 | ||
3202bf01 GC |
57 | #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) |
58 | ||
5ec69017 TP |
59 | #define IPI_DOORBELL_START (0) |
60 | #define IPI_DOORBELL_END (8) | |
61 | #define IPI_DOORBELL_MASK 0xFF | |
31f614ed TP |
62 | #define PCI_MSI_DOORBELL_START (16) |
63 | #define PCI_MSI_DOORBELL_NR (16) | |
64 | #define PCI_MSI_DOORBELL_END (32) | |
65 | #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 | |
344e873e | 66 | |
9ae6f740 TP |
67 | static void __iomem *per_cpu_int_base; |
68 | static void __iomem *main_int_base; | |
69 | static struct irq_domain *armada_370_xp_mpic_domain; | |
0f077eb5 | 70 | static u32 doorbell_mask_reg; |
5724be84 | 71 | static int parent_irq; |
31f614ed TP |
72 | #ifdef CONFIG_PCI_MSI |
73 | static struct irq_domain *armada_370_xp_msi_domain; | |
fcc392d5 | 74 | static struct irq_domain *armada_370_xp_msi_inner_domain; |
31f614ed TP |
75 | static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); |
76 | static DEFINE_MUTEX(msi_used_lock); | |
77 | static phys_addr_t msi_doorbell_addr; | |
78 | #endif | |
9ae6f740 | 79 | |
2c299de5 EG |
80 | static inline bool is_percpu_irq(irq_hw_number_t irq) |
81 | { | |
080481f9 | 82 | if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) |
2c299de5 | 83 | return true; |
080481f9 MR |
84 | |
85 | return false; | |
2c299de5 EG |
86 | } |
87 | ||
3202bf01 GC |
88 | /* |
89 | * In SMP mode: | |
90 | * For shared global interrupts, mask/unmask global enable bit | |
097ef18d | 91 | * For CPU interrupts, mask/unmask the calling CPU's bit |
3202bf01 | 92 | */ |
9ae6f740 TP |
93 | static void armada_370_xp_irq_mask(struct irq_data *d) |
94 | { | |
3202bf01 GC |
95 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
96 | ||
2c299de5 | 97 | if (!is_percpu_irq(hwirq)) |
3202bf01 GC |
98 | writel(hwirq, main_int_base + |
99 | ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | |
100 | else | |
101 | writel(hwirq, per_cpu_int_base + | |
102 | ARMADA_370_XP_INT_SET_MASK_OFFS); | |
9ae6f740 TP |
103 | } |
104 | ||
105 | static void armada_370_xp_irq_unmask(struct irq_data *d) | |
106 | { | |
3202bf01 GC |
107 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
108 | ||
2c299de5 | 109 | if (!is_percpu_irq(hwirq)) |
3202bf01 GC |
110 | writel(hwirq, main_int_base + |
111 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); | |
112 | else | |
113 | writel(hwirq, per_cpu_int_base + | |
114 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
9ae6f740 TP |
115 | } |
116 | ||
31f614ed TP |
117 | #ifdef CONFIG_PCI_MSI |
118 | ||
fcc392d5 | 119 | static struct irq_chip armada_370_xp_msi_irq_chip = { |
f692a172 | 120 | .name = "MPIC MSI", |
fcc392d5 TP |
121 | .irq_mask = pci_msi_mask_irq, |
122 | .irq_unmask = pci_msi_unmask_irq, | |
123 | }; | |
31f614ed | 124 | |
fcc392d5 | 125 | static struct msi_domain_info armada_370_xp_msi_domain_info = { |
a71b9412 TP |
126 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
127 | MSI_FLAG_MULTI_PCI_MSI), | |
fcc392d5 TP |
128 | .chip = &armada_370_xp_msi_irq_chip, |
129 | }; | |
31f614ed | 130 | |
fcc392d5 | 131 | static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
31f614ed | 132 | { |
fcc392d5 TP |
133 | msg->address_lo = lower_32_bits(msi_doorbell_addr); |
134 | msg->address_hi = upper_32_bits(msi_doorbell_addr); | |
135 | msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START); | |
31f614ed TP |
136 | } |
137 | ||
fcc392d5 TP |
138 | static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, |
139 | const struct cpumask *mask, bool force) | |
31f614ed | 140 | { |
fcc392d5 TP |
141 | return -EINVAL; |
142 | } | |
31f614ed | 143 | |
fcc392d5 | 144 | static struct irq_chip armada_370_xp_msi_bottom_irq_chip = { |
f692a172 | 145 | .name = "MPIC MSI", |
fcc392d5 TP |
146 | .irq_compose_msi_msg = armada_370_xp_compose_msi_msg, |
147 | .irq_set_affinity = armada_370_xp_msi_set_affinity, | |
148 | }; | |
3930115e | 149 | |
fcc392d5 TP |
150 | static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq, |
151 | unsigned int nr_irqs, void *args) | |
152 | { | |
a71b9412 | 153 | int hwirq, i; |
31f614ed | 154 | |
fcc392d5 | 155 | mutex_lock(&msi_used_lock); |
a71b9412 TP |
156 | |
157 | hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR, | |
158 | 0, nr_irqs, 0); | |
fcc392d5 TP |
159 | if (hwirq >= PCI_MSI_DOORBELL_NR) { |
160 | mutex_unlock(&msi_used_lock); | |
161 | return -ENOSPC; | |
31f614ed TP |
162 | } |
163 | ||
a71b9412 | 164 | bitmap_set(msi_used, hwirq, nr_irqs); |
fcc392d5 | 165 | mutex_unlock(&msi_used_lock); |
31f614ed | 166 | |
a71b9412 TP |
167 | for (i = 0; i < nr_irqs; i++) { |
168 | irq_domain_set_info(domain, virq + i, hwirq + i, | |
169 | &armada_370_xp_msi_bottom_irq_chip, | |
170 | domain->host_data, handle_simple_irq, | |
171 | NULL, NULL); | |
172 | } | |
31f614ed | 173 | |
fcc392d5 | 174 | return hwirq; |
31f614ed TP |
175 | } |
176 | ||
fcc392d5 TP |
177 | static void armada_370_xp_msi_free(struct irq_domain *domain, |
178 | unsigned int virq, unsigned int nr_irqs) | |
31f614ed | 179 | { |
fcc392d5 | 180 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
31f614ed | 181 | |
fcc392d5 | 182 | mutex_lock(&msi_used_lock); |
a71b9412 | 183 | bitmap_clear(msi_used, d->hwirq, nr_irqs); |
fcc392d5 | 184 | mutex_unlock(&msi_used_lock); |
31f614ed TP |
185 | } |
186 | ||
fcc392d5 TP |
187 | static const struct irq_domain_ops armada_370_xp_msi_domain_ops = { |
188 | .alloc = armada_370_xp_msi_alloc, | |
189 | .free = armada_370_xp_msi_free, | |
31f614ed TP |
190 | }; |
191 | ||
192 | static int armada_370_xp_msi_init(struct device_node *node, | |
193 | phys_addr_t main_int_phys_base) | |
194 | { | |
31f614ed | 195 | u32 reg; |
31f614ed TP |
196 | |
197 | msi_doorbell_addr = main_int_phys_base + | |
198 | ARMADA_370_XP_SW_TRIG_INT_OFFS; | |
199 | ||
fcc392d5 TP |
200 | armada_370_xp_msi_inner_domain = |
201 | irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, | |
202 | &armada_370_xp_msi_domain_ops, NULL); | |
203 | if (!armada_370_xp_msi_inner_domain) | |
31f614ed TP |
204 | return -ENOMEM; |
205 | ||
31f614ed | 206 | armada_370_xp_msi_domain = |
fcc392d5 TP |
207 | pci_msi_create_irq_domain(of_node_to_fwnode(node), |
208 | &armada_370_xp_msi_domain_info, | |
209 | armada_370_xp_msi_inner_domain); | |
31f614ed | 210 | if (!armada_370_xp_msi_domain) { |
fcc392d5 | 211 | irq_domain_remove(armada_370_xp_msi_inner_domain); |
31f614ed TP |
212 | return -ENOMEM; |
213 | } | |
214 | ||
31f614ed TP |
215 | reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) |
216 | | PCI_MSI_DOORBELL_MASK; | |
217 | ||
218 | writel(reg, per_cpu_int_base + | |
219 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); | |
220 | ||
221 | /* Unmask IPI interrupt */ | |
222 | writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | #else | |
227 | static inline int armada_370_xp_msi_init(struct device_node *node, | |
228 | phys_addr_t main_int_phys_base) | |
229 | { | |
230 | return 0; | |
231 | } | |
232 | #endif | |
233 | ||
344e873e | 234 | #ifdef CONFIG_SMP |
19e61d41 AE |
235 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
236 | ||
344e873e GC |
237 | static int armada_xp_set_affinity(struct irq_data *d, |
238 | const struct cpumask *mask_val, bool force) | |
239 | { | |
3202bf01 | 240 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
8cc3cfc5 | 241 | unsigned long reg, mask; |
3202bf01 GC |
242 | int cpu; |
243 | ||
8cc3cfc5 TG |
244 | /* Select a single core from the affinity mask which is online */ |
245 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
246 | mask = 1UL << cpu_logical_map(cpu); | |
3202bf01 GC |
247 | |
248 | raw_spin_lock(&irq_controller_lock); | |
3202bf01 | 249 | reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); |
8cc3cfc5 | 250 | reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; |
3202bf01 | 251 | writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); |
3202bf01 GC |
252 | raw_spin_unlock(&irq_controller_lock); |
253 | ||
1dacf194 | 254 | return IRQ_SET_MASK_OK; |
344e873e GC |
255 | } |
256 | #endif | |
257 | ||
9ae6f740 | 258 | static struct irq_chip armada_370_xp_irq_chip = { |
f692a172 | 259 | .name = "MPIC", |
9ae6f740 TP |
260 | .irq_mask = armada_370_xp_irq_mask, |
261 | .irq_mask_ack = armada_370_xp_irq_mask, | |
262 | .irq_unmask = armada_370_xp_irq_unmask, | |
344e873e GC |
263 | #ifdef CONFIG_SMP |
264 | .irq_set_affinity = armada_xp_set_affinity, | |
265 | #endif | |
0d8e1d80 | 266 | .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, |
9ae6f740 TP |
267 | }; |
268 | ||
269 | static int armada_370_xp_mpic_irq_map(struct irq_domain *h, | |
270 | unsigned int virq, irq_hw_number_t hw) | |
271 | { | |
272 | armada_370_xp_irq_mask(irq_get_irq_data(virq)); | |
2c299de5 | 273 | if (!is_percpu_irq(hw)) |
600468d0 GC |
274 | writel(hw, per_cpu_int_base + |
275 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
276 | else | |
277 | writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); | |
9ae6f740 | 278 | irq_set_status_flags(virq, IRQ_LEVEL); |
3a6f08a3 | 279 | |
2c299de5 | 280 | if (is_percpu_irq(hw)) { |
3a6f08a3 GC |
281 | irq_set_percpu_devid(virq); |
282 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | |
283 | handle_percpu_devid_irq); | |
284 | ||
285 | } else { | |
286 | irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, | |
287 | handle_level_irq); | |
288 | } | |
d17cab44 | 289 | irq_set_probe(virq); |
353d6d6c | 290 | irq_clear_status_flags(virq, IRQ_NOAUTOEN); |
9ae6f740 TP |
291 | |
292 | return 0; | |
293 | } | |
294 | ||
d7df84b3 | 295 | static void armada_xp_mpic_smp_cpu_init(void) |
344e873e | 296 | { |
b73842b7 TP |
297 | u32 control; |
298 | int nr_irqs, i; | |
299 | ||
300 | control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); | |
301 | nr_irqs = (control >> 2) & 0x3ff; | |
302 | ||
303 | for (i = 0; i < nr_irqs; i++) | |
304 | writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); | |
305 | ||
344e873e GC |
306 | /* Clear pending IPIs */ |
307 | writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | |
308 | ||
309 | /* Enable first 8 IPIs */ | |
5ec69017 | 310 | writel(IPI_DOORBELL_MASK, per_cpu_int_base + |
344e873e GC |
311 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); |
312 | ||
313 | /* Unmask IPI interrupt */ | |
314 | writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
315 | } | |
d7df84b3 | 316 | |
28da06df MR |
317 | static void armada_xp_mpic_perf_init(void) |
318 | { | |
319 | unsigned long cpuid = cpu_logical_map(smp_processor_id()); | |
320 | ||
321 | /* Enable Performance Counter Overflow interrupts */ | |
322 | writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), | |
323 | per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); | |
324 | } | |
325 | ||
933a24b0 EG |
326 | #ifdef CONFIG_SMP |
327 | static void armada_mpic_send_doorbell(const struct cpumask *mask, | |
328 | unsigned int irq) | |
329 | { | |
330 | int cpu; | |
331 | unsigned long map = 0; | |
332 | ||
333 | /* Convert our logical CPU mask into a physical one. */ | |
334 | for_each_cpu(cpu, mask) | |
335 | map |= 1 << cpu_logical_map(cpu); | |
336 | ||
337 | /* | |
338 | * Ensure that stores to Normal memory are visible to the | |
339 | * other CPUs before issuing the IPI. | |
340 | */ | |
341 | dsb(); | |
342 | ||
343 | /* submit softirq */ | |
344 | writel((map << 8) | irq, main_int_base + | |
345 | ARMADA_370_XP_SW_TRIG_INT_OFFS); | |
346 | } | |
347 | ||
cb5ff2d2 | 348 | static int armada_xp_mpic_starting_cpu(unsigned int cpu) |
d7df84b3 | 349 | { |
cb5ff2d2 RC |
350 | armada_xp_mpic_perf_init(); |
351 | armada_xp_mpic_smp_cpu_init(); | |
352 | return 0; | |
d7df84b3 TP |
353 | } |
354 | ||
cb5ff2d2 | 355 | static int mpic_cascaded_starting_cpu(unsigned int cpu) |
5724be84 | 356 | { |
cb5ff2d2 RC |
357 | armada_xp_mpic_perf_init(); |
358 | enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); | |
359 | return 0; | |
5724be84 | 360 | } |
c76c15e6 | 361 | #endif |
344e873e | 362 | |
96009736 | 363 | static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = { |
9ae6f740 TP |
364 | .map = armada_370_xp_mpic_irq_map, |
365 | .xlate = irq_domain_xlate_onecell, | |
366 | }; | |
367 | ||
9b8cf779 | 368 | #ifdef CONFIG_PCI_MSI |
bc69b8ad | 369 | static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) |
9b8cf779 EG |
370 | { |
371 | u32 msimask, msinr; | |
372 | ||
373 | msimask = readl_relaxed(per_cpu_int_base + | |
374 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) | |
375 | & PCI_MSI_DOORBELL_MASK; | |
376 | ||
377 | writel(~msimask, per_cpu_int_base + | |
378 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); | |
379 | ||
380 | for (msinr = PCI_MSI_DOORBELL_START; | |
381 | msinr < PCI_MSI_DOORBELL_END; msinr++) { | |
382 | int irq; | |
383 | ||
384 | if (!(msimask & BIT(msinr))) | |
385 | continue; | |
386 | ||
e89c6a06 | 387 | if (is_chained) { |
fcc392d5 | 388 | irq = irq_find_mapping(armada_370_xp_msi_inner_domain, |
0636bab6 | 389 | msinr - PCI_MSI_DOORBELL_START); |
bc69b8ad | 390 | generic_handle_irq(irq); |
e89c6a06 | 391 | } else { |
0636bab6 | 392 | irq = msinr - PCI_MSI_DOORBELL_START; |
fcc392d5 | 393 | handle_domain_irq(armada_370_xp_msi_inner_domain, |
e89c6a06 MZ |
394 | irq, regs); |
395 | } | |
9b8cf779 EG |
396 | } |
397 | } | |
398 | #else | |
bc69b8ad | 399 | static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} |
9b8cf779 EG |
400 | #endif |
401 | ||
bd0b9ac4 | 402 | static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) |
bc69b8ad | 403 | { |
5b29264c | 404 | struct irq_chip *chip = irq_desc_get_chip(desc); |
758e8366 | 405 | unsigned long irqmap, irqn, irqsrc, cpuid; |
bc69b8ad EG |
406 | unsigned int cascade_irq; |
407 | ||
408 | chained_irq_enter(chip, desc); | |
409 | ||
410 | irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); | |
758e8366 | 411 | cpuid = cpu_logical_map(smp_processor_id()); |
bc69b8ad EG |
412 | |
413 | for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { | |
758e8366 GJ |
414 | irqsrc = readl_relaxed(main_int_base + |
415 | ARMADA_370_XP_INT_SOURCE_CTL(irqn)); | |
416 | ||
417 | /* Check if the interrupt is not masked on current CPU. | |
418 | * Test IRQ (0-1) and FIQ (8-9) mask bits. | |
419 | */ | |
420 | if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) | |
421 | continue; | |
422 | ||
423 | if (irqn == 1) { | |
424 | armada_370_xp_handle_msi_irq(NULL, true); | |
425 | continue; | |
426 | } | |
427 | ||
bc69b8ad EG |
428 | cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn); |
429 | generic_handle_irq(cascade_irq); | |
430 | } | |
431 | ||
432 | chained_irq_exit(chip, desc); | |
433 | } | |
434 | ||
8783dd3a | 435 | static void __exception_irq_entry |
9339d432 | 436 | armada_370_xp_handle_irq(struct pt_regs *regs) |
9ae6f740 TP |
437 | { |
438 | u32 irqstat, irqnr; | |
439 | ||
440 | do { | |
441 | irqstat = readl_relaxed(per_cpu_int_base + | |
442 | ARMADA_370_XP_CPU_INTACK_OFFS); | |
443 | irqnr = irqstat & 0x3FF; | |
444 | ||
344e873e GC |
445 | if (irqnr > 1022) |
446 | break; | |
447 | ||
31f614ed | 448 | if (irqnr > 1) { |
e89c6a06 MZ |
449 | handle_domain_irq(armada_370_xp_mpic_domain, |
450 | irqnr, regs); | |
9ae6f740 TP |
451 | continue; |
452 | } | |
31f614ed | 453 | |
31f614ed | 454 | /* MSI handling */ |
9b8cf779 | 455 | if (irqnr == 1) |
bc69b8ad | 456 | armada_370_xp_handle_msi_irq(regs, false); |
31f614ed | 457 | |
344e873e GC |
458 | #ifdef CONFIG_SMP |
459 | /* IPI Handling */ | |
460 | if (irqnr == 0) { | |
461 | u32 ipimask, ipinr; | |
462 | ||
463 | ipimask = readl_relaxed(per_cpu_int_base + | |
464 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) | |
5ec69017 | 465 | & IPI_DOORBELL_MASK; |
344e873e | 466 | |
a6f089e9 | 467 | writel(~ipimask, per_cpu_int_base + |
344e873e GC |
468 | ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); |
469 | ||
470 | /* Handle all pending doorbells */ | |
5ec69017 TP |
471 | for (ipinr = IPI_DOORBELL_START; |
472 | ipinr < IPI_DOORBELL_END; ipinr++) { | |
344e873e GC |
473 | if (ipimask & (0x1 << ipinr)) |
474 | handle_IPI(ipinr, regs); | |
475 | } | |
476 | continue; | |
477 | } | |
478 | #endif | |
9ae6f740 | 479 | |
9ae6f740 TP |
480 | } while (1); |
481 | } | |
482 | ||
0f077eb5 TP |
483 | static int armada_370_xp_mpic_suspend(void) |
484 | { | |
485 | doorbell_mask_reg = readl(per_cpu_int_base + | |
486 | ARMADA_370_XP_IN_DRBEL_MSK_OFFS); | |
487 | return 0; | |
488 | } | |
489 | ||
490 | static void armada_370_xp_mpic_resume(void) | |
491 | { | |
492 | int nirqs; | |
493 | irq_hw_number_t irq; | |
494 | ||
495 | /* Re-enable interrupts */ | |
496 | nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; | |
497 | for (irq = 0; irq < nirqs; irq++) { | |
498 | struct irq_data *data; | |
499 | int virq; | |
500 | ||
501 | virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); | |
502 | if (virq == 0) | |
503 | continue; | |
504 | ||
080481f9 | 505 | if (!is_percpu_irq(irq)) |
0f077eb5 TP |
506 | writel(irq, per_cpu_int_base + |
507 | ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
508 | else | |
509 | writel(irq, main_int_base + | |
510 | ARMADA_370_XP_INT_SET_ENABLE_OFFS); | |
511 | ||
512 | data = irq_get_irq_data(virq); | |
513 | if (!irqd_irq_disabled(data)) | |
514 | armada_370_xp_irq_unmask(data); | |
515 | } | |
516 | ||
517 | /* Reconfigure doorbells for IPIs and MSIs */ | |
518 | writel(doorbell_mask_reg, | |
519 | per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); | |
520 | if (doorbell_mask_reg & IPI_DOORBELL_MASK) | |
521 | writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
522 | if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) | |
523 | writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | |
524 | } | |
525 | ||
6c880902 | 526 | static struct syscore_ops armada_370_xp_mpic_syscore_ops = { |
0f077eb5 TP |
527 | .suspend = armada_370_xp_mpic_suspend, |
528 | .resume = armada_370_xp_mpic_resume, | |
529 | }; | |
530 | ||
b313ada8 TP |
531 | static int __init armada_370_xp_mpic_of_init(struct device_node *node, |
532 | struct device_node *parent) | |
9ae6f740 | 533 | { |
627dfcc2 | 534 | struct resource main_int_res, per_cpu_int_res; |
5724be84 | 535 | int nr_irqs, i; |
b313ada8 TP |
536 | u32 control; |
537 | ||
627dfcc2 TP |
538 | BUG_ON(of_address_to_resource(node, 0, &main_int_res)); |
539 | BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); | |
b313ada8 | 540 | |
627dfcc2 TP |
541 | BUG_ON(!request_mem_region(main_int_res.start, |
542 | resource_size(&main_int_res), | |
543 | node->full_name)); | |
544 | BUG_ON(!request_mem_region(per_cpu_int_res.start, | |
545 | resource_size(&per_cpu_int_res), | |
546 | node->full_name)); | |
547 | ||
548 | main_int_base = ioremap(main_int_res.start, | |
549 | resource_size(&main_int_res)); | |
b313ada8 | 550 | BUG_ON(!main_int_base); |
627dfcc2 TP |
551 | |
552 | per_cpu_int_base = ioremap(per_cpu_int_res.start, | |
553 | resource_size(&per_cpu_int_res)); | |
b313ada8 TP |
554 | BUG_ON(!per_cpu_int_base); |
555 | ||
556 | control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); | |
b73842b7 TP |
557 | nr_irqs = (control >> 2) & 0x3ff; |
558 | ||
559 | for (i = 0; i < nr_irqs; i++) | |
560 | writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); | |
b313ada8 TP |
561 | |
562 | armada_370_xp_mpic_domain = | |
b73842b7 | 563 | irq_domain_add_linear(node, nr_irqs, |
b313ada8 | 564 | &armada_370_xp_mpic_irq_ops, NULL); |
627dfcc2 | 565 | BUG_ON(!armada_370_xp_mpic_domain); |
fcc392d5 | 566 | armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED; |
b313ada8 | 567 | |
933a24b0 | 568 | /* Setup for the boot CPU */ |
28da06df | 569 | armada_xp_mpic_perf_init(); |
b313ada8 | 570 | armada_xp_mpic_smp_cpu_init(); |
b313ada8 | 571 | |
31f614ed TP |
572 | armada_370_xp_msi_init(node, main_int_res.start); |
573 | ||
bc69b8ad EG |
574 | parent_irq = irq_of_parse_and_map(node, 0); |
575 | if (parent_irq <= 0) { | |
576 | irq_set_default_host(armada_370_xp_mpic_domain); | |
577 | set_handle_irq(armada_370_xp_handle_irq); | |
ef37d337 TP |
578 | #ifdef CONFIG_SMP |
579 | set_smp_cross_call(armada_mpic_send_doorbell); | |
cb5ff2d2 RC |
580 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, |
581 | "AP_IRQ_ARMADA_XP_STARTING", | |
582 | armada_xp_mpic_starting_cpu, NULL); | |
ef37d337 | 583 | #endif |
bc69b8ad | 584 | } else { |
5724be84 | 585 | #ifdef CONFIG_SMP |
cb5ff2d2 RC |
586 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING, |
587 | "AP_IRQ_ARMADA_CASC_STARTING", | |
588 | mpic_cascaded_starting_cpu, NULL); | |
5724be84 | 589 | #endif |
bc69b8ad EG |
590 | irq_set_chained_handler(parent_irq, |
591 | armada_370_xp_mpic_handle_cascade_irq); | |
592 | } | |
b313ada8 | 593 | |
0f077eb5 TP |
594 | register_syscore_ops(&armada_370_xp_mpic_syscore_ops); |
595 | ||
b313ada8 | 596 | return 0; |
9ae6f740 | 597 | } |
b313ada8 | 598 | |
9339d432 | 599 | IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); |