[deliverable/linux.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

#include "irqchip.h"

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static int armada_370_xp_alloc_msi(void)
{
	int hwirq;

	mutex_lock(&msi_used_lock);
	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	if (hwirq >= PCI_MSI_DOORBELL_NR)
		hwirq = -ENOSPC;
	else
		set_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);

	return hwirq;
}

static void armada_370_xp_free_msi(int hwirq)
{
	mutex_lock(&msi_used_lock);
	if (!test_bit(hwirq, msi_used))
		pr_err("trying to free unused MSI#%d\n", hwirq);
	else
		clear_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);
}

static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
				       struct pci_dev *pdev,
				       struct msi_desc *desc)
{
	struct msi_msg msg;
	irq_hw_number_t hwirq;
	int virq;

	hwirq = armada_370_xp_alloc_msi();
	if (hwirq < 0)
		return hwirq;

	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	if (!virq) {
		armada_370_xp_free_msi(hwirq);
		return -EINVAL;
	}

	irq_set_msi_desc(virq, desc);

	msg.address_lo = msi_doorbell_addr;
	msg.address_hi = 0;
	msg.data = 0xf00 | (hwirq + 16);

	write_msi_msg(virq, &msg);
	return 0;
}

static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
					   unsigned int irq)
{
	struct irq_data *d = irq_get_irq_data(irq);
	irq_dispose_mapping(irq);
	armada_370_xp_free_msi(d->hwirq);
}

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "armada_370_xp_msi_irq",
	.irq_enable = unmask_msi_irq,
	.irq_disable = mask_msi_irq,
	.irq_mask = mask_msi_irq,
	.irq_unmask = unmask_msi_irq,
};

static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
				 handle_simple_irq);
	set_irq_flags(virq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	.map = armada_370_xp_msi_map,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	struct msi_chip *msi_chip;
	u32 reg;
	int ret;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	if (!msi_chip)
		return -ENOMEM;

	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	msi_chip->of_node = node;

	armada_370_xp_msi_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_irq_ops,
				      NULL);
	if (!armada_370_xp_msi_domain) {
		kfree(msi_chip);
		return -ENOMEM;
	}

	ret = of_pci_msi_chip_add(msi_chip);
	if (ret < 0) {
		irq_domain_remove(armada_370_xp_msi_domain);
		kfree(msi_chip);
		return ret;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	unsigned long reg;
	unsigned long new_mask = 0;
	unsigned long online_mask = 0;
	unsigned long count = 0;
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	int cpu;

	for_each_cpu(cpu, mask_val) {
		new_mask |= 1 << cpu_logical_map(cpu);
		count++;
	}

	/*
	 * Forbid mutlicore interrupt affinity
	 * This is required since the MPIC HW doesn't limit
	 * several CPUs from acknowledging the same interrupt.
	 */
	if (count > 1)
		return -EINVAL;

	for_each_cpu(cpu, cpu_online_mask)
		online_mask |= 1 << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);

	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~online_mask)) | new_mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));

	raw_spin_unlock(&irq_controller_lock);

	return 0;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "armada_370_xp_irq",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

#ifdef CONFIG_SMP
void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

void armada_xp_mpic_smp_cpu_init(void)
{
	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}
#endif /* CONFIG_SMP */

static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

static asmlinkage void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			irqnr =	irq_find_mapping(armada_370_xp_mpic_domain,
					irqnr);
			handle_IRQ(irqnr, regs);
			continue;
		}

#ifdef CONFIG_PCI_MSI
		/* MSI handling */
		if (irqnr == 1) {
			u32 msimask, msinr;

			msimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& PCI_MSI_DOORBELL_MASK;

			writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
			       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			for (msinr = PCI_MSI_DOORBELL_START;
			     msinr < PCI_MSI_DOORBELL_END; msinr++) {
				int irq;

				if (!(msimask & BIT(msinr)))
					continue;

				irq = irq_find_mapping(armada_370_xp_msi_domain,
						       msinr - 16);
				handle_IRQ(irq, regs);
			}
		}
#endif

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~IPI_DOORBELL_MASK, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, (control >> 2) & 0x3ff,
				&armada_370_xp_mpic_irq_ops, NULL);

	BUG_ON(!armada_370_xp_mpic_domain);

	irq_set_default_host(armada_370_xp_mpic_domain);

#ifdef CONFIG_SMP
	armada_xp_mpic_smp_cpu_init();

	/*
	 * Set the default affinity from all CPUs to the boot cpu.
	 * This is required since the MPIC doesn't limit several CPUs
	 * from acknowledging the same interrupt.
	 */
	cpumask_clear(irq_default_affinity);
	cpumask_set_cpu(smp_processor_id(), irq_default_affinity);

#endif

	armada_370_xp_msi_init(node, main_int_res.start);

	set_handle_irq(armada_370_xp_handle_irq);

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/io.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
31f614ed	24	#include <linux/of_pci.h>
9ae6f740	25	#include <linux/irqdomain.h>
31f614ed TP	26	#include <linux/slab.h>
31f614ed TP	27	#include <linux/msi.h>
9ae6f740 TP	28	#include <asm/mach/arch.h>
9ae6f740 TP	29	#include <asm/exception.h>
344e873e	30	#include <asm/smp_plat.h>
9339d432 TP	31	#include <asm/mach/irq.h>
	32
	33	#include "irqchip.h"
9ae6f740 TP	34
	35	/* Interrupt Controller Registers Map */
	36	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	37	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
	38
f3e16ccd	39	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	40	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	41	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	42	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
9ae6f740 TP	43
	44	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
	45
344e873e GC	46	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	47	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	48	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	49
3202bf01 GC	50	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	51
7f23f62f GC	52	#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
7f23f62f GC	53
5ec69017 TP	54	#define IPI_DOORBELL_START (0)
	55	#define IPI_DOORBELL_END (8)
	56	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	57	#define PCI_MSI_DOORBELL_START (16)
	58	#define PCI_MSI_DOORBELL_NR (16)
	59	#define PCI_MSI_DOORBELL_END (32)
	60	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	61
3202bf01 GC	62	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
3202bf01 GC	63
9ae6f740 TP	64	static void __iomem *per_cpu_int_base;
	65	static void __iomem *main_int_base;
	66	static struct irq_domain *armada_370_xp_mpic_domain;
31f614ed TP	67	#ifdef CONFIG_PCI_MSI
	68	static struct irq_domain *armada_370_xp_msi_domain;
	69	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	70	static DEFINE_MUTEX(msi_used_lock);
	71	static phys_addr_t msi_doorbell_addr;
	72	#endif
9ae6f740	73
3202bf01 GC	74	/*
	75	* In SMP mode:
	76	* For shared global interrupts, mask/unmask global enable bit
097ef18d	77	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	78	*/
9ae6f740 TP	79	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	80	{
3202bf01 GC	81	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	82
7f23f62f	83	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
3202bf01 GC	84	writel(hwirq, main_int_base +
	85	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	86	else
	87	writel(hwirq, per_cpu_int_base +
	88	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	89	}
	90
	91	static void armada_370_xp_irq_unmask(struct irq_data *d)
	92	{
3202bf01 GC	93	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	94
7f23f62f	95	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
3202bf01 GC	96	writel(hwirq, main_int_base +
	97	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	98	else
	99	writel(hwirq, per_cpu_int_base +
	100	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	101	}
9ae6f740 TP	102
31f614ed TP	103	#ifdef CONFIG_PCI_MSI
	104
	105	static int armada_370_xp_alloc_msi(void)
	106	{
	107	int hwirq;
	108
	109	mutex_lock(&msi_used_lock);
	110	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	111	if (hwirq >= PCI_MSI_DOORBELL_NR)
	112	hwirq = -ENOSPC;
	113	else
	114	set_bit(hwirq, msi_used);
	115	mutex_unlock(&msi_used_lock);
	116
	117	return hwirq;
	118	}
	119
	120	static void armada_370_xp_free_msi(int hwirq)
	121	{
	122	mutex_lock(&msi_used_lock);
	123	if (!test_bit(hwirq, msi_used))
	124	pr_err("trying to free unused MSI#%d\n", hwirq);
	125	else
	126	clear_bit(hwirq, msi_used);
	127	mutex_unlock(&msi_used_lock);
	128	}
	129
	130	static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
	131	struct pci_dev *pdev,
	132	struct msi_desc *desc)
	133	{
	134	struct msi_msg msg;
	135	irq_hw_number_t hwirq;
	136	int virq;
	137
	138	hwirq = armada_370_xp_alloc_msi();
	139	if (hwirq < 0)
	140	return hwirq;
	141
	142	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	143	if (!virq) {
	144	armada_370_xp_free_msi(hwirq);
	145	return -EINVAL;
	146	}
	147
	148	irq_set_msi_desc(virq, desc);
	149
	150	msg.address_lo = msi_doorbell_addr;
	151	msg.address_hi = 0;
	152	msg.data = 0xf00 \| (hwirq + 16);
	153
	154	write_msi_msg(virq, &msg);
	155	return 0;
	156	}
	157
	158	static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
	159	unsigned int irq)
	160	{
	161	struct irq_data *d = irq_get_irq_data(irq);
	162	irq_dispose_mapping(irq);
	163	armada_370_xp_free_msi(d->hwirq);
	164	}
	165
	166	static struct irq_chip armada_370_xp_msi_irq_chip = {
167	.name = "armada_370_xp_msi_irq",
168	.irq_enable = unmask_msi_irq,
169	.irq_disable = mask_msi_irq,
170	.irq_mask = mask_msi_irq,
171	.irq_unmask = unmask_msi_irq,
172	};
173
174	static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
175	irq_hw_number_t hw)
176	{
177	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
178	handle_simple_irq);
179	set_irq_flags(virq, IRQF_VALID);
180
181	return 0;
182	}
183
184	static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
185	.map = armada_370_xp_msi_map,
186	};
187
188	static int armada_370_xp_msi_init(struct device_node *node,
189	phys_addr_t main_int_phys_base)
190	{
191	struct msi_chip *msi_chip;
192	u32 reg;
193	int ret;
194
195	msi_doorbell_addr = main_int_phys_base +
196	ARMADA_370_XP_SW_TRIG_INT_OFFS;
197
198	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
199	if (!msi_chip)
200	return -ENOMEM;
201
202	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
203	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
204	msi_chip->of_node = node;
205
206	armada_370_xp_msi_domain =
207	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
208	&armada_370_xp_msi_irq_ops,
209	NULL);
210	if (!armada_370_xp_msi_domain) {
211	kfree(msi_chip);
212	return -ENOMEM;
213	}
214
215	ret = of_pci_msi_chip_add(msi_chip);
216	if (ret < 0) {
217	irq_domain_remove(armada_370_xp_msi_domain);
218	kfree(msi_chip);
219	return ret;
220	}
221
222	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
223	\| PCI_MSI_DOORBELL_MASK;
224
225	writel(reg, per_cpu_int_base +
226	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
227
228	/* Unmask IPI interrupt */
229	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
230
231	return 0;
232	}
233	#else
234	static inline int armada_370_xp_msi_init(struct device_node *node,
235	phys_addr_t main_int_phys_base)
236	{
237	return 0;
238	}
239	#endif
240
344e873e GC	241	#ifdef CONFIG_SMP
	242	static int armada_xp_set_affinity(struct irq_data *d,
	243	const struct cpumask *mask_val, bool force)
	244	{
3202bf01 GC	245	unsigned long reg;
	246	unsigned long new_mask = 0;
	247	unsigned long online_mask = 0;
	248	unsigned long count = 0;
	249	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	250	int cpu;
	251
	252	for_each_cpu(cpu, mask_val) {
	253	new_mask \|= 1 << cpu_logical_map(cpu);
	254	count++;
	255	}
	256
	257	/*
	258	* Forbid mutlicore interrupt affinity
	259	* This is required since the MPIC HW doesn't limit
	260	* several CPUs from acknowledging the same interrupt.
	261	*/
	262	if (count > 1)
	263	return -EINVAL;
	264
	265	for_each_cpu(cpu, cpu_online_mask)
	266	online_mask \|= 1 << cpu_logical_map(cpu);
	267
	268	raw_spin_lock(&irq_controller_lock);
	269
	270	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	271	reg = (reg & (~online_mask)) \| new_mask;
	272	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	273
	274	raw_spin_unlock(&irq_controller_lock);
	275
344e873e GC	276	return 0;
	277	}
	278	#endif
	279
9ae6f740 TP	280	static struct irq_chip armada_370_xp_irq_chip = {
	281	.name = "armada_370_xp_irq",
	282	.irq_mask = armada_370_xp_irq_mask,
	283	.irq_mask_ack = armada_370_xp_irq_mask,
	284	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	285	#ifdef CONFIG_SMP
	286	.irq_set_affinity = armada_xp_set_affinity,
	287	#endif
9ae6f740 TP	288	};
	289
	290	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	291	unsigned int virq, irq_hw_number_t hw)
	292	{
	293	armada_370_xp_irq_mask(irq_get_irq_data(virq));
600468d0 GC	294	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
	295	writel(hw, per_cpu_int_base +
	296	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	297	else
	298	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	299	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	300
7f23f62f	301	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
3a6f08a3 GC	302	irq_set_percpu_devid(virq);
	303	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	304	handle_percpu_devid_irq);
	305
	306	} else {
	307	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	308	handle_level_irq);
	309	}
9ae6f740 TP	310	set_irq_flags(virq, IRQF_VALID \| IRQF_PROBE);
	311
	312	return 0;
	313	}
	314
344e873e GC	315	#ifdef CONFIG_SMP
	316	void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
	317	{
	318	int cpu;
	319	unsigned long map = 0;
	320
	321	/* Convert our logical CPU mask into a physical one. */
	322	for_each_cpu(cpu, mask)
	323	map \|= 1 << cpu_logical_map(cpu);
	324
	325	/*
	326	* Ensure that stores to Normal memory are visible to the
	327	* other CPUs before issuing the IPI.
	328	*/
	329	dsb();
	330
	331	/* submit softirq */
	332	writel((map << 8) \| irq, main_int_base +
	333	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	334	}
	335
	336	void armada_xp_mpic_smp_cpu_init(void)
	337	{
	338	/* Clear pending IPIs */
	339	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	340
	341	/* Enable first 8 IPIs */
5ec69017	342	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	343	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	344
	345	/* Unmask IPI interrupt */
	346	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	347	}
	348	#endif /* CONFIG_SMP */
	349
9ae6f740 TP	350	static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	351	.map = armada_370_xp_mpic_irq_map,
	352	.xlate = irq_domain_xlate_onecell,
	353	};
	354
9339d432 TP	355	static asmlinkage void __exception_irq_entry
9339d432 TP	356	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	357	{
	358	u32 irqstat, irqnr;
	359
	360	do {
	361	irqstat = readl_relaxed(per_cpu_int_base +
	362	ARMADA_370_XP_CPU_INTACK_OFFS);
	363	irqnr = irqstat & 0x3FF;
	364
344e873e GC	365	if (irqnr > 1022)
	366	break;
	367
31f614ed	368	if (irqnr > 1) {
344e873e GC	369	irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
344e873e GC	370	irqnr);
9ae6f740 TP	371	handle_IRQ(irqnr, regs);
	372	continue;
	373	}
31f614ed TP	374
	375	#ifdef CONFIG_PCI_MSI
	376	/* MSI handling */
	377	if (irqnr == 1) {
	378	u32 msimask, msinr;
	379
	380	msimask = readl_relaxed(per_cpu_int_base +
	381	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	382	& PCI_MSI_DOORBELL_MASK;
	383
	384	writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
	385	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	386
	387	for (msinr = PCI_MSI_DOORBELL_START;
	388	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	389	int irq;
	390
	391	if (!(msimask & BIT(msinr)))
	392	continue;
	393
	394	irq = irq_find_mapping(armada_370_xp_msi_domain,
	395	msinr - 16);
	396	handle_IRQ(irq, regs);
	397	}
	398	}
	399	#endif
	400
344e873e GC	401	#ifdef CONFIG_SMP
	402	/* IPI Handling */
	403	if (irqnr == 0) {
	404	u32 ipimask, ipinr;
	405
	406	ipimask = readl_relaxed(per_cpu_int_base +
	407	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	408	& IPI_DOORBELL_MASK;
344e873e	409
5ec69017	410	writel(~IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	411	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	412
	413	/* Handle all pending doorbells */
5ec69017 TP	414	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	415	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	416	if (ipimask & (0x1 << ipinr))
	417	handle_IPI(ipinr, regs);
	418	}
	419	continue;
	420	}
	421	#endif
9ae6f740	422
9ae6f740 TP	423	} while (1);
	424	}
	425
b313ada8 TP	426	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	427	struct device_node *parent)
9ae6f740	428	{
627dfcc2	429	struct resource main_int_res, per_cpu_int_res;
b313ada8 TP	430	u32 control;
b313ada8 TP	431
627dfcc2 TP	432	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	433	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	434
627dfcc2 TP	435	BUG_ON(!request_mem_region(main_int_res.start,
	436	resource_size(&main_int_res),
	437	node->full_name));
	438	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	439	resource_size(&per_cpu_int_res),
	440	node->full_name));
	441
	442	main_int_base = ioremap(main_int_res.start,
	443	resource_size(&main_int_res));
b313ada8	444	BUG_ON(!main_int_base);
627dfcc2 TP	445
	446	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	447	resource_size(&per_cpu_int_res));
b313ada8 TP	448	BUG_ON(!per_cpu_int_base);
	449
	450	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	451
	452	armada_370_xp_mpic_domain =
	453	irq_domain_add_linear(node, (control >> 2) & 0x3ff,
	454	&armada_370_xp_mpic_irq_ops, NULL);
	455
627dfcc2	456	BUG_ON(!armada_370_xp_mpic_domain);
b313ada8 TP	457
	458	irq_set_default_host(armada_370_xp_mpic_domain);
	459
	460	#ifdef CONFIG_SMP
	461	armada_xp_mpic_smp_cpu_init();
	462
	463	/*
	464	* Set the default affinity from all CPUs to the boot cpu.
	465	* This is required since the MPIC doesn't limit several CPUs
	466	* from acknowledging the same interrupt.
	467	*/
	468	cpumask_clear(irq_default_affinity);
	469	cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
	470
d792b1e9	471	#endif
b313ada8	472
31f614ed TP	473	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	474
b313ada8 TP	475	set_handle_irq(armada_370_xp_handle_irq);
	476
	477	return 0;
9ae6f740	478	}
b313ada8	479
9339d432	480	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);