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7f646e92 FF |
1 | /* |
2 | * Generic Broadcom Set Top Box Level 2 Interrupt controller driver | |
3 | * | |
4 | * Copyright (C) 2014 Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/module.h> | |
1abbdbac | 21 | #include <linux/kconfig.h> |
7f646e92 | 22 | #include <linux/platform_device.h> |
05f12757 | 23 | #include <linux/spinlock.h> |
7f646e92 FF |
24 | #include <linux/of.h> |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/irqdomain.h> | |
32 | #include <linux/irqchip.h> | |
33 | #include <linux/irqchip/chained_irq.h> | |
34 | ||
7f646e92 FF |
35 | #include "irqchip.h" |
36 | ||
37 | /* Register offsets in the L2 interrupt controller */ | |
38 | #define CPU_STATUS 0x00 | |
39 | #define CPU_SET 0x04 | |
40 | #define CPU_CLEAR 0x08 | |
41 | #define CPU_MASK_STATUS 0x0c | |
42 | #define CPU_MASK_SET 0x10 | |
43 | #define CPU_MASK_CLEAR 0x14 | |
44 | ||
45 | /* L2 intc private data structure */ | |
46 | struct brcmstb_l2_intc_data { | |
47 | int parent_irq; | |
48 | void __iomem *base; | |
49 | struct irq_domain *domain; | |
50 | bool can_wake; | |
51 | u32 saved_mask; /* for suspend/resume */ | |
52 | }; | |
53 | ||
54 | static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc) | |
55 | { | |
56 | struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); | |
1abbdbac | 57 | struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0); |
7f646e92 FF |
58 | struct irq_chip *chip = irq_desc_get_chip(desc); |
59 | u32 status; | |
60 | ||
61 | chained_irq_enter(chip, desc); | |
62 | ||
1abbdbac KC |
63 | status = irq_reg_readl(gc, CPU_STATUS) & |
64 | ~(irq_reg_readl(gc, CPU_MASK_STATUS)); | |
7f646e92 FF |
65 | |
66 | if (status == 0) { | |
05f12757 KC |
67 | raw_spin_lock(&desc->lock); |
68 | handle_bad_irq(irq, desc); | |
69 | raw_spin_unlock(&desc->lock); | |
7f646e92 FF |
70 | goto out; |
71 | } | |
72 | ||
73 | do { | |
74 | irq = ffs(status) - 1; | |
75 | /* ack at our level */ | |
1abbdbac | 76 | irq_reg_writel(gc, 1 << irq, CPU_CLEAR); |
7f646e92 FF |
77 | status &= ~(1 << irq); |
78 | generic_handle_irq(irq_find_mapping(b->domain, irq)); | |
79 | } while (status); | |
80 | out: | |
81 | chained_irq_exit(chip, desc); | |
82 | } | |
83 | ||
84 | static void brcmstb_l2_intc_suspend(struct irq_data *d) | |
85 | { | |
86 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
87 | struct brcmstb_l2_intc_data *b = gc->private; | |
88 | ||
89 | irq_gc_lock(gc); | |
90 | /* Save the current mask */ | |
1abbdbac | 91 | b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS); |
7f646e92 FF |
92 | |
93 | if (b->can_wake) { | |
94 | /* Program the wakeup mask */ | |
1abbdbac KC |
95 | irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET); |
96 | irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR); | |
7f646e92 FF |
97 | } |
98 | irq_gc_unlock(gc); | |
99 | } | |
100 | ||
101 | static void brcmstb_l2_intc_resume(struct irq_data *d) | |
102 | { | |
103 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
104 | struct brcmstb_l2_intc_data *b = gc->private; | |
105 | ||
106 | irq_gc_lock(gc); | |
107 | /* Clear unmasked non-wakeup interrupts */ | |
1abbdbac | 108 | irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR); |
7f646e92 FF |
109 | |
110 | /* Restore the saved mask */ | |
1abbdbac KC |
111 | irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET); |
112 | irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR); | |
7f646e92 FF |
113 | irq_gc_unlock(gc); |
114 | } | |
115 | ||
116 | int __init brcmstb_l2_intc_of_init(struct device_node *np, | |
117 | struct device_node *parent) | |
118 | { | |
119 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
120 | struct brcmstb_l2_intc_data *data; | |
121 | struct irq_chip_generic *gc; | |
122 | struct irq_chip_type *ct; | |
123 | int ret; | |
1abbdbac | 124 | unsigned int flags; |
7f646e92 FF |
125 | |
126 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
127 | if (!data) | |
128 | return -ENOMEM; | |
129 | ||
130 | data->base = of_iomap(np, 0); | |
131 | if (!data->base) { | |
132 | pr_err("failed to remap intc L2 registers\n"); | |
133 | ret = -ENOMEM; | |
134 | goto out_free; | |
135 | } | |
136 | ||
137 | /* Disable all interrupts by default */ | |
1abbdbac | 138 | writel(0xffffffff, data->base + CPU_MASK_SET); |
c9ae71e0 BN |
139 | |
140 | /* Wakeup interrupts may be retained from S5 (cold boot) */ | |
141 | data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); | |
142 | if (!data->can_wake) | |
143 | writel(0xffffffff, data->base + CPU_CLEAR); | |
7f646e92 FF |
144 | |
145 | data->parent_irq = irq_of_parse_and_map(np, 0); | |
d99ba446 | 146 | if (!data->parent_irq) { |
7f646e92 | 147 | pr_err("failed to find parent interrupt\n"); |
d99ba446 | 148 | ret = -EINVAL; |
7f646e92 FF |
149 | goto out_unmap; |
150 | } | |
151 | ||
152 | data->domain = irq_domain_add_linear(np, 32, | |
153 | &irq_generic_chip_ops, NULL); | |
154 | if (!data->domain) { | |
155 | ret = -ENOMEM; | |
156 | goto out_unmap; | |
157 | } | |
158 | ||
1abbdbac KC |
159 | /* MIPS chips strapped for BE will automagically configure the |
160 | * peripheral registers for CPU-native byte order. | |
161 | */ | |
162 | flags = 0; | |
163 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) | |
164 | flags |= IRQ_GC_BE_IO; | |
165 | ||
7f646e92 FF |
166 | /* Allocate a single Generic IRQ chip for this node */ |
167 | ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, | |
1abbdbac | 168 | np->full_name, handle_edge_irq, clr, 0, flags); |
7f646e92 FF |
169 | if (ret) { |
170 | pr_err("failed to allocate generic irq chip\n"); | |
171 | goto out_free_domain; | |
172 | } | |
173 | ||
174 | /* Set the IRQ chaining logic */ | |
175 | irq_set_handler_data(data->parent_irq, data); | |
176 | irq_set_chained_handler(data->parent_irq, brcmstb_l2_intc_irq_handle); | |
177 | ||
178 | gc = irq_get_domain_generic_chip(data->domain, 0); | |
179 | gc->reg_base = data->base; | |
180 | gc->private = data; | |
181 | ct = gc->chip_types; | |
182 | ||
183 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
184 | ct->regs.ack = CPU_CLEAR; | |
185 | ||
186 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
187 | ct->regs.disable = CPU_MASK_SET; | |
188 | ||
189 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
190 | ct->regs.enable = CPU_MASK_CLEAR; | |
191 | ||
192 | ct->chip.irq_suspend = brcmstb_l2_intc_suspend; | |
193 | ct->chip.irq_resume = brcmstb_l2_intc_resume; | |
194 | ||
c9ae71e0 | 195 | if (data->can_wake) { |
7f646e92 FF |
196 | /* This IRQ chip can wake the system, set all child interrupts |
197 | * in wake_enabled mask | |
198 | */ | |
199 | gc->wake_enabled = 0xffffffff; | |
200 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
201 | } | |
202 | ||
203 | pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n", | |
204 | data->base, data->parent_irq); | |
205 | ||
206 | return 0; | |
207 | ||
208 | out_free_domain: | |
209 | irq_domain_remove(data->domain); | |
210 | out_unmap: | |
211 | iounmap(data->base); | |
212 | out_free: | |
213 | kfree(data); | |
214 | return ret; | |
215 | } | |
216 | IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init); |