[deliverable/linux.git] / drivers / irqchip / irq-gic-common.c

/*
 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/arm-gic.h>

#include "irq-gic-common.h"

void gic_configure_irq(unsigned int irq, unsigned int type,
		       void __iomem *base, void (*sync_access)(void))
{
	u32 enablemask = 1 << (irq % 32);
	u32 enableoff = (irq / 32) * 4;
	u32 confmask = 0x2 << ((irq % 16) * 2);
	u32 confoff = (irq / 16) * 4;
	bool enabled = false;
	u32 val;

	/*
	 * Read current configuration register, and insert the config
	 * for "irq", depending on "type".
	 */
	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
	if (type == IRQ_TYPE_LEVEL_HIGH)
		val &= ~confmask;
	else if (type == IRQ_TYPE_EDGE_RISING)
		val |= confmask;

	/*
	 * As recommended by the spec, disable the interrupt before changing
	 * the configuration
	 */
	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
		if (sync_access)
			sync_access();
		enabled = true;
	}

	/*
	 * Write back the new configuration, and possibly re-enable
	 * the interrupt.
	 */
	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);

	if (enabled)
		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);

	if (sync_access)
		sync_access();
}

void __init gic_dist_config(void __iomem *base, int gic_irqs,
			    void (*sync_access)(void))
{
	unsigned int i;

	/*
	 * Set all global interrupts to be level triggered, active low.
	 */
	for (i = 32; i < gic_irqs; i += 16)
		writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
					base + GIC_DIST_CONFIG + i / 4);

	/*
	 * Set priority on all global interrupts.
	 */
	for (i = 32; i < gic_irqs; i += 4)
		writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);

	/*
	 * Disable all interrupts.  Leave the PPI and SGIs alone
	 * as they are enabled by redistributor registers.
	 */
	for (i = 32; i < gic_irqs; i += 32)
		writel_relaxed(GICD_INT_EN_CLR_X32,
					base + GIC_DIST_ENABLE_CLEAR + i / 8);

	if (sync_access)
		sync_access();
}

void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
{
	int i;

	/*
	 * Deal with the banked PPI and SGI interrupts - disable all
	 * PPI interrupts, ensure all SGI interrupts are enabled.
	 */
	writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);

	/*
	 * Set priority on PPI and SGI interrupts
	 */
	for (i = 0; i < 32; i += 4)
		writel_relaxed(GICD_INT_DEF_PRI_X4,
					base + GIC_DIST_PRI + i * 4 / 4);

	if (sync_access)
		sync_access();
}
Commit	Line	Data
d51d0af4 MZ	1	/*
	2	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/interrupt.h>
	18	#include <linux/io.h>
	19	#include <linux/irq.h>
	20	#include <linux/irqchip/arm-gic.h>
	21
	22	#include "irq-gic-common.h"
	23
	24	void gic_configure_irq(unsigned int irq, unsigned int type,
	25	void __iomem base, void (sync_access)(void))
	26	{
	27	u32 enablemask = 1 << (irq % 32);
	28	u32 enableoff = (irq / 32) * 4;
	29	u32 confmask = 0x2 << ((irq % 16) * 2);
	30	u32 confoff = (irq / 16) * 4;
	31	bool enabled = false;
	32	u32 val;
	33
	34	/*
	35	* Read current configuration register, and insert the config
	36	* for "irq", depending on "type".
	37	*/
	38	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
	39	if (type == IRQ_TYPE_LEVEL_HIGH)
	40	val &= ~confmask;
	41	else if (type == IRQ_TYPE_EDGE_RISING)
	42	val \|= confmask;
	43
	44	/*
	45	* As recommended by the spec, disable the interrupt before changing
	46	* the configuration
	47	*/
	48	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
	49	writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
	50	if (sync_access)
	51	sync_access();
	52	enabled = true;
	53	}
	54
	55	/*
	56	* Write back the new configuration, and possibly re-enable
	57	* the interrupt.
	58	*/
	59	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
	60
	61	if (enabled)
	62	writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
	63
	64	if (sync_access)
65	sync_access();
66	}
67
68	void __init gic_dist_config(void __iomem *base, int gic_irqs,
69	void (*sync_access)(void))
70	{
71	unsigned int i;
72
73	/*
74	* Set all global interrupts to be level triggered, active low.
75	*/
76	for (i = 32; i < gic_irqs; i += 16)
e5f81539 FK	77	writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
e5f81539 FK	78	base + GIC_DIST_CONFIG + i / 4);
d51d0af4 MZ	79
	80	/*
	81	* Set priority on all global interrupts.
	82	*/
	83	for (i = 32; i < gic_irqs; i += 4)
e5f81539	84	writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
d51d0af4 MZ	85
	86	/*
	87	* Disable all interrupts. Leave the PPI and SGIs alone
	88	* as they are enabled by redistributor registers.
	89	*/
	90	for (i = 32; i < gic_irqs; i += 32)
e5f81539 FK	91	writel_relaxed(GICD_INT_EN_CLR_X32,
e5f81539 FK	92	base + GIC_DIST_ENABLE_CLEAR + i / 8);
d51d0af4 MZ	93
	94	if (sync_access)
	95	sync_access();
	96	}
	97
	98	void gic_cpu_config(void __iomem base, void (sync_access)(void))
	99	{
	100	int i;
	101
	102	/*
	103	* Deal with the banked PPI and SGI interrupts - disable all
	104	* PPI interrupts, ensure all SGI interrupts are enabled.
	105	*/
e5f81539 FK	106	writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
e5f81539 FK	107	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
d51d0af4 MZ	108
	109	/*
	110	* Set priority on PPI and SGI interrupts
	111	*/
	112	for (i = 0; i < 32; i += 4)
e5f81539 FK	113	writel_relaxed(GICD_INT_DEF_PRI_X4,
e5f81539 FK	114	base + GIC_DIST_PRI + i * 4 / 4);
d51d0af4 MZ	115
	116	if (sync_access)
	117	sync_access();
	118	}