[deliverable/linux.git] / drivers / irqchip / irq-gic-v2m.c

/*
 * ARM GIC v2m MSI(-X) support
 * Support for Message Signaled Interrupts for systems that
 * implement ARM Generic Interrupt Controller: GICv2m.
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
 *	    Brandon Anderson <brandon.anderson@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#define pr_fmt(fmt) "GICv2m: " fmt

#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

/*
* MSI_TYPER:
*     [31:26] Reserved
*     [25:16] lowest SPI assigned to MSI
*     [15:10] Reserved
*     [9:0]   Numer of SPIs assigned to MSI
*/
#define V2M_MSI_TYPER		       0x008
#define V2M_MSI_TYPER_BASE_SHIFT       16
#define V2M_MSI_TYPER_BASE_MASK	       0x3FF
#define V2M_MSI_TYPER_NUM_MASK	       0x3FF
#define V2M_MSI_SETSPI_NS	       0x040
#define V2M_MIN_SPI		       32
#define V2M_MAX_SPI		       1019

#define V2M_MSI_TYPER_BASE_SPI(x)      \
	       (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)

#define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)

struct v2m_data {
	spinlock_t msi_cnt_lock;
	struct resource res;	/* GICv2m resource */
	void __iomem *base;	/* GICv2m virt address */
	u32 spi_start;		/* The SPI number that MSIs start */
	u32 nr_spis;		/* The number of SPIs for MSIs */
	unsigned long *bm;	/* MSI vector bitmap */
	struct irq_domain *domain;
};

static void gicv2m_mask_msi_irq(struct irq_data *d)
{
	pci_msi_mask_irq(d);
	irq_chip_mask_parent(d);
}

static void gicv2m_unmask_msi_irq(struct irq_data *d)
{
	pci_msi_unmask_irq(d);
	irq_chip_unmask_parent(d);
}

static struct irq_chip gicv2m_msi_irq_chip = {
	.name			= "MSI",
	.irq_mask		= gicv2m_mask_msi_irq,
	.irq_unmask		= gicv2m_unmask_msi_irq,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
};

static struct msi_domain_info gicv2m_msi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
		   MSI_FLAG_PCI_MSIX),
	.chip	= &gicv2m_msi_irq_chip,
};

static int gicv2m_set_affinity(struct irq_data *irq_data,
			       const struct cpumask *mask, bool force)
{
	int ret;

	ret = irq_chip_set_affinity_parent(irq_data, mask, force);
	if (ret == IRQ_SET_MASK_OK)
		ret = IRQ_SET_MASK_OK_DONE;

	return ret;
}

static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;

	msg->address_hi = (u32) (addr >> 32);
	msg->address_lo = (u32) (addr);
	msg->data = data->hwirq;
}

static struct irq_chip gicv2m_irq_chip = {
	.name			= "GICv2m",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= gicv2m_set_affinity,
	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,
};

static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
				       unsigned int virq,
				       irq_hw_number_t hwirq)
{
	struct of_phandle_args args;
	struct irq_data *d;
	int err;

	args.np = domain->parent->of_node;
	args.args_count = 3;
	args.args[0] = 0;
	args.args[1] = hwirq - 32;
	args.args[2] = IRQ_TYPE_EDGE_RISING;

	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
	if (err)
		return err;

	/* Configure the interrupt line to be edge */
	d = irq_domain_get_irq_data(domain->parent, virq);
	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
{
	int pos;

	pos = hwirq - v2m->spi_start;
	if (pos < 0 || pos >= v2m->nr_spis) {
		pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
		return;
	}

	spin_lock(&v2m->msi_cnt_lock);
	__clear_bit(pos, v2m->bm);
	spin_unlock(&v2m->msi_cnt_lock);
}

static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *args)
{
	struct v2m_data *v2m = domain->host_data;
	int hwirq, offset, err = 0;

	spin_lock(&v2m->msi_cnt_lock);
	offset = find_first_zero_bit(v2m->bm, v2m->nr_spis);
	if (offset < v2m->nr_spis)
		__set_bit(offset, v2m->bm);
	else
		err = -ENOSPC;
	spin_unlock(&v2m->msi_cnt_lock);

	if (err)
		return err;

	hwirq = v2m->spi_start + offset;

	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
	if (err) {
		gicv2m_unalloc_msi(v2m, hwirq);
		return err;
	}

	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
				      &gicv2m_irq_chip, v2m);

	return 0;
}

static void gicv2m_irq_domain_free(struct irq_domain *domain,
				   unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);

	BUG_ON(nr_irqs != 1);
	gicv2m_unalloc_msi(v2m, d->hwirq);
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops gicv2m_domain_ops = {
	.alloc			= gicv2m_irq_domain_alloc,
	.free			= gicv2m_irq_domain_free,
};

static bool is_msi_spi_valid(u32 base, u32 num)
{
	if (base < V2M_MIN_SPI) {
		pr_err("Invalid MSI base SPI (base:%u)\n", base);
		return false;
	}

	if ((num == 0) || (base + num > V2M_MAX_SPI)) {
		pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
		return false;
	}

	return true;
}

static int __init gicv2m_init_one(struct device_node *node,
				  struct irq_domain *parent)
{
	int ret;
	struct v2m_data *v2m;
	struct irq_domain *inner_domain;

	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	if (!v2m) {
		pr_err("Failed to allocate struct v2m_data.\n");
		return -ENOMEM;
	}

	ret = of_address_to_resource(node, 0, &v2m->res);
	if (ret) {
		pr_err("Failed to allocate v2m resource.\n");
		goto err_free_v2m;
	}

	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	if (!v2m->base) {
		pr_err("Failed to map GICv2m resource\n");
		ret = -ENOMEM;
		goto err_free_v2m;
	}

	if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
	    !of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
		pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
			v2m->spi_start, v2m->nr_spis);
	} else {
		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);

		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	}

	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
		ret = -EINVAL;
		goto err_iounmap;
	}

	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
			  GFP_KERNEL);
	if (!v2m->bm) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	inner_domain = irq_domain_add_tree(node, &gicv2m_domain_ops, v2m);
	if (!inner_domain) {
		pr_err("Failed to create GICv2m domain\n");
		ret = -ENOMEM;
		goto err_free_bm;
	}

	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	inner_domain->parent = parent;
	v2m->domain = pci_msi_create_irq_domain(node, &gicv2m_msi_domain_info,
						inner_domain);
	if (!v2m->domain) {
		pr_err("Failed to create MSI domain\n");
		ret = -ENOMEM;
		goto err_free_domains;
	}

	spin_lock_init(&v2m->msi_cnt_lock);

	pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
		(unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
		v2m->spi_start, (v2m->spi_start + v2m->nr_spis));

	return 0;

err_free_domains:
	if (v2m->domain)
		irq_domain_remove(v2m->domain);
	if (inner_domain)
		irq_domain_remove(inner_domain);
err_free_bm:
	kfree(v2m->bm);
err_iounmap:
	iounmap(v2m->base);
err_free_v2m:
	kfree(v2m);
	return ret;
}

static struct of_device_id gicv2m_device_id[] = {
	{	.compatible	= "arm,gic-v2m-frame",	},
	{},
};

int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
{
	int ret = 0;
	struct device_node *child;

	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	     child = of_find_matching_node(child, gicv2m_device_id)) {
		if (!of_find_property(child, "msi-controller", NULL))
			continue;

		ret = gicv2m_init_one(child, parent);
		if (ret) {
			of_node_put(node);
			break;
		}
	}

	return ret;
}
Commit	Line	Data
853a33ce SS	1	/*
	2	* ARM GIC v2m MSI(-X) support
	3	* Support for Message Signaled Interrupts for systems that
	4	* implement ARM Generic Interrupt Controller: GICv2m.
	5	*
	6	* Copyright (C) 2014 Advanced Micro Devices, Inc.
	7	* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
	8	* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
	9	* Brandon Anderson <brandon.anderson@amd.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published
	13	* by the Free Software Foundation.
	14	*/
	15
	16	#define pr_fmt(fmt) "GICv2m: " fmt
	17
	18	#include <linux/irq.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/kernel.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_pci.h>
	23	#include <linux/slab.h>
	24	#include <linux/spinlock.h>
	25
	26	/*
	27	* MSI_TYPER:
	28	* [31:26] Reserved
	29	* [25:16] lowest SPI assigned to MSI
	30	* [15:10] Reserved
	31	* [9:0] Numer of SPIs assigned to MSI
	32	*/
	33	#define V2M_MSI_TYPER 0x008
	34	#define V2M_MSI_TYPER_BASE_SHIFT 16
	35	#define V2M_MSI_TYPER_BASE_MASK 0x3FF
	36	#define V2M_MSI_TYPER_NUM_MASK 0x3FF
	37	#define V2M_MSI_SETSPI_NS 0x040
	38	#define V2M_MIN_SPI 32
	39	#define V2M_MAX_SPI 1019
	40
	41	#define V2M_MSI_TYPER_BASE_SPI(x) \
	42	(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
	43
	44	#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
	45
	46	struct v2m_data {
	47	spinlock_t msi_cnt_lock;
853a33ce SS	48	struct resource res; /* GICv2m resource */
	49	void __iomem base; / GICv2m virt address */
	50	u32 spi_start; /* The SPI number that MSIs start */
	51	u32 nr_spis; /* The number of SPIs for MSIs */
	52	unsigned long bm; / MSI vector bitmap */
	53	struct irq_domain *domain;
	54	};
	55
	56	static void gicv2m_mask_msi_irq(struct irq_data *d)
	57	{
	58	pci_msi_mask_irq(d);
	59	irq_chip_mask_parent(d);
	60	}
	61
	62	static void gicv2m_unmask_msi_irq(struct irq_data *d)
	63	{
	64	pci_msi_unmask_irq(d);
	65	irq_chip_unmask_parent(d);
	66	}
	67
	68	static struct irq_chip gicv2m_msi_irq_chip = {
	69	.name = "MSI",
	70	.irq_mask = gicv2m_mask_msi_irq,
	71	.irq_unmask = gicv2m_unmask_msi_irq,
	72	.irq_eoi = irq_chip_eoi_parent,
	73	.irq_write_msi_msg = pci_msi_domain_write_msg,
	74	};
	75
	76	static struct msi_domain_info gicv2m_msi_domain_info = {
	77	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	78	MSI_FLAG_PCI_MSIX),
	79	.chip = &gicv2m_msi_irq_chip,
	80	};
	81
	82	static int gicv2m_set_affinity(struct irq_data *irq_data,
	83	const struct cpumask *mask, bool force)
	84	{
	85	int ret;
	86
	87	ret = irq_chip_set_affinity_parent(irq_data, mask, force);
	88	if (ret == IRQ_SET_MASK_OK)
	89	ret = IRQ_SET_MASK_OK_DONE;
	90
	91	return ret;
	92	}
	93
	94	static void gicv2m_compose_msi_msg(struct irq_data data, struct msi_msg msg)
	95	{
	96	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	97	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
	98
	99	msg->address_hi = (u32) (addr >> 32);
	100	msg->address_lo = (u32) (addr);
	101	msg->data = data->hwirq;
	102	}
	103
	104	static struct irq_chip gicv2m_irq_chip = {
	105	.name = "GICv2m",
	106	.irq_mask = irq_chip_mask_parent,
	107	.irq_unmask = irq_chip_unmask_parent,
	108	.irq_eoi = irq_chip_eoi_parent,
	109	.irq_set_affinity = gicv2m_set_affinity,
	110	.irq_compose_msi_msg = gicv2m_compose_msi_msg,
	111	};
112
113	static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
114	unsigned int virq,
115	irq_hw_number_t hwirq)
116	{
117	struct of_phandle_args args;
118	struct irq_data *d;
119	int err;
120
121	args.np = domain->parent->of_node;
122	args.args_count = 3;
123	args.args[0] = 0;
124	args.args[1] = hwirq - 32;
125	args.args[2] = IRQ_TYPE_EDGE_RISING;
126
127	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
128	if (err)
129	return err;
130
131	/* Configure the interrupt line to be edge */
132	d = irq_domain_get_irq_data(domain->parent, virq);
133	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
134	return 0;
135	}
136
137	static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
138	{
139	int pos;
140
141	pos = hwirq - v2m->spi_start;
142	if (pos < 0 \|\| pos >= v2m->nr_spis) {
143	pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
144	return;
145	}
146
147	spin_lock(&v2m->msi_cnt_lock);
148	__clear_bit(pos, v2m->bm);
149	spin_unlock(&v2m->msi_cnt_lock);
150	}
151
152	static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
153	unsigned int nr_irqs, void *args)
154	{
155	struct v2m_data *v2m = domain->host_data;
156	int hwirq, offset, err = 0;
157
158	spin_lock(&v2m->msi_cnt_lock);
159	offset = find_first_zero_bit(v2m->bm, v2m->nr_spis);
160	if (offset < v2m->nr_spis)
161	__set_bit(offset, v2m->bm);
162	else
163	err = -ENOSPC;
164	spin_unlock(&v2m->msi_cnt_lock);
165
166	if (err)
167	return err;
168
169	hwirq = v2m->spi_start + offset;
170
171	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
172	if (err) {
173	gicv2m_unalloc_msi(v2m, hwirq);
174	return err;
175	}
176
177	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
178	&gicv2m_irq_chip, v2m);
179
180	return 0;
181	}
182
183	static void gicv2m_irq_domain_free(struct irq_domain *domain,
184	unsigned int virq, unsigned int nr_irqs)
185	{
186	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
187	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
188
189	BUG_ON(nr_irqs != 1);
190	gicv2m_unalloc_msi(v2m, d->hwirq);
191	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
192	}
193
194	static const struct irq_domain_ops gicv2m_domain_ops = {
195	.alloc = gicv2m_irq_domain_alloc,
196	.free = gicv2m_irq_domain_free,
197	};
198
199	static bool is_msi_spi_valid(u32 base, u32 num)
200	{
201	if (base < V2M_MIN_SPI) {
202	pr_err("Invalid MSI base SPI (base:%u)\n", base);
203	return false;
204	}
205
206	if ((num == 0) \|\| (base + num > V2M_MAX_SPI)) {
207	pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
208	num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
209	return false;
210	}
211
212	return true;
213	}
214
215	static int __init gicv2m_init_one(struct device_node *node,
216	struct irq_domain *parent)
217	{
218	int ret;
219	struct v2m_data *v2m;
5cedceb3	220	struct irq_domain *inner_domain;
853a33ce SS	221
	222	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	223	if (!v2m) {
	224	pr_err("Failed to allocate struct v2m_data.\n");
	225	return -ENOMEM;
	226	}
	227
	228	ret = of_address_to_resource(node, 0, &v2m->res);
	229	if (ret) {
	230	pr_err("Failed to allocate v2m resource.\n");
	231	goto err_free_v2m;
	232	}
	233
	234	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	235	if (!v2m->base) {
	236	pr_err("Failed to map GICv2m resource\n");
	237	ret = -ENOMEM;
	238	goto err_free_v2m;
	239	}
	240
	241	if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
	242	!of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
	243	pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	244	v2m->spi_start, v2m->nr_spis);
	245	} else {
	246	u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
	247
	248	v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
	249	v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	250	}
	251
	252	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
	253	ret = -EINVAL;
	254	goto err_iounmap;
	255	}
	256
	257	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
	258	GFP_KERNEL);
	259	if (!v2m->bm) {
	260	ret = -ENOMEM;
	261	goto err_iounmap;
	262	}
	263
5cedceb3 MZ	264	inner_domain = irq_domain_add_tree(node, &gicv2m_domain_ops, v2m);
5cedceb3 MZ	265	if (!inner_domain) {
853a33ce SS	266	pr_err("Failed to create GICv2m domain\n");
	267	ret = -ENOMEM;
	268	goto err_free_bm;
	269	}
	270
5cedceb3 MZ	271	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	272	inner_domain->parent = parent;
	273	v2m->domain = pci_msi_create_irq_domain(node, &gicv2m_msi_domain_info,
	274	inner_domain);
	275	if (!v2m->domain) {
853a33ce SS	276	pr_err("Failed to create MSI domain\n");
	277	ret = -ENOMEM;
	278	goto err_free_domains;
	279	}
	280
	281	spin_lock_init(&v2m->msi_cnt_lock);
	282
853a33ce SS	283	pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
	284	(unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
	285	v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
	286
	287	return 0;
	288
	289	err_free_domains:
853a33ce SS	290	if (v2m->domain)
853a33ce SS	291	irq_domain_remove(v2m->domain);
5cedceb3 MZ	292	if (inner_domain)
5cedceb3 MZ	293	irq_domain_remove(inner_domain);
853a33ce SS	294	err_free_bm:
	295	kfree(v2m->bm);
	296	err_iounmap:
	297	iounmap(v2m->base);
	298	err_free_v2m:
	299	kfree(v2m);
	300	return ret;
	301	}
	302
	303	static struct of_device_id gicv2m_device_id[] = {
	304	{ .compatible = "arm,gic-v2m-frame", },
	305	{},
	306	};
	307
	308	int __init gicv2m_of_init(struct device_node node, struct irq_domain parent)
	309	{
	310	int ret = 0;
	311	struct device_node *child;
	312
	313	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	314	child = of_find_matching_node(child, gicv2m_device_id)) {
	315	if (!of_find_property(child, "msi-controller", NULL))
	316	continue;
	317
	318	ret = gicv2m_init_one(child, parent);
	319	if (ret) {
	320	of_node_put(node);
	321	break;
	322	}
	323	}
	324
	325	return ret;
	326	}