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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
68628bb8 JG |
18 | #define pr_fmt(fmt) "GICv3: " fmt |
19 | ||
ffa7d616 | 20 | #include <linux/acpi.h> |
021f6537 | 21 | #include <linux/cpu.h> |
3708d52f | 22 | #include <linux/cpu_pm.h> |
021f6537 MZ |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
ffa7d616 | 25 | #include <linux/irqdomain.h> |
021f6537 MZ |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
31 | ||
41a83e06 | 32 | #include <linux/irqchip.h> |
1839e576 | 33 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 34 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 35 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
36 | |
37 | #include <asm/cputype.h> | |
38 | #include <asm/exception.h> | |
39 | #include <asm/smp_plat.h> | |
0b6a3da9 | 40 | #include <asm/virt.h> |
021f6537 MZ |
41 | |
42 | #include "irq-gic-common.h" | |
021f6537 | 43 | |
f5c1434c MZ |
44 | struct redist_region { |
45 | void __iomem *redist_base; | |
46 | phys_addr_t phys_base; | |
b70fb7af | 47 | bool single_redist; |
f5c1434c MZ |
48 | }; |
49 | ||
021f6537 | 50 | struct gic_chip_data { |
e3825ba1 | 51 | struct fwnode_handle *fwnode; |
021f6537 | 52 | void __iomem *dist_base; |
f5c1434c MZ |
53 | struct redist_region *redist_regions; |
54 | struct rdists rdists; | |
021f6537 MZ |
55 | struct irq_domain *domain; |
56 | u64 redist_stride; | |
f5c1434c | 57 | u32 nr_redist_regions; |
021f6537 | 58 | unsigned int irq_nr; |
e3825ba1 | 59 | struct partition_desc *ppi_descs[16]; |
021f6537 MZ |
60 | }; |
61 | ||
62 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 63 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 64 | |
1839e576 JG |
65 | static struct gic_kvm_info gic_v3_kvm_info; |
66 | ||
f5c1434c MZ |
67 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
68 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
69 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
70 | ||
71 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
72 | #define DEFAULT_PMR_VALUE 0xf0 | |
73 | ||
74 | static inline unsigned int gic_irq(struct irq_data *d) | |
75 | { | |
76 | return d->hwirq; | |
77 | } | |
78 | ||
79 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
80 | { | |
81 | return gic_irq(d) < 32; | |
82 | } | |
83 | ||
84 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
85 | { | |
86 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
87 | return gic_data_rdist_sgi_base(); | |
88 | ||
89 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
90 | return gic_data.dist_base; | |
91 | ||
021f6537 MZ |
92 | return NULL; |
93 | } | |
94 | ||
95 | static void gic_do_wait_for_rwp(void __iomem *base) | |
96 | { | |
97 | u32 count = 1000000; /* 1s! */ | |
98 | ||
99 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
100 | count--; | |
101 | if (!count) { | |
102 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
103 | return; | |
104 | } | |
105 | cpu_relax(); | |
106 | udelay(1); | |
107 | }; | |
108 | } | |
109 | ||
110 | /* Wait for completion of a distributor change */ | |
111 | static void gic_dist_wait_for_rwp(void) | |
112 | { | |
113 | gic_do_wait_for_rwp(gic_data.dist_base); | |
114 | } | |
115 | ||
116 | /* Wait for completion of a redistributor change */ | |
117 | static void gic_redist_wait_for_rwp(void) | |
118 | { | |
119 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
120 | } | |
121 | ||
7936e914 | 122 | #ifdef CONFIG_ARM64 |
8ac2a170 | 123 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
6d4e11c5 RR |
124 | |
125 | static u64 __maybe_unused gic_read_iar(void) | |
126 | { | |
8ac2a170 | 127 | if (static_branch_unlikely(&is_cavium_thunderx)) |
6d4e11c5 RR |
128 | return gic_read_iar_cavium_thunderx(); |
129 | else | |
130 | return gic_read_iar_common(); | |
131 | } | |
7936e914 | 132 | #endif |
021f6537 | 133 | |
a2c22510 | 134 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
135 | { |
136 | void __iomem *rbase; | |
137 | u32 count = 1000000; /* 1s! */ | |
138 | u32 val; | |
139 | ||
140 | rbase = gic_data_rdist_rd_base(); | |
141 | ||
021f6537 | 142 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
143 | if (enable) |
144 | /* Wake up this CPU redistributor */ | |
145 | val &= ~GICR_WAKER_ProcessorSleep; | |
146 | else | |
147 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
148 | writel_relaxed(val, rbase + GICR_WAKER); |
149 | ||
a2c22510 SH |
150 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
151 | val = readl_relaxed(rbase + GICR_WAKER); | |
152 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
153 | return; /* No PM support in this redistributor */ | |
154 | } | |
155 | ||
156 | while (count--) { | |
157 | val = readl_relaxed(rbase + GICR_WAKER); | |
158 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
159 | break; | |
021f6537 MZ |
160 | cpu_relax(); |
161 | udelay(1); | |
162 | }; | |
a2c22510 SH |
163 | if (!count) |
164 | pr_err_ratelimited("redistributor failed to %s...\n", | |
165 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
166 | } |
167 | ||
168 | /* | |
169 | * Routines to disable, enable, EOI and route interrupts | |
170 | */ | |
b594c6e2 MZ |
171 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
172 | { | |
173 | u32 mask = 1 << (gic_irq(d) % 32); | |
174 | void __iomem *base; | |
175 | ||
176 | if (gic_irq_in_rdist(d)) | |
177 | base = gic_data_rdist_sgi_base(); | |
178 | else | |
179 | base = gic_data.dist_base; | |
180 | ||
181 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
182 | } | |
183 | ||
021f6537 MZ |
184 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
185 | { | |
186 | u32 mask = 1 << (gic_irq(d) % 32); | |
187 | void (*rwp_wait)(void); | |
188 | void __iomem *base; | |
189 | ||
190 | if (gic_irq_in_rdist(d)) { | |
191 | base = gic_data_rdist_sgi_base(); | |
192 | rwp_wait = gic_redist_wait_for_rwp; | |
193 | } else { | |
194 | base = gic_data.dist_base; | |
195 | rwp_wait = gic_dist_wait_for_rwp; | |
196 | } | |
197 | ||
198 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
199 | rwp_wait(); | |
200 | } | |
201 | ||
021f6537 MZ |
202 | static void gic_mask_irq(struct irq_data *d) |
203 | { | |
204 | gic_poke_irq(d, GICD_ICENABLER); | |
205 | } | |
206 | ||
0b6a3da9 MZ |
207 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
208 | { | |
209 | gic_mask_irq(d); | |
530bf353 MZ |
210 | /* |
211 | * When masking a forwarded interrupt, make sure it is | |
212 | * deactivated as well. | |
213 | * | |
214 | * This ensures that an interrupt that is getting | |
215 | * disabled/masked will not get "stuck", because there is | |
216 | * noone to deactivate it (guest is being terminated). | |
217 | */ | |
4df7f54d | 218 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 219 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
220 | } |
221 | ||
021f6537 MZ |
222 | static void gic_unmask_irq(struct irq_data *d) |
223 | { | |
224 | gic_poke_irq(d, GICD_ISENABLER); | |
225 | } | |
226 | ||
b594c6e2 MZ |
227 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
228 | enum irqchip_irq_state which, bool val) | |
229 | { | |
230 | u32 reg; | |
231 | ||
232 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
233 | return -EINVAL; | |
234 | ||
235 | switch (which) { | |
236 | case IRQCHIP_STATE_PENDING: | |
237 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
238 | break; | |
239 | ||
240 | case IRQCHIP_STATE_ACTIVE: | |
241 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
242 | break; | |
243 | ||
244 | case IRQCHIP_STATE_MASKED: | |
245 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
246 | break; | |
247 | ||
248 | default: | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
252 | gic_poke_irq(d, reg); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
257 | enum irqchip_irq_state which, bool *val) | |
258 | { | |
259 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
260 | return -EINVAL; | |
261 | ||
262 | switch (which) { | |
263 | case IRQCHIP_STATE_PENDING: | |
264 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
265 | break; | |
266 | ||
267 | case IRQCHIP_STATE_ACTIVE: | |
268 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
269 | break; | |
270 | ||
271 | case IRQCHIP_STATE_MASKED: | |
272 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
273 | break; | |
274 | ||
275 | default: | |
276 | return -EINVAL; | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
021f6537 MZ |
282 | static void gic_eoi_irq(struct irq_data *d) |
283 | { | |
284 | gic_write_eoir(gic_irq(d)); | |
285 | } | |
286 | ||
0b6a3da9 MZ |
287 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
288 | { | |
289 | /* | |
530bf353 MZ |
290 | * No need to deactivate an LPI, or an interrupt that |
291 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 292 | */ |
4df7f54d | 293 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
294 | return; |
295 | gic_write_dir(gic_irq(d)); | |
296 | } | |
297 | ||
021f6537 MZ |
298 | static int gic_set_type(struct irq_data *d, unsigned int type) |
299 | { | |
300 | unsigned int irq = gic_irq(d); | |
301 | void (*rwp_wait)(void); | |
302 | void __iomem *base; | |
303 | ||
304 | /* Interrupt configuration for SGIs can't be changed */ | |
305 | if (irq < 16) | |
306 | return -EINVAL; | |
307 | ||
fb7e7deb LD |
308 | /* SPIs have restrictions on the supported types */ |
309 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
310 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
311 | return -EINVAL; |
312 | ||
313 | if (gic_irq_in_rdist(d)) { | |
314 | base = gic_data_rdist_sgi_base(); | |
315 | rwp_wait = gic_redist_wait_for_rwp; | |
316 | } else { | |
317 | base = gic_data.dist_base; | |
318 | rwp_wait = gic_dist_wait_for_rwp; | |
319 | } | |
320 | ||
fb7e7deb | 321 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
322 | } |
323 | ||
530bf353 MZ |
324 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
325 | { | |
4df7f54d TG |
326 | if (vcpu) |
327 | irqd_set_forwarded_to_vcpu(d); | |
328 | else | |
329 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
330 | return 0; |
331 | } | |
332 | ||
f6c86a41 | 333 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
334 | { |
335 | u64 aff; | |
336 | ||
f6c86a41 | 337 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
338 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
339 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
340 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
341 | ||
342 | return aff; | |
343 | } | |
344 | ||
345 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
346 | { | |
f6c86a41 | 347 | u32 irqnr; |
021f6537 MZ |
348 | |
349 | do { | |
350 | irqnr = gic_read_iar(); | |
351 | ||
da33f31d | 352 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 353 | int err; |
0b6a3da9 MZ |
354 | |
355 | if (static_key_true(&supports_deactivate)) | |
356 | gic_write_eoir(irqnr); | |
357 | ||
ebc6de00 MZ |
358 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
359 | if (err) { | |
da33f31d | 360 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
361 | if (static_key_true(&supports_deactivate)) { |
362 | if (irqnr < 8192) | |
363 | gic_write_dir(irqnr); | |
364 | } else { | |
365 | gic_write_eoir(irqnr); | |
366 | } | |
021f6537 | 367 | } |
ebc6de00 | 368 | continue; |
021f6537 MZ |
369 | } |
370 | if (irqnr < 16) { | |
371 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
372 | if (static_key_true(&supports_deactivate)) |
373 | gic_write_dir(irqnr); | |
021f6537 | 374 | #ifdef CONFIG_SMP |
f86c4fbd WD |
375 | /* |
376 | * Unlike GICv2, we don't need an smp_rmb() here. | |
377 | * The control dependency from gic_read_iar to | |
378 | * the ISB in gic_write_eoir is enough to ensure | |
379 | * that any shared data read by handle_IPI will | |
380 | * be read after the ACK. | |
381 | */ | |
021f6537 MZ |
382 | handle_IPI(irqnr, regs); |
383 | #else | |
384 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
385 | #endif | |
386 | continue; | |
387 | } | |
388 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
389 | } | |
390 | ||
391 | static void __init gic_dist_init(void) | |
392 | { | |
393 | unsigned int i; | |
394 | u64 affinity; | |
395 | void __iomem *base = gic_data.dist_base; | |
396 | ||
397 | /* Disable the distributor */ | |
398 | writel_relaxed(0, base + GICD_CTLR); | |
399 | gic_dist_wait_for_rwp(); | |
400 | ||
7c9b9730 MZ |
401 | /* |
402 | * Configure SPIs as non-secure Group-1. This will only matter | |
403 | * if the GIC only has a single security state. This will not | |
404 | * do the right thing if the kernel is running in secure mode, | |
405 | * but that's not the intended use case anyway. | |
406 | */ | |
407 | for (i = 32; i < gic_data.irq_nr; i += 32) | |
408 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); | |
409 | ||
021f6537 MZ |
410 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
411 | ||
412 | /* Enable distributor with ARE, Group1 */ | |
413 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
414 | base + GICD_CTLR); | |
415 | ||
416 | /* | |
417 | * Set all global interrupts to the boot CPU only. ARE must be | |
418 | * enabled. | |
419 | */ | |
420 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
421 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 422 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
423 | } |
424 | ||
425 | static int gic_populate_rdist(void) | |
426 | { | |
f6c86a41 | 427 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
021f6537 MZ |
428 | u64 typer; |
429 | u32 aff; | |
430 | int i; | |
431 | ||
432 | /* | |
433 | * Convert affinity to a 32bit value that can be matched to | |
434 | * GICR_TYPER bits [63:32]. | |
435 | */ | |
436 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
437 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
438 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
439 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
440 | ||
f5c1434c MZ |
441 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
442 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
443 | u32 reg; |
444 | ||
445 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
446 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
447 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
448 | pr_warn("No redistributor present @%p\n", ptr); | |
449 | break; | |
450 | } | |
451 | ||
452 | do { | |
72c97126 | 453 | typer = gic_read_typer(ptr + GICR_TYPER); |
021f6537 | 454 | if ((typer >> 32) == aff) { |
f5c1434c | 455 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 456 | gic_data_rdist_rd_base() = ptr; |
f5c1434c | 457 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
f6c86a41 JPB |
458 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
459 | smp_processor_id(), mpidr, i, | |
460 | &gic_data_rdist()->phys_base); | |
021f6537 MZ |
461 | return 0; |
462 | } | |
463 | ||
b70fb7af TN |
464 | if (gic_data.redist_regions[i].single_redist) |
465 | break; | |
466 | ||
021f6537 MZ |
467 | if (gic_data.redist_stride) { |
468 | ptr += gic_data.redist_stride; | |
469 | } else { | |
470 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
471 | if (typer & GICR_TYPER_VLPIS) | |
472 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
473 | } | |
474 | } while (!(typer & GICR_TYPER_LAST)); | |
475 | } | |
476 | ||
477 | /* We couldn't even deal with ourselves... */ | |
f6c86a41 JPB |
478 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
479 | smp_processor_id(), mpidr); | |
021f6537 MZ |
480 | return -ENODEV; |
481 | } | |
482 | ||
3708d52f SH |
483 | static void gic_cpu_sys_reg_init(void) |
484 | { | |
7cabd008 MZ |
485 | /* |
486 | * Need to check that the SRE bit has actually been set. If | |
487 | * not, it means that SRE is disabled at EL2. We're going to | |
488 | * die painfully, and there is nothing we can do about it. | |
489 | * | |
490 | * Kindly inform the luser. | |
491 | */ | |
492 | if (!gic_enable_sre()) | |
493 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f SH |
494 | |
495 | /* Set priority mask register */ | |
496 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
497 | ||
0b6a3da9 MZ |
498 | if (static_key_true(&supports_deactivate)) { |
499 | /* EOI drops priority only (mode 1) */ | |
500 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
501 | } else { | |
502 | /* EOI deactivates interrupt too (mode 0) */ | |
503 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
504 | } | |
3708d52f SH |
505 | |
506 | /* ... and let's hit the road... */ | |
507 | gic_write_grpen1(1); | |
508 | } | |
509 | ||
da33f31d MZ |
510 | static int gic_dist_supports_lpis(void) |
511 | { | |
512 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
513 | } | |
514 | ||
021f6537 MZ |
515 | static void gic_cpu_init(void) |
516 | { | |
517 | void __iomem *rbase; | |
518 | ||
519 | /* Register ourselves with the rest of the world */ | |
520 | if (gic_populate_rdist()) | |
521 | return; | |
522 | ||
a2c22510 | 523 | gic_enable_redist(true); |
021f6537 MZ |
524 | |
525 | rbase = gic_data_rdist_sgi_base(); | |
526 | ||
7c9b9730 MZ |
527 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
528 | writel_relaxed(~0, rbase + GICR_IGROUPR0); | |
529 | ||
021f6537 MZ |
530 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
531 | ||
da33f31d MZ |
532 | /* Give LPIs a spin */ |
533 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
534 | its_cpu_init(); | |
535 | ||
3708d52f SH |
536 | /* initialise system registers */ |
537 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
538 | } |
539 | ||
540 | #ifdef CONFIG_SMP | |
541 | static int gic_secondary_init(struct notifier_block *nfb, | |
542 | unsigned long action, void *hcpu) | |
543 | { | |
544 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
545 | gic_cpu_init(); | |
546 | return NOTIFY_OK; | |
547 | } | |
548 | ||
549 | /* | |
550 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
551 | * priority because the GIC needs to be up before the ARM generic timers. | |
552 | */ | |
553 | static struct notifier_block gic_cpu_notifier = { | |
554 | .notifier_call = gic_secondary_init, | |
555 | .priority = 100, | |
556 | }; | |
557 | ||
558 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
f6c86a41 | 559 | unsigned long cluster_id) |
021f6537 MZ |
560 | { |
561 | int cpu = *base_cpu; | |
f6c86a41 | 562 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
563 | u16 tlist = 0; |
564 | ||
565 | while (cpu < nr_cpu_ids) { | |
566 | /* | |
567 | * If we ever get a cluster of more than 16 CPUs, just | |
568 | * scream and skip that CPU. | |
569 | */ | |
570 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
571 | goto out; | |
572 | ||
573 | tlist |= 1 << (mpidr & 0xf); | |
574 | ||
575 | cpu = cpumask_next(cpu, mask); | |
614be385 | 576 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
577 | goto out; |
578 | ||
579 | mpidr = cpu_logical_map(cpu); | |
580 | ||
581 | if (cluster_id != (mpidr & ~0xffUL)) { | |
582 | cpu--; | |
583 | goto out; | |
584 | } | |
585 | } | |
586 | out: | |
587 | *base_cpu = cpu; | |
588 | return tlist; | |
589 | } | |
590 | ||
7e580278 AP |
591 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
592 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
593 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
594 | ||
021f6537 MZ |
595 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
596 | { | |
597 | u64 val; | |
598 | ||
7e580278 AP |
599 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
600 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
601 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
602 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
603 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
604 | |
605 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
606 | gic_write_sgi1r(val); | |
607 | } | |
608 | ||
609 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
610 | { | |
611 | int cpu; | |
612 | ||
613 | if (WARN_ON(irq >= 16)) | |
614 | return; | |
615 | ||
616 | /* | |
617 | * Ensure that stores to Normal memory are visible to the | |
618 | * other CPUs before issuing the IPI. | |
619 | */ | |
620 | smp_wmb(); | |
621 | ||
f9b531fe | 622 | for_each_cpu(cpu, mask) { |
f6c86a41 | 623 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
021f6537 MZ |
624 | u16 tlist; |
625 | ||
626 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
627 | gic_send_sgi(cluster_id, tlist, irq); | |
628 | } | |
629 | ||
630 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
631 | isb(); | |
632 | } | |
633 | ||
634 | static void gic_smp_init(void) | |
635 | { | |
636 | set_smp_cross_call(gic_raise_softirq); | |
637 | register_cpu_notifier(&gic_cpu_notifier); | |
638 | } | |
639 | ||
640 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
641 | bool force) | |
642 | { | |
643 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
644 | void __iomem *reg; | |
645 | int enabled; | |
646 | u64 val; | |
647 | ||
648 | if (gic_irq_in_rdist(d)) | |
649 | return -EINVAL; | |
650 | ||
651 | /* If interrupt was enabled, disable it first */ | |
652 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
653 | if (enabled) | |
654 | gic_mask_irq(d); | |
655 | ||
656 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
657 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
658 | ||
72c97126 | 659 | gic_write_irouter(val, reg); |
021f6537 MZ |
660 | |
661 | /* | |
662 | * If the interrupt was enabled, enabled it again. Otherwise, | |
663 | * just wait for the distributor to have digested our changes. | |
664 | */ | |
665 | if (enabled) | |
666 | gic_unmask_irq(d); | |
667 | else | |
668 | gic_dist_wait_for_rwp(); | |
669 | ||
0fc6fa29 | 670 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
671 | } |
672 | #else | |
673 | #define gic_set_affinity NULL | |
674 | #define gic_smp_init() do { } while(0) | |
675 | #endif | |
676 | ||
3708d52f SH |
677 | #ifdef CONFIG_CPU_PM |
678 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
679 | unsigned long cmd, void *v) | |
680 | { | |
681 | if (cmd == CPU_PM_EXIT) { | |
682 | gic_enable_redist(true); | |
683 | gic_cpu_sys_reg_init(); | |
684 | } else if (cmd == CPU_PM_ENTER) { | |
685 | gic_write_grpen1(0); | |
686 | gic_enable_redist(false); | |
687 | } | |
688 | return NOTIFY_OK; | |
689 | } | |
690 | ||
691 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
692 | .notifier_call = gic_cpu_pm_notifier, | |
693 | }; | |
694 | ||
695 | static void gic_cpu_pm_init(void) | |
696 | { | |
697 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
698 | } | |
699 | ||
700 | #else | |
701 | static inline void gic_cpu_pm_init(void) { } | |
702 | #endif /* CONFIG_CPU_PM */ | |
703 | ||
021f6537 MZ |
704 | static struct irq_chip gic_chip = { |
705 | .name = "GICv3", | |
706 | .irq_mask = gic_mask_irq, | |
707 | .irq_unmask = gic_unmask_irq, | |
708 | .irq_eoi = gic_eoi_irq, | |
709 | .irq_set_type = gic_set_type, | |
710 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
711 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
712 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 713 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
714 | }; |
715 | ||
0b6a3da9 MZ |
716 | static struct irq_chip gic_eoimode1_chip = { |
717 | .name = "GICv3", | |
718 | .irq_mask = gic_eoimode1_mask_irq, | |
719 | .irq_unmask = gic_unmask_irq, | |
720 | .irq_eoi = gic_eoimode1_eoi_irq, | |
721 | .irq_set_type = gic_set_type, | |
722 | .irq_set_affinity = gic_set_affinity, | |
723 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
724 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 725 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
726 | .flags = IRQCHIP_SET_TYPE_MASKED, |
727 | }; | |
728 | ||
da33f31d MZ |
729 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
730 | ||
021f6537 MZ |
731 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
732 | irq_hw_number_t hw) | |
733 | { | |
0b6a3da9 MZ |
734 | struct irq_chip *chip = &gic_chip; |
735 | ||
736 | if (static_key_true(&supports_deactivate)) | |
737 | chip = &gic_eoimode1_chip; | |
738 | ||
021f6537 MZ |
739 | /* SGIs are private to the core kernel */ |
740 | if (hw < 16) | |
741 | return -EPERM; | |
da33f31d MZ |
742 | /* Nothing here */ |
743 | if (hw >= gic_data.irq_nr && hw < 8192) | |
744 | return -EPERM; | |
745 | /* Off limits */ | |
746 | if (hw >= GIC_ID_NR) | |
747 | return -EPERM; | |
748 | ||
021f6537 MZ |
749 | /* PPIs */ |
750 | if (hw < 32) { | |
751 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 752 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 753 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 754 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
755 | } |
756 | /* SPIs */ | |
757 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 758 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 759 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 760 | irq_set_probe(irq); |
021f6537 | 761 | } |
da33f31d MZ |
762 | /* LPIs */ |
763 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
764 | if (!gic_dist_supports_lpis()) | |
765 | return -EPERM; | |
0b6a3da9 | 766 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 767 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
768 | } |
769 | ||
021f6537 MZ |
770 | return 0; |
771 | } | |
772 | ||
f833f57f MZ |
773 | static int gic_irq_domain_translate(struct irq_domain *d, |
774 | struct irq_fwspec *fwspec, | |
775 | unsigned long *hwirq, | |
776 | unsigned int *type) | |
021f6537 | 777 | { |
f833f57f MZ |
778 | if (is_of_node(fwspec->fwnode)) { |
779 | if (fwspec->param_count < 3) | |
780 | return -EINVAL; | |
021f6537 | 781 | |
db8c70ec MZ |
782 | switch (fwspec->param[0]) { |
783 | case 0: /* SPI */ | |
784 | *hwirq = fwspec->param[1] + 32; | |
785 | break; | |
786 | case 1: /* PPI */ | |
787 | *hwirq = fwspec->param[1] + 16; | |
788 | break; | |
789 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
790 | *hwirq = fwspec->param[1]; | |
791 | break; | |
792 | default: | |
793 | return -EINVAL; | |
794 | } | |
f833f57f MZ |
795 | |
796 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
797 | return 0; | |
021f6537 MZ |
798 | } |
799 | ||
ffa7d616 TN |
800 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
801 | if(fwspec->param_count != 2) | |
802 | return -EINVAL; | |
803 | ||
804 | *hwirq = fwspec->param[0]; | |
805 | *type = fwspec->param[1]; | |
806 | return 0; | |
807 | } | |
808 | ||
f833f57f | 809 | return -EINVAL; |
021f6537 MZ |
810 | } |
811 | ||
443acc4f MZ |
812 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
813 | unsigned int nr_irqs, void *arg) | |
814 | { | |
815 | int i, ret; | |
816 | irq_hw_number_t hwirq; | |
817 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 818 | struct irq_fwspec *fwspec = arg; |
443acc4f | 819 | |
f833f57f | 820 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
821 | if (ret) |
822 | return ret; | |
823 | ||
824 | for (i = 0; i < nr_irqs; i++) | |
825 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
830 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
831 | unsigned int nr_irqs) | |
832 | { | |
833 | int i; | |
834 | ||
835 | for (i = 0; i < nr_irqs; i++) { | |
836 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
837 | irq_set_handler(virq + i, NULL); | |
838 | irq_domain_reset_irq_data(d); | |
839 | } | |
840 | } | |
841 | ||
e3825ba1 MZ |
842 | static int gic_irq_domain_select(struct irq_domain *d, |
843 | struct irq_fwspec *fwspec, | |
844 | enum irq_domain_bus_token bus_token) | |
845 | { | |
846 | /* Not for us */ | |
847 | if (fwspec->fwnode != d->fwnode) | |
848 | return 0; | |
849 | ||
850 | /* If this is not DT, then we have a single domain */ | |
851 | if (!is_of_node(fwspec->fwnode)) | |
852 | return 1; | |
853 | ||
854 | /* | |
855 | * If this is a PPI and we have a 4th (non-null) parameter, | |
856 | * then we need to match the partition domain. | |
857 | */ | |
858 | if (fwspec->param_count >= 4 && | |
859 | fwspec->param[0] == 1 && fwspec->param[3] != 0) | |
860 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); | |
861 | ||
862 | return d == gic_data.domain; | |
863 | } | |
864 | ||
021f6537 | 865 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 866 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
867 | .alloc = gic_irq_domain_alloc, |
868 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
869 | .select = gic_irq_domain_select, |
870 | }; | |
871 | ||
872 | static int partition_domain_translate(struct irq_domain *d, | |
873 | struct irq_fwspec *fwspec, | |
874 | unsigned long *hwirq, | |
875 | unsigned int *type) | |
876 | { | |
877 | struct device_node *np; | |
878 | int ret; | |
879 | ||
880 | np = of_find_node_by_phandle(fwspec->param[3]); | |
881 | if (WARN_ON(!np)) | |
882 | return -EINVAL; | |
883 | ||
884 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
885 | of_node_to_fwnode(np)); | |
886 | if (ret < 0) | |
887 | return ret; | |
888 | ||
889 | *hwirq = ret; | |
890 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
895 | static const struct irq_domain_ops partition_domain_ops = { | |
896 | .translate = partition_domain_translate, | |
897 | .select = gic_irq_domain_select, | |
021f6537 MZ |
898 | }; |
899 | ||
6d4e11c5 RR |
900 | static void gicv3_enable_quirks(void) |
901 | { | |
7936e914 | 902 | #ifdef CONFIG_ARM64 |
6d4e11c5 | 903 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
8ac2a170 | 904 | static_branch_enable(&is_cavium_thunderx); |
7936e914 | 905 | #endif |
6d4e11c5 RR |
906 | } |
907 | ||
db57d746 TN |
908 | static int __init gic_init_bases(void __iomem *dist_base, |
909 | struct redist_region *rdist_regs, | |
910 | u32 nr_redist_regions, | |
911 | u64 redist_stride, | |
912 | struct fwnode_handle *handle) | |
021f6537 | 913 | { |
db57d746 | 914 | struct device_node *node; |
f5c1434c | 915 | u32 typer; |
021f6537 MZ |
916 | int gic_irqs; |
917 | int err; | |
021f6537 | 918 | |
0b6a3da9 MZ |
919 | if (!is_hyp_mode_available()) |
920 | static_key_slow_dec(&supports_deactivate); | |
921 | ||
922 | if (static_key_true(&supports_deactivate)) | |
923 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
924 | ||
e3825ba1 | 925 | gic_data.fwnode = handle; |
021f6537 | 926 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
927 | gic_data.redist_regions = rdist_regs; |
928 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
929 | gic_data.redist_stride = redist_stride; |
930 | ||
6d4e11c5 RR |
931 | gicv3_enable_quirks(); |
932 | ||
021f6537 MZ |
933 | /* |
934 | * Find out how many interrupts are supported. | |
935 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
936 | */ | |
f5c1434c MZ |
937 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
938 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
939 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
940 | if (gic_irqs > 1020) |
941 | gic_irqs = 1020; | |
942 | gic_data.irq_nr = gic_irqs; | |
943 | ||
db57d746 TN |
944 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
945 | &gic_data); | |
f5c1434c | 946 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 947 | |
f5c1434c | 948 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
949 | err = -ENOMEM; |
950 | goto out_free; | |
951 | } | |
952 | ||
953 | set_handle_irq(gic_handle_irq); | |
954 | ||
db57d746 TN |
955 | node = to_of_node(handle); |
956 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && | |
957 | node) /* Temp hack to prevent ITS init for ACPI */ | |
da33f31d MZ |
958 | its_init(node, &gic_data.rdists, gic_data.domain); |
959 | ||
021f6537 MZ |
960 | gic_smp_init(); |
961 | gic_dist_init(); | |
962 | gic_cpu_init(); | |
3708d52f | 963 | gic_cpu_pm_init(); |
021f6537 MZ |
964 | |
965 | return 0; | |
966 | ||
967 | out_free: | |
968 | if (gic_data.domain) | |
969 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 970 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
971 | return err; |
972 | } | |
973 | ||
974 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
975 | { | |
976 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
977 | ||
978 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
979 | return -ENODEV; | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
e3825ba1 MZ |
984 | static int get_cpu_number(struct device_node *dn) |
985 | { | |
986 | const __be32 *cell; | |
987 | u64 hwid; | |
988 | int i; | |
989 | ||
990 | cell = of_get_property(dn, "reg", NULL); | |
991 | if (!cell) | |
992 | return -1; | |
993 | ||
994 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
995 | ||
996 | /* | |
997 | * Non affinity bits must be set to 0 in the DT | |
998 | */ | |
999 | if (hwid & ~MPIDR_HWID_BITMASK) | |
1000 | return -1; | |
1001 | ||
1002 | for (i = 0; i < num_possible_cpus(); i++) | |
1003 | if (cpu_logical_map(i) == hwid) | |
1004 | return i; | |
1005 | ||
1006 | return -1; | |
1007 | } | |
1008 | ||
1009 | /* Create all possible partitions at boot time */ | |
7beaa24b | 1010 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
1011 | { |
1012 | struct device_node *parts_node, *child_part; | |
1013 | int part_idx = 0, i; | |
1014 | int nr_parts; | |
1015 | struct partition_affinity *parts; | |
1016 | ||
1017 | parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); | |
1018 | if (!parts_node) | |
1019 | return; | |
1020 | ||
1021 | nr_parts = of_get_child_count(parts_node); | |
1022 | ||
1023 | if (!nr_parts) | |
1024 | return; | |
1025 | ||
1026 | parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); | |
1027 | if (WARN_ON(!parts)) | |
1028 | return; | |
1029 | ||
1030 | for_each_child_of_node(parts_node, child_part) { | |
1031 | struct partition_affinity *part; | |
1032 | int n; | |
1033 | ||
1034 | part = &parts[part_idx]; | |
1035 | ||
1036 | part->partition_id = of_node_to_fwnode(child_part); | |
1037 | ||
1038 | pr_info("GIC: PPI partition %s[%d] { ", | |
1039 | child_part->name, part_idx); | |
1040 | ||
1041 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1042 | sizeof(u32)); | |
1043 | WARN_ON(n <= 0); | |
1044 | ||
1045 | for (i = 0; i < n; i++) { | |
1046 | int err, cpu; | |
1047 | u32 cpu_phandle; | |
1048 | struct device_node *cpu_node; | |
1049 | ||
1050 | err = of_property_read_u32_index(child_part, "affinity", | |
1051 | i, &cpu_phandle); | |
1052 | if (WARN_ON(err)) | |
1053 | continue; | |
1054 | ||
1055 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1056 | if (WARN_ON(!cpu_node)) | |
1057 | continue; | |
1058 | ||
1059 | cpu = get_cpu_number(cpu_node); | |
1060 | if (WARN_ON(cpu == -1)) | |
1061 | continue; | |
1062 | ||
1063 | pr_cont("%s[%d] ", cpu_node->full_name, cpu); | |
1064 | ||
1065 | cpumask_set_cpu(cpu, &part->mask); | |
1066 | } | |
1067 | ||
1068 | pr_cont("}\n"); | |
1069 | part_idx++; | |
1070 | } | |
1071 | ||
1072 | for (i = 0; i < 16; i++) { | |
1073 | unsigned int irq; | |
1074 | struct partition_desc *desc; | |
1075 | struct irq_fwspec ppi_fwspec = { | |
1076 | .fwnode = gic_data.fwnode, | |
1077 | .param_count = 3, | |
1078 | .param = { | |
1079 | [0] = 1, | |
1080 | [1] = i, | |
1081 | [2] = IRQ_TYPE_NONE, | |
1082 | }, | |
1083 | }; | |
1084 | ||
1085 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1086 | if (WARN_ON(!irq)) | |
1087 | continue; | |
1088 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1089 | irq, &partition_domain_ops); | |
1090 | if (WARN_ON(!desc)) | |
1091 | continue; | |
1092 | ||
1093 | gic_data.ppi_descs[i] = desc; | |
1094 | } | |
1095 | } | |
1096 | ||
1839e576 JG |
1097 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1098 | { | |
1099 | int ret; | |
1100 | struct resource r; | |
1101 | u32 gicv_idx; | |
1102 | ||
1103 | gic_v3_kvm_info.type = GIC_V3; | |
1104 | ||
1105 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1106 | if (!gic_v3_kvm_info.maint_irq) | |
1107 | return; | |
1108 | ||
1109 | if (of_property_read_u32(node, "#redistributor-regions", | |
1110 | &gicv_idx)) | |
1111 | gicv_idx = 1; | |
1112 | ||
1113 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
1114 | ret = of_address_to_resource(node, gicv_idx, &r); | |
1115 | if (!ret) | |
1116 | gic_v3_kvm_info.vcpu = r; | |
1117 | ||
1118 | gic_set_kvm_info(&gic_v3_kvm_info); | |
1119 | } | |
1120 | ||
db57d746 TN |
1121 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1122 | { | |
1123 | void __iomem *dist_base; | |
1124 | struct redist_region *rdist_regs; | |
1125 | u64 redist_stride; | |
1126 | u32 nr_redist_regions; | |
1127 | int err, i; | |
1128 | ||
1129 | dist_base = of_iomap(node, 0); | |
1130 | if (!dist_base) { | |
1131 | pr_err("%s: unable to map gic dist registers\n", | |
1132 | node->full_name); | |
1133 | return -ENXIO; | |
1134 | } | |
1135 | ||
1136 | err = gic_validate_dist_version(dist_base); | |
1137 | if (err) { | |
1138 | pr_err("%s: no distributor detected, giving up\n", | |
1139 | node->full_name); | |
1140 | goto out_unmap_dist; | |
1141 | } | |
1142 | ||
1143 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1144 | nr_redist_regions = 1; | |
1145 | ||
1146 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); | |
1147 | if (!rdist_regs) { | |
1148 | err = -ENOMEM; | |
1149 | goto out_unmap_dist; | |
1150 | } | |
1151 | ||
1152 | for (i = 0; i < nr_redist_regions; i++) { | |
1153 | struct resource res; | |
1154 | int ret; | |
1155 | ||
1156 | ret = of_address_to_resource(node, 1 + i, &res); | |
1157 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1158 | if (ret || !rdist_regs[i].redist_base) { | |
1159 | pr_err("%s: couldn't map region %d\n", | |
1160 | node->full_name, i); | |
1161 | err = -ENODEV; | |
1162 | goto out_unmap_rdist; | |
1163 | } | |
1164 | rdist_regs[i].phys_base = res.start; | |
1165 | } | |
1166 | ||
1167 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1168 | redist_stride = 0; | |
1169 | ||
1170 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
1171 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1172 | if (err) |
1173 | goto out_unmap_rdist; | |
1174 | ||
1175 | gic_populate_ppi_partitions(node); | |
7beaa24b | 1176 | gic_of_setup_kvm_info(node); |
e3825ba1 | 1177 | return 0; |
db57d746 | 1178 | |
021f6537 | 1179 | out_unmap_rdist: |
f5c1434c MZ |
1180 | for (i = 0; i < nr_redist_regions; i++) |
1181 | if (rdist_regs[i].redist_base) | |
1182 | iounmap(rdist_regs[i].redist_base); | |
1183 | kfree(rdist_regs); | |
021f6537 MZ |
1184 | out_unmap_dist: |
1185 | iounmap(dist_base); | |
1186 | return err; | |
1187 | } | |
1188 | ||
1189 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1190 | |
1191 | #ifdef CONFIG_ACPI | |
611f039f JG |
1192 | static struct |
1193 | { | |
1194 | void __iomem *dist_base; | |
1195 | struct redist_region *redist_regs; | |
1196 | u32 nr_redist_regions; | |
1197 | bool single_redist; | |
1839e576 JG |
1198 | u32 maint_irq; |
1199 | int maint_irq_mode; | |
1200 | phys_addr_t vcpu_base; | |
611f039f | 1201 | } acpi_data __initdata; |
b70fb7af TN |
1202 | |
1203 | static void __init | |
1204 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1205 | { | |
1206 | static int count = 0; | |
1207 | ||
611f039f JG |
1208 | acpi_data.redist_regs[count].phys_base = phys_base; |
1209 | acpi_data.redist_regs[count].redist_base = redist_base; | |
1210 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
1211 | count++; |
1212 | } | |
ffa7d616 TN |
1213 | |
1214 | static int __init | |
1215 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
1216 | const unsigned long end) | |
1217 | { | |
1218 | struct acpi_madt_generic_redistributor *redist = | |
1219 | (struct acpi_madt_generic_redistributor *)header; | |
1220 | void __iomem *redist_base; | |
ffa7d616 TN |
1221 | |
1222 | redist_base = ioremap(redist->base_address, redist->length); | |
1223 | if (!redist_base) { | |
1224 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1225 | return -ENOMEM; | |
1226 | } | |
1227 | ||
b70fb7af | 1228 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1229 | return 0; |
1230 | } | |
1231 | ||
b70fb7af TN |
1232 | static int __init |
1233 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1234 | const unsigned long end) | |
1235 | { | |
1236 | struct acpi_madt_generic_interrupt *gicc = | |
1237 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 1238 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
1239 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
1240 | void __iomem *redist_base; | |
1241 | ||
1242 | redist_base = ioremap(gicc->gicr_base_address, size); | |
1243 | if (!redist_base) | |
1244 | return -ENOMEM; | |
1245 | ||
1246 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static int __init gic_acpi_collect_gicr_base(void) | |
1251 | { | |
1252 | acpi_tbl_entry_handler redist_parser; | |
1253 | enum acpi_madt_type type; | |
1254 | ||
611f039f | 1255 | if (acpi_data.single_redist) { |
b70fb7af TN |
1256 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
1257 | redist_parser = gic_acpi_parse_madt_gicc; | |
1258 | } else { | |
1259 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1260 | redist_parser = gic_acpi_parse_madt_redist; | |
1261 | } | |
1262 | ||
1263 | /* Collect redistributor base addresses in GICR entries */ | |
1264 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1265 | return 0; | |
1266 | ||
1267 | pr_info("No valid GICR entries exist\n"); | |
1268 | return -ENODEV; | |
1269 | } | |
1270 | ||
ffa7d616 TN |
1271 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1272 | const unsigned long end) | |
1273 | { | |
1274 | /* Subtable presence means that redist exists, that's it */ | |
1275 | return 0; | |
1276 | } | |
1277 | ||
b70fb7af TN |
1278 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1279 | const unsigned long end) | |
1280 | { | |
1281 | struct acpi_madt_generic_interrupt *gicc = | |
1282 | (struct acpi_madt_generic_interrupt *)header; | |
1283 | ||
1284 | /* | |
1285 | * If GICC is enabled and has valid gicr base address, then it means | |
1286 | * GICR base is presented via GICC | |
1287 | */ | |
1288 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1289 | return 0; | |
1290 | ||
1291 | return -ENODEV; | |
1292 | } | |
1293 | ||
1294 | static int __init gic_acpi_count_gicr_regions(void) | |
1295 | { | |
1296 | int count; | |
1297 | ||
1298 | /* | |
1299 | * Count how many redistributor regions we have. It is not allowed | |
1300 | * to mix redistributor description, GICR and GICC subtables have to be | |
1301 | * mutually exclusive. | |
1302 | */ | |
1303 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1304 | gic_acpi_match_gicr, 0); | |
1305 | if (count > 0) { | |
611f039f | 1306 | acpi_data.single_redist = false; |
b70fb7af TN |
1307 | return count; |
1308 | } | |
1309 | ||
1310 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1311 | gic_acpi_match_gicc, 0); | |
1312 | if (count > 0) | |
611f039f | 1313 | acpi_data.single_redist = true; |
b70fb7af TN |
1314 | |
1315 | return count; | |
1316 | } | |
1317 | ||
ffa7d616 TN |
1318 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1319 | struct acpi_probe_entry *ape) | |
1320 | { | |
1321 | struct acpi_madt_generic_distributor *dist; | |
1322 | int count; | |
1323 | ||
1324 | dist = (struct acpi_madt_generic_distributor *)header; | |
1325 | if (dist->version != ape->driver_data) | |
1326 | return false; | |
1327 | ||
1328 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1329 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1330 | if (count <= 0) |
1331 | return false; | |
1332 | ||
611f039f | 1333 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
1334 | return true; |
1335 | } | |
1336 | ||
1839e576 JG |
1337 | static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, |
1338 | const unsigned long end) | |
1339 | { | |
1340 | struct acpi_madt_generic_interrupt *gicc = | |
1341 | (struct acpi_madt_generic_interrupt *)header; | |
1342 | int maint_irq_mode; | |
1343 | static int first_madt = true; | |
1344 | ||
1345 | /* Skip unusable CPUs */ | |
1346 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1347 | return 0; | |
1348 | ||
1349 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1350 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1351 | ||
1352 | if (first_madt) { | |
1353 | first_madt = false; | |
1354 | ||
1355 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
1356 | acpi_data.maint_irq_mode = maint_irq_mode; | |
1357 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * The maintenance interrupt and GICV should be the same for every CPU | |
1364 | */ | |
1365 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
1366 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
1367 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
1368 | return -EINVAL; | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static bool __init gic_acpi_collect_virt_info(void) | |
1374 | { | |
1375 | int count; | |
1376 | ||
1377 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1378 | gic_acpi_parse_virt_madt_gicc, 0); | |
1379 | ||
1380 | return (count > 0); | |
1381 | } | |
1382 | ||
ffa7d616 | 1383 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
1384 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1385 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1386 | ||
1387 | static void __init gic_acpi_setup_kvm_info(void) | |
1388 | { | |
1389 | int irq; | |
1390 | ||
1391 | if (!gic_acpi_collect_virt_info()) { | |
1392 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
1393 | return; | |
1394 | } | |
1395 | ||
1396 | gic_v3_kvm_info.type = GIC_V3; | |
1397 | ||
1398 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1399 | acpi_data.maint_irq_mode, | |
1400 | ACPI_ACTIVE_HIGH); | |
1401 | if (irq <= 0) | |
1402 | return; | |
1403 | ||
1404 | gic_v3_kvm_info.maint_irq = irq; | |
1405 | ||
1406 | if (acpi_data.vcpu_base) { | |
1407 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
1408 | ||
1409 | vcpu->flags = IORESOURCE_MEM; | |
1410 | vcpu->start = acpi_data.vcpu_base; | |
1411 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1412 | } | |
1413 | ||
1414 | gic_set_kvm_info(&gic_v3_kvm_info); | |
1415 | } | |
ffa7d616 TN |
1416 | |
1417 | static int __init | |
1418 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1419 | { | |
1420 | struct acpi_madt_generic_distributor *dist; | |
1421 | struct fwnode_handle *domain_handle; | |
611f039f | 1422 | size_t size; |
b70fb7af | 1423 | int i, err; |
ffa7d616 TN |
1424 | |
1425 | /* Get distributor base address */ | |
1426 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
1427 | acpi_data.dist_base = ioremap(dist->base_address, |
1428 | ACPI_GICV3_DIST_MEM_SIZE); | |
1429 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
1430 | pr_err("Unable to map GICD registers\n"); |
1431 | return -ENOMEM; | |
1432 | } | |
1433 | ||
611f039f | 1434 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 1435 | if (err) { |
611f039f JG |
1436 | pr_err("No distributor detected at @%p, giving up", |
1437 | acpi_data.dist_base); | |
ffa7d616 TN |
1438 | goto out_dist_unmap; |
1439 | } | |
1440 | ||
611f039f JG |
1441 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
1442 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
1443 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
1444 | err = -ENOMEM; |
1445 | goto out_dist_unmap; | |
1446 | } | |
1447 | ||
b70fb7af TN |
1448 | err = gic_acpi_collect_gicr_base(); |
1449 | if (err) | |
ffa7d616 | 1450 | goto out_redist_unmap; |
ffa7d616 | 1451 | |
611f039f | 1452 | domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); |
ffa7d616 TN |
1453 | if (!domain_handle) { |
1454 | err = -ENOMEM; | |
1455 | goto out_redist_unmap; | |
1456 | } | |
1457 | ||
611f039f JG |
1458 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
1459 | acpi_data.nr_redist_regions, 0, domain_handle); | |
ffa7d616 TN |
1460 | if (err) |
1461 | goto out_fwhandle_free; | |
1462 | ||
1463 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
1839e576 JG |
1464 | gic_acpi_setup_kvm_info(); |
1465 | ||
ffa7d616 TN |
1466 | return 0; |
1467 | ||
1468 | out_fwhandle_free: | |
1469 | irq_domain_free_fwnode(domain_handle); | |
1470 | out_redist_unmap: | |
611f039f JG |
1471 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
1472 | if (acpi_data.redist_regs[i].redist_base) | |
1473 | iounmap(acpi_data.redist_regs[i].redist_base); | |
1474 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 1475 | out_dist_unmap: |
611f039f | 1476 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
1477 | return err; |
1478 | } | |
1479 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1480 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1481 | gic_acpi_init); | |
1482 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1483 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1484 | gic_acpi_init); | |
1485 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1486 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1487 | gic_acpi_init); | |
1488 | #endif |