ethernet: ti: davinci_emac: add missing of_node_put after calling of_parse_phandle
[deliverable/linux.git] / drivers / irqchip / irq-gic.c
CommitLineData
f27ecacc 1/*
f27ecacc
RK
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
b3a1bde4
CM
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
f27ecacc
RK
18 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
f37a53cc 25#include <linux/err.h>
7e1efcf5 26#include <linux/module.h>
f27ecacc
RK
27#include <linux/list.h>
28#include <linux/smp.h>
c0114709 29#include <linux/cpu.h>
254056f3 30#include <linux/cpu_pm.h>
dcb86e8c 31#include <linux/cpumask.h>
fced80c7 32#include <linux/io.h>
b3f7ed03
RH
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
d60fc389 36#include <linux/acpi.h>
4294f8ba 37#include <linux/irqdomain.h>
292b293c
MZ
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41a83e06 41#include <linux/irqchip.h>
de88cbb7 42#include <linux/irqchip/chained_irq.h>
520f7bd7 43#include <linux/irqchip/arm-gic.h>
f27ecacc 44
29e697b1 45#include <asm/cputype.h>
f27ecacc 46#include <asm/irq.h>
562e0027 47#include <asm/exception.h>
eb50439b 48#include <asm/smp_plat.h>
0b996fd3 49#include <asm/virt.h>
f27ecacc 50
d51d0af4 51#include "irq-gic-common.h"
f27ecacc 52
76e52dd0
MZ
53#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
25fc11ae 58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
76e52dd0
MZ
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
db0d4db2
MZ
66union gic_base {
67 void __iomem *common_base;
6859358e 68 void __percpu * __iomem *percpu_base;
db0d4db2
MZ
69};
70
71struct gic_chip_data {
58b89649 72 struct irq_chip chip;
db0d4db2
MZ
73 union gic_base dist_base;
74 union gic_base cpu_base;
f673b9b5
JH
75 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base;
77 u32 percpu_offset;
9c8edddf 78#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
db0d4db2 79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
1c7d4dd4 80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
db0d4db2
MZ
81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
83 u32 __percpu *saved_ppi_enable;
1c7d4dd4 84 u32 __percpu *saved_ppi_active;
db0d4db2
MZ
85 u32 __percpu *saved_ppi_conf;
86#endif
75294957 87 struct irq_domain *domain;
db0d4db2
MZ
88 unsigned int gic_irqs;
89#ifdef CONFIG_GIC_NON_BANKED
90 void __iomem *(*get_base)(union gic_base *);
91#endif
92};
93
bd31b859 94static DEFINE_RAW_SPINLOCK(irq_controller_lock);
f27ecacc 95
384a2902
NP
96/*
97 * The GIC mapping of CPU interfaces does not necessarily match
98 * the logical CPU numbering. Let's use a mapping as returned
99 * by the GIC itself.
100 */
101#define NR_GIC_CPU_IF 8
102static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
103
0b996fd3
MZ
104static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
105
a27d21e0 106static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
b3a1bde4 107
502d6df1
JG
108static struct gic_kvm_info gic_v2_kvm_info;
109
db0d4db2
MZ
110#ifdef CONFIG_GIC_NON_BANKED
111static void __iomem *gic_get_percpu_base(union gic_base *base)
112{
513d1a28 113 return raw_cpu_read(*base->percpu_base);
db0d4db2
MZ
114}
115
116static void __iomem *gic_get_common_base(union gic_base *base)
117{
118 return base->common_base;
119}
120
121static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
122{
123 return data->get_base(&data->dist_base);
124}
125
126static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
127{
128 return data->get_base(&data->cpu_base);
129}
130
131static inline void gic_set_base_accessor(struct gic_chip_data *data,
132 void __iomem *(*f)(union gic_base *))
133{
134 data->get_base = f;
135}
136#else
137#define gic_data_dist_base(d) ((d)->dist_base.common_base)
138#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
46f101df 139#define gic_set_base_accessor(d, f)
db0d4db2
MZ
140#endif
141
7d1f4288 142static inline void __iomem *gic_dist_base(struct irq_data *d)
b3a1bde4 143{
7d1f4288 144 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
db0d4db2 145 return gic_data_dist_base(gic_data);
b3a1bde4
CM
146}
147
7d1f4288 148static inline void __iomem *gic_cpu_base(struct irq_data *d)
b3a1bde4 149{
7d1f4288 150 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
db0d4db2 151 return gic_data_cpu_base(gic_data);
b3a1bde4
CM
152}
153
7d1f4288 154static inline unsigned int gic_irq(struct irq_data *d)
b3a1bde4 155{
4294f8ba 156 return d->hwirq;
b3a1bde4
CM
157}
158
01f779f4
MZ
159static inline bool cascading_gic_irq(struct irq_data *d)
160{
161 void *data = irq_data_get_irq_handler_data(d);
162
163 /*
71466535
TG
164 * If handler_data is set, this is a cascading interrupt, and
165 * it cannot possibly be forwarded.
01f779f4 166 */
71466535 167 return data != NULL;
01f779f4
MZ
168}
169
f27ecacc
RK
170/*
171 * Routines to acknowledge, disable and enable interrupts
f27ecacc 172 */
56717807
MZ
173static void gic_poke_irq(struct irq_data *d, u32 offset)
174{
175 u32 mask = 1 << (gic_irq(d) % 32);
176 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
177}
178
179static int gic_peek_irq(struct irq_data *d, u32 offset)
f27ecacc 180{
4294f8ba 181 u32 mask = 1 << (gic_irq(d) % 32);
56717807
MZ
182 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
183}
184
185static void gic_mask_irq(struct irq_data *d)
186{
56717807 187 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
f27ecacc
RK
188}
189
0b996fd3
MZ
190static void gic_eoimode1_mask_irq(struct irq_data *d)
191{
192 gic_mask_irq(d);
01f779f4
MZ
193 /*
194 * When masking a forwarded interrupt, make sure it is
195 * deactivated as well.
196 *
197 * This ensures that an interrupt that is getting
198 * disabled/masked will not get "stuck", because there is
199 * noone to deactivate it (guest is being terminated).
200 */
71466535 201 if (irqd_is_forwarded_to_vcpu(d))
01f779f4 202 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
0b996fd3
MZ
203}
204
7d1f4288 205static void gic_unmask_irq(struct irq_data *d)
f27ecacc 206{
56717807 207 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
f27ecacc
RK
208}
209
1a01753e
WD
210static void gic_eoi_irq(struct irq_data *d)
211{
6ac77e46 212 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
1a01753e
WD
213}
214
0b996fd3
MZ
215static void gic_eoimode1_eoi_irq(struct irq_data *d)
216{
01f779f4 217 /* Do not deactivate an IRQ forwarded to a vcpu. */
71466535 218 if (irqd_is_forwarded_to_vcpu(d))
01f779f4
MZ
219 return;
220
0b996fd3
MZ
221 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
222}
223
56717807
MZ
224static int gic_irq_set_irqchip_state(struct irq_data *d,
225 enum irqchip_irq_state which, bool val)
226{
227 u32 reg;
228
229 switch (which) {
230 case IRQCHIP_STATE_PENDING:
231 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
232 break;
233
234 case IRQCHIP_STATE_ACTIVE:
235 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
236 break;
237
238 case IRQCHIP_STATE_MASKED:
239 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
240 break;
241
242 default:
243 return -EINVAL;
244 }
245
246 gic_poke_irq(d, reg);
247 return 0;
248}
249
250static int gic_irq_get_irqchip_state(struct irq_data *d,
251 enum irqchip_irq_state which, bool *val)
252{
253 switch (which) {
254 case IRQCHIP_STATE_PENDING:
255 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
256 break;
257
258 case IRQCHIP_STATE_ACTIVE:
259 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
260 break;
261
262 case IRQCHIP_STATE_MASKED:
263 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
264 break;
265
266 default:
267 return -EINVAL;
268 }
269
270 return 0;
271}
272
7d1f4288 273static int gic_set_type(struct irq_data *d, unsigned int type)
5c0c1f08 274{
7d1f4288
LB
275 void __iomem *base = gic_dist_base(d);
276 unsigned int gicirq = gic_irq(d);
5c0c1f08
RV
277
278 /* Interrupt configuration for SGIs can't be changed */
279 if (gicirq < 16)
280 return -EINVAL;
281
fb7e7deb
LD
282 /* SPIs have restrictions on the supported types */
283 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
284 type != IRQ_TYPE_EDGE_RISING)
5c0c1f08
RV
285 return -EINVAL;
286
1dcc73d7 287 return gic_configure_irq(gicirq, type, base, NULL);
d7ed36a4
SS
288}
289
01f779f4
MZ
290static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
291{
292 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
293 if (cascading_gic_irq(d))
294 return -EINVAL;
295
71466535
TG
296 if (vcpu)
297 irqd_set_forwarded_to_vcpu(d);
298 else
299 irqd_clr_forwarded_to_vcpu(d);
01f779f4
MZ
300 return 0;
301}
302
a06f5466 303#ifdef CONFIG_SMP
c191789c
RK
304static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
305 bool force)
f27ecacc 306{
7d1f4288 307 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
ffde1de6 308 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
c191789c 309 u32 val, mask, bit;
cf613871 310 unsigned long flags;
f27ecacc 311
ffde1de6
TG
312 if (!force)
313 cpu = cpumask_any_and(mask_val, cpu_online_mask);
314 else
315 cpu = cpumask_first(mask_val);
316
384a2902 317 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
87507500 318 return -EINVAL;
c191789c 319
cf613871 320 raw_spin_lock_irqsave(&irq_controller_lock, flags);
c191789c 321 mask = 0xff << shift;
384a2902 322 bit = gic_cpu_map[cpu] << shift;
6ac77e46
SS
323 val = readl_relaxed(reg) & ~mask;
324 writel_relaxed(val | bit, reg);
cf613871 325 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
d5dedd45 326
0407dace 327 return IRQ_SET_MASK_OK_DONE;
f27ecacc 328}
a06f5466 329#endif
f27ecacc 330
8783dd3a 331static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
562e0027
MZ
332{
333 u32 irqstat, irqnr;
334 struct gic_chip_data *gic = &gic_data[0];
335 void __iomem *cpu_base = gic_data_cpu_base(gic);
336
337 do {
338 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
b8802f76 339 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
562e0027 340
327ebe1f 341 if (likely(irqnr > 15 && irqnr < 1020)) {
0b996fd3
MZ
342 if (static_key_true(&supports_deactivate))
343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
60031b4e 344 handle_domain_irq(gic->domain, irqnr, regs);
562e0027
MZ
345 continue;
346 }
347 if (irqnr < 16) {
348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
0b996fd3
MZ
349 if (static_key_true(&supports_deactivate))
350 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
562e0027 351#ifdef CONFIG_SMP
f86c4fbd
WD
352 /*
353 * Ensure any shared data written by the CPU sending
354 * the IPI is read after we've read the ACK register
355 * on the GIC.
356 *
357 * Pairs with the write barrier in gic_raise_softirq
358 */
359 smp_rmb();
562e0027
MZ
360 handle_IPI(irqnr, regs);
361#endif
362 continue;
363 }
364 break;
365 } while (1);
366}
367
bd0b9ac4 368static void gic_handle_cascade_irq(struct irq_desc *desc)
b3a1bde4 369{
5b29264c
JL
370 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
371 struct irq_chip *chip = irq_desc_get_chip(desc);
0f347bb9 372 unsigned int cascade_irq, gic_irq;
b3a1bde4
CM
373 unsigned long status;
374
1a01753e 375 chained_irq_enter(chip, desc);
b3a1bde4 376
bd31b859 377 raw_spin_lock(&irq_controller_lock);
db0d4db2 378 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
bd31b859 379 raw_spin_unlock(&irq_controller_lock);
b3a1bde4 380
e5f81539
FK
381 gic_irq = (status & GICC_IAR_INT_ID_MASK);
382 if (gic_irq == GICC_INT_SPURIOUS)
b3a1bde4 383 goto out;
b3a1bde4 384
75294957
GL
385 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
386 if (unlikely(gic_irq < 32 || gic_irq > 1020))
bd0b9ac4 387 handle_bad_irq(desc);
0f347bb9
RK
388 else
389 generic_handle_irq(cascade_irq);
b3a1bde4
CM
390
391 out:
1a01753e 392 chained_irq_exit(chip, desc);
b3a1bde4
CM
393}
394
38c677cb 395static struct irq_chip gic_chip = {
7d1f4288
LB
396 .irq_mask = gic_mask_irq,
397 .irq_unmask = gic_unmask_irq,
1a01753e 398 .irq_eoi = gic_eoi_irq,
7d1f4288 399 .irq_set_type = gic_set_type,
56717807
MZ
400 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
401 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
aec89ef7
SH
402 .flags = IRQCHIP_SET_TYPE_MASKED |
403 IRQCHIP_SKIP_SET_WAKE |
404 IRQCHIP_MASK_ON_SUSPEND,
f27ecacc
RK
405};
406
b3a1bde4
CM
407void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
408{
a27d21e0 409 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
4d83fcf8
TG
410 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
411 &gic_data[gic_nr]);
b3a1bde4
CM
412}
413
2bb31351
RK
414static u8 gic_get_cpumask(struct gic_chip_data *gic)
415{
416 void __iomem *base = gic_data_dist_base(gic);
417 u32 mask, i;
418
419 for (i = mask = 0; i < 32; i += 4) {
420 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
421 mask |= mask >> 16;
422 mask |= mask >> 8;
423 if (mask)
424 break;
425 }
426
6e3aca44 427 if (!mask && num_possible_cpus() > 1)
2bb31351
RK
428 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
429
430 return mask;
431}
432
4c2880b3 433static void gic_cpu_if_up(struct gic_chip_data *gic)
32289506 434{
4c2880b3 435 void __iomem *cpu_base = gic_data_cpu_base(gic);
32289506 436 u32 bypass = 0;
0b996fd3
MZ
437 u32 mode = 0;
438
389a00d3 439 if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
0b996fd3 440 mode = GIC_CPU_CTRL_EOImodeNS;
32289506
FK
441
442 /*
443 * Preserve bypass disable bits to be written back later
444 */
445 bypass = readl(cpu_base + GIC_CPU_CTRL);
446 bypass &= GICC_DIS_BYPASS_MASK;
447
0b996fd3 448 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
32289506
FK
449}
450
451
cdbb813d 452static void gic_dist_init(struct gic_chip_data *gic)
f27ecacc 453{
75294957 454 unsigned int i;
267840f3 455 u32 cpumask;
4294f8ba 456 unsigned int gic_irqs = gic->gic_irqs;
db0d4db2 457 void __iomem *base = gic_data_dist_base(gic);
f27ecacc 458
e5f81539 459 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
f27ecacc 460
f27ecacc
RK
461 /*
462 * Set all global interrupts to this CPU only.
463 */
2bb31351
RK
464 cpumask = gic_get_cpumask(gic);
465 cpumask |= cpumask << 8;
466 cpumask |= cpumask << 16;
e6afec9b 467 for (i = 32; i < gic_irqs; i += 4)
6ac77e46 468 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
f27ecacc 469
d51d0af4 470 gic_dist_config(base, gic_irqs, NULL);
f27ecacc 471
e5f81539 472 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
f27ecacc
RK
473}
474
dc9722cc 475static int gic_cpu_init(struct gic_chip_data *gic)
f27ecacc 476{
db0d4db2
MZ
477 void __iomem *dist_base = gic_data_dist_base(gic);
478 void __iomem *base = gic_data_cpu_base(gic);
384a2902 479 unsigned int cpu_mask, cpu = smp_processor_id();
9395f6ea
RK
480 int i;
481
384a2902 482 /*
567e5a01
JH
483 * Setting up the CPU map is only relevant for the primary GIC
484 * because any nested/secondary GICs do not directly interface
485 * with the CPU(s).
384a2902 486 */
567e5a01
JH
487 if (gic == &gic_data[0]) {
488 /*
489 * Get what the GIC says our CPU mask is.
490 */
dc9722cc
JH
491 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
492 return -EINVAL;
493
25fc11ae 494 gic_check_cpu_features();
567e5a01
JH
495 cpu_mask = gic_get_cpumask(gic);
496 gic_cpu_map[cpu] = cpu_mask;
384a2902 497
567e5a01
JH
498 /*
499 * Clear our mask from the other map entries in case they're
500 * still undefined.
501 */
502 for (i = 0; i < NR_GIC_CPU_IF; i++)
503 if (i != cpu)
504 gic_cpu_map[i] &= ~cpu_mask;
505 }
384a2902 506
d51d0af4 507 gic_cpu_config(dist_base, NULL);
9395f6ea 508
e5f81539 509 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
4c2880b3 510 gic_cpu_if_up(gic);
dc9722cc
JH
511
512 return 0;
f27ecacc
RK
513}
514
4c2880b3 515int gic_cpu_if_down(unsigned int gic_nr)
10d9eb8a 516{
4c2880b3 517 void __iomem *cpu_base;
32289506
FK
518 u32 val = 0;
519
a27d21e0 520 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
4c2880b3
JH
521 return -EINVAL;
522
523 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
32289506
FK
524 val = readl(cpu_base + GIC_CPU_CTRL);
525 val &= ~GICC_ENABLE;
526 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
4c2880b3
JH
527
528 return 0;
10d9eb8a
NP
529}
530
9c8edddf 531#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
254056f3
CC
532/*
533 * Saves the GIC distributor registers during suspend or idle. Must be called
534 * with interrupts disabled but before powering down the GIC. After calling
535 * this function, no interrupts will be delivered by the GIC, and another
536 * platform-specific wakeup source must be enabled.
537 */
cdbb813d 538void gic_dist_save(struct gic_chip_data *gic)
254056f3
CC
539{
540 unsigned int gic_irqs;
541 void __iomem *dist_base;
542 int i;
543
6e5b5924
JH
544 if (WARN_ON(!gic))
545 return;
254056f3 546
6e5b5924
JH
547 gic_irqs = gic->gic_irqs;
548 dist_base = gic_data_dist_base(gic);
254056f3
CC
549
550 if (!dist_base)
551 return;
552
553 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
6e5b5924 554 gic->saved_spi_conf[i] =
254056f3
CC
555 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
556
557 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
6e5b5924 558 gic->saved_spi_target[i] =
254056f3
CC
559 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
560
561 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
6e5b5924 562 gic->saved_spi_enable[i] =
254056f3 563 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
1c7d4dd4
MZ
564
565 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
6e5b5924 566 gic->saved_spi_active[i] =
1c7d4dd4 567 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
254056f3
CC
568}
569
570/*
571 * Restores the GIC distributor registers during resume or when coming out of
572 * idle. Must be called before enabling interrupts. If a level interrupt
573 * that occured while the GIC was suspended is still present, it will be
574 * handled normally, but any edge interrupts that occured will not be seen by
575 * the GIC and need to be handled by the platform-specific wakeup source.
576 */
cdbb813d 577void gic_dist_restore(struct gic_chip_data *gic)
254056f3
CC
578{
579 unsigned int gic_irqs;
580 unsigned int i;
581 void __iomem *dist_base;
582
6e5b5924
JH
583 if (WARN_ON(!gic))
584 return;
254056f3 585
6e5b5924
JH
586 gic_irqs = gic->gic_irqs;
587 dist_base = gic_data_dist_base(gic);
254056f3
CC
588
589 if (!dist_base)
590 return;
591
e5f81539 592 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
254056f3
CC
593
594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
6e5b5924 595 writel_relaxed(gic->saved_spi_conf[i],
254056f3
CC
596 dist_base + GIC_DIST_CONFIG + i * 4);
597
598 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
e5f81539 599 writel_relaxed(GICD_INT_DEF_PRI_X4,
254056f3
CC
600 dist_base + GIC_DIST_PRI + i * 4);
601
602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
6e5b5924 603 writel_relaxed(gic->saved_spi_target[i],
254056f3
CC
604 dist_base + GIC_DIST_TARGET + i * 4);
605
92eda4ad
MZ
606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
607 writel_relaxed(GICD_INT_EN_CLR_X32,
608 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
6e5b5924 609 writel_relaxed(gic->saved_spi_enable[i],
254056f3 610 dist_base + GIC_DIST_ENABLE_SET + i * 4);
92eda4ad 611 }
254056f3 612
1c7d4dd4
MZ
613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
614 writel_relaxed(GICD_INT_EN_CLR_X32,
615 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
6e5b5924 616 writel_relaxed(gic->saved_spi_active[i],
1c7d4dd4
MZ
617 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
618 }
619
e5f81539 620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
254056f3
CC
621}
622
cdbb813d 623void gic_cpu_save(struct gic_chip_data *gic)
254056f3
CC
624{
625 int i;
626 u32 *ptr;
627 void __iomem *dist_base;
628 void __iomem *cpu_base;
629
6e5b5924
JH
630 if (WARN_ON(!gic))
631 return;
254056f3 632
6e5b5924
JH
633 dist_base = gic_data_dist_base(gic);
634 cpu_base = gic_data_cpu_base(gic);
254056f3
CC
635
636 if (!dist_base || !cpu_base)
637 return;
638
6e5b5924 639 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
254056f3
CC
640 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
641 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
642
6e5b5924 643 ptr = raw_cpu_ptr(gic->saved_ppi_active);
1c7d4dd4
MZ
644 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
645 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
646
6e5b5924 647 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
254056f3
CC
648 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
649 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
650
651}
652
cdbb813d 653void gic_cpu_restore(struct gic_chip_data *gic)
254056f3
CC
654{
655 int i;
656 u32 *ptr;
657 void __iomem *dist_base;
658 void __iomem *cpu_base;
659
6e5b5924
JH
660 if (WARN_ON(!gic))
661 return;
254056f3 662
6e5b5924
JH
663 dist_base = gic_data_dist_base(gic);
664 cpu_base = gic_data_cpu_base(gic);
254056f3
CC
665
666 if (!dist_base || !cpu_base)
667 return;
668
6e5b5924 669 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
92eda4ad
MZ
670 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
671 writel_relaxed(GICD_INT_EN_CLR_X32,
672 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
254056f3 673 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
92eda4ad 674 }
254056f3 675
6e5b5924 676 ptr = raw_cpu_ptr(gic->saved_ppi_active);
1c7d4dd4
MZ
677 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
678 writel_relaxed(GICD_INT_EN_CLR_X32,
679 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
680 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
681 }
682
6e5b5924 683 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
254056f3
CC
684 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
685 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
686
687 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
e5f81539
FK
688 writel_relaxed(GICD_INT_DEF_PRI_X4,
689 dist_base + GIC_DIST_PRI + i * 4);
254056f3 690
e5f81539 691 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
6e5b5924 692 gic_cpu_if_up(gic);
254056f3
CC
693}
694
695static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
696{
697 int i;
698
a27d21e0 699 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
db0d4db2
MZ
700#ifdef CONFIG_GIC_NON_BANKED
701 /* Skip over unused GICs */
702 if (!gic_data[i].get_base)
703 continue;
704#endif
254056f3
CC
705 switch (cmd) {
706 case CPU_PM_ENTER:
6e5b5924 707 gic_cpu_save(&gic_data[i]);
254056f3
CC
708 break;
709 case CPU_PM_ENTER_FAILED:
710 case CPU_PM_EXIT:
6e5b5924 711 gic_cpu_restore(&gic_data[i]);
254056f3
CC
712 break;
713 case CPU_CLUSTER_PM_ENTER:
6e5b5924 714 gic_dist_save(&gic_data[i]);
254056f3
CC
715 break;
716 case CPU_CLUSTER_PM_ENTER_FAILED:
717 case CPU_CLUSTER_PM_EXIT:
6e5b5924 718 gic_dist_restore(&gic_data[i]);
254056f3
CC
719 break;
720 }
721 }
722
723 return NOTIFY_OK;
724}
725
726static struct notifier_block gic_notifier_block = {
727 .notifier_call = gic_notifier,
728};
729
cdbb813d 730static int gic_pm_init(struct gic_chip_data *gic)
254056f3
CC
731{
732 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
733 sizeof(u32));
dc9722cc
JH
734 if (WARN_ON(!gic->saved_ppi_enable))
735 return -ENOMEM;
254056f3 736
1c7d4dd4
MZ
737 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
738 sizeof(u32));
dc9722cc
JH
739 if (WARN_ON(!gic->saved_ppi_active))
740 goto free_ppi_enable;
1c7d4dd4 741
254056f3
CC
742 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
743 sizeof(u32));
dc9722cc
JH
744 if (WARN_ON(!gic->saved_ppi_conf))
745 goto free_ppi_active;
254056f3 746
abdd7b91
MZ
747 if (gic == &gic_data[0])
748 cpu_pm_register_notifier(&gic_notifier_block);
dc9722cc
JH
749
750 return 0;
751
752free_ppi_active:
753 free_percpu(gic->saved_ppi_active);
754free_ppi_enable:
755 free_percpu(gic->saved_ppi_enable);
756
757 return -ENOMEM;
254056f3
CC
758}
759#else
cdbb813d 760static int gic_pm_init(struct gic_chip_data *gic)
254056f3 761{
dc9722cc 762 return 0;
254056f3
CC
763}
764#endif
765
b1cffebf 766#ifdef CONFIG_SMP
6859358e 767static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
b1cffebf
RH
768{
769 int cpu;
1a6b69b6
NP
770 unsigned long flags, map = 0;
771
772 raw_spin_lock_irqsave(&irq_controller_lock, flags);
b1cffebf
RH
773
774 /* Convert our logical CPU mask into a physical one. */
775 for_each_cpu(cpu, mask)
91bdf0d0 776 map |= gic_cpu_map[cpu];
b1cffebf
RH
777
778 /*
779 * Ensure that stores to Normal memory are visible to the
8adbf57f 780 * other CPUs before they observe us issuing the IPI.
b1cffebf 781 */
8adbf57f 782 dmb(ishst);
b1cffebf
RH
783
784 /* this always happens on GIC0 */
785 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
1a6b69b6
NP
786
787 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
788}
789#endif
790
791#ifdef CONFIG_BL_SWITCHER
14d2ca61
NP
792/*
793 * gic_send_sgi - send a SGI directly to given CPU interface number
794 *
795 * cpu_id: the ID for the destination CPU interface
796 * irq: the IPI number to send a SGI for
797 */
798void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
799{
800 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
801 cpu_id = 1 << cpu_id;
802 /* this always happens on GIC0 */
803 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
804}
805
ed96762e
NP
806/*
807 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
808 *
809 * @cpu: the logical CPU number to get the GIC ID for.
810 *
811 * Return the CPU interface ID for the given logical CPU number,
812 * or -1 if the CPU number is too large or the interface ID is
813 * unknown (more than one bit set).
814 */
815int gic_get_cpu_id(unsigned int cpu)
816{
817 unsigned int cpu_bit;
818
819 if (cpu >= NR_GIC_CPU_IF)
820 return -1;
821 cpu_bit = gic_cpu_map[cpu];
822 if (cpu_bit & (cpu_bit - 1))
823 return -1;
824 return __ffs(cpu_bit);
825}
826
1a6b69b6
NP
827/*
828 * gic_migrate_target - migrate IRQs to another CPU interface
829 *
830 * @new_cpu_id: the CPU target ID to migrate IRQs to
831 *
832 * Migrate all peripheral interrupts with a target matching the current CPU
833 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
834 * is also updated. Targets to other CPU interfaces are unchanged.
835 * This must be called with IRQs locally disabled.
836 */
837void gic_migrate_target(unsigned int new_cpu_id)
838{
839 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
840 void __iomem *dist_base;
841 int i, ror_val, cpu = smp_processor_id();
842 u32 val, cur_target_mask, active_mask;
843
a27d21e0 844 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
1a6b69b6
NP
845
846 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
847 if (!dist_base)
848 return;
849 gic_irqs = gic_data[gic_nr].gic_irqs;
850
851 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
852 cur_target_mask = 0x01010101 << cur_cpu_id;
853 ror_val = (cur_cpu_id - new_cpu_id) & 31;
854
855 raw_spin_lock(&irq_controller_lock);
856
857 /* Update the target interface for this logical CPU */
858 gic_cpu_map[cpu] = 1 << new_cpu_id;
859
860 /*
861 * Find all the peripheral interrupts targetting the current
862 * CPU interface and migrate them to the new CPU interface.
863 * We skip DIST_TARGET 0 to 7 as they are read-only.
864 */
865 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
866 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
867 active_mask = val & cur_target_mask;
868 if (active_mask) {
869 val &= ~active_mask;
870 val |= ror32(active_mask, ror_val);
871 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
872 }
873 }
874
875 raw_spin_unlock(&irq_controller_lock);
876
877 /*
878 * Now let's migrate and clear any potential SGIs that might be
879 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
880 * is a banked register, we can only forward the SGI using
881 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
882 * doesn't use that information anyway.
883 *
884 * For the same reason we do not adjust SGI source information
885 * for previously sent SGIs by us to other CPUs either.
886 */
887 for (i = 0; i < 16; i += 4) {
888 int j;
889 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
890 if (!val)
891 continue;
892 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
893 for (j = i; j < i + 4; j++) {
894 if (val & 0xff)
895 writel_relaxed((1 << (new_cpu_id + 16)) | j,
896 dist_base + GIC_DIST_SOFTINT);
897 val >>= 8;
898 }
899 }
b1cffebf 900}
eeb44658
NP
901
902/*
903 * gic_get_sgir_physaddr - get the physical address for the SGI register
904 *
905 * REturn the physical address of the SGI register to be used
906 * by some early assembly code when the kernel is not yet available.
907 */
908static unsigned long gic_dist_physaddr;
909
910unsigned long gic_get_sgir_physaddr(void)
911{
912 if (!gic_dist_physaddr)
913 return 0;
914 return gic_dist_physaddr + GIC_DIST_SOFTINT;
915}
916
917void __init gic_init_physaddr(struct device_node *node)
918{
919 struct resource res;
920 if (of_address_to_resource(node, 0, &res) == 0) {
921 gic_dist_physaddr = res.start;
922 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
923 }
924}
925
926#else
927#define gic_init_physaddr(node) do { } while (0)
b1cffebf
RH
928#endif
929
75294957
GL
930static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
931 irq_hw_number_t hw)
932{
58b89649 933 struct gic_chip_data *gic = d->host_data;
0b996fd3 934
75294957
GL
935 if (hw < 32) {
936 irq_set_percpu_devid(irq);
58b89649 937 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
9a1091ef 938 handle_percpu_devid_irq, NULL, NULL);
d17cab44 939 irq_set_status_flags(irq, IRQ_NOAUTOEN);
75294957 940 } else {
58b89649 941 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
9a1091ef 942 handle_fasteoi_irq, NULL, NULL);
d17cab44 943 irq_set_probe(irq);
75294957 944 }
75294957
GL
945 return 0;
946}
947
006e983b
S
948static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
949{
006e983b
S
950}
951
f833f57f
MZ
952static int gic_irq_domain_translate(struct irq_domain *d,
953 struct irq_fwspec *fwspec,
954 unsigned long *hwirq,
955 unsigned int *type)
956{
957 if (is_of_node(fwspec->fwnode)) {
958 if (fwspec->param_count < 3)
959 return -EINVAL;
960
961 /* Get the interrupt number and add 16 to skip over SGIs */
962 *hwirq = fwspec->param[1] + 16;
963
964 /*
965 * For SPIs, we need to add 16 more to get the GIC irq
966 * ID number
967 */
968 if (!fwspec->param[0])
969 *hwirq += 16;
970
971 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
972 return 0;
973 }
974
75aba7b0 975 if (is_fwnode_irqchip(fwspec->fwnode)) {
891ae769
MZ
976 if(fwspec->param_count != 2)
977 return -EINVAL;
978
979 *hwirq = fwspec->param[0];
980 *type = fwspec->param[1];
981 return 0;
982 }
983
f833f57f
MZ
984 return -EINVAL;
985}
986
93131f7a 987static int gic_starting_cpu(unsigned int cpu)
c0114709 988{
93131f7a
RC
989 gic_cpu_init(&gic_data[0]);
990 return 0;
c0114709
CM
991}
992
9a1091ef
YC
993static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
994 unsigned int nr_irqs, void *arg)
995{
996 int i, ret;
997 irq_hw_number_t hwirq;
998 unsigned int type = IRQ_TYPE_NONE;
f833f57f 999 struct irq_fwspec *fwspec = arg;
9a1091ef 1000
f833f57f 1001 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
9a1091ef
YC
1002 if (ret)
1003 return ret;
1004
1005 for (i = 0; i < nr_irqs; i++)
1006 gic_irq_domain_map(domain, virq + i, hwirq + i);
1007
1008 return 0;
1009}
1010
1011static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
f833f57f 1012 .translate = gic_irq_domain_translate,
9a1091ef
YC
1013 .alloc = gic_irq_domain_alloc,
1014 .free = irq_domain_free_irqs_top,
1015};
1016
6859358e 1017static const struct irq_domain_ops gic_irq_domain_ops = {
75294957 1018 .map = gic_irq_domain_map,
006e983b 1019 .unmap = gic_irq_domain_unmap,
4294f8ba
RH
1020};
1021
faea6455
JH
1022static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1023 const char *name, bool use_eoimode1)
b580b899 1024{
58b89649 1025 /* Initialize irq_chip */
c2baa2f3 1026 gic->chip = gic_chip;
faea6455
JH
1027 gic->chip.name = name;
1028 gic->chip.parent_device = dev;
c2baa2f3 1029
faea6455 1030 if (use_eoimode1) {
c2baa2f3
JH
1031 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1032 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1033 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
58b89649
LW
1034 }
1035
7bf29d3a 1036#ifdef CONFIG_SMP
f673b9b5 1037 if (gic == &gic_data[0])
7bf29d3a
JH
1038 gic->chip.irq_set_affinity = gic_set_affinity;
1039#endif
faea6455
JH
1040}
1041
1042static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1043 struct fwnode_handle *handle)
1044{
1045 irq_hw_number_t hwirq_base;
1046 int gic_irqs, irq_base, ret;
7bf29d3a 1047
f673b9b5 1048 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
dc9722cc 1049 /* Frankein-GIC without banked registers... */
db0d4db2
MZ
1050 unsigned int cpu;
1051
1052 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1053 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1054 if (WARN_ON(!gic->dist_base.percpu_base ||
1055 !gic->cpu_base.percpu_base)) {
dc9722cc
JH
1056 ret = -ENOMEM;
1057 goto error;
db0d4db2
MZ
1058 }
1059
1060 for_each_possible_cpu(cpu) {
29e697b1
TF
1061 u32 mpidr = cpu_logical_map(cpu);
1062 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
f673b9b5
JH
1063 unsigned long offset = gic->percpu_offset * core_id;
1064 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1065 gic->raw_dist_base + offset;
1066 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1067 gic->raw_cpu_base + offset;
db0d4db2
MZ
1068 }
1069
1070 gic_set_base_accessor(gic, gic_get_percpu_base);
dc9722cc
JH
1071 } else {
1072 /* Normal, sane GIC... */
f673b9b5 1073 WARN(gic->percpu_offset,
db0d4db2 1074 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
f673b9b5
JH
1075 gic->percpu_offset);
1076 gic->dist_base.common_base = gic->raw_dist_base;
1077 gic->cpu_base.common_base = gic->raw_cpu_base;
db0d4db2
MZ
1078 gic_set_base_accessor(gic, gic_get_common_base);
1079 }
bef8f9ee 1080
4294f8ba
RH
1081 /*
1082 * Find out how many interrupts are supported.
1083 * The GIC only supports up to 1020 interrupt sources.
1084 */
db0d4db2 1085 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
4294f8ba
RH
1086 gic_irqs = (gic_irqs + 1) * 32;
1087 if (gic_irqs > 1020)
1088 gic_irqs = 1020;
1089 gic->gic_irqs = gic_irqs;
1090
891ae769
MZ
1091 if (handle) { /* DT/ACPI */
1092 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1093 &gic_irq_domain_hierarchy_ops,
1094 gic);
1095 } else { /* Legacy support */
9a1091ef
YC
1096 /*
1097 * For primary GICs, skip over SGIs.
1098 * For secondary GICs, skip over PPIs, too.
1099 */
f673b9b5 1100 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
9a1091ef
YC
1101 hwirq_base = 16;
1102 if (irq_start != -1)
1103 irq_start = (irq_start & ~31) + 16;
1104 } else {
1105 hwirq_base = 32;
1106 }
1107
1108 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
006e983b 1109
006e983b
S
1110 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1111 numa_node_id());
287980e4 1112 if (irq_base < 0) {
006e983b
S
1113 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1114 irq_start);
1115 irq_base = irq_start;
1116 }
1117
891ae769 1118 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
006e983b 1119 hwirq_base, &gic_irq_domain_ops, gic);
f37a53cc 1120 }
006e983b 1121
dc9722cc
JH
1122 if (WARN_ON(!gic->domain)) {
1123 ret = -ENODEV;
1124 goto error;
1125 }
bef8f9ee 1126
4294f8ba 1127 gic_dist_init(gic);
dc9722cc
JH
1128 ret = gic_cpu_init(gic);
1129 if (ret)
1130 goto error;
1131
1132 ret = gic_pm_init(gic);
1133 if (ret)
1134 goto error;
1135
1136 return 0;
1137
1138error:
f673b9b5 1139 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
dc9722cc
JH
1140 free_percpu(gic->dist_base.percpu_base);
1141 free_percpu(gic->cpu_base.percpu_base);
1142 }
1143
dc9722cc 1144 return ret;
b580b899
RK
1145}
1146
d6ce564c
JH
1147static int __init __gic_init_bases(struct gic_chip_data *gic,
1148 int irq_start,
1149 struct fwnode_handle *handle)
1150{
faea6455
JH
1151 char *name;
1152 int i, ret;
d6ce564c
JH
1153
1154 if (WARN_ON(!gic || gic->domain))
1155 return -EINVAL;
1156
1157 if (gic == &gic_data[0]) {
1158 /*
1159 * Initialize the CPU interface map to all CPUs.
1160 * It will be refined as each CPU probes its ID.
1161 * This is only necessary for the primary GIC.
1162 */
1163 for (i = 0; i < NR_GIC_CPU_IF; i++)
1164 gic_cpu_map[i] = 0xff;
1165#ifdef CONFIG_SMP
1166 set_smp_cross_call(gic_raise_softirq);
d6ce564c 1167#endif
93131f7a
RC
1168 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1169 "AP_IRQ_GIC_STARTING",
1170 gic_starting_cpu, NULL);
d6ce564c
JH
1171 set_handle_irq(gic_handle_irq);
1172 if (static_key_true(&supports_deactivate))
1173 pr_info("GIC: Using split EOI/Deactivate mode\n");
1174 }
1175
faea6455
JH
1176 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1177 name = kasprintf(GFP_KERNEL, "GICv2");
1178 gic_init_chip(gic, NULL, name, true);
1179 } else {
1180 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1181 gic_init_chip(gic, NULL, name, false);
1182 }
1183
1184 ret = gic_init_bases(gic, irq_start, handle);
1185 if (ret)
1186 kfree(name);
1187
1188 return ret;
d6ce564c
JH
1189}
1190
e81a7cd9
MZ
1191void __init gic_init(unsigned int gic_nr, int irq_start,
1192 void __iomem *dist_base, void __iomem *cpu_base)
4a6ac304 1193{
f673b9b5
JH
1194 struct gic_chip_data *gic;
1195
1196 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1197 return;
1198
4a6ac304
MZ
1199 /*
1200 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1201 * bother with these...
1202 */
1203 static_key_slow_dec(&supports_deactivate);
f673b9b5
JH
1204
1205 gic = &gic_data[gic_nr];
1206 gic->raw_dist_base = dist_base;
1207 gic->raw_cpu_base = cpu_base;
1208
1209 __gic_init_bases(gic, irq_start, NULL);
4a6ac304
MZ
1210}
1211
d6490461
JH
1212static void gic_teardown(struct gic_chip_data *gic)
1213{
1214 if (WARN_ON(!gic))
1215 return;
1216
1217 if (gic->raw_dist_base)
1218 iounmap(gic->raw_dist_base);
1219 if (gic->raw_cpu_base)
1220 iounmap(gic->raw_cpu_base);
4a6ac304
MZ
1221}
1222
b3f7ed03 1223#ifdef CONFIG_OF
46f101df 1224static int gic_cnt __initdata;
b3f7ed03 1225
12e14066
MZ
1226static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1227{
1228 struct resource cpuif_res;
1229
1230 of_address_to_resource(node, 1, &cpuif_res);
1231
1232 if (!is_hyp_mode_available())
1233 return false;
1234 if (resource_size(&cpuif_res) < SZ_8K)
1235 return false;
1236 if (resource_size(&cpuif_res) == SZ_128K) {
1237 u32 val_low, val_high;
1238
1239 /*
1240 * Verify that we have the first 4kB of a GIC400
1241 * aliased over the first 64kB by checking the
1242 * GICC_IIDR register on both ends.
1243 */
1244 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1245 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1246 if ((val_low & 0xffff0fff) != 0x0202043B ||
1247 val_low != val_high)
1248 return false;
1249
1250 /*
1251 * Move the base up by 60kB, so that we have a 8kB
1252 * contiguous region, which allows us to use GICC_DIR
1253 * at its normal offset. Please pass me that bucket.
1254 */
1255 *base += 0xf000;
1256 cpuif_res.start += 0xf000;
1257 pr_warn("GIC: Adjusting CPU interface base to %pa",
1258 &cpuif_res.start);
1259 }
1260
1261 return true;
1262}
1263
9c8edddf 1264static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
d6490461
JH
1265{
1266 if (!gic || !node)
1267 return -EINVAL;
1268
1269 gic->raw_dist_base = of_iomap(node, 0);
1270 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1271 goto error;
1272
1273 gic->raw_cpu_base = of_iomap(node, 1);
1274 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1275 goto error;
1276
1277 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1278 gic->percpu_offset = 0;
1279
1280 return 0;
1281
1282error:
1283 gic_teardown(gic);
1284
1285 return -ENOMEM;
1286}
1287
9c8edddf
JH
1288int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1289{
1290 int ret;
1291
1292 if (!dev || !dev->of_node || !gic || !irq)
1293 return -EINVAL;
1294
1295 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1296 if (!*gic)
1297 return -ENOMEM;
1298
1299 gic_init_chip(*gic, dev, dev->of_node->name, false);
1300
1301 ret = gic_of_setup(*gic, dev->of_node);
1302 if (ret)
1303 return ret;
1304
1305 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1306 if (ret) {
1307 gic_teardown(*gic);
1308 return ret;
1309 }
1310
1311 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1312
1313 return 0;
1314}
1315
502d6df1
JG
1316static void __init gic_of_setup_kvm_info(struct device_node *node)
1317{
1318 int ret;
1319 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1320 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1321
1322 gic_v2_kvm_info.type = GIC_V2;
1323
1324 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1325 if (!gic_v2_kvm_info.maint_irq)
1326 return;
1327
1328 ret = of_address_to_resource(node, 2, vctrl_res);
1329 if (ret)
1330 return;
1331
1332 ret = of_address_to_resource(node, 3, vcpu_res);
1333 if (ret)
1334 return;
1335
1336 gic_set_kvm_info(&gic_v2_kvm_info);
1337}
1338
8673c1d7 1339int __init
6859358e 1340gic_of_init(struct device_node *node, struct device_node *parent)
b3f7ed03 1341{
f673b9b5 1342 struct gic_chip_data *gic;
dc9722cc 1343 int irq, ret;
b3f7ed03
RH
1344
1345 if (WARN_ON(!node))
1346 return -ENODEV;
1347
f673b9b5
JH
1348 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1349 return -EINVAL;
1350
1351 gic = &gic_data[gic_cnt];
b3f7ed03 1352
d6490461
JH
1353 ret = gic_of_setup(gic, node);
1354 if (ret)
1355 return ret;
b3f7ed03 1356
0b996fd3
MZ
1357 /*
1358 * Disable split EOI/Deactivate if either HYP is not available
1359 * or the CPU interface is too small.
1360 */
f673b9b5 1361 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
0b996fd3
MZ
1362 static_key_slow_dec(&supports_deactivate);
1363
f673b9b5 1364 ret = __gic_init_bases(gic, -1, &node->fwnode);
dc9722cc 1365 if (ret) {
d6490461 1366 gic_teardown(gic);
dc9722cc
JH
1367 return ret;
1368 }
db0d4db2 1369
502d6df1 1370 if (!gic_cnt) {
eeb44658 1371 gic_init_physaddr(node);
502d6df1
JG
1372 gic_of_setup_kvm_info(node);
1373 }
b3f7ed03
RH
1374
1375 if (parent) {
1376 irq = irq_of_parse_and_map(node, 0);
1377 gic_cascade_irq(gic_cnt, irq);
1378 }
853a33ce
SS
1379
1380 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
0644b3da 1381 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
853a33ce 1382
b3f7ed03
RH
1383 gic_cnt++;
1384 return 0;
1385}
144cb088 1386IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
fa6e2eec
LW
1387IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1388IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
81243e44
RH
1389IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1390IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
a97e8027 1391IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
81243e44
RH
1392IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1393IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
8709b9eb 1394IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
9c8edddf
JH
1395#else
1396int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1397{
1398 return -ENOTSUPP;
1399}
b3f7ed03 1400#endif
d60fc389
TN
1401
1402#ifdef CONFIG_ACPI
bafa9193
JG
1403static struct
1404{
1405 phys_addr_t cpu_phys_base;
502d6df1
JG
1406 u32 maint_irq;
1407 int maint_irq_mode;
1408 phys_addr_t vctrl_base;
1409 phys_addr_t vcpu_base;
bafa9193 1410} acpi_data __initdata;
d60fc389
TN
1411
1412static int __init
1413gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1414 const unsigned long end)
1415{
1416 struct acpi_madt_generic_interrupt *processor;
1417 phys_addr_t gic_cpu_base;
1418 static int cpu_base_assigned;
1419
1420 processor = (struct acpi_madt_generic_interrupt *)header;
1421
99e3e3ae 1422 if (BAD_MADT_GICC_ENTRY(processor, end))
d60fc389
TN
1423 return -EINVAL;
1424
1425 /*
1426 * There is no support for non-banked GICv1/2 register in ACPI spec.
1427 * All CPU interface addresses have to be the same.
1428 */
1429 gic_cpu_base = processor->base_address;
bafa9193 1430 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
d60fc389
TN
1431 return -EINVAL;
1432
bafa9193 1433 acpi_data.cpu_phys_base = gic_cpu_base;
502d6df1
JG
1434 acpi_data.maint_irq = processor->vgic_interrupt;
1435 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1436 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1437 acpi_data.vctrl_base = processor->gich_base_address;
1438 acpi_data.vcpu_base = processor->gicv_base_address;
1439
d60fc389
TN
1440 cpu_base_assigned = 1;
1441 return 0;
1442}
1443
f26527b1
MZ
1444/* The things you have to do to just *count* something... */
1445static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1446 const unsigned long end)
d60fc389 1447{
f26527b1
MZ
1448 return 0;
1449}
d60fc389 1450
f26527b1
MZ
1451static bool __init acpi_gic_redist_is_present(void)
1452{
1453 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1454 acpi_dummy_func, 0) > 0;
1455}
d60fc389 1456
f26527b1
MZ
1457static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1458 struct acpi_probe_entry *ape)
1459{
1460 struct acpi_madt_generic_distributor *dist;
1461 dist = (struct acpi_madt_generic_distributor *)header;
d60fc389 1462
f26527b1
MZ
1463 return (dist->version == ape->driver_data &&
1464 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1465 !acpi_gic_redist_is_present()));
d60fc389
TN
1466}
1467
f26527b1
MZ
1468#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1469#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
502d6df1
JG
1470#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1471#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1472
1473static void __init gic_acpi_setup_kvm_info(void)
1474{
1475 int irq;
1476 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1477 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1478
1479 gic_v2_kvm_info.type = GIC_V2;
1480
1481 if (!acpi_data.vctrl_base)
1482 return;
1483
1484 vctrl_res->flags = IORESOURCE_MEM;
1485 vctrl_res->start = acpi_data.vctrl_base;
1486 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1487
1488 if (!acpi_data.vcpu_base)
1489 return;
1490
1491 vcpu_res->flags = IORESOURCE_MEM;
1492 vcpu_res->start = acpi_data.vcpu_base;
1493 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1494
1495 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1496 acpi_data.maint_irq_mode,
1497 ACPI_ACTIVE_HIGH);
1498 if (irq <= 0)
1499 return;
1500
1501 gic_v2_kvm_info.maint_irq = irq;
1502
1503 gic_set_kvm_info(&gic_v2_kvm_info);
1504}
f26527b1
MZ
1505
1506static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1507 const unsigned long end)
d60fc389 1508{
f26527b1 1509 struct acpi_madt_generic_distributor *dist;
891ae769 1510 struct fwnode_handle *domain_handle;
f673b9b5 1511 struct gic_chip_data *gic = &gic_data[0];
dc9722cc 1512 int count, ret;
d60fc389
TN
1513
1514 /* Collect CPU base addresses */
f26527b1
MZ
1515 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1516 gic_acpi_parse_madt_cpu, 0);
d60fc389
TN
1517 if (count <= 0) {
1518 pr_err("No valid GICC entries exist\n");
1519 return -EINVAL;
1520 }
1521
7beaa24b 1522 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
f673b9b5 1523 if (!gic->raw_cpu_base) {
d60fc389
TN
1524 pr_err("Unable to map GICC registers\n");
1525 return -ENOMEM;
1526 }
1527
f26527b1 1528 dist = (struct acpi_madt_generic_distributor *)header;
f673b9b5
JH
1529 gic->raw_dist_base = ioremap(dist->base_address,
1530 ACPI_GICV2_DIST_MEM_SIZE);
1531 if (!gic->raw_dist_base) {
d60fc389 1532 pr_err("Unable to map GICD registers\n");
d6490461 1533 gic_teardown(gic);
d60fc389
TN
1534 return -ENOMEM;
1535 }
1536
0b996fd3
MZ
1537 /*
1538 * Disable split EOI/Deactivate if HYP is not available. ACPI
1539 * guarantees that we'll always have a GICv2, so the CPU
1540 * interface will always be the right size.
1541 */
1542 if (!is_hyp_mode_available())
1543 static_key_slow_dec(&supports_deactivate);
1544
d60fc389 1545 /*
891ae769 1546 * Initialize GIC instance zero (no multi-GIC support).
d60fc389 1547 */
f673b9b5 1548 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
891ae769
MZ
1549 if (!domain_handle) {
1550 pr_err("Unable to allocate domain handle\n");
d6490461 1551 gic_teardown(gic);
891ae769
MZ
1552 return -ENOMEM;
1553 }
1554
f673b9b5 1555 ret = __gic_init_bases(gic, -1, domain_handle);
dc9722cc
JH
1556 if (ret) {
1557 pr_err("Failed to initialise GIC\n");
1558 irq_domain_free_fwnode(domain_handle);
d6490461 1559 gic_teardown(gic);
dc9722cc
JH
1560 return ret;
1561 }
d8f4f161 1562
891ae769 1563 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
0644b3da
SS
1564
1565 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1566 gicv2m_init(NULL, gic_data[0].domain);
1567
502d6df1
JG
1568 gic_acpi_setup_kvm_info();
1569
d60fc389
TN
1570 return 0;
1571}
f26527b1
MZ
1572IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1573 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1574 gic_v2_acpi_init);
1575IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1576 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1577 gic_v2_acpi_init);
d60fc389 1578#endif
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