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9869848d LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * JZ4740 platform IRQ support | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
70342287 | 6 | * under the terms of the GNU General Public License as published by the |
9869848d LPC |
7 | * Free Software Foundation; either version 2 of the License, or (at your |
8 | * option) any later version. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License along | |
11 | * with this program; if not, write to the Free Software Foundation, Inc., | |
12 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/errno.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
41a83e06 | 21 | #include <linux/irqchip.h> |
44e08e70 | 22 | #include <linux/irqchip/ingenic.h> |
3aa94590 | 23 | #include <linux/of_address.h> |
adbdce77 | 24 | #include <linux/of_irq.h> |
9869848d LPC |
25 | #include <linux/timex.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
28 | ||
9869848d | 29 | #include <asm/io.h> |
942e22df BN |
30 | #include <asm/mach-jz4740/irq.h> |
31 | ||
fe778ece PB |
32 | struct ingenic_intc_data { |
33 | void __iomem *base; | |
943d69c6 | 34 | unsigned num_chips; |
fe778ece | 35 | }; |
9869848d LPC |
36 | |
37 | #define JZ_REG_INTC_STATUS 0x00 | |
38 | #define JZ_REG_INTC_MASK 0x04 | |
39 | #define JZ_REG_INTC_SET_MASK 0x08 | |
40 | #define JZ_REG_INTC_CLEAR_MASK 0x0c | |
41 | #define JZ_REG_INTC_PENDING 0x10 | |
943d69c6 | 42 | #define CHIP_SIZE 0x20 |
9869848d | 43 | |
2da01884 | 44 | static irqreturn_t intc_cascade(int irq, void *data) |
9869848d | 45 | { |
fe778ece | 46 | struct ingenic_intc_data *intc = irq_get_handler_data(irq); |
83bc7692 | 47 | uint32_t irq_reg; |
943d69c6 | 48 | unsigned i; |
9869848d | 49 | |
943d69c6 PB |
50 | for (i = 0; i < intc->num_chips; i++) { |
51 | irq_reg = readl(intc->base + (i * CHIP_SIZE) + | |
52 | JZ_REG_INTC_PENDING); | |
53 | if (!irq_reg) | |
54 | continue; | |
9869848d | 55 | |
943d69c6 PB |
56 | generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE); |
57 | } | |
83bc7692 LPC |
58 | |
59 | return IRQ_HANDLED; | |
42b64f38 TG |
60 | } |
61 | ||
2da01884 | 62 | static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) |
9869848d | 63 | { |
83bc7692 | 64 | struct irq_chip_regs *regs = &gc->chip_types->regs; |
9869848d | 65 | |
83bc7692 LPC |
66 | writel(mask, gc->reg_base + regs->enable); |
67 | writel(~mask, gc->reg_base + regs->disable); | |
9869848d LPC |
68 | } |
69 | ||
2da01884 | 70 | void ingenic_intc_irq_suspend(struct irq_data *data) |
9869848d | 71 | { |
83bc7692 | 72 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
2da01884 | 73 | intc_irq_set_mask(gc, gc->wake_active); |
83bc7692 | 74 | } |
9869848d | 75 | |
2da01884 | 76 | void ingenic_intc_irq_resume(struct irq_data *data) |
83bc7692 LPC |
77 | { |
78 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); | |
2da01884 | 79 | intc_irq_set_mask(gc, gc->mask_cache); |
9869848d LPC |
80 | } |
81 | ||
2da01884 PB |
82 | static struct irqaction intc_cascade_action = { |
83 | .handler = intc_cascade, | |
84 | .name = "SoC intc cascade interrupt", | |
9869848d LPC |
85 | }; |
86 | ||
943d69c6 PB |
87 | static int __init ingenic_intc_of_init(struct device_node *node, |
88 | unsigned num_chips) | |
9869848d | 89 | { |
fe778ece | 90 | struct ingenic_intc_data *intc; |
83bc7692 LPC |
91 | struct irq_chip_generic *gc; |
92 | struct irq_chip_type *ct; | |
638c8851 | 93 | struct irq_domain *domain; |
fe778ece | 94 | int parent_irq, err = 0; |
943d69c6 | 95 | unsigned i; |
fe778ece PB |
96 | |
97 | intc = kzalloc(sizeof(*intc), GFP_KERNEL); | |
98 | if (!intc) { | |
99 | err = -ENOMEM; | |
100 | goto out_err; | |
101 | } | |
69ce4b22 PB |
102 | |
103 | parent_irq = irq_of_parse_and_map(node, 0); | |
fe778ece PB |
104 | if (!parent_irq) { |
105 | err = -EINVAL; | |
106 | goto out_free; | |
107 | } | |
83bc7692 | 108 | |
fe778ece PB |
109 | err = irq_set_handler_data(parent_irq, intc); |
110 | if (err) | |
111 | goto out_unmap_irq; | |
112 | ||
943d69c6 | 113 | intc->num_chips = num_chips; |
3aa94590 PB |
114 | intc->base = of_iomap(node, 0); |
115 | if (!intc->base) { | |
116 | err = -ENODEV; | |
117 | goto out_unmap_irq; | |
118 | } | |
9869848d | 119 | |
943d69c6 PB |
120 | for (i = 0; i < num_chips; i++) { |
121 | /* Mask all irqs */ | |
122 | writel(0xffffffff, intc->base + (i * CHIP_SIZE) + | |
123 | JZ_REG_INTC_SET_MASK); | |
124 | ||
125 | gc = irq_alloc_generic_chip("INTC", 1, | |
126 | JZ4740_IRQ_BASE + (i * 32), | |
127 | intc->base + (i * CHIP_SIZE), | |
128 | handle_level_irq); | |
129 | ||
130 | gc->wake_enabled = IRQ_MSK(32); | |
131 | ||
132 | ct = gc->chip_types; | |
133 | ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; | |
134 | ct->regs.disable = JZ_REG_INTC_SET_MASK; | |
135 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
136 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
137 | ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; | |
138 | ct->chip.irq_set_wake = irq_gc_set_wake; | |
2da01884 PB |
139 | ct->chip.irq_suspend = ingenic_intc_irq_suspend; |
140 | ct->chip.irq_resume = ingenic_intc_irq_resume; | |
943d69c6 PB |
141 | |
142 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, | |
143 | IRQ_NOPROBE | IRQ_LEVEL); | |
144 | } | |
9869848d | 145 | |
638c8851 PB |
146 | domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0, |
147 | &irq_domain_simple_ops, NULL); | |
148 | if (!domain) | |
149 | pr_warn("unable to register IRQ domain\n"); | |
150 | ||
2da01884 | 151 | setup_irq(parent_irq, &intc_cascade_action); |
adbdce77 | 152 | return 0; |
fe778ece PB |
153 | |
154 | out_unmap_irq: | |
155 | irq_dispose_mapping(parent_irq); | |
156 | out_free: | |
157 | kfree(intc); | |
158 | out_err: | |
159 | return err; | |
9869848d | 160 | } |
943d69c6 PB |
161 | |
162 | static int __init intc_1chip_of_init(struct device_node *node, | |
163 | struct device_node *parent) | |
164 | { | |
165 | return ingenic_intc_of_init(node, 1); | |
166 | } | |
167 | IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); | |
24ccfa06 PB |
168 | |
169 | static int __init intc_2chip_of_init(struct device_node *node, | |
170 | struct device_node *parent) | |
171 | { | |
172 | return ingenic_intc_of_init(node, 2); | |
173 | } | |
174 | IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); | |
175 | IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); | |
176 | IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); |