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i2c: au1550: relax bus timings a bit
[deliverable/linux.git] / drivers / irqchip / irq-mips-gic.c
CommitLineData
2299c49d
SH		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
39b8d525 9#include <linux/bitmap.h>
fb8f7be1 10#include <linux/clocksource.h>
39b8d525 11#include <linux/init.h>
18743d27 12#include <linux/interrupt.h>
fb8f7be1 13#include <linux/irq.h>
41a83e06 14#include <linux/irqchip.h>
4060bbe9 15#include <linux/irqchip/mips-gic.h>
a7057270 16#include <linux/of_address.h>
18743d27 17#include <linux/sched.h>
631330f5 18#include <linux/smp.h>
39b8d525 19
a7057270 20#include <asm/mips-cm.h>
98b67c37
SH		 21#include <asm/setup.h>
22#include <asm/traps.h>
39b8d525 23
a7057270
AB		 24#include <dt-bindings/interrupt-controller/mips-gic.h>
25
ff86714f 26unsigned int gic_present;
98b67c37 27
822350bc 28struct gic_pcpu_mask {
fbd55241 29 DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
822350bc
JD		 30};
31
5f68fea0 32static void __iomem *gic_base;
0b271f56 33static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
95150ae8 34static DEFINE_SPINLOCK(gic_lock);
c49581a4 35static struct irq_domain *gic_irq_domain;
fbd55241 36static int gic_shared_intrs;
e9de688d 37static int gic_vpes;
3263d085 38static unsigned int gic_cpu_pin;
1b6af71a 39static unsigned int timer_cpu_pin;
4a6a3ea3 40static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
39b8d525 41
18743d27
AB		 42static void __gic_irq_dispatch(void);
43
c3f57f02 44static inline u32 gic_read32(unsigned int reg)
5f68fea0
AB		 45{
46 return __raw_readl(gic_base + reg);
47}
48
c3f57f02 49static inline u64 gic_read64(unsigned int reg)
5f68fea0 50{
c3f57f02 51 return __raw_readq(gic_base + reg);
5f68fea0
AB		 52}
53
c3f57f02 54static inline unsigned long gic_read(unsigned int reg)
5f68fea0 55{
c3f57f02
MC		 56 if (!mips_cm_is64)
57 return gic_read32(reg);
58 else
59 return gic_read64(reg);
60}
61
62static inline void gic_write32(unsigned int reg, u32 val)
63{
64 return __raw_writel(val, gic_base + reg);
65}
66
67static inline void gic_write64(unsigned int reg, u64 val)
68{
69 return __raw_writeq(val, gic_base + reg);
70}
71
72static inline void gic_write(unsigned int reg, unsigned long val)
73{
74 if (!mips_cm_is64)
75 return gic_write32(reg, (u32)val);
76 else
77 return gic_write64(reg, (u64)val);
78}
79
80static inline void gic_update_bits(unsigned int reg, unsigned long mask,
81 unsigned long val)
82{
83 unsigned long regval;
5f68fea0
AB		 84
85 regval = gic_read(reg);
86 regval &= ~mask;
87 regval |= val;
88 gic_write(reg, regval);
89}
90
91static inline void gic_reset_mask(unsigned int intr)
92{
93 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
c3f57f02 94 1ul << GIC_INTR_BIT(intr));
5f68fea0
AB		 95}
96
97static inline void gic_set_mask(unsigned int intr)
98{
99 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
c3f57f02 100 1ul << GIC_INTR_BIT(intr));
5f68fea0
AB		 101}
102
103static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
104{
105 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
c3f57f02
MC		 106 GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
107 (unsigned long)pol << GIC_INTR_BIT(intr));
5f68fea0
AB		 108}
109
110static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
111{
112 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
c3f57f02
MC		 113 GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
114 (unsigned long)trig << GIC_INTR_BIT(intr));
5f68fea0
AB		 115}
116
117static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
118{
119 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
c3f57f02
MC		 120 1ul << GIC_INTR_BIT(intr),
121 (unsigned long)dual << GIC_INTR_BIT(intr));
5f68fea0
AB		 122}
123
124static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
125{
c3f57f02
MC		 126 gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
127 GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
5f68fea0
AB		 128}
129
130static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
131{
132 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
133 GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
134 GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
135}
136
a331ce63 137#ifdef CONFIG_CLKSRC_MIPS_GIC
dfa762e1
SH		 138cycle_t gic_read_count(void)
139{
140 unsigned int hi, hi2, lo;
141
6f50c835
MC		 142 if (mips_cm_is64)
143 return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));
144
dfa762e1 145 do {
c3f57f02
MC		 146 hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
147 lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
148 hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
dfa762e1
SH		 149 } while (hi2 != hi);
150
151 return (((cycle_t) hi) << 32) + lo;
152}
0ab2b7d0 153
387904ff
AB		 154unsigned int gic_get_count_width(void)
155{
156 unsigned int bits, config;
157
5f68fea0 158 config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
387904ff
AB		 159 bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
160 GIC_SH_CONFIG_COUNTBITS_SHF);
161
162 return bits;
163}
164
0ab2b7d0
RG		 165void gic_write_compare(cycle_t cnt)
166{
6f50c835
MC		 167 if (mips_cm_is64) {
168 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);
169 } else {
170 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
171 (int)(cnt >> 32));
172 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
173 (int)(cnt & 0xffffffff));
174 }
0ab2b7d0
RG		 175}
176
414408d0
PB		 177void gic_write_cpu_compare(cycle_t cnt, int cpu)
178{
179 unsigned long flags;
180
181 local_irq_save(flags);
182
5f68fea0 183 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
6f50c835
MC		 184
185 if (mips_cm_is64) {
186 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);
187 } else {
188 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
189 (int)(cnt >> 32));
190 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
191 (int)(cnt & 0xffffffff));
192 }
414408d0
PB		 193
194 local_irq_restore(flags);
195}
196
0ab2b7d0
RG		 197cycle_t gic_read_compare(void)
198{
199 unsigned int hi, lo;
200
6f50c835
MC		 201 if (mips_cm_is64)
202 return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));
203
c3f57f02
MC		 204 hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
205 lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
0ab2b7d0
RG		 206
207 return (((cycle_t) hi) << 32) + lo;
208}
8fa4b930
MC		 209
210void gic_start_count(void)
211{
212 u32 gicconfig;
213
214 /* Start the counter */
215 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
216 gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
217 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
218}
219
220void gic_stop_count(void)
221{
222 u32 gicconfig;
223
224 /* Stop the counter */
225 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
226 gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
227 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
228}
229
dfa762e1
SH		 230#endif
231
e9de688d
AB		 232static bool gic_local_irq_is_routable(int intr)
233{
234 u32 vpe_ctl;
235
236 /* All local interrupts are routable in EIC mode. */
237 if (cpu_has_veic)
238 return true;
239
c3f57f02 240 vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
e9de688d
AB		 241 switch (intr) {
242 case GIC_LOCAL_INT_TIMER:
243 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
244 case GIC_LOCAL_INT_PERFCTR:
245 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
246 case GIC_LOCAL_INT_FDC:
247 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
248 case GIC_LOCAL_INT_SWINT0:
249 case GIC_LOCAL_INT_SWINT1:
250 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
251 default:
252 return true;
253 }
254}
255
3263d085 256static void gic_bind_eic_interrupt(int irq, int set)
98b67c37
SH		 257{
258 /* Convert irq vector # to hw int # */
259 irq -= GIC_PIN_TO_VEC_OFFSET;
260
261 /* Set irq to use shadow set */
5f68fea0
AB		 262 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
263 GIC_VPE_EIC_SS(irq), set);
98b67c37
SH		 264}
265
39b8d525
RB		 266void gic_send_ipi(unsigned int intr)
267{
53a7bc81 268 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
39b8d525
RB		 269}
270
e9de688d
AB		 271int gic_get_c0_compare_int(void)
272{
273 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
274 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
275 return irq_create_mapping(gic_irq_domain,
276 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
277}
278
279int gic_get_c0_perfcount_int(void)
280{
281 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
7e3e6cb2 282 /* Is the performance counter shared with the timer? */
e9de688d
AB		 283 if (cp0_perfcount_irq < 0)
284 return -1;
285 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
286 }
287 return irq_create_mapping(gic_irq_domain,
288 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
289}
290
6429e2b6
JH		 291int gic_get_c0_fdc_int(void)
292{
293 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
294 /* Is the FDC IRQ even present? */
295 if (cp0_fdc_irq < 0)
296 return -1;
297 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
298 }
299
6429e2b6
JH		 300 return irq_create_mapping(gic_irq_domain,
301 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
302}
303
1b3ed367 304static void gic_handle_shared_int(bool chained)
39b8d525 305{
c3f57f02 306 unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
8f5ee79c 307 unsigned long *pcpu_mask;
5f68fea0 308 unsigned long pending_reg, intrmask_reg;
8f5ee79c
AB		 309 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
310 DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
39b8d525
RB		 311
312 /* Get per-cpu bitmaps */
39b8d525
RB		 313 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
314
824f3f7f
AB		 315 pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
316 intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
39b8d525 317
fbd55241 318 for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
5f68fea0
AB		 319 pending[i] = gic_read(pending_reg);
320 intrmask[i] = gic_read(intrmask_reg);
c3f57f02
MC		 321 pending_reg += gic_reg_step;
322 intrmask_reg += gic_reg_step;
d77d5ac9
PB		 323
324 if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
325 continue;
326
327 pending[i] |= (u64)gic_read(pending_reg) << 32;
328 intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
329 pending_reg += gic_reg_step;
330 intrmask_reg += gic_reg_step;
39b8d525
RB		 331 }
332
fbd55241
AB		 333 bitmap_and(pending, pending, intrmask, gic_shared_intrs);
334 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
39b8d525 335
d7eb4f2e
QY		 336 intr = find_first_bit(pending, gic_shared_intrs);
337 while (intr != gic_shared_intrs) {
338 virq = irq_linear_revmap(gic_irq_domain,
339 GIC_SHARED_TO_HWIRQ(intr));
1b3ed367
RV		 340 if (chained)
341 generic_handle_irq(virq);
342 else
343 do_IRQ(virq);
d7eb4f2e
QY		 344
345 /* go to next pending bit */
346 bitmap_clear(pending, intr, 1);
347 intr = find_first_bit(pending, gic_shared_intrs);
348 }
39b8d525
RB		 349}
350
161d049e 351static void gic_mask_irq(struct irq_data *d)
39b8d525 352{
5f68fea0 353 gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
39b8d525
RB		 354}
355
161d049e 356static void gic_unmask_irq(struct irq_data *d)
39b8d525 357{
5f68fea0 358 gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
39b8d525
RB		 359}
360
5561c9e4
AB		 361static void gic_ack_irq(struct irq_data *d)
362{
e9de688d 363 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
c49581a4 364
53a7bc81 365 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
5561c9e4
AB		 366}
367
95150ae8
AB		 368static int gic_set_type(struct irq_data *d, unsigned int type)
369{
e9de688d 370 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
95150ae8
AB		 371 unsigned long flags;
372 bool is_edge;
373
374 spin_lock_irqsave(&gic_lock, flags);
375 switch (type & IRQ_TYPE_SENSE_MASK) {
376 case IRQ_TYPE_EDGE_FALLING:
5f68fea0
AB		 377 gic_set_polarity(irq, GIC_POL_NEG);
378 gic_set_trigger(irq, GIC_TRIG_EDGE);
379 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
95150ae8
AB		 380 is_edge = true;
381 break;
382 case IRQ_TYPE_EDGE_RISING:
5f68fea0
AB		 383 gic_set_polarity(irq, GIC_POL_POS);
384 gic_set_trigger(irq, GIC_TRIG_EDGE);
385 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
95150ae8
AB		 386 is_edge = true;
387 break;
388 case IRQ_TYPE_EDGE_BOTH:
389 /* polarity is irrelevant in this case */
5f68fea0
AB		 390 gic_set_trigger(irq, GIC_TRIG_EDGE);
391 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
95150ae8
AB		 392 is_edge = true;
393 break;
394 case IRQ_TYPE_LEVEL_LOW:
5f68fea0
AB		 395 gic_set_polarity(irq, GIC_POL_NEG);
396 gic_set_trigger(irq, GIC_TRIG_LEVEL);
397 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
95150ae8
AB		 398 is_edge = false;
399 break;
400 case IRQ_TYPE_LEVEL_HIGH:
401 default:
5f68fea0
AB		 402 gic_set_polarity(irq, GIC_POL_POS);
403 gic_set_trigger(irq, GIC_TRIG_LEVEL);
404 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
95150ae8
AB		 405 is_edge = false;
406 break;
407 }
408
a595fc51
TG		 409 if (is_edge)
410 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
411 handle_edge_irq, NULL);
412 else
413 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
414 handle_level_irq, NULL);
95150ae8 415 spin_unlock_irqrestore(&gic_lock, flags);
39b8d525 416
95150ae8
AB		 417 return 0;
418}
419
420#ifdef CONFIG_SMP
161d049e
TG		 421static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
422 bool force)
39b8d525 423{
e9de688d 424 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
39b8d525
RB		 425 cpumask_t tmp = CPU_MASK_NONE;
426 unsigned long flags;
427 int i;
428
0de26520 429 cpumask_and(&tmp, cpumask, cpu_online_mask);
f9b531fe 430 if (cpumask_empty(&tmp))
14d160ab 431 return -EINVAL;
39b8d525
RB		 432
433 /* Assumption : cpumask refers to a single CPU */
434 spin_lock_irqsave(&gic_lock, flags);
39b8d525 435
c214c035 436 /* Re-route this IRQ */
ab41f6c8 437 gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
c214c035
TW		 438
439 /* Update the pcpu_masks */
440 for (i = 0; i < NR_CPUS; i++)
441 clear_bit(irq, pcpu_masks[i].pcpu_mask);
f9b531fe 442 set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
39b8d525 443
72f86db4 444 cpumask_copy(irq_data_get_affinity_mask(d), cpumask);
39b8d525
RB		 445 spin_unlock_irqrestore(&gic_lock, flags);
446
161d049e 447 return IRQ_SET_MASK_OK_NOCOPY;
39b8d525
RB		 448}
449#endif
450
4a6a3ea3
AB		 451static struct irq_chip gic_level_irq_controller = {
452 .name = "MIPS GIC",
453 .irq_mask = gic_mask_irq,
454 .irq_unmask = gic_unmask_irq,
455 .irq_set_type = gic_set_type,
456#ifdef CONFIG_SMP
457 .irq_set_affinity = gic_set_affinity,
458#endif
459};
460
461static struct irq_chip gic_edge_irq_controller = {
161d049e 462 .name = "MIPS GIC",
5561c9e4 463 .irq_ack = gic_ack_irq,
161d049e 464 .irq_mask = gic_mask_irq,
161d049e 465 .irq_unmask = gic_unmask_irq,
95150ae8 466 .irq_set_type = gic_set_type,
39b8d525 467#ifdef CONFIG_SMP
161d049e 468 .irq_set_affinity = gic_set_affinity,
39b8d525
RB		 469#endif
470};
471
1b3ed367 472static void gic_handle_local_int(bool chained)
e9de688d
AB		 473{
474 unsigned long pending, masked;
d7eb4f2e 475 unsigned int intr, virq;
e9de688d 476
c3f57f02
MC		 477 pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
478 masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
e9de688d
AB		 479
480 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
481
d7eb4f2e
QY		 482 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
483 while (intr != GIC_NUM_LOCAL_INTRS) {
484 virq = irq_linear_revmap(gic_irq_domain,
485 GIC_LOCAL_TO_HWIRQ(intr));
1b3ed367
RV		 486 if (chained)
487 generic_handle_irq(virq);
488 else
489 do_IRQ(virq);
d7eb4f2e
QY		 490
491 /* go to next pending bit */
492 bitmap_clear(&pending, intr, 1);
493 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
494 }
e9de688d
AB		 495}
496
497static void gic_mask_local_irq(struct irq_data *d)
498{
499 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
500
c3f57f02 501 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
e9de688d
AB		 502}
503
504static void gic_unmask_local_irq(struct irq_data *d)
505{
506 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
507
c3f57f02 508 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
e9de688d
AB		 509}
510
511static struct irq_chip gic_local_irq_controller = {
512 .name = "MIPS GIC Local",
513 .irq_mask = gic_mask_local_irq,
514 .irq_unmask = gic_unmask_local_irq,
515};
516
517static void gic_mask_local_irq_all_vpes(struct irq_data *d)
518{
519 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
520 int i;
521 unsigned long flags;
522
523 spin_lock_irqsave(&gic_lock, flags);
524 for (i = 0; i < gic_vpes; i++) {
5f68fea0 525 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
c3f57f02 526 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
e9de688d
AB		 527 }
528 spin_unlock_irqrestore(&gic_lock, flags);
529}
530
531static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
532{
533 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
534 int i;
535 unsigned long flags;
536
537 spin_lock_irqsave(&gic_lock, flags);
538 for (i = 0; i < gic_vpes; i++) {
5f68fea0 539 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
c3f57f02 540 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
e9de688d
AB		 541 }
542 spin_unlock_irqrestore(&gic_lock, flags);
543}
544
545static struct irq_chip gic_all_vpes_local_irq_controller = {
546 .name = "MIPS GIC Local",
547 .irq_mask = gic_mask_local_irq_all_vpes,
548 .irq_unmask = gic_unmask_local_irq_all_vpes,
549};
550
18743d27 551static void __gic_irq_dispatch(void)
39b8d525 552{
1b3ed367
RV		 553 gic_handle_local_int(false);
554 gic_handle_shared_int(false);
18743d27 555}
39b8d525 556
bd0b9ac4 557static void gic_irq_dispatch(struct irq_desc *desc)
18743d27 558{
1b3ed367
RV		 559 gic_handle_local_int(true);
560 gic_handle_shared_int(true);
18743d27
AB		 561}
562
563#ifdef CONFIG_MIPS_GIC_IPI
564static int gic_resched_int_base;
565static int gic_call_int_base;
566
567unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
568{
569 return gic_resched_int_base + cpu;
570}
39b8d525 571
18743d27
AB		 572unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
573{
574 return gic_call_int_base + cpu;
575}
39b8d525 576
18743d27
AB		 577static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
578{
579 scheduler_ipi();
580
581 return IRQ_HANDLED;
582}
583
584static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
585{
4ace6139 586 generic_smp_call_function_interrupt();
18743d27
AB		 587
588 return IRQ_HANDLED;
589}
b0a88ae5 590
18743d27
AB		 591static struct irqaction irq_resched = {
592 .handler = ipi_resched_interrupt,
593 .flags = IRQF_PERCPU,
594 .name = "IPI resched"
595};
596
597static struct irqaction irq_call = {
598 .handler = ipi_call_interrupt,
599 .flags = IRQF_PERCPU,
600 .name = "IPI call"
601};
602
603static __init void gic_ipi_init_one(unsigned int intr, int cpu,
604 struct irqaction *action)
605{
e9de688d
AB		 606 int virq = irq_create_mapping(gic_irq_domain,
607 GIC_SHARED_TO_HWIRQ(intr));
18743d27
AB		 608 int i;
609
ab41f6c8 610 gic_map_to_vpe(intr, mips_cm_vp_id(cpu));
c49581a4
AB		 611 for (i = 0; i < NR_CPUS; i++)
612 clear_bit(intr, pcpu_masks[i].pcpu_mask);
b0a88ae5
JD		 613 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
614
18743d27
AB		 615 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
616
617 irq_set_handler(virq, handle_percpu_irq);
618 setup_irq(virq, action);
39b8d525
RB		 619}
620
18743d27 621static __init void gic_ipi_init(void)
39b8d525 622{
18743d27
AB		 623 int i;
624
625 /* Use last 2 * NR_CPUS interrupts as IPIs */
fbd55241 626 gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
18743d27
AB		 627 gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
628
629 for (i = 0; i < nr_cpu_ids; i++) {
630 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
631 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
632 }
633}
634#else
635static inline void gic_ipi_init(void)
636{
637}
638#endif
639
e9de688d 640static void __init gic_basic_init(void)
18743d27
AB		 641{
642 unsigned int i;
98b67c37
SH		 643
644 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
39b8d525
RB		 645
646 /* Setup defaults */
fbd55241 647 for (i = 0; i < gic_shared_intrs; i++) {
5f68fea0
AB		 648 gic_set_polarity(i, GIC_POL_POS);
649 gic_set_trigger(i, GIC_TRIG_LEVEL);
650 gic_reset_mask(i);
39b8d525
RB		 651 }
652
e9de688d
AB		 653 for (i = 0; i < gic_vpes; i++) {
654 unsigned int j;
655
5f68fea0 656 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
e9de688d
AB		 657 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
658 if (!gic_local_irq_is_routable(j))
659 continue;
c3f57f02 660 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
e9de688d
AB		 661 }
662 }
39b8d525
RB		 663}
664
e9de688d
AB		 665static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
666 irq_hw_number_t hw)
c49581a4 667{
e9de688d
AB		 668 int intr = GIC_HWIRQ_TO_LOCAL(hw);
669 int ret = 0;
670 int i;
671 unsigned long flags;
672
673 if (!gic_local_irq_is_routable(intr))
674 return -EPERM;
675
676 /*
677 * HACK: These are all really percpu interrupts, but the rest
678 * of the MIPS kernel code does not use the percpu IRQ API for
679 * the CP0 timer and performance counter interrupts.
680 */
b720fd8b
JH		 681 switch (intr) {
682 case GIC_LOCAL_INT_TIMER:
683 case GIC_LOCAL_INT_PERFCTR:
684 case GIC_LOCAL_INT_FDC:
685 irq_set_chip_and_handler(virq,
686 &gic_all_vpes_local_irq_controller,
687 handle_percpu_irq);
688 break;
689 default:
e9de688d
AB		 690 irq_set_chip_and_handler(virq,
691 &gic_local_irq_controller,
692 handle_percpu_devid_irq);
693 irq_set_percpu_devid(virq);
b720fd8b 694 break;
e9de688d
AB		 695 }
696
697 spin_lock_irqsave(&gic_lock, flags);
698 for (i = 0; i < gic_vpes; i++) {
699 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
700
5f68fea0 701 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
e9de688d
AB		 702
703 switch (intr) {
704 case GIC_LOCAL_INT_WD:
c3f57f02 705 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
e9de688d
AB		 706 break;
707 case GIC_LOCAL_INT_COMPARE:
c3f57f02
MC		 708 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
709 val);
e9de688d
AB		 710 break;
711 case GIC_LOCAL_INT_TIMER:
1b6af71a
JH		 712 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
713 val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
c3f57f02
MC		 714 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
715 val);
e9de688d
AB		 716 break;
717 case GIC_LOCAL_INT_PERFCTR:
c3f57f02
MC		 718 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
719 val);
e9de688d
AB		 720 break;
721 case GIC_LOCAL_INT_SWINT0:
c3f57f02
MC		 722 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
723 val);
e9de688d
AB		 724 break;
725 case GIC_LOCAL_INT_SWINT1:
c3f57f02
MC		 726 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
727 val);
e9de688d
AB		 728 break;
729 case GIC_LOCAL_INT_FDC:
c3f57f02 730 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
e9de688d
AB		 731 break;
732 default:
733 pr_err("Invalid local IRQ %d\n", intr);
734 ret = -EINVAL;
735 break;
736 }
737 }
738 spin_unlock_irqrestore(&gic_lock, flags);
739
740 return ret;
741}
742
743static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
744 irq_hw_number_t hw)
745{
746 int intr = GIC_HWIRQ_TO_SHARED(hw);
c49581a4
AB		 747 unsigned long flags;
748
4a6a3ea3
AB		 749 irq_set_chip_and_handler(virq, &gic_level_irq_controller,
750 handle_level_irq);
c49581a4
AB		 751
752 spin_lock_irqsave(&gic_lock, flags);
5f68fea0 753 gic_map_to_pin(intr, gic_cpu_pin);
c49581a4 754 /* Map to VPE 0 by default */
5f68fea0 755 gic_map_to_vpe(intr, 0);
e9de688d 756 set_bit(intr, pcpu_masks[0].pcpu_mask);
c49581a4
AB		 757 spin_unlock_irqrestore(&gic_lock, flags);
758
759 return 0;
760}
761
e9de688d
AB		 762static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
763 irq_hw_number_t hw)
764{
765 if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
766 return gic_local_irq_domain_map(d, virq, hw);
767 return gic_shared_irq_domain_map(d, virq, hw);
768}
769
a7057270
AB		 770static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
771 const u32 *intspec, unsigned int intsize,
772 irq_hw_number_t *out_hwirq,
773 unsigned int *out_type)
774{
775 if (intsize != 3)
776 return -EINVAL;
777
778 if (intspec[0] == GIC_SHARED)
779 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
780 else if (intspec[0] == GIC_LOCAL)
781 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
782 else
783 return -EINVAL;
784 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
785
786 return 0;
787}
788
96009736 789static const struct irq_domain_ops gic_irq_domain_ops = {
c49581a4 790 .map = gic_irq_domain_map,
a7057270 791 .xlate = gic_irq_domain_xlate,
c49581a4
AB		 792};
793
a7057270
AB		 794static void __init __gic_init(unsigned long gic_base_addr,
795 unsigned long gic_addrspace_size,
796 unsigned int cpu_vec, unsigned int irqbase,
797 struct device_node *node)
39b8d525
RB		 798{
799 unsigned int gicconfig;
800
5f68fea0 801 gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
39b8d525 802
5f68fea0 803 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
fbd55241 804 gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
39b8d525 805 GIC_SH_CONFIG_NUMINTRS_SHF;
fbd55241 806 gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
39b8d525 807
e9de688d 808 gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
39b8d525 809 GIC_SH_CONFIG_NUMVPES_SHF;
e9de688d 810 gic_vpes = gic_vpes + 1;
39b8d525 811
18743d27
AB		 812 if (cpu_has_veic) {
813 /* Always use vector 1 in EIC mode */
814 gic_cpu_pin = 0;
1b6af71a 815 timer_cpu_pin = gic_cpu_pin;
18743d27
AB		 816 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
817 __gic_irq_dispatch);
818 } else {
819 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
820 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
821 gic_irq_dispatch);
1b6af71a
JH		 822 /*
823 * With the CMP implementation of SMP (deprecated), other CPUs
824 * are started by the bootloader and put into a timer based
825 * waiting poll loop. We must not re-route those CPU's local
826 * timer interrupts as the wait instruction will never finish,
827 * so just handle whatever CPU interrupt it is routed to by
828 * default.
829 *
830 * This workaround should be removed when CMP support is
831 * dropped.
832 */
833 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
834 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
c3f57f02 835 timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
1b6af71a
JH		 836 GIC_VPE_TIMER_MAP)) &
837 GIC_MAP_MSK;
838 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
839 GIC_CPU_PIN_OFFSET +
840 timer_cpu_pin,
841 gic_irq_dispatch);
842 } else {
843 timer_cpu_pin = gic_cpu_pin;
844 }
18743d27
AB		 845 }
846
a7057270 847 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
e9de688d 848 gic_shared_intrs, irqbase,
c49581a4
AB		 849 &gic_irq_domain_ops, NULL);
850 if (!gic_irq_domain)
851 panic("Failed to add GIC IRQ domain");
0b271f56 852
e9de688d 853 gic_basic_init();
18743d27
AB		 854
855 gic_ipi_init();
39b8d525 856}
a7057270
AB		 857
858void __init gic_init(unsigned long gic_base_addr,
859 unsigned long gic_addrspace_size,
860 unsigned int cpu_vec, unsigned int irqbase)
861{
862 __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
863}
864
865static int __init gic_of_init(struct device_node *node,
866 struct device_node *parent)
867{
868 struct resource res;
869 unsigned int cpu_vec, i = 0, reserved = 0;
870 phys_addr_t gic_base;
871 size_t gic_len;
872
873 /* Find the first available CPU vector. */
874 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
875 i++, &cpu_vec))
876 reserved |= BIT(cpu_vec);
877 for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
878 if (!(reserved & BIT(cpu_vec)))
879 break;
880 }
881 if (cpu_vec == 8) {
882 pr_err("No CPU vectors available for GIC\n");
883 return -ENODEV;
884 }
885
886 if (of_address_to_resource(node, 0, &res)) {
887 /*
888 * Probe the CM for the GIC base address if not specified
889 * in the device-tree.
890 */
891 if (mips_cm_present()) {
892 gic_base = read_gcr_gic_base() &
893 ~CM_GCR_GIC_BASE_GICEN_MSK;
894 gic_len = 0x20000;
895 } else {
896 pr_err("Failed to get GIC memory range\n");
897 return -ENODEV;
898 }
899 } else {
900 gic_base = res.start;
901 gic_len = resource_size(&res);
902 }
903
904 if (mips_cm_present())
905 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
906 gic_present = true;
907
908 __gic_init(gic_base, gic_len, cpu_vec, 0, node);
909
910 return 0;
911}
912IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
Linux kernel - Deliverables
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